Hi Michael, SCTs are in scope. It is only deciding when they get run and how much pre-commit execution time developers are willing to wait for a pass/fail result. The on-demand testing feature is one

Hi Michael, would it make sense to run SCT (using UnixHost and/or qemu) to verify the high level logic or do you think that would be too much to do for each PR? Also, do we want to run all these check

Hi Sean, These tests sound awesome! commits. I'd like to keep the per-PR tests down to 10 minutes. On the other hand, it would be great if all of these tests could be performed daily or weekly. Are th

Laszlo Ersek <lersek@...> wrote: Ok, let me check if we could cannibalize q35 pci-host for the task or it would be easier to extend MMIO cpu-hotplug interface. I'll probably come back with questions a

I was going through the steps Jiewen and Yingwen recommended. In step (02), the new CPU is expected to set up RAM access. In step (03), the new CPU, executing code from flash, is expected to "send boa

Laszlo Ersek <lersek@...> wrote: currently there is no SMRAM at 0x30000, so all access falls through into RAM address space and we are about to change that. but firmware doesn't have to use it as RAM,

I'm sure you are *technically* right, but you seem to be assuming that I can modify or rearrange anything I want in edk2. :) If we can solve the above in OVMF platform code, that's great. If not (e.g.

Hi everyone, Putty is a popular terminal console software in windows and it support various types of terminal keyboard type. I would like to add most of the type support. Here is the key map info. Hop

Hello, I have a question about user error reporting during SecureBoot image validation. From my testing with OVMF/Secureboot, when an image to be loaded fails validation (i.e. due to missing or incorr

lpc already has SMI negotiation feature, extend it by adding optin ICH9_LPC_SMI_F_LOCKED_SMBASE_BIT to supported features. Writing this bit into "etc/smi/requested-features" fw_cfg file, tells QEMU to

Try #2 using PCI config space of MCH to negotiate/lock SMRAM at 0x30000. CC: yingwen.chen@... CC: devel@edk2.groups.io CC: phillip.goerl@... CC: alex.williamson@... CC: jiewen.yao@... CC: jun.nakajima

Use commit (2f295167e0 q35/mch: implement extended TSEG sizes) for inspiration and (ab)use reserved register in config space at 0x9c offset [*] to extend q35 pci-host with ability to use 128K at 0x300

test lockable SMRAM at default SMBASE feature introduced by commit "q35: implement 128K SMRAM at default SMBASE address" Signed-off-by: Igor Mammedov <imammedo@...> --- tests/q35-test.c | 105 ++++++++

"Laszlo Ersek" <lersek@...> wrote: If we don't have to 'park' hotplugged CPUs, then I don't see a need for an extra controller. Thanks for the tip! ... patches with a stolen register are on the way to

In that wiki page, it says: "To work with this branch and run tests immediately, all you need to do is: |pip install --upgrade -r requirements.txt stuart_setup -c .\CISettings.py stuart_update -c .\CI

Hi Igor, (+Brijesh) long-ish pondering ahead, with a question at the end. I haven't written any OVMF code for this yet, but I've spent a few hours thinking about it. Progress! :) So, this looks really

Hello, This is a proposal for a first step towards continuous integration for all TianoCore repositories to help improve to quality of commits and automate testing and release processes for all EDK II

Yes. The maintainer will prepare a local branch that is rebased to master, and has all the mailing list feedback tags (Reviewed-by, etc) applied. The maintainer also does all the local testing that th

Hi Sean, This looks really good and I agree we can combine the RFCs and enable more pre-commits tests. Additional responses below. Mike

Hi Sean, Which OS/Compiler configurations are currently enabled for the Code Compilation Test? I have been working on enabling multiple OS/Compiler configurations in Azure Pipelines. There are some to