[AMD Official Use Only - General] Hi community, We are going to upstream generic edk2 SPI driver stack that is compliant with UEFI PI spec. The SPI driver stack is proposed to be located under MdeModu

[AMD Official Use Only - General] Hi all, This is the RFC to occupy BIT23 of debug error level for Manageability messages. This debug print error level covers below packages and purposes, * edk2 Redfi

[AMD Official Use Only - General] Hi edk2 community, We are proposing to introduce a new repository under Tianocore Github which is edk2-redfish-client. The plan is to have RedfishClientPkg, Redfish s

Hello everyone, Submitted for the community to evaluate and provide any feedback. We are looking to move to GitHub Security Reporting and Security advisories. This makes some minor changes to the Secu

Hello, In the past few years there has been some effort to add unit tests to EDK2 components. Some unit tests that execute under OS and can be run as a part of CI were added for some simple modules su

Hi, I have already one ticket in Discussion Forum. Please check it for more details -https://edk2.groups.io/g/devel/message/98333?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3Arecentpostdate%2Fsticky%2C%2Ciscsi%2C20

Hi, I have already one ticket in Discussion Forum. Please check it for more details -https://edk2.groups.io/g/devel/message/98333?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3Arecentpostdate%2Fsticky%2C%2Ciscsi%2C20

EL3 firmware may implement PSCI interface on aarch64 platforms, including qemu-tcg-aarch64. However, EL3 firmware does not usually own pulling and deploying ACPI tables from qemu fw_cfg. Thus the only

Hi EDK2 community, I have a used case, where I am trying to change boot order for multiboot (multiple OS) systems and for singleboot systems. I was able to change the boot order and set auto boot time

CXL Early Discovery Table (CEDT) enables OSes to locate CXL Host Bridges and location of Host Bridge Registers early during boot and configure Host Bridge Decoders according to ACPI information. This

CEDT structure type, CXL Host Bridge(CHBS) describes the location of CXL Host Bridge, allowing OS to configure CXL Host Bridge. CEDT structure type, CXL Fixed Memory Window(CFMWS) describes Host Physi

Get remote memory node details(number of memory nodes, remote memory range address) by using CxlProtocol interfaces. Prepare SRAT table with both Local memory, remote memory blocks, along with other n

Adds support for CXL driver. The present solution supports - Discovering PCIe device with CXL and DOE capbility. Execute DOE operation to fetch CDAT structures, which holds information about remote CX

This patch series adds support for discovering and reading out CXL device capabilities, also it prepares SRAT, HMAT, CEDT tables. First patch adds a CXL DXE. It discovers PCIe device with CXL and DOE

Hello, I am exploring a proposal to use GitHub PR for code review. Specifically the last option listed in the following discussion: https://github.com/tianocore/edk2/discussions/3017 I am using the ed

Hi All, I would like to propose adding Alert standard format support which is based on ASF2.0 specification(DSP0136). The drivers would use smbus to send standard alert message base on the status code

This patch modifies the build system in order to generate and use metadata to add it to the efi binaries. It uses python-uswid [1], given a set of config files (.ini) with the metadata it converts the

This is version 2 of the proposal that provides additional details regarding the bring up process. The initial version is at https://edk2.groups.io/g/rfc/message/696 The goal of the proposal is integr

I can sign up to maintain XCODE. I think Rebecca has been running test builds with XCODE. The XCODE5 names comes from the compiler flags needing to change for Xcode 5. Yes 2013 called and wants it com

Hi, It's basically gcc 5 & newer. I think all the GCC4x variants can be dropped by now. take care, Gerd