CEDT structure type, CXL Host Bridge(CHBS) describes the location of CXL
Host Bridge, allowing OS to configure CXL Host Bridge.
CEDT structure type, CXL Fixed Memory Window(CFMWS) describes Host
Physical Address(HPA) window that is associated with a CXL Host bridge.
ACPI0017 is a SW entity under System Bus of ACPI tree, that indicates
the presence of CEDT table.
ACPI0016 is a SW entity under System Bus of ACPI tree, that represents
a CXL Host Bridge.
This patch demonstrates, the addition of CEDT structures, that allows
OS drivers to detect the presence of CXL Host bridge and CEDT structures
and then perform necessary configuration of CXL Host bridge registers
according to ACPI information.
In this patch, Interleave target number is considered 1 for demonstrating
a reference solution with CEDT structures. There is no real interleaving
address windows across multiple ports with this configuraiton. It is
same as single port CXL Host bridge.
Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@...>
---
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 7 +-
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Cedt.aslc | 86 ++++++++++++=
++
Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Ssdt.asl | 119 ++++++++++++=
++++++++
3 files changed, 210 insertions(+), 2 deletions(-)
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf b/Plat=
form/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
index 4b36c3e5ce..72d8b58c31 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
@@ -1,7 +1,7 @@
## @file
# ACPI table data and ASL sources required to boot the platform.
#
-# Copyright (c) 2021, Arm Ltd. All rights reserved.
+# Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -23,8 +23,10 @@
RdN2Cfg1/Dsdt.asl
RdN2Cfg1/Madt.aslc
RdN2Cfg1/Pptt.aslc
+ RdN2Cfg1/Cedt.aslc
+ RdN2Cfg1/Ssdt.asl
Spcr.aslc
- Ssdt.asl
+ Mcfg.aslc
SsdtRos.asl
SsdtEvents.asl
=20
@@ -73,3 +75,4 @@
gArmSgiTokenSpaceGuid.PcdWdogWS1Gsiv
=20
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Cedt.aslc b/Platform=
/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Cedt.aslc
new file mode 100644
index 0000000000..9ff59c68e5
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Cedt.aslc
@@ -0,0 +1,86 @@
+/** @file
+ CXL Early Discovery Table (CEDT) for RD-N2-Cfg1 platform
+
+ This file describes CXL Host Bridge Structure(CHBS) and
+ CXL Fixed Memory Window Structure(CFMWS), which are used by Operating
+ System during boot for locating CXL host bridge and performing necessa=
ry
+ decoder configuration according to ACPI information.
+
+ Copyright (c) 2022, Arm Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - CXL Specificiation Revision 3.0, Version 0.7, Chapter 9.16.1,
+ CXL Early Discovery Table (CEDT)
+**/
+
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
+
+#define INTERLEAVE_TARGETS 1
+
+#pragma pack (1)
+
+typedef struct {
+ EFI_ACPI_CEDT_CFMWS_STRUCTURE Cfmws;
+ UINT32 InterleaveTarget[INTERLEAVE_TARGETS];
+} EFI_ACPI_CEDT_CFMWS_AND_INTERLEAVE_TARGET_STRUCTURE;
+
+typedef struct {
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_ACPI_CEDT_CFMWS_AND_INTERLEAVE_TARGET_STRUCTURE CfmwsTarget;
+ EFI_ACPI_CEDT_CHBS_STRUCTURE Chbs;
+} EFI_ACPI_CEDT_STRUCTURE_TABLE;
+
+#pragma pack ()
+
+STATIC EFI_ACPI_CEDT_STRUCTURE_TABLE Cedt =3D {
+ ARM_ACPI_HEADER (
+ EFI_ACPI_6_4_CEDT_SIGNATURE,
+ EFI_ACPI_CEDT_STRUCTURE_TABLE,
+ 1
+ ),
+ {
+ {
+ // CFMWS
+ {
+ 1,
+ EFI_ACPI_RESERVED_BYTE,
+ sizeof (EFI_ACPI_CEDT_CFMWS_AND_INTERLEAVE_TARGET_STRUCTURE)
+ },
+ EFI_ACPI_RESERVED_DWORD,
+ 0x3fe00000000,
+ 0x200000000,
+ 0,
+ 0,
+ EFI_ACPI_RESERVED_WORD,
+ 4,
+ 2,
+ 0
+ },
+ {
+ //Interleave target list
+ 1
+ }
+ },
+ {
+ // CHBS
+ {
+ 0,
+ EFI_ACPI_RESERVED_BYTE,
+ sizeof (EFI_ACPI_CEDT_CHBS_STRUCTURE)
+ },
+ 1,
+ 1,
+ EFI_ACPI_RESERVED_DWORD,
+ 0x10D0000000,
+ 0x1000
+ }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from rem=
oving
+// the data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable =3D &Cedt;
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Ssdt.asl b/Platform/=
ARM/SgiPkg/AcpiTables/RdN2Cfg1/Ssdt.asl
new file mode 100644
index 0000000000..119f35b59d
--- /dev/null
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Ssdt.asl
@@ -0,0 +1,119 @@
+/** @file
+ Secondary System Description Table (SSDT)
+
+ Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "SgiAcpiHeader.h"
+
+DefinitionBlock("SsdtPci.aml", "SSDT", 2, "ARMLTD", "ARMSGI", EFI_ACPI_A=
RM_OEM_REVISION) {
+ Scope (_SB) {
+ // PCI Root Complex
+ Device (PCI0) {
+ Name (_HID, "ACPI0016") // CXL Host Bridge
+ Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, Zero) // PCI Segment Group number
+ Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_UID, 1) // Unique ID
+ Name (_CCA, 1) // Cache Coherency Attribute
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x60000000, // Min Base Address
+ 0x6FFFFFFF, // Max Base Address
+ 0x00000000, // Translate
+ 0x10000000 // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x4000000000, // Min Base Address
+ 0x5FFFFFFFFF, // Max Base Address
+ 0x00000000, // Translate
+ 0x2000000000 // Length
+ )
+
+ DWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ 0x00000000, // Min Base Address
+ 0x007FFFFF, // Max Base Address
+ 0x77800000, // Translate
+ 0x00800000, // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ }) // Name (RBUF)
+
+ Return (RBUF)
+ } // Method (_CRS)
+
+ Device (RES0)
+ {
+ Name (_HID, "PNP0C02") // PNP Motherboard Resources
+ Name (_CRS, ResourceTemplate ()
+ {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x00000000,
+ 0x1010000000, // ECAM Start
+ 0x101FFFFFFF, // ECAM End
+ 0x00000000,
+ FixedPcdGet64 (PcdPciExpressBaseSize), // ECAM Size
+ ,
+ ,
+ ,
+ AddressRangeMemory,
+ TypeStatic
+ )
+ })
+ }
+ }
+
+ Device (CXL1) { // Host bridge CEDT
+ Name (_HID, "ACPI0017")
+ Name (_UID, 1)
+ }
+ }
+}
--=20
2.17.1
