Hello everyone, Submitted for the community to evaluate and provide any feedback. We are looking to move to GitHub Security Reporting and Security advisories. This makes some minor changes to the

Hello, In the past few years there has been some effort to add unit tests to EDK2 components. Some unit tests that execute under OS and can be run as a part of CI were added for some simple modules

Hi, I have already one ticket in Discussion Forum. Please check it for more details

Hi, I have already one ticket in Discussion Forum. Please check it for more details

EL3 firmware may implement PSCI interface on aarch64 platforms, including qemu-tcg-aarch64. However, EL3 firmware does not usually own pulling and deploying ACPI tables from qemu fw_cfg. Thus the only

EL3 firmware may implement PSCI interface on aarch64 platforms, including qemu-tcg-aarch64. However, EL3 firmware does not usually own pulling and deploying ACPI tables from qemu fw_cfg. Thus the only

PS: With "emulates" I mean that it uses RAM to store variables. This naturally ends up getting cleared on a reboot, which is possibly what you're seeing. wrote: -- Pedro Falcato

Hi, (cc devel) NVRAM has nothing to do with disks or EFI partitions. Are you using OVMF? How are you using it? OVMF itself emulates variable storage if you run it in the wrong way. -- Pedro

Hi EDK2 community, I have a used case, where I am trying to change boot order for multiboot (multiple OS) systems and for singleboot systems. I was able to change the boot order and set auto

CXL Early Discovery Table (CEDT) enables OSes to locate CXL Host Bridges and location of Host Bridge Registers early during boot and configure Host Bridge Decoders according to ACPI information. This

CEDT structure type, CXL Host Bridge(CHBS) describes the location of CXL Host Bridge, allowing OS to configure CXL Host Bridge. CEDT structure type, CXL Fixed Memory Window(CFMWS) describes

Get remote memory node details(number of memory nodes, remote memory range address) by using CxlProtocol interfaces. Prepare SRAT table with both Local memory, remote memory blocks, along with other

Adds support for CXL driver. The present solution supports - Discovering PCIe device with CXL and DOE capbility. Execute DOE operation to fetch CDAT structures, which holds information about

This patch series adds support for discovering and reading out CXL device capabilities, also it prepares SRAT, HMAT, CEDT tables. First patch adds a CXL DXE. It discovers PCIe device with CXL and

Hello, I am exploring a proposal to use GitHub PR for code review. Specifically the last option listed in the following discussion: https://github.com/tianocore/edk2/discussions/3017 I am

Hi All, I would like to propose adding Alert standard format support which is based on ASF2.0 specification(DSP0136). The drivers would use smbus to send standard alert message base on the status

That works for me too. See you on Tuesday!

Hi Richard Yes, the 7th of July That time allowance will be perfect.. I will give you the first time slot to make sure we can meet your schedule. See you there.. Thank you for working with me on

On the 7th? In which case I can do 1700 BST but I have a hard stop at 1745 -- if that helps. Sorry! RIchard.

Hmm, that's 3:30 AM BST for me. Martin, that's 1:00 AM for you? I think we might have to send our apologies Miki, unless we can record something tomorrow for you to show? Richard.