Re: MemoryFence()

Ankur Arora

On 2021-02-09 10:40 p.m., Paolo Bonzini wrote:
Il mer 10 feb 2021, 07:37 Ankur Arora <ankur.a.arora@... <mailto:ankur.a.arora@...>> ha scritto:
So I don't quite see what would make "memory_order_seq_cst" harder?
 From the spec (
"Atomic operations tagged memory_order_seq_cst not only order
memory the same way as release/acquire ordering (everything
that happened-before a store in one thread becomes a visible
side effect in the thread that did a load), but also establish
a single total modification order of all atomic operations
that are so tagged."
The problem is that the ordering does not extend to relaxed (or even acquire/release) loads and stores. Therefore *every* store that needs to be ordered before a seq_cst load must also be seq_cst. This is hard enough to guarantee that using a fence is preferable.
Thanks for the explanation. That does sound like a pain to work with.

I wonder if there are CPUs with ordering primitives fine-grained
enough where this would be useful.


Is the total modification order the problem?

> Paolo

Join to automatically receive all group messages.