Re: MemoryFence()


Ard Biesheuvel <ardb@...>
 

On Mon, 8 Feb 2021 at 17:11, Laszlo Ersek <lersek@...> wrote:

On 02/06/21 09:37, Ard Biesheuvel wrote:

On ARM, 'inner shareable' is [generally] the subset of nodes and
edges that make up the CPUs, caches and cache-coherent DMA masters
(but not main memory)
This seems consistent with the fact that Paolo recommended variants of
"dmb ish" for all the memory (not compiler) fences -- I guess we don't
care about actual RAM content as long as all CPUs and cache-coherent DMA
masters see the same data.

Generally, yes. But I already mentioned non-cache coherent DMA
devices, and we also have some ARM platforms that use non-shareable
mappings for SRAM, which is used as temporary PEI memory in some
cases.

So the safe option is really to just use system-wide barriers - if
anyone has a use case where this is a performance bottleneck, we can
always revisit this later.

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