On ARM, 'inner shareable' is [generally] the subset of nodes and edges that make up the CPUs, caches and cache-coherent DMA masters (but not main memory)
This seems consistent with the fact that Paolo recommended variants of "dmb ish" for all the memory (not compiler) fences -- I guess we don't care about actual RAM content as long as all CPUs and cache-coherent DMA masters see the same data.
