On Fri, 5 Feb 2021 at 20:35, Laszlo Ersek <lersek@...> wrote:

rant warning

On 02/05/21 19:29, Ni, Ray wrote:

I read a bit about c memory model.
https://gcc.gnu.org/wiki/Atomic/GCCMM/AtomicSync

Thanks.

I think what happened here is a catastrophic impedance mismatch.

The underlying, physical architecture is a message-passing one.

Yet the mental abstraction that is built atop, for programmers to deal
with, is "shared memory". Which suggests a global shared state.

This is *suicidal*.

<snip>

I don't think the message passing paradigm is 100% accurate but it is
very close.

You should realize that a modern system is a network of CPUs, caches,
DRAM controllers and other bus masters, which is being traversed by
packets that represent the memory transactions (request/response pairs
for reads and non-posted writes). There is no natural 'grand scheme'
ordering of things, and when a certain memory ordering is required,
additional work is needed, which translates into additional packets,
packet types and silicon gates. (Disclaimer: I'm not a HW engineer)

A barrier is a packet that is broadcast on this network to instruct
all nodes that all transactions of a certain type need to be completed
before servicing or initiating new ones. On ARM, 'inner shareable' is
[generally] the subset of nodes and edges that make up the CPUs,
caches and cache-coherent DMA masters (but not main memory)

This is why it is more difficult for x86 to scale to 100s of cores:
there are simply more of these broadcasts being sent for ordinary
memory accesses, which gets out of hand quite quickly when scaling
out.