Re: MemoryFence()

Laszlo Ersek

On 02/05/21 19:17, Paolo Bonzini wrote:

On x86 load-load, load-store and store-store ordering is already guaranteed
by the processor. Therefore on x86 the AcquireMemoryFence and
ReleaseMemoryFence are just like CompilerFence: they only have to block
compiler-level reordering. MemoryFence is the only one that blocks
store-load reordering and needs to emit an MFENCE instruction.
This is exactly what the fence API implementations should have in their
comments, preferably with Intel / AMD manual references...

On ARM (either 32- or 64-bit) the processor-level guarantees are weaker,
and you need to emit a "dmb" instruction for acquire and release fences as
Same, just with the ARM ARM.


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