Paolo Bonzini <pbonzini@...>
On 14/08/19 15:20, Yao, Jiewen wrote:
Yes, this would be a new operation mode for QEMU, that only applies to- Does this part require a new branch somewhere in the OVMF SEC code?[Jiewen] I think this is blocked from hardware perspective, since the first instruction.
hot-plugged CPUs. In this mode the AP doesn't reply to INIT or SMI, in
fact it doesn't reply to anything at all.
You do not need a reset vector or INIT/SIPI/SIPI sequence at all in- How do we tell the hot-plugged AP where to start execution? (I.e. that[Jiewen] Same real mode reset vector at FFFF:FFF0.
QEMU. The AP does not start execution at all when it is unplugged, so
no cache-as-RAM etc.
We only need to modify QEMU so that hot-plugged APIs do not reply to
I don’t think there is problem for real hardware, who always has CAR.Why is a CPU-specific region needed if every other processor is in SMM
and thus trusted.
I can answer this: the SMM handler would interact with the hotplugDoes CPU hotplug apply only at the socket level? If the CPU is
controller in the same way that ACPI DSDT does normally. This supports
multiple hotplugs already.
Writes to the hotplug controller from outside SMM would be ignored.
The QEMU DSDT could be modified (when secure boot is in effect) to OUT(03) New CPU: (Flash) send board message to tell host CPU (GPIO->SCI)Maybe we can simplify this in QEMU by broadcasting an SMI to existent
to 0xB2 when hotplug happens. It could write a well-known value to
0xB2, to be read by an SMI handler in edk2.
Right, this would be a write to the CPU hotplug controller[Jiewen] The new CPU does not enable SMI at reset.(NOTE: Host CPU can onlysendinstruction in SMM mode. -- The register is SMM only)Sorry, I don't follow -- what register are we talking about here, and
See above.[Jiewen] OS here means the Host CPU running code in OS environment, not in SMM environment.(04) Host CPU: (OS) get message from board that a new CPU is added.I don't understand the OS involvement here. But, again, perhaps QEMU can
See above.[Jiewen] Right. That is the register to let host CPU tell new CPU to enable SMI.(06) Host CPU: (SMM) Save 38000, Update 38000 -- fill simple SMMAha, so this is the SMM-only register you mention in step (03). Is the
So in our case we'd need an INIT/SIPI/SIPI sequence between (06) and (07).[Jiewen] The new CPU exits SMM and return to original place - where it is(10) New CPU: (SMM) Response first SMI at 38000, and rebase SMBASE toWhat code does the new CPU execute after it completes step (10)? Does it
I'd rather avoid this and stay as close as possible to real hardware.(11) Host CPU: (SMM) Restore 38000.These steps (i.e., (06) through (11)) don't appear RAS-specific. The