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Is there any provision to adjust Bus Range (Number of buses assigned to root bridge) during or after PciBusDxe (PciBusDriverBindingStart) call.
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With my little understanding of whole PCI stack on edkii, i am writing this.
I am seeing EFI_OUT_OF_RESOURCES failure (due to limited bus numbers assigned for root bridge at PEI phase) in PciBusDriverBindingStart call.
The function call flow is following :
PciBusDriverBindingStart () -> PciEnumerator () -> PciHostBridgeEnumerator () -> PciRootBridgeEnumerator () -> PciScanBus () -> PciAllocateBusNumber() returns EFI_OUT_OF_RESOURCES.
This happens because the PCI card connected to particular root bridge goes beyond assigned bus range (total number of bus assigned to this root bridge at PEI phase). And the failure returns till PciBusDriverBiningingStart call.
So my questions are:
1. In scenarios where we have limited bus number like 256 buses (on platform, there could be multiple root bridge), how one would decide on how many PCI buses should be assigned to each root bridge? PCI enumeration happens at DXE phase till that time we do not know how many bus numbers would be claimed by devices under root bridges.
2. Is there any solution, like we have for MMIO resource conflict scenario. Where we have PciResourceConflict () callback which reassigns or reallocates MMIO resources among the root bridges according to requirement captured during DXE phase.
Any help on above would be appreciated.
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