But won't it?
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There can be only two scenarios :
1. PCI address space coincides with CPU address space.
In this case host address = device address and translation = 0
2. PCI address space lies at some offset in CPU address space. Like the example I mention in LX2160A
In this case host address = device address + translation, where translation > 0
Can there be a scenario where translation < 0 ? I don't think so
From: Ni, Ray <firstname.lastname@example.org>
Sent: Monday, May 11, 2020 7:37 AM
To: Pankaj Bansal <email@example.com>; Heyi Guo <firstname.lastname@example.org>;
Yi Li <email@example.com>; Ard Biesheuvel <firstname.lastname@example.org>
Subject: RE: Clarification needed for PCI address translation
I don't think the assumption is valid that host address be "always" greater than
From: Pankaj Bansal <email@example.com>
Sent: Sunday, May 10, 2020 12:10 PM
To: Heyi Guo <firstname.lastname@example.org>; Yi Li <email@example.com>; Ni,
<firstname.lastname@example.org>; Ard Biesheuvel <email@example.com>
Subject: Clarification needed for PCI address translation
Hi Heyi Guo et al,
I have a question about the patch that you submitted in edk2:
Author: Heyi Guo <firstname.lastname@example.org>
Date: Thu Feb 8 11:13:27 2018 +0800
MdeModulePkg/PciBus: return CPU address for GetBarAttributes
According to UEFI spec 2.7, PciIo->GetBarAttributes should return host
address (CPU view ddress) rather than device address (PCI view
device address = host address + address translation offset,
so we subtract translation from device address before returning.
diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciIo.c
index fef3eceb7f62..62179eb44bbd 100644
@@ -1972,6 +1972,10 @@ PciIoGetBarAttributes (
+ // According to UEFI spec 2.7, we need return host address for
+ // PciIo->GetBarAttributes, and host address = device address - translation.
+ Descriptor->AddrRangeMin -= Descriptor->AddrTranslationOffset;
Now I have a question about this statement : "host address = device address -
Won't the host address be "always" greater than device address ?
As I see the PCI controller integration in out ARM64 based SOC (LX2160), the
PCI address space
of a controller starts at > 4 GB offset in HOST address space. E.g. :
Start address | End address | Size | Allocation
0x3600000 | 0x360FFFF | 64K | PCI controller registers
0x80000000 | 0xFFFFFFFF | 2GB | DDR
0x8000000000 | 0x87FFFFFFFF | 32GB | PCI Express
All the BAR allocations (IO/MEM32/MEM64) are done from 32 GB PCI express
space (i.e. 0x8000000000 - 0x87FFFFFFFF)
The corresponding PCI addresses for devices are in 32 GB range i.e. 0x0 -
If I take translation = 0x8000000000, So for this case :
host address = device address + translation.