Implement the SpeculationBarrier with implementations consisting of fence instruction which provides finer-grain memory orderings. Perform Data Barrier in RiscV: fence rw,rw Perform Instruction Barrie

Could someone push the merge button on this pr please? https://github.com/tianocore/edk2/pull/4470

Edk2 was failing, rather than creating more PML4 entries, when they weren't present in the initial memory acceptance flow. Because of that VMs with more than 512G memory were crashing. This code fixes

Currently, CharEncodingCheckPlugin prints a message for every file that passes the test, which for some platforms can cause most of the CI build log to be filled with this print. It does not add any v

If there is no port multiplier, PortMultiplierPort should be converted to 0 to follow AHCI spec. The same logic already applied in AtaAtapiPassThruDxe driver. Signed-off-by: Neo Hsueh <Hong-Chih.Hsueh

From: Ranbir Singh <Ranbir.Singh3@...> Line number 365 does contain a typecast with UINT32, but it is after all the operations (16-bit left shift followed by OR'ing) are over. To avoid any SIGN_EXTENS

From: Ranbir Singh <Ranbir.Singh3@...> The return value stored in Status after call to SetDriveParameters is not made of any use thereafter and hence it remains as UNUSED. Assuming, this non-usage is

From: Ranbir Singh <Ranbir.Singh3@...> Line number 1348 does contain a typecast with UINT32, but it is after all the operations (16-bit left shift followed by OR'ing) are over. To avoid any SIGN_EXTEN

From: Aryeh Chen <aryeh.chen@...> Fix issue: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4474 ACPI_Spec_6_5_Aug29 Table 5.19 page #128 that MADT Revision field is 6. Cc: Michael D Kinney <michael

gcc-13 for RISC-V enables unwind tables by default similar to ARM64. This generates .eh_frame_hdr section which is not handled well by GenFw causing failures. Disable the unwind tables by adding -fno-

Uncrustify checks are too rigid, making them counter-productive: - it leads to code that is arguably harder to parse visually (e.g., the changes to ArmPkg/Include/Chipset/AArch64Mmu.h in commit 429309

Now that ArmSetMemoryAttributes() permits a mask to be provided, we can simplify the implementation the UEFI memory attribute protocol substantially, and just pass on the requested mask to be set or c

Now that we have a generic method to manage memory permissions using a PPI, we can switch to the generic version of the DXE handoff code in DxeIpl, and drop the ARM specific version. Signed-off-by: Ar

Implement the newly defined PPI that permits the PEI core and DXE IPL to manage memory permissions on ranges of DRAM, for doing things like mapping the stack non-executable, or granting executable per

Currently, ArmSetMemoryAttributes () takes a combination of EFI_MEMORY_xx constants describing the memory type and permission attributes that should be set on a region of memory. In cases where the me

If the associated PCD is set to TRUE, use the memory attribute PPI to remap the stack non-executable. This provides a generic method for doing so, which will be used by ARM and AArch64 as well once th

The Risc-V and LoongArch specific versions of the DXE core handoff code in DxeIpl are essentially copies of the EBC version (modulo the copyright in the header and some debug prints in the code). In p

Define a PPI interface that may be used by the PEI core or other PEIMs to manage permissions on memory ranges. This is primarily intended for restricting permissions to what is actually needed for cor

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4468=0D =0D This is a followup to the RFC that I sent to the edk2-devel list on the=0D 25th of May.=0D =0D In an attempt to make some incremental

Signed-off-by: Gerd Hoffmann <kraxel@...> --- CryptoPkg/Library/OpensslLib/openssl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CryptoPkg/Library/OpensslLib/openssl b/CryptoPkg/Li