Hello everyone. There are some tests in Rust std that statically link to a C static library to check ffi. Since if Rust is ever used in edk2, it would probably have to integrate with the existing C co

Run all Linux based jobs in a container, using a custom Fedora 35 image (gcc 11). The image is hosted on ghcr.io and the Dockerfiles are here: https://github.com/tianocore/containers The version numbe

Remove BaseTools/Bin/gcc*_linux_ext_dep.yaml to stop downloading gcc from external locations; use the toolchains provided by the container image instead. The image needs to set the GCC5_*_PREFIX accor

Fix pip install. Signed-off-by: Oliver Steffen <osteffen@...> --- .azurepipelines/templates/platform-build-run-steps.yml | 6 ++++++ .azurepipelines/templates/pr-gate-steps.yml | 6 ++++++ 2 files chang

Use the Python supplied by the container image. Signed-off-by: Oliver Steffen <osteffen@...> --- .azurepipelines/templates/platform-build-run-steps.yml | 1 + .azurepipelines/templates/pr-gate-steps.ym

Update CI, run all Linux (aka Ubuntu-GCC5) based jobs in custom containers. The container image provides the required compiler toolchains and Qemu for the supported architectures. These are then no lo

Remove clearing CR0.WP when marking the memory used for page table as read-only in the page table itself created by UefiPayloadEntry. This page table address is written to Cr3 after these protection s

Remove clearing CR0.WP when marking the memory used for page table as read-only in the page table itself created by DxeIpl. This page table address is written to Cr3 after these protection steps. Till

This patch is code refactoring and doesn't change any functionality. Remove mInternalCr3 in PiSmmCpuDxe pagetable related code. In previous code, mInternalCr3 is used to pass address of page table whi

This patch adds strnlen function wrapper that internally calls AsciiStrnLenS defined in BaseLib. Signed-off-by: Mateusz Mówka <mateusz.mowka@...> --- StdLib/Include/string.h | 11 +++++++++++ StdLib/Li

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3998 Certain OSes will complain if the ECAM config space is not reserved in the ACPI namespace. This change adds a function to reserve PNP motherb

Add NVME_ENABLE macro to control NvmExpressDxe driver. Cc: Guo Dong <guo.dong@...> Cc: Ray Ni <ray.ni@...> Cc: Sean Rhodes <sean@...> Cc: Gua Guo <gua.guo@...> Signed-off-by: Kavya <k.kavyax.sravanthi

From: Laszlo Ersek <lersek@...> Increase the maximum line length for debug messages. While log messages should be short, they can still get quite long, for example when printing device paths or config

Increase the maximum line length for debug messages. While log messages should be short, they can still get quite long, for example when printing device paths or config strings in HII routing. 512 cha

Ref:https://bugzilla.tianocore.org/show_bug.cgi?id=4000 Change flow to bus scan all root bridge instances even when any one root bridge meet bus resource OUT_OF_RESOURCE case. thus platform handler of

Reviewed-by: Liming Gao <gaoliming@...> > -----邮件原件----- > 发件人: Michael D Kinney <michael.d.kinney@...> > 发送时间: 2022年8月10日 12:38 > 收件人: devel@edk2.groups.io > 抄送: Liming Gao <gaoliming@...>; Zhiguang

This patch is code refactoring and doesn't change any functionality. Add a new IsShadowStack flag to identify whether current memory is shadow stack. Previous smm code logic regards a RO range as shad

Splited previos patch to two patches for different pkg. Dun Tan (2): MdeModulePkg/DxeIpl: Remove clearing CR0.WP when protecting pagetable UefiPayloadPkg: Remove clearing CR0.WP when protecting pageta

Changed IsShadowStack to mIsShadowStack. Updated the commit message to explain this code refactoring. Dun Tan (2): UefiCpuPkg/PiSmmCpuDxeSmm: Add a new mIsShadowStack flag UefiCpuPkg/PiSmmCpuDxeSmm: R

From: KasimX Liu <kasimx.liu@...> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4013 For the SMBIOS version can be update by UPL,we create the gUniversalPayloadSmbios3TableGuid HOB to store th