From: Ranbir Singh <Ranbir.Singh3@...> The return value stored in Status after call to SetDriveParameters is not made of any use thereafter and hence it remains as UNUSED. Assuming, this non-usage is

Add the new section for Secure Boot. Signed-off-by: Alexander Goncharov <chat@...> --- OvmfPkg/README | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/OvmfPkg/RE

As sbsa-ref board uses xhci to replace ehci, the DSDT is updated to match the platform xhci controller. This also removes previous ehci structure. Signed-off-by: Yuquan Wang <wangyuquan1236@...> Chang

This registers the non-discoverable XHCI for sbsa-ref. Signed-off-by: Yuquan Wang <wangyuquan1236@...> Change-Id: Iace5a04ea6087de6b0d855e84c90b4754a66594a --- .../SbsaQemuPlatformDxe/SbsaQemuPlatform

Backward-compatibility changes: This patch series removes the SmmCpuFeaturesReadSaveStateRegister and SmmCpuFeaturesWriteSaveStateRegister interface/function. SmmReadSaveState() and SmmWriteSaveState(

For replace function, when target Ffs and new ffs are with same size, the output file can not be generated successfully. This patch fixes this issue. Cc: Rebecca Cran <rebecca@...> Cc: Bob Feng <bob.c

1. FvLength not change issue; 2. FileSystemGuid align with File Size; Cc: Rebecca Cran <rebecca@...> Cc: Liming Gao <gaoliming@...> Cc: Bob Feng <bob.c.feng@...> Signed-off-by: Yuwei Chen <yuwei.chen@

Currently, Python FMMT tool does not support automatically select FMMTConf.ini file which saves GuidTool settings. This patch support this features. Cc: Rebecca Cran <rebecca@...> Cc: Liming Gao <gaol

Implement the SpeculationBarrier with implementations consisting of fence instruction which provides finer-grain memory orderings. Perform Data Barrier in RiscV: fence rw,rw Perform Instruction Barrie

N1 uses '0000' values which mean: Support for 4KB granule at stage 2 is identified in the ID_AA64MMFR0_EL1.TGran{4,16,64} field. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@...> --- ArmPkg/A

There is no point of having double spaces. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@...> --- ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c | 24 +++++++++++----------- 1 file changed, 12 inse

If cpu supports SVE or SME then display information of supported features. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@...> --- ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c | 344 +++++++++++++

Having two places with same formatting is error-prone. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@...> --- ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c | 2 +- 1 file changed, 1 insertion(+),

If system register is empty (value =3D=3D 0) then do not display informat= ion from it. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@...> --- ArmPkg/Application/ArmCpuInfo/ArmCpuInfo.c | 35 +

ID_AA64ZFR0_EL1 and ID_AA64SMFR0_EL1 system registers are needed for ArmCpuInfo application to show state of SVE/SME support. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@...> --- ArmPkg/Libr

This changeset was supposed to add SVE/SME information but got some updates to improve output of ArmCpuInfo application a bit too. Probably would need to definition of system registers for older toolc

It is hard to fit in 80 columns so let drop extra spaces and ID_AA64 prefix from system register names. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@...> --- ArmPkg/Application/ArmCpuInfo/Arm

First nibbles of DFR0/ISAR1/ISAR2/MMRF2/PFR0 system registers were read in wrong way -- second one was used instead. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@...> --- ArmPkg/Application/A

They are useful for those platforms where SMC SiP calls exist. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@...> --- ArmPkg/Include/IndustryStandard/ArmStdSmc.h | 9 +++++++++ 1 file changed,