REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4468=0D =0D This is a followup to the RFC that I sent to the edk2-devel list on the=0D 25th of May.=0D =0D In an attempt to make some incremental

Signed-off-by: Gerd Hoffmann <kraxel@...> --- CryptoPkg/Library/OpensslLib/openssl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/CryptoPkg/Library/OpensslLib/openssl b/CryptoPkg/Li

These patches helps to add new SMBIOS Tables (Type 16, 17, 19) and refactor SmbiosPlatformDxe. Minh Nguyen (4): JadePkg: Correct PCD names for SMBIOS Type 0 JadePkg: Leverage ArmPkg/Smbios (Type 0, 1,

These patches support NVMe Hot Plug feature for Ampere Altra and Ampere Altra Max. Minh Nguyen (2): AmpereAltraPkg: Add Hot Plug Slot Capable during PCIe port initialization AmpereAltraPkg: Change PCI

These patches help to improve PCIe core for Link training sequence and add logic to check PCIe card is present or not. One patch also removes unnecessary checks for PCIe Devmap mode. Minh Nguyen (2):

They are useful for those platforms where SMC SiP calls exist. Signed-off-by: Marcin Juszkiewicz <marcin.juszkiewicz@...> --- ArmPkg/Include/IndustryStandard/ArmStdSmc.h | 9 +++++++++ 1 file changed,

When ArmPkg's CpuDxe driver initializes, it attempts to sync the=0D GCD with the page table. However, unlike when the UefiCpuPkg's=0D CpuDxe initializes, the Arm version does not update the GCD=0D cap

This commit is code refinement to current smm pagetable generation code. Add a new GenSmmPageTable() API to create smm page table based on the PageTableMap() API in CpuPageTableLib. Caller only needs

Today the delay is 10us but the QSP simulates the multiprocessor by dividing time into segments and serializing processors within a segment. The length of the segment is configurable and Simics open b

Add 2 drivers (IntelVTdCorePei, IntelVTdCoreDxe) for pre-boot DMA protection feature. Signed-off-by: Sheng Wei <w.sheng@...> Cc: Ray Ni <ray.ni@...> Cc: Rangasai V Chaganty <rangasai.v.chaganty@...> C

This commit is code refinement to current smm runtime InitPaging() page table update code. In InitPaging(), if PcdCpuSmmProfileEnable is TRUE, use ConvertMemoryPageAttributes() API to map the range in

Sort mProtectionMemRange in InitProtectedMemRange() when ReadyToLock. Signed-off-by: Dun Tan <dun.tan@...> Cc: Eric Dong <eric.dong@...> Cc: Ray Ni <ray.ni@...> Cc: Rahul Kumar <rahul1.kumar@...> Cc:

Remove unnecessary function SetNotPresentPage(). We can directly use ConvertMemoryPageAttributes to set a range to non-present. Signed-off-by: Dun Tan <dun.tan@...> Cc: Eric Dong <eric.dong@...> Cc: R

Sort mSmmCpuSmramRanges after get the SMRAM info in FindSmramInfo() function. Signed-off-by: Dun Tan <dun.tan@...> Cc: Eric Dong <eric.dong@...> Cc: Ray Ni <ray.ni@...> Cc: Rahul Kumar <rahul1.kumar@.

Use GenSmmPageTable() to create both IA32 and X64 Smm S3 page table. Then Gen4GPageTable() is not used any more and delete it. Signed-off-by: Dun Tan <dun.tan@...> Cc: Eric Dong <eric.dong@...> Cc: Ra

Extern mSmmShadowStackSize in PiSmmCpuDxeSmm.h and remove extern for mSmmShadowStackSize in c files to simplify code. Signed-off-by: Dun Tan <dun.tan@...> Cc: Eric Dong <eric.dong@...> Cc: Ray Ni <ray

Clear CR0.WP before modify smm page table. Currently, there is an assumption that smm pagetable is always RW before ReadyToLock. However, when AMD SEV is enabled, FvbServicesSmm driver calls MemEncryp

Add two functions to disable/enable CR0.WP. These two unctions will also be used in later commits. This commit doesn't change any functionality. Signed-off-by: Dun Tan <dun.tan@...> Cc: Eric Dong <eri

Does not yet pass CI, mostly IA32 build failures due to compiler intrinsics missing. Openssl configuration has been reorganized, all generated files are in a single subtree now, and the script to conf

Hello Maciej: This is regarding an inquiry about usage of Load File 2 Protocol in HTTP Boot. From the UEFI Specification refence below the driver supposed to install Load File 2 Protocol to get the HT