Change xor to Xor to avoid C++ reserved work name collisions when building with C++ compilers. NOTE: This is a non-backwards compatible change to Tpm12.h and Tmp20.h. And consumers of these include fi

Update Tpm12.h and Tpm20.h and not use c++ reserved keywords operator and xor in C structures to support use of these include files when building with a C++ compiler. * Change operator -> Operator * C

Update Tpm12.h and Tpm20.h and not use c++ reserved keywords operator and xor in C structures to support use of these include files when building with a C++ compiler. Update SecurityPkg Tpm2CommandLib

Reminder: Tools, CI, Code base construction meeting series When: Monday, May 29, 2023 4:30pm to 5:30pm (UTC-07:00) America/Los Angeles Where: https://github.com/tianocore/edk2/discussions/2614 View Ev

Hello all, Regarding https://github.com/tianocore/edk2/pull/4442 could someone please explain to me: - what went wrong, - where to find the button to push to resubmit this PR to CI Thanks, Ard.

Update the TF-A binaries to have FEAT_FGT support. This support was merged into TF-A: https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/19459 This allows SBSA Reference Platform to boot L

Customize PeiReportFvLib library for AMD platforms by adding below changes. Installs Advanced Security FV. Adds facility to install FV above 4GB address space. Cc: Abner Chang <abner.chang@...> Signed

From: Abdul Lateef Attar <AbdulLateef.Attar@...> Implements PCI hotplug init protocol. Adds resources padding based on PCD values. Cc: Abner Chang <abner.chang@...> Signed-off-by: Abdul Lateef Attar <

Normally, DXE driver would add device resource to GCD before start using. But some key resources such as uart, flash base address are being accessing directly in some core modules. Those resources sho

The RISC-V version of the DXE IPL does not implement setting the stack NX, so before switching to an implementation that will ASSERT() on the missing support, drop the PCD setting that enables it. Sig

The GIC v2 base addresses can be 64bit, don't limit to 32 on 64bit machines. Signed-off-by: Neil Jones <neil.jones@...> --- ArmPkg/Drivers/ArmGic/GicV2/ArmGicV2Dxe.c | 4 ++-- 1 file changed, 2 inserti

Not needed any more, SMM + 64-bit PEI + S3 suspend works now. While being at it also remove it from Bhyve (where it is dead code). Fixed by commits: - 8bd2028f9ac3 ("MdeModulePkg: Supporting S3 in 64b

Flip the default for IO address space reservations for PCI(e) bridges and root ports with hotplug support from TRUE to FALSE. PCI(e) bridges will still get IO address space assigned in case: (a) Downs

Gerd Hoffmann (3): OvmfPkg/PlatformInitLib: check PcdUse1GPageTable OvmfPkg/OvmfPkgIa32X64: enable 1G pages OvmfPkg/MicrovmX64: enable 1G pages OvmfPkg/Microvm/MicrovmX64.dsc | 3 +++ OvmfPkg/OvmfPkgIa

Now that both PEI and DXE can deal with memory being mapped non-execute by default, update the early mapping code to create non-execute mappings for all of DRAM. While at it, map the NOR flash read-on

Add ArmCpuDxe and its dependencies to the APRIORI DXE section, and use a rule override to emit the executable images in a way that permits them to execute in place from the firmware volume. This allow

Introduce a new bit in the NX memory protection policy PCD mask that specifies that the platform enters DXE with all unused and all non-code regions mapped with non-execute permissions. This removes t

Before handing over to the DXE core, iterate over all known FFS files and find the ones that can execute in place. These files are then relocated in place and mapped with restricted permissions, allow

In the image loader, check whether an image has already been relocated to the address from which it is being loaded. This is not something that can happen by accident, and so we can assume that this m

Expose the EDK2 specific memory mapped FV protocol in addition to the firmware volume protocol defined by PI when the underlying firmware volume block protocol informs us that the firmware volume is m