Thank for that, it looks good for me now. Thanks, Gua

I have removed push limitation in Edk2 repo. Please try again. Thanks Liming 发件人: Guo, Gua <gua.guo@...> 发送时间: 2023年5月29日 8:43 收件人: devel@edk2.groups.io; Gao, Liming <gaoliming@...> 主题: RE: [edk2-deve

Hi, all The tag edk2-stable202305 has been created. https://github.com/tianocore/edk2/releases/tag/edk2-stable202305 git clone -b edk2-stable202305 https://github.com/tianocore/edk2.git The tag edk2-s

Reminder: Tools, CI, Code base construction meeting series When: Monday, May 29, 2023 4:30pm to 5:30pm (UTC-07:00) America/Los Angeles Where: https://github.com/tianocore/edk2/discussions/2614 View Ev

Move initialization of local variable structure from declaration to statements to fix VS2015x86 build break. Cc: Ard Biesheuvel <ardb+tianocore@...> Cc: Jiewen Yao <jiewen.yao@...> Cc: Jordan Justen <

From: Yong Li <yong.li@...> Impelement the SpeculationBarrier with implementations consisting of fence instruction which provides finer-grain memory orderings. Data Barrier: fence rw,rw Instruction Ba

The timer compare register is 64-bit so simplifying the delay function. Signed-off-by: Tuan Phan <tphan@...> --- MdePkg/Include/Register/RiscV64/RiscVImpl.h | 1 - .../BaseRiscV64CpuTimerLib/CpuTimerLi

SbiSetTimer expects core tick value. Signed-off-by: Tuan Phan <tphan@...> --- .../CpuTimerDxeRiscV64/CpuTimerDxeRiscV64.inf | 3 +++ UefiCpuPkg/CpuTimerDxeRiscV64/Timer.c | 26 ++++++++++++++++--- UefiC

Normally, DXE driver would add device resource to GCD before start using. But some key resources such as uart, flash base address are being accessing directly in some core modules. Those resources sho

The flash base address can be added to GCD before this driver run. So only add it if it has not been done. Signed-off-by: Tuan Phan <tphan@...> Reviewed-by: Andrei Warkentin <andrei.warkentin@...> ---

The size should be for single region, not the whole firmware FD. Signed-off-by: Tuan Phan <tphan@...> Reviewed-by: Andrei Warkentin <andrei.warkentin@...> --- .../Library/VirtNorFlashPlatformLib/VirtN

MMU now is initialized in CpuDxe. There is no point to set satp to bare mode as that should be the default mode when booting edk2. Signed-off-by: Tuan Phan <tphan@...> Reviewed-by: Andrei Warkentin <a

During CpuDxe initialization, MMU will be setup with the highest mode that HW supports. Signed-off-by: Tuan Phan <tphan@...> Reviewed-by: Andrei Warkentin <andrei.warkentin@...> --- UefiCpuPkg/CpuDxeR

The satp mode bits shift is used cross modules. It should be defined in one place. Signed-off-by: Tuan Phan <tphan@...> Reviewed-by: Andrei Warkentin <andrei.warkentin@...> --- MdePkg/Include/Register

Add an API to retrieve satp register value. Signed-off-by: Tuan Phan <tphan@...> Reviewed-by: Andrei Warkentin <andrei.warkentin@...> --- MdePkg/Include/Library/BaseLib.h | 5 +++++ MdePkg/Library/Base

RISC-V: Add MMU support This series adds MMU support for RISC-V. Only SV39/48/57 modes are supported and tested. The MMU is required to support setting page attribute which is the first basic step to

When the AARCH64 CpuDxe attempts to SyncCacheConfig() with the GCD, it collects the page attributes as: EntryAttribute =3D Entry & TT_ATTR_INDX_MASK However, TT_ATTR_INDX_MASK only masks the cacheabil

From: Gua Guo <gua.guo@...> Ideally behavior is like below order that can support one local build machine, clone multiple Edk2, some of edk2 repo use old tag and some of edk2 repo use new tag, they ca

Following procedures are perf-logged: * SmmReadyToBootHandler * SmmReadyToLockHandler * SmmEndOfDxeHandler * SmmEntryPoint (It's the main routine run in BSP when SMI happens.) * SmiManage Cc: Jian J W

The patch adds perf-logging for the following potential time-consuming BSP procedures: * PiCpuSmmEntry - SmmRelocateBases * ExecuteFirstSmiInit * BSPHandler - SmmWaitForApArrival - PerformRemainingTas