MP procedures are those procedures that run in every CPU thread. The EDKII perf infra is not MP safe so it doesn't support to be called from those MP procedures. The patch adds SMM MP perf-logging sup

Ray Ni (3): UefiCpuPkg/CpuSmm: Add perf-logging for time-consuming BSP procedures UefiCpuPkg/CpuSmm: Add perf-logging for MP procedures MdeModulePkg/SmmCore: Add perf-logging for time-consuming proced

Ray Ni (6): SimicsOpenBoardPkg: Remove un-used PlatformBootManagerLib SimicsOpenBoardPkg: Remove logic that loads variable from disk file SimicsOpenBoardPkg: Enable serial terminal MinPlatform/build_b

Add two functions to disable/enable CR0.WP. These two unctions will also be used in later commits. This commit doesn't change any functionality. Signed-off-by: Dun Tan <dun.tan@...> Cc: Eric Dong <eri

From: Abdul Lateef Attar <AbdulLateef.Attar@...> Implements PCI hotplug init protocol. Adds resources padding based on PCD values. Cc: Abner Chang <abner.chang@...> Signed-off-by: Abdul Lateef Attar <

From: Abdul Lateef Attar <AbdulLateef.Attar@...> Implements PCI hotplug init protocol. Adds resources padding based on PCD values. Cc: Abner Chang <abner.chang@...> Signed-off-by: Abdul Lateef Attar <

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4468=0D =0D This is a proof-of-concept RFC that implements a PEI phase PPI to manage=0D memory permission attributes, and wires it up to the PEI i

Add a notification callback to the PEI core to grab a reference to the memory attributes PPI as soon as it is registered, and use it in the image loader to set restricted memory permissions after load

Google Test, and CPP, has more keywords C uses. Tpm12.h and Tpm20.h have references to struct names that are `operator` and `xor`, both of which trigger build errors because they conflict with CPP’s k

The newly released TF-A v2.9 contains a fix for an issue that has been affecting some Raspberry Pi 3 users, when trying to issue a reboot with some types of SD cards (See: pftf/RPi3#17, pftf/RPi3#24).

Check whenever flash is actually writable. Signed-off-by: Gerd Hoffmann <kraxel@...> --- OvmfPkg/QemuFlashFvbServicesRuntimeDxe/QemuFlash.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 dele

Kvmtool allows guest VMs to be launched with or without a CFI flash device. The guest hardware configuration can be seen in the device tree that Kvmtool hands off to the guest firmware. Therefore, add

Gerd Hoffmann (3): OvmfPkg/PlatformInitLib: check PcdUse1GPageTable OvmfPkg/OvmfPkgIa32X64: enable 1G pages OvmfPkg/MicrovmX64: enable 1G pages OvmfPkg/Microvm/MicrovmX64.dsc | 3 +++ OvmfPkg/OvmfPkgIa

Flip the default for IO address space reservations for PCI(e) bridges and root ports with hotplug support from TRUE to FALSE. PCI(e) bridges will still get IO address space assigned in case: (a) Downs

The flash base address can be added to GCD before this driver run. So only add it if it has not been done. Signed-off-by: Tuan Phan <tphan@...> --- OvmfPkg/VirtNorFlashDxe/VirtNorFlashDxe.c | 25 +++++

Now that we have a generic method to manage memory permissions using a PPI, we can switch to the generic version of the DXE handoff code in DxeIpl, and drop the ARM specific version. Signed-off-by: Ar

If the associated PCD is set to TRUE, use the memory attribute PPI to remap the stack non-executable. This provides a generic method for doing so, which will be used by ARM and AArch64 as well once th

The Risc-V and LoongArch specific versions of the DXE core handoff code in DxeIpl are essentially copies of the EBC version (modulo the copyright in the header and some debug prints in the code). In p

Implement the newly defined PPI that permits the PEI core and DXE IPL to manage memory permissions on ranges of DRAM, for doing things like mapping the stack non-executable, or granting executable per

Define a PPI interface that may be used by the PEI core or other PEIMs to manage permissions on memory ranges. This is primarily intended for restricting permissions to what is actually needed for cor