In order to allow booting with the MMU and caches enabled really early, we need to ensure that the code that populates the page tables can access those page tables with the statically defined ID map a

To substantially reduce the amount of processing that takes place with the MMU and caches off, implemnt a version of ArmPlatformLib specific for QEMU/mach-virt in AArch64 mode that carries a staticall

Permit the use of this library with the MMU and caches already enabled. This removes the need for any cache maintenance for coherency, and is generally better for robustness and performance, especiall

Some platforms may set up a preliminary ID map in flash and enter EFI with the MMU and caches enabled, as this removes a lot of the complexity around cache coherency. Let's take this into account, and

When executing at EL1, disabling and re-enabling the MMU every time we need to replace a live translation entry is slightly problematic, given that memory accesses performed with the MMU off have non-

We currently do a substantial amount of processing before enabling the MMU and caches, which is bad for performance, but also risky, as it requires cache coherency to be managed by hand. This also mea

Drop the optimization that replaces table entries with block entries and frees the page tables in the subhierarchy that is being replaced. This rarely occurs in practice anyway, and will require more

Add a new device entry in the SSDT ACPI table to describe the serial port used as the debug port. On the Neoverse reference design platforms, the UART0 port of the SoC is used as the debug port. Signe

Patch 433b5b1b0f7f ("Platform/Sgi: Route logs to different sets of consoles") assigns different address for the console UART and the debug UART. Correspondingly, update the SPCR and SSDT ACPI tables t

This problem has been fixed in edk2 20b292d0cdf7dce58d824fdf9ab1613c2a1ad2ec * BaseTools: Fix the issue caused by tostring() removal on Py39 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3136 Py

From: Pierre Gondois <pierre.gondois@...> Bugzilla: Bug 3971 (https://bugzilla.tianocore.org/show_bug.cgi?id=3D3971= ) Add support for a Deterministic Random Bits Generator (Drbg). The specifications

From: Pierre Gondois <Pierre.Gondois@...> BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3970 The FIPS PUB 197: "Advanced Encryption Standard (AES)" details the AES algorithm. Add a library to a

Some platfoms may want to modify the ACPI table created. Add support for protocol that can provide an alternative implementation. Signed-off-by: Jeff Brasen <jbrasen@...> --- DynamicTablesPkg/DynamicT

Add support for selecting to use index or segment number as UID and name. This allows the path of the nodes to be well known. Signed-off-by: Jeff Brasen <jbrasen@...> --- DynamicTablesPkg/DynamicTable

From: Jason1 Lin <jason1.lin@...> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3959 As per FIT BIOS Specification 1.2 Rules, the size bytes (3 bytes) / reserved byte (1 byte) / CheckSum byte

From: Jason1 Lin <jason1.lin@...> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3958 FitGen tool exists lots of typecasting and pointer usage. This code change is used to reduce these in FillF

From: Jason1 Lin <jason1.lin@...> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3958 Within current FitGen tool there had limitation only allow one S-ACM to generate the Type 2 entry. This cod

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3923 According to definition of PcdTpm2HashMask, the mask reflects the PCR banks which need to be extended. In the Tcg2Pei SyncPcrAllocationsAndPcrMa

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3923 According to definition of PcdTpm2HashMask, the mask reflects the PCR banks which need to be extended. In the Tcg2Pei SyncPcrAllocationsAndPcrMa

Nice find! How did you spot this? Through inspection? Or due to an actual failure? Reviewed-by: Ard Biesheuvel <ardb@...> I'll go and queue this up, thanks.