Code refinement to the code to set page table as RO in DxeIpl module. Set all page table pools as ReadOnly by calling PageTableMap() in CpuPageTableLib multiple times instead of searching each page ta

Modify CreateIdentityMappingPageTables() to create page table based on CpuPageTableLib in DxeIpl module. This function can be used to create both IA32 PAE paging and long mode 4-level, 5-level paging

Add CpuPageTableLib instance required by DxeIpl in EmulatorPkg.dsc. Signed-off-by: Dun Tan <dun.tan@...> Cc: Andrew Fish <afish@...> Cc: Ray Ni <ray.ni@...> --- EmulatorPkg/EmulatorPkg.dsc | 3 ++- 1 f

The CPU exception handler library code was rewritten at some point to populate the vector code templates with absolute references at runtime, given that the XCODE linker does not permit absolute refer

Cc: Ard Biesheuvel <ardb+tianocore@...> Cc: Jiewen Yao <jiewen.yao@...> Cc: Jordan Justen <jordan.l.justen@...> Cc: Gerd Hoffmann <kraxel@...> Cc: Sunil V L <sunilvl@...> Cc: Andrei Warkentin <andrei.

Adding code to support Cache Management Operations (CMO) defined by RV spec https://github.com/riscv/riscv-CMOs Notes: 1. CMO only supports block based Operations. Meaning complete cache flush/invd/cl

Current implementation for cache management (instruction/data flush/invd) depends on fence.i instruction. All RV platforms may not use the same method for cache management. Instead RV defines CMO Cach

In IA32 code, remove the duplicated code to enable NX. In the previous patch, IA32 code also uses the new CreateIdentityMappingPageTables() to create PAE page table. This function calls EnableExecuteD

Add CpuPageTableLib instance required by DxeIpl in QemuFspPkg.dsc of IntelFsp2Pkg. Signed-off-by: Dun Tan <dun.tan@...> Reviewed-by: Chasel Chiu <chasel.chiu@...> Cc: Nate DeSimone <nathaniel.l.desimo

Ray Ni (6): MdePkg: Add TME-MK related CPUID and MSR definitions UefiCpuPkg/MtrrTest: Only claim CPUID max leaf as 1 UefiCpuPkg/MtrrLib: Substract TME-MK KEY_ID_BITS from CPU max PA UefiCpuPkg/CpuDxe:

This library is no longer used or needed, so let's remove it. Signed-off-by: Ard Biesheuvel <ardb@...> Reviewed-by: Ray Ni <ray.ni@...> --- UefiCpuPkg/Library/CpuExceptionHandlerLib/Xcode5SecPeiCpuExc

The generic and XCODE5 versions of this library are now identical, so drop the special case. The library will be removed entirely in a subsequent patch. Signed-off-by: Ard Biesheuvel <ardb@...> Acked-

We rely on PIE executables to get the codegen that is suitable for PE/COFF conversion where the resulting executables can be loaded anywhere in the address space. However, ELF linkers may default to d

Recent versions of the XCODE linker can be instructed to permit text relocations, so we no longer have to work around this, which is especially nice as our workaround assumes that the .text section is

Currently, we use the non-Xcode5 version of ExceptionHandlerAsm.nasm only for the SEC and PEI phases, and this version was not compatible with the XCODE or LLD linkers, which do not permit absolute re

This patch series provides some fixes around AP creation: - An erratum on AMD hardware requires that a VMSA not be aligned on a 2MB boundary. To work around this issue, allocate 2 pages of memory and

Code refinement to the code to set page table as RO in DxeIpl module. Set all page table pools as ReadOnly by calling PageTableMap() in CpuPageTableLib multiple times instead of searching each page ta

Add UefiCpuPkg/UefiCpuPkg.dec in MdeModulePkg.ci.yaml to pass DependencyCheck since DxeIpl in MdeModulePkg needs to consume CpuPageTableLib in UefiCpuPkg. Signed-off-by: Dun Tan <dun.tan@...> Cc: Limi

Modify CreateIdentityMappingPageTables() to create page table based on CpuPageTableLib in DxeIpl module. This function can be used to create both IA32 PAE paging and long mode 4-level, 5-level paging

In IA32 code, remove the duplicated code to enable NX. In the previous patch, IA32 code also uses the new CreateIdentityMappingPageTables() to create PAE page table. This function calls EnableExecuteD