Why use PY 3.6? Even PY 3.8 is about to be deprecated by Python community.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3779 This comit fixes the Python interpreter build issues with GCC 32 bit compiler tool chain. The changes are needed in StdLibC as given below * Ad

Hello everyone, I have been somewhat successful in implementing Rust stdio for UEFI. This means it is now possible to do things like this: ```rust let s = 10; println!("ConOut: {}", s); eprintl!("StdE

Reminder: TianoCore Bug Triage - APAC / NAMO When: 06/28/2022 6:30pm to 7:30pm (UTC-07:00) America/Los Angeles Where: https://teams.microsoft.com/l/meetup-join/19%3ameeting_OTk1YzJhN2UtOGQwNi00NjY4LWE

Tools, CI, Code base construction meeting series When: 06/27/2022 4:30pm to 5:30pm (UTC-07:00) America/Los Angeles Where: https://github.com/tianocore/edk2/discussions/2614 View Event Description: Tia

Add debug messages to make it easier to verify PlatformSecLib is passing the data properly. Cc: Eric Dong <eric.dong@...> Cc: Ray Ni <ray.ni@...> Cc: Rahul Kumar <rahul1.kumar@...> Cc: Debkumar De <de

(Replying under Mike for devel visibility) Felix, Why coverity? I feel like we could run something akin to LLVM's clang-tidy + scan-build; it's open source (transparent *and* we can improve it or add

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3957 The reserved IDT table size in SecCore is too small for X64. Changed the ty= pe of IdtTable in SEC_IDT_TABLE from UINT64 to IA32_IDT_GATE_DESC

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3957 The reserved IDT table size in SecCore is too small for X64. Changed the ty= pe of IdtTable in SEC_IDT_TABLE from UINT64 to IA32_IDT_GATE_DESC

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3957 The reserved IDT table size in SecCore is too small for X64. Changed the type of IdtTable in SEC_IDT_TABLE from UINT64 to IA32_IDT_GATE_DESCRIPT

VTd Queued Invalidation IOTLB descriptor need to use CAP_REG.DWD and CAP_REG.DRD. Queued Invalidation descriptor is a 128 bits value. Register-based invalidation interface supported by hardware implem

Extend the SMBIOS support for RD-N2-Cfg2 platform which is a quad-chip variant of the RD-N2 platform. Most the SMBIOS information is shared with the RD-N2 platform except for the number of the CPUs su

From: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@...> The RD-N2-Cfg2 platform is a quad-chip variant of the RD-N2 platform. Each chip has reduced core count of four Neoverse N2 CPUs when com

From: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@...> Add MADT, DSDT and SRAT ACPI tables that are specific for RD-N2-Cfg2 platform. The rest of the ACPI tables are reused from the shared AC

From: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@...> The RD-N2-Cfg2 platform is a quad-chip variant of the RD-N2 platform but with reduced core count, that is, each instance of the RD-N2 ch

From: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@...> Add a new PCD to define the maximum number of address bits used for addresses within a chip. The value of this PCD can be used to derive

Update the RD-N2-Cfg1 platform specific ACPI tables to ACPI version v6.4. Significant changes introduced are to add SPE overflow interrupt number field to GICC structure of MADT table and adding cache

Update the RD-N2 platform specific ACPI tables to ACPI version v6.4. Significant changes introduced are to add SPE overflow interrupt number field to GICC structure of MADT table and adding cache ID f

Update the RD-V1-MC platform specific ACPI tables to ACPI version v6.4. Significant changes introduced are to add SPE overflow interrupt number field to GICC structure of MADT table and adding cache I

Update the RD-V1 platform specific ACPI tables to ACPI version v6.4. Significant changes introduced are to add SPE overflow interrupt number field to GICC structure of MADT table and adding cache ID f