From: Min M Xu <min.m.xu@...> TdxValidateCfv validates the integrity of Configuration FV (CFV). It was implemented in PeilessStartupLib which is included in IntelTdxX64. In OvmfPkgX64 we should valida

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3962 Two SMM variables (mSmrrSupported & mSmmFeatureControlSupported) are global variables, they control whether the SMRR and SMM Feature Control MS

Hi All, Intel is pleased to announce that Alder Lake FSP is now available at https://github.com/intel/FSP. With Best Regards, Nate

Reviewed-by: Liming Gao <gaoliming@...> > -----邮件原件----- > 发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Miki Shindo > 发送时间: 2022年6月23日 11:40 > 收件人: devel@edk2.groups.io > 抄送: Michael D Kinney <

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3788 Removed an outdated reference to py2.7 in the Windows systems wiki page and replaced it with the py3.7 to align with the updated build instruct

Changes since V1: - Rebased on top of latest master branch. The DSDT ACPI table used for Neoverse reference design platforms include the _LPI control method for the kernel to enter idle states. This p

RD-N2-Cfg1 platform supports only the platform co-ordinated LPI. So fix the LPI Level ID value accordingly. Additionally, as this platform does not support residency counter, clear the residency count

RD-N2 platform supports only the platform co-ordinated LPI. So fix the LPI Level ID value accordingly. Additionally, as this platform does not support residency counter, clear the residency counter fr

RD-V1-MC platform supports only the platform co-ordinated LPI. So fix the LPI Level ID value accordingly. Additionally, as this platform does not support residency counter, clear the residency counter

RD-V1 platform supports only the platform co-ordinated LPI. So fix the LPI Level ID value accordingly. Additionally, as this platform does not support residency counter, clear the residency counter fr

RD-N1-Edge-X2 platform supports only the platform co-ordinated LPI. So fix the LPI Level ID value accordingly. Additionally, as this platform does not support residency counter, clear the residency co

RD-N1-Edge platform supports only the platform co-ordinated LPI. So fix the LPI Level ID value accordingly. Additionally, as this platform does not support residency counter, clear the residency count

SGI-575 platform supports only the platform co-ordinated LPI. So fix the LPI Level ID value accordingly. Additionally, as this platform does not support residency counter, clear the residency counter

SBBR requires platforms to provide the _STA ACPI method for each defined device. This patch implements a stub method that always indicates devices are present and functional. Cc: Ard Biesheuvel <ardb+

From: James Lu <james.lu@...> REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3967 Add macros to decide modules built into UPL.elf. Macro list: - GENERIC_MEMORY_TEST_ENABLE: GenericMemoryTestDxe

RD-N2-Cfg2 platform is the multichip variant of the RD-N2 platform. The platform is based on 4xMP1 Neoverse N2 CPUs per chip, CMN-700 interconnect 6x6 mesh, multiple AXI expansion ports for I/O Cohere

Changes since V3: - Addressed comments from Pierre Gondois - Rebased on top of latest master branch Changes since V2: - Rebased on top of latest master branch - Update PPTT table with unique cache ID

I am not python expert. Above statement might be interpreted as: 1. (upld_info.hdr.Attribute |= 1) if BuildTarget == "DEBUG" else 0 2. upld_info_hdr.Attribute |= (1 if BuildTarget == "DEBUG" else 0) A

Why use PY 3.6? Even PY 3.8 is about to be deprecated by Python community.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3779 This comit fixes the Python interpreter build issues with GCC 32 bit compiler tool chain. The changes are needed in StdLibC as given below * Ad