Currently, we rely on the logic in DXE IPL to create new page tables from scratch when executing in X64 mode, which means that we run with the initial page tables all throughout PEI, and never enable

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3966 This change updated the default value of TPM device subclass PCD to `0x010E0000` in order to match the definition of EFI_PERIPHERAL_TPM from

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3966 This change introduces a new peripheral subclass definition from PI specification v1.8. The new subclass definition will cover system reboot

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3794 This change introduces a new error code definitions under Host Software class according to PI specification v1.8. The new error code definiti

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3794 REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3966 This v2 series is a follow up of previously submitted patches: https://edk2.groups.io/

The DEBUG print that outputs the base and size of the page table allocation always prints 0x0 for the size, given that BufferSize will be updated by PageTableMap () and contain the unused allocation o

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4468=0D =0D Take a step towards enabling a generic approach to manage memory=0D permissions in PEI, by wiring up the existing IA32 page table crea

Hi all, We found an issue a while back on ARM systems, where the Standalone MM drivers with Depex specified will run into a hang when TFA hands off to Standalone MM core. (https://bugzilla.tianocore.o

From: Patrick Henz <patrick.henz@...> REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2948 Timeouts in the XhciDxe driver are taking longer than expected due to the timeout loops not accounting for

TianoCore Community Meeting EMEA/NAMO When: Thursday, June 8, 2023 8:00am to 9:00am (UTC-07:00) America/Los Angeles Where: Microsoft Teams meeting Join on your computer or mobile app Click here to joi

Reminder: TianoCore Community Meeting EMEA/NAMO When: Thursday, June 8, 2023 8:00am to 9:00am (UTC-07:00) America/Los Angeles Where: Microsoft Teams meeting Join on your computer or mobile app Click h

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3394 The function MtrrLibInitializeMtrrMask is a private function in MtrrLib.c from UefiCpuPkg, and it can be replace with new API GetMaxPlatformAdd

Add StandaloneMmIplPei IA32/X64 driver at PEI stage. FSP will use this driver to load Standalone MM code to dispatch other Standalone MM drivers. And this is the 1st patch to implement the entrypoint

From: Ranbir Singh <Ranbir.Singh3@...> The return value stored in Status after call to SetDriveParameters is not made of any use thereafter and hence it remains as UNUSED. Assuming, this non-usage is

From: Ranbir Singh <Ranbir.Singh3@...> Line number 365 does contain a typecast with UINT32, but it is after all the operations (16-bit left shift followed by OR'ing) are over. To avoid any SIGN_EXTENS

Remove RO and NX protection when unset guard page. When UnsetGuardPage(), remove all the memory attribute protection for guarded page. Signed-off-by: Dun Tan <dun.tan@...> Cc: Liming Gao <gaoliming@..

Remove code that apply AddressEncMask to non-leaf entry when split smm page table by MemEncryptSevLib. In FvbServicesSmm driver, it calls MemEncryptSevClearMmioPageEncMask to clear AddressEncMask bit

In ConvertMemoryPageAttributes() function, when clear RP for a specific range [BaseAddress, BaseAddress + Length], it means to set the present bit to 1 and assign default value for other attributes in

In PiSmmCpuDxeSmm code, SetMemMapAttributes() marks memory ranges in SmmMemoryAttributesTable to RO/NX. There may exist non-present range in these memory ranges. Set other attributes for a non-present

Simplify the ConvertMemoryPageAttributes API to convert paging attribute by CpuPageTableLib. In the new API, it calls PageTableMap() to update the page attributes of a memory range. With the PageTable