REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 RiscVVirt is created to support EDK2 for RISC-V qemu virt machine platform. Add maintainer entries. Cc: Andrew Fish <afish@...> Cc: Leif Lindho

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add infrastructure files to build edk2 for RISC-V qemu virt machine. - It follows PEI less design. - EDK2 for qemu virt is booted in S-mode as

Add the SEC module for RISC-V Qemu virt machine support. It uses the PEI less design. Cc: Ard Biesheuvel <ardb+tianocore@...> Cc: Jiewen Yao <jiewen.yao@...> Cc: Jordan Justen <jordan.l.justen@...> Cc

Add PciCpuIo2Dxe driver to implement EFI_CPU_IO2_PROTOCOL to add the translation for IO access. This is copied from ArmPciCpuIo2Dxe driver. Cc: Ard Biesheuvel <ardb+tianocore@...> Cc: Jiewen Yao <jiew

Qemu NOR flash driver needs this library. Add this library for RISC-V leveraged from SbsaQemu. Cc: Ard Biesheuvel <ardb+tianocore@...> Cc: Jiewen Yao <jiewen.yao@...> Cc: Jordan Justen <jordan.l.juste

RISC-V Qemu virt uses SBI calls to implement the reset. Add the base class library. Cc: Ard Biesheuvel <ardb+tianocore@...> Cc: Jiewen Yao <jiewen.yao@...> Cc: Jordan Justen <jordan.l.justen@...> Cc:

Add the PrePiHobListPointerLib required for RISC-V Qemu Virt machine since it follows PEIless design. Cc: Ard Biesheuvel <ardb+tianocore@...> Cc: Jiewen Yao <jiewen.yao@...> Cc: Jordan Justen <jordan.

RISC-V Qemu Virt platfform needs the PlatformBootManagerLib similar to the one in ArmVirtPlatform. Add the library in OvmfPkg/RiscVVirt leveraging the one from Arm. Cc: Ard Biesheuvel <ardb+tianocore@

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 PlatformHasAcpiDtDxe is required by other architectures also. Hence, it is moved to OvmfPkg. So, update the consumers of this module with the n

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 This module is required by other architectures like RISC-V. Hence, move this to OvmfPkg. Cc: Ard Biesheuvel <ardb+tianocore@...> Cc: Jiewen Yao

This PCD is required to be enabled so that PrePiLib can be used in RISC-V. Cc: Leif Lindholm <quic_llindhol@...> Cc: Ard Biesheuvel <ardb+tianocore@...> Cc: Abner Chang <abner.chang@...> Cc: Daniel Sc

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 RISC-V register names do not follow the EDK2 formatting. So, add it to ignore list for now. Cc: Eric Dong <eric.dong@...> Cc: Ray Ni <ray.ni@..

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVTimerLib Cc: Eric Dong <eric.dong@...> Cc: Ray Ni <ray.ni@..

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 This is copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Universal/CpuDxe Cc: Eric Dong <eric.dong@...> Cc: Ray Ni <ray.ni@...> Cc: Rahul

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add Cpu Exception Handler library for RISC-V. This is copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library/RiscVExceptionLib Cc: Eric

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 This DXE module initializes the timer interrupt handler and installs the Arch Timer protocol. Cc: Eric Dong <eric.dong@...> Cc: Ray Ni <ray.ni@

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 RISC-V UEFI based platforms need to support RISCV_EFI_BOOT_PROTOCOL. Add this protocol GUID definition and the header file required. Cc: Eric D

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 This library is required to make SBI ecalls from the S-mode EDK2. This is mostly copied from edk2-platforms/Silicon/RISC-V/ProcessorPkg/Library

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Few of the basic helper functions required for any RISC-V CPU were added in edk2-platforms. To support qemu virt, they need to be added in Base

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4076 Add register definitions and access routines for RISC-V. These headers are leveraged from opensbi repo. Cc: Daniel Schaefer <git@...> Cc: Micha