[PATCH v8 07/32] OvmfPkg/ResetVector: pre-validate the data pages used in SEC phase


Brijesh Singh
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3275

An SEV-SNP guest requires that private memory (aka pages mapped encrypted)
must be validated before being accessed.

The validation process consist of the following sequence:

1) Set the memory encryption attribute in the page table (aka C-bit).
Note: If the processor is in non-PAE mode, then all the memory accesses
are considered private.
2) Add the memory range as private in the RMP table. This can be performed
using the Page State Change VMGEXIT defined in the GHCB specification.
3) Use the PVALIDATE instruction to set the Validated Bit in the RMP table.

During the guest creation time, the VMM encrypts the OVMF_CODE.fd using
the SEV-SNP firmware provided LAUNCH_UPDATE_DATA command. In addition to
encrypting the content, the command also validates the memory region.
This allows us to execute the code without going through the validation
sequence.

During execution, the reset vector need to access some data pages
(such as page tables, SevESWorkarea, Sec stack). The data pages are
accessed as private memory. The data pages are not part of the
OVMF_CODE.fd, so they were not validated during the guest creation.

There are two approaches we can take to validate the data pages before
the access:

a) Enhance the OVMF reset vector code to validate the pages as described
above (go through step 2 - 3).
OR
b) Validate the pages during the guest creation time. The SEV firmware
provides a command which can be used by the VMM to validate the pages
without affecting the measurement of the launch.

Approach #b seems much simpler; it does not require any changes to the
OVMF reset vector code.

Update the OVMF metadata with the list of regions that must be
pre-validated by the VMM before the boot.

Cc: Michael Roth <michael.roth@amd.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
---
OvmfPkg/ResetVector/ResetVector.inf | 7 +++
OvmfPkg/ResetVector/ResetVector.nasmb | 29 +++++++++++++
OvmfPkg/ResetVector/X64/OvmfMetadata.asm | 54 ++++++++++++++++++++++++
3 files changed, 90 insertions(+)

diff --git a/OvmfPkg/ResetVector/ResetVector.inf b/OvmfPkg/ResetVector/ResetVector.inf
index 4cb81a3233f0..af3cf610a2cd 100644
--- a/OvmfPkg/ResetVector/ResetVector.inf
+++ b/OvmfPkg/ResetVector/ResetVector.inf
@@ -37,6 +37,8 @@ [Pcd]
gUefiCpuPkgTokenSpaceGuid.PcdSevEsWorkAreaBase
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBase
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbSize
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupBase
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbBackupSize
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableBase
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecGhcbPageTableSize
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase
@@ -44,6 +46,11 @@ [Pcd]
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize
+ gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress
+ gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize

[FixedPcd]
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase
diff --git a/OvmfPkg/ResetVector/ResetVector.nasmb b/OvmfPkg/ResetVector/ResetVector.nasmb
index 84cb5ae81b66..dc4dde2ff9d2 100644
--- a/OvmfPkg/ResetVector/ResetVector.nasmb
+++ b/OvmfPkg/ResetVector/ResetVector.nasmb
@@ -70,6 +70,7 @@
%define PT_ADDR(Offset) (FixedPcdGet32 (PcdOvmfSecPageTablesBase) + (Offset))

%define GHCB_PT_ADDR (FixedPcdGet32 (PcdOvmfSecGhcbPageTableBase))
+ %define GHCB_PT_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbPageTableSize))
%define GHCB_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBase))
%define GHCB_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbSize))
%define WORK_AREA_GUEST_TYPE (FixedPcdGet32 (PcdOvmfWorkAreaBase))
@@ -81,6 +82,34 @@
%define SEV_SNP_SECRETS_SIZE (FixedPcdGet32 (PcdOvmfSnpSecretsSize))
%define CPUID_BASE (FixedPcdGet32 (PcdOvmfCpuidBase))
%define CPUID_SIZE (FixedPcdGet32 (PcdOvmfCpuidSize))
+ %define SEC_PAGE_TABLE_BASE (FixedPcdGet32 (PcdOvmfSecPageTablesBase))
+ %define SEC_PAGE_TABLE_SIZE (FixedPcdGet32 (PcdOvmfSecPageTablesSize))
+ %define LOCK_BOX_STORAGE_BASE (FixedPcdGet32 (PcdOvmfLockBoxStorageBase))
+ %define LOCK_BOX_STORAGE_SIZE (FixedPcdGet32 (PcdOvmfLockBoxStorageSize))
+ ;
+ ; The PcdGuidedExtractHandlerTableAddress is a 64-bit PCD. The FixedPcdGet64() returns
+ ; a number suffix with 'ULL' (e.g 0x1111ULL). NASM does not like the constant ending
+ ; with anything other than 'h'. So, instead of using the FixedPcdGet64(), calculate
+ ; the base address of GuidedExtractHandlerTableBase
+ ;
+ %define GUID_EXTRACT_HANDLER_TABLE_BASE (LOCK_BOX_STORAGE_BASE + LOCK_BOX_STORAGE_SIZE)
+ %define GUID_EXTRACT_HANDLER_TABLE_SIZE (FixedPcdGet32 (PcdGuidedExtractHandlerTableSize))
+ %define WORK_AREA_BASE (FixedPcdGet32 (PcdOvmfWorkAreaBase))
+ %define WORK_AREA_SIZE (FixedPcdGet32 (PcdOvmfWorkAreaSize))
+ %define SEC_PEI_TEMP_RAM_BASE (FixedPcdGet32 (PcdOvmfSecPeiTempRamBase))
+ %define SEC_PEI_TEMP_RAM_SIZE (FixedPcdGet32 (PcdOvmfSecPeiTempRamSize))
+
+ ;
+ ; The PcdOvmfSecGhcbBase reserves two GHCB pages. The first page is used
+ ; as GHCB shared page and second is used for bookkeeping to support the
+ ; nested GHCB in SEC phase. The bookkeeping page is mapped private. The VMM
+ ; does not need to validate the shared page but it need to validate the
+ ; bookkeeping page
+ ;
+ %define GHCB_SEC_BACKUP_BASE (FixedPcdGet32 (PcdOvmfSecGhcbBackupBase))
+ %define GHCB_SEC_BACKUP_SIZE (FixedPcdGet32 (PcdOvmfSecGhcbBackupSize))
+ %define GHCB_BOOKKEEPING_BASE (GHCB_BASE + 0x1000)
+ %define GHCB_BOOKKEEPING_SIZE (GHCB_SIZE - 0x1000)

%include "Ia32/Flat32ToFlat64.asm"
%include "Ia32/AmdSev.asm"
diff --git a/OvmfPkg/ResetVector/X64/OvmfMetadata.asm b/OvmfPkg/ResetVector/X64/OvmfMetadata.asm
index 3f4b017104fc..8df170e8e649 100644
--- a/OvmfPkg/ResetVector/X64/OvmfMetadata.asm
+++ b/OvmfPkg/ResetVector/X64/OvmfMetadata.asm
@@ -35,6 +35,12 @@ BITS 64
; AMD SEV-SNP specific sections
%define OVMF_SECTION_TYPE_SNP_SECRETS 0x200

+; The section must be validated by the VMM before the boot.
+; The section is used for the GHCB memory. The GHCB memory is used as mailbox
+; in the TDX guest. This special section is similar to the
+; OVMF_SECTION_TYPE_SEC_MEM but its applicable for the SEV guest only.
+%define OVMF_SECTION_TYPE_SNP_SEC_MEM 0x201
+
ALIGN 16

TIMES (15 - ((OvmfGuidedStructureEnd - OvmfGuidedStructureStart + 15) % 16)) DB 0
@@ -53,6 +59,48 @@ _Descriptor:
DD OVMF_METADATA_VERSION ; Version
DD (OvmfGuidedStructureEnd - _Descriptor - 16) / 12 ; Number of sections

+; Page table used during SEC
+SecPageTable:
+ DD SEC_PAGE_TABLE_BASE
+ DD SEC_PAGE_TABLE_SIZE
+ DD OVMF_SECTION_TYPE_SEC_MEM
+
+; Lockbox storage
+LockBoxStorage:
+ DD LOCK_BOX_STORAGE_BASE
+ DD LOCK_BOX_STORAGE_SIZE
+ DD OVMF_SECTION_TYPE_SEC_MEM
+
+; Guided Extract Handler Table
+ExtractHandlerTable:
+ DD GUID_EXTRACT_HANDLER_TABLE_BASE
+ DD GUID_EXTRACT_HANDLER_TABLE_SIZE
+ DD OVMF_SECTION_TYPE_SEC_MEM
+
+; GHCB page table
+GhcbPageTable:
+ DD GHCB_PT_ADDR
+ DD GHCB_PT_SIZE
+ DD OVMF_SECTION_TYPE_SNP_SEC_MEM
+
+; GHCB bookkeeping page used in SEC phase
+GhcbBookkeeping:
+ DD GHCB_BOOKKEEPING_BASE
+ DD GHCB_BOOKKEEPING_SIZE
+ DD OVMF_SECTION_TYPE_SNP_SEC_MEM
+
+; Confidential computing work area
+WorkArea:
+ DD WORK_AREA_BASE
+ DD WORK_AREA_SIZE
+ DD OVMF_SECTION_TYPE_SEC_MEM
+
+; GHCB backup page used in SEC
+GhcbBackup:
+ DD GHCB_SEC_BACKUP_BASE
+ DD GHCB_SEC_BACKUP_SIZE
+ DD OVMF_SECTION_TYPE_SNP_SEC_MEM
+
; SEV-SNP Secrets page
SevSnpSecrets:
DD SEV_SNP_SECRETS_BASE
@@ -65,5 +113,11 @@ CpuidSec:
DD CPUID_SIZE
DD OVMF_SECTION_TYPE_CPUID

+; Temporary RAM used in SEC phase
+SecPeiTempRam:
+ DD SEC_PEI_TEMP_RAM_BASE
+ DD SEC_PEI_TEMP_RAM_SIZE
+ DD OVMF_SECTION_TYPE_SEC_MEM
+
OvmfGuidedStructureEnd:
ALIGN 16
--
2.25.1