[PATCH v4 5/7] Platform/ARM/N1Sdp: Introduce platform specific asl tables


Khasim Mohammed
 

This patch creates Dsdt.asl, SsdtPci.asl and SsdtRemotePci.asl files
to provide the platform specific APCI table entries.

Three PCI root ports are available on N1Sdp, PCI0 is the default root port
PCI1 is the CCIX root port and PCI2 is the Remote host root port.

The Remote host specific entries are defined in a separate file
SsdtRemotePci.asl to avoid confusions with other PCI entries
and for better readability and understanding of interfaces.

Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
Signed-off-by: Khasim Syed Mohammed <khasim.mohammed@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Signed-off-by: anukou01 <anurag.koul@arm.com>
Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
---
.../AslTables/Dsdt.asl | 482 ++++++++++++++++++
.../AslTables/SsdtPci.asl | 252 +++++++++
.../AslTables/SsdtRemotePci.asl | 161 ++++++
3 files changed, 895 insertions(+)
create mode 100644 Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
create mode 100644 Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
create mode 100644 Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl

diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
new file mode 100644
index 0000000000..818862cd75
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
@@ -0,0 +1,482 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Reference(s):
+ - ACPI for CoreSight 1.1, Platform Design Document
+ - ACPI for Arm Components 1.0, Platform Design Document
+
+**/
+
+#include "N1SdpAcpiHeader.h"
+#include "NeoverseN1Soc.h"
+
+#define ACPI_GRAPH_REV 0
+#define ACPI_GRAPH_UUID "ab02a46b-74c7-45a2-bd68-f7d344ef2153"
+
+#define CORESIGHT_GRAPH_UUID "3ecbc8b6-1d0e-4fb3-8107-e627f805c6cd"
+
+#define CS_LINK_MASTER 1
+#define CS_LINK_SLAVE 0
+
+#define DSD_CS_GRAPH_BEGIN(_nports) \
+ Package () { \
+ 1, \
+ ToUUID(CORESIGHT_GRAPH_UUID), \
+ _nports,
+
+#define DSD_CS_GRAPH_END \
+ }
+
+#define DSD_GRAPH_BEGIN(_nports) \
+ ToUUID(ACPI_GRAPH_UUID), \
+ Package() { \
+ ACPI_GRAPH_REV, \
+ 1, \
+ DSD_CS_GRAPH_BEGIN(_nports)
+
+#define DSD_GRAPH_END \
+ DSD_CS_GRAPH_END \
+ }
+
+#define DSD_PORTS_BEGIN(_nports) \
+ Name (_DSD, Package () { \
+ DSD_GRAPH_BEGIN(_nports)
+
+#define DSD_PORTS_END \
+ DSD_GRAPH_END \
+ })
+
+#define CS_PORT(_port, _rport, _rphandle, _dir) \
+ Package () { _port, _rport, _rphandle, _dir}
+
+#define CS_INPUT_PORT(_port, _rport, _rphandle) \
+ CS_PORT(_port, _rport, _rphandle, CS_LINK_SLAVE)
+
+#define CS_OUTPUT_PORT(_port, _rport, _rphandle) \
+ CS_PORT(_port, _rport, _rphandle, CS_LINK_MASTER)
+
+DefinitionBlock("Dsdt.aml", "DSDT", 1, "ARMLTD", "N1Sdp", EFI_ACPI_ARM_OEM_REVISION) {
+ Scope(_SB) {
+ Device(CP00) { // Ares-0: Cluster 0, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ Name(_STA, 0xF)
+ Device(ETM0) { // ETM on Cluster0 CPU0
+ Name (_HID, "ARMHC500")
+ Name (_CID, "ARMHC500")
+ Name (_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtm0Base), // Min Base Address
+ FixedPcdGet64 (PcdCsEtm0MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+ DSD_PORTS_BEGIN(1)
+ CS_OUTPUT_PORT(0, 0, \_SB_.SFN0)
+ DSD_PORTS_END
+ } // ETM0
+ }
+
+ Device(CP01) { // Ares-1: Cluster 0, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 1)
+ Name(_STA, 0xF)
+ Device(ETM1) { // ETM on Cluster0 CPU1
+ Name (_HID, "ARMHC500")
+ Name (_CID, "ARMHC500")
+ Name (_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtm1Base), // Min Base Address
+ FixedPcdGet64 (PcdCsEtm1MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+ DSD_PORTS_BEGIN(1)
+ CS_OUTPUT_PORT(0, 1, \_SB_.SFN0)
+ DSD_PORTS_END
+ } // ETM1
+ }
+
+ Device(CP02) { // Ares-2: Cluster 1, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 2)
+ Name(_STA, 0xF)
+ Device(ETM2) { // ETM on Cluster1 CPU0
+ Name (_HID, "ARMHC500")
+ Name (_CID, "ARMHC500")
+ Name (_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtm2Base), // Min Base Address
+ FixedPcdGet64 (PcdCsEtm2MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+ DSD_PORTS_BEGIN(1)
+ CS_OUTPUT_PORT(0, 0, \_SB_.SFN1)
+ DSD_PORTS_END
+ } // ETM2
+ }
+
+ Device(CP03) { // Ares-3: Cluster 1, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 3)
+ Name(_STA, 0xF)
+ Device(ETM3) { // ETM on Cluster0 CPU0
+ Name (_HID, "ARMHC500")
+ Name (_CID, "ARMHC500")
+ Name (_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtm3Base), // Min Base Address
+ FixedPcdGet64 (PcdCsEtm3MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ DSD_PORTS_BEGIN(1)
+ CS_OUTPUT_PORT(0, 1, \_SB_.SFN1)
+ DSD_PORTS_END
+ } // ETM3
+ }
+
+ Device(ETF0) {
+ Name(_HID, "ARMHC97C") // TMC
+ Name(_CID, "ARMHC97C") // TMC
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtf0Base), // Min Base Address
+ FixedPcdGet64 (PcdCsEtf0MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ DSD_PORTS_BEGIN(2)
+ CS_OUTPUT_PORT(0, 0, \_SB_.FUN),
+ CS_INPUT_PORT(0, 0, \_SB_.SFN0)
+ DSD_PORTS_END
+ } // ETF0
+
+ Device(ETF1) {
+ Name(_HID, "ARMHC97C") // TMC
+ Name(_CID, "ARMHC97C") // TMC
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtf1Base), // Min Base Address
+ FixedPcdGet64 (PcdCsEtf1MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ DSD_PORTS_BEGIN(2)
+ CS_OUTPUT_PORT(0, 1, \_SB_.FUN),
+ CS_INPUT_PORT(0, 0, \_SB_.SFN1)
+ DSD_PORTS_END
+ } // ETF1
+
+ Device(ETF2) {
+ Name(_HID, "ARMHC97C") // TMC
+ Name(_CID, "ARMHC97C") // TMC
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtf2Base), // Min Base Address
+ FixedPcdGet64 (PcdCsEtf2MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ DSD_PORTS_BEGIN(2)
+ CS_OUTPUT_PORT(0, 5, \_SB_.MFUN),
+ CS_INPUT_PORT(0, 0, \_SB_.STM0)
+ DSD_PORTS_END
+ } // ETF2
+
+ Device(FUN) {
+ Name(_HID, "ARMHC9FF")
+ Name(_CID, "ARMHC9FF")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsFunnel0Base), // Min Base Address
+ FixedPcdGet64 (PcdCsFunnel0MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+ DSD_PORTS_BEGIN(3)
+ CS_OUTPUT_PORT(0, 0, \_SB_.MFUN),
+ CS_INPUT_PORT(0, 0, \_SB_.ETF0),
+ CS_INPUT_PORT(1, 0, \_SB_.ETF1)
+ DSD_PORTS_END
+ } // FUN
+
+ Device(STM0) {
+ Name(_HID, "ARMHC502") // STM
+ Name(_CID, "ARMHC502")
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsStmBase), // Min Base Address
+ FixedPcdGet64 (PcdCsStmMaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ Memory32Fixed(ReadWrite,
+ FixedPcdGet32 (PcdCsStmStimulusBase),
+ FixedPcdGet32 (PcdCsStmStimulusSize))
+ })
+
+ DSD_PORTS_BEGIN(1)
+ CS_OUTPUT_PORT(0, 0, \_SB_.ETF2)
+ DSD_PORTS_END
+ }
+
+ Device(MFUN) { // Master Funnel
+ Name(_HID, "ARMHC9FF") // Funnel
+ Name(_CID, "ARMHC9FF") // Funnel
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsFunnel1Base), // Min Base Address
+ FixedPcdGet64 (PcdCsFunnel1MaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ DSD_PORTS_BEGIN(3)
+ CS_OUTPUT_PORT(0, 0, \_SB_.REP),
+ CS_INPUT_PORT(0, 0, \_SB_.FUN),
+ CS_INPUT_PORT(5, 0, \_SB_.ETF2)
+ DSD_PORTS_END
+ } // MFUN
+
+ Device(REP) {
+ Name(_HID, "ARMHC98D") // Replicator
+ Name(_CID, "ARMHC98D") // Replicator
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsReplicatorBase), // Min Base Address
+ FixedPcdGet64 (PcdCsReplicatorMaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ DSD_PORTS_BEGIN(3)
+ CS_OUTPUT_PORT(0, 0, \_SB_.TPIU),
+ CS_OUTPUT_PORT(1, 0, \_SB_.ETR),
+ CS_INPUT_PORT(0, 0, \_SB_.MFUN)
+ DSD_PORTS_END
+ } // REP
+
+ Device(TPIU) {
+ Name(_HID, "ARMHC979") // TPIU
+ Name(_CID, "ARMHC979") // TPIU
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsTpiuBase), // Min Base Address
+ FixedPcdGet64 (PcdCsTpiuMaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ DSD_PORTS_BEGIN(1)
+ CS_INPUT_PORT(0, 0, \_SB_.REP)
+ DSD_PORTS_END
+ } // TPIU
+
+ Device(ETR) {
+ Name(_HID, "ARMHC97C") // TMC
+ Name(_CID, "ARMHC97C") // TMC
+ Name(_CCA, 0) // The ETR on this platform is not coherent
+ Name(_CRS, ResourceTemplate() {
+ QWordMemory (
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCsEtrBase), // Min Base Address
+ FixedPcdGet64 (PcdCsEtrMaxBase), // Max Base Address
+ 0, // Translate
+ FixedPcdGet32 (PcdCsComponentSize) // Length
+ )
+ })
+
+ Name(_DSD, Package() {
+ DSD_GRAPH_BEGIN(1)
+ CS_INPUT_PORT(0, 1, \_SB_.REP)
+ DSD_GRAPH_END,
+
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package() {
+ Package(2) {"arm,scatter-gather", 1}
+ }
+ })
+
+ } // ETR
+
+ Device(SFN0) { // Static Funnel 0
+ Name(_HID, "ARMHC9FE") // Funnel
+ Name(_CID, "ARMHC9FE") // Funnel
+
+ DSD_PORTS_BEGIN(3)
+ CS_OUTPUT_PORT(0, 0, \_SB_.ETF0),
+ CS_INPUT_PORT(0, 0, \_SB_.CP00.ETM0),
+ CS_INPUT_PORT(1, 0, \_SB_.CP01.ETM1)
+ DSD_PORTS_END
+ } // SFN0
+
+ Device(SFN1) { // Static Funnel 1
+ Name(_HID, "ARMHC9FE") // Funnel
+ Name(_CID, "ARMHC9FE") // Funnel
+
+ DSD_PORTS_BEGIN(3)
+ CS_OUTPUT_PORT(0, 0, \_SB_.ETF1),
+ CS_INPUT_PORT(0, 0, \_SB_.CP02.ETM2),
+ CS_INPUT_PORT(1, 0, \_SB_.CP03.ETM3)
+ DSD_PORTS_END
+ } // SFN1
+
+ Device(CMN6) {
+ Name(_HID, "ARMHC600")
+
+ Name(_CRS, ResourceTemplate () {
+ // Region location is platform specific
+ // Other name(s) of this region: PERIPHBASE
+ QWordMemory (
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x00000000,
+ 0x50000000,
+ 0x5FFFFFFF,
+ 0x00000000,
+ 0x10000000,
+ ,
+ ,
+ CFGR
+ )
+
+ // Sub-region location is platform specific
+ // Other name(s) of this region: ROOTNODEBASE
+ QWordMemory (
+ ResourceConsumer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x00000000,
+ 0x50D00000,
+ 0x50D03FFF,
+ 0x00000000,
+ 0x00004000,
+ ,
+ ,
+ ROOT
+ )
+
+ // CMN600_INTREQPMU_DTC0
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 78 }
+ })
+ }
+ } // Scope(_SB)
+}
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
new file mode 100644
index 0000000000..cdbd42c154
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
@@ -0,0 +1,252 @@
+/** @file
+ Secondary System Description Table (SSDT)
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Reference(s):
+ - ACPI for CoreSight 1.1, Platform Design Document
+ - ACPI for Arm Components 1.0, Platform Design Document
+
+**/
+
+#include "N1SdpAcpiHeader.h"
+
+/*
+ See ACPI 6.4 Section 6.2.13
+
+ There are two ways that _PRT can be used.
+
+ In the first model, a PCI Link device is used to provide additional
+ configuration information such as whether the interrupt is Level or
+ Edge triggered, it is active High or Low, Shared or Exclusive, etc.
+
+ In the second model, the PCI interrupts are hardwired to specific
+ interrupt inputs on the interrupt controller and are not
+ configurable. In this case, the Source field in _PRT does not
+ reference a device, but instead contains the value zero, and the
+ Source Index field contains the global system interrupt to which the
+ PCI interrupt is hardwired.
+
+ We use the first model with link indirection to set the correct
+ interrupt type as PCI defaults (Level Triggered, Active Low) are not
+ compatible with GICv2.
+*/
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+ Device(Link_Name) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, Unique_Id) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+}
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, /* uses the same format as _ADR */ \
+ Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD) */ \
+ Link, /* Interrupt allocated via Link device */ \
+ Zero /* global system interrupt number (no used) */ \
+}
+
+/*
+ See Reference [1] 6.1.1
+ "High word-Device #, Low word-Function #. (for example, device 3,
+ function 2 is 0x00030002). To refer to all the functions on a device #,
+ use a function number of FFFF)."
+*/
+#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) // Device 0 for Bridge.
+
+DefinitionBlock("SsdtPci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
+ EFI_ACPI_ARM_OEM_REVISION)
+{
+ Scope (_SB) {
+
+ // PCI Root Complex
+ LNK_DEVICE(1, LNKA, 201)
+ LNK_DEVICE(2, LNKB, 202)
+ LNK_DEVICE(3, LNKC, 203)
+ LNK_DEVICE(4, LNKD, 204)
+ LNK_DEVICE(5, LNKE, 233)
+ LNK_DEVICE(6, LNKF, 234)
+ LNK_DEVICE(7, LNKG, 235)
+ LNK_DEVICE(8, LNKH, 236)
+
+ // PCI Root Complex
+ Device(PCI0) {
+ Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, Zero) // PCI Segment Group number
+ Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_CCA, 1) // Cache Coherency Attribute
+
+ // Root Complex 0
+ Device (RP0) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKA), // INTA
+ ROOT_PRT_ENTRY(1, LNKB), // INTB
+ ROOT_PRT_ENTRY(2, LNKC), // INTC
+ ROOT_PRT_ENTRY(3, LNKD), // INTD
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ FixedPcdGet32 (PcdPcieBusMin), // AddressMinimum - Minimum Bus Number
+ FixedPcdGet32 (PcdPcieBusMax), // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ FixedPcdGet32 (PcdPcieBusCount) // RangeLength - Number of Busses
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdPcieMmio32Base), // Min Base Address
+ FixedPcdGet32 (PcdPcieMmio32MaxBase), // Max Base Address
+ FixedPcdGet32 (PcdPcieMmio32Translation), // Translate
+ FixedPcdGet32 (PcdPcieMmio32Size) // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdPcieMmio64Base), // Min Base Address
+ FixedPcdGet64 (PcdPcieMmio64MaxBase), // Max Base Address
+ FixedPcdGet64 (PcdPcieMmio64Translation), // Translate
+ FixedPcdGet64 (PcdPcieMmio64Size) // Length
+ )
+
+ DWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdPcieIoBase), // Min Base Address
+ FixedPcdGet32 (PcdPcieIoMaxBase), // Max Base Address
+ FixedPcdGet32 (PcdPcieIoTranslation), // Translate
+ FixedPcdGet32 (PcdPcieIoSize), // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ }) // Name(RBUF)
+
+ Return (RBUF)
+ } // Method (_CRS)
+ }
+
+ // CCIX Root Complex
+ Device(PCI1) {
+ Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, 1) // PCI Segment Group number
+ Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_CCA, 1) // Cache Coherency Attribute
+
+ // Root Complex 1
+ Device (RP1) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKE), // INTA
+ ROOT_PRT_ENTRY(1, LNKF), // INTB
+ ROOT_PRT_ENTRY(2, LNKG), // INTC
+ ROOT_PRT_ENTRY(3, LNKH), // INTD
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ FixedPcdGet32 (PcdCcixBusMin), // AddressMinimum - Minimum Bus Number
+ FixedPcdGet32 (PcdCcixBusMax), // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ FixedPcdGet32 (PcdCcixBusCount) // RangeLength - Number of Busses
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdCcixMmio32Base), // Min Base Address
+ FixedPcdGet32 (PcdCcixMmio32MaxBase), // Max Base Address
+ FixedPcdGet32 (PcdCcixMmio32Translation), // Translate
+ FixedPcdGet32 (PcdCcixMmio32Size) // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdCcixMmio64Base), // Min Base Address
+ FixedPcdGet64 (PcdCcixMmio64MaxBase), // Max Base Address
+ FixedPcdGet64 (PcdCcixMmio64Translation), // Translate
+ FixedPcdGet64 (PcdCcixMmio64Size) // Length
+ )
+
+ DWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdCcixIoBase), // Min Base Address
+ FixedPcdGet32 (PcdCcixIoMaxBase), // Max Base Address
+ FixedPcdGet32 (PcdCcixIoTranslation), // Translate
+ FixedPcdGet32 (PcdCcixIoSize), // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ }) // Name(RBUF)
+
+ Return (RBUF)
+ } // Method (_CRS)
+ }
+
+ }
+}
diff --git a/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
new file mode 100644
index 0000000000..b6bec7c106
--- /dev/null
+++ b/Platform/ARM/N1Sdp/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtRemotePci.asl
@@ -0,0 +1,161 @@
+/** @file
+ Secondary System Description Table (SSDT)
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Reference(s):
+ - ACPI for CoreSight 1.1, Platform Design Document
+ - ACPI for Arm Components 1.0, Platform Design Document
+
+**/
+
+#include "N1SdpAcpiHeader.h"
+
+/*
+ See ACPI 6.4 Section 6.2.13
+
+ There are two ways that _PRT can be used.
+
+ In the first model, a PCI Link device is used to provide additional
+ configuration information such as whether the interrupt is Level or
+ Edge triggered, it is active High or Low, Shared or Exclusive, etc.
+
+ In the second model, the PCI interrupts are hardwired to specific
+ interrupt inputs on the interrupt controller and are not
+ configurable. In this case, the Source field in _PRT does not
+ reference a device, but instead contains the value zero, and the
+ Source Index field contains the global system interrupt to which the
+ PCI interrupt is hardwired.
+
+ We use the first model with link indirection to set the correct
+ interrupt type as PCI defaults (Level Triggered, Active Low) are not
+ compatible with GICv2.
+*/
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+ Device(Link_Name) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, Unique_Id) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+}
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, /* uses the same format as _ADR */ \
+ Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD) */ \
+ Link, /* Interrupt allocated via Link device */ \
+ Zero /* global system interrupt number (no used) */ \
+}
+
+/*
+ See Reference [1] 6.1.1
+ "High word-Device #, Low word-Function #. (for example, device 3,
+ function 2 is 0x00030002). To refer to all the functions on a device #,
+ use a function number of FFFF)."
+*/
+#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link) // Device 0 for Bridge.
+
+DefinitionBlock("SsdtRemotePci.aml", "SSDT", 1, "ARMLTD", "N1Sdp",
+ EFI_ACPI_ARM_OEM_REVISION)
+{
+ Scope (_SB) {
+
+ // Remote PCI Root Complex
+ LNK_DEVICE(9, LNKI, 681)
+ LNK_DEVICE(10, LNKJ, 682)
+ LNK_DEVICE(11, LNKK, 683)
+ LNK_DEVICE(12, LNKL, 684)
+
+ //Remote PCIe root complex
+ Device(PCI2) {
+ Name (_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name (_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, 2) // PCI Segment Group number
+ Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_CCA, 1) // Cache Coherency Attribute
+
+ // Remote Root Complex 0
+ Device (RP0) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKI), // INTA
+ ROOT_PRT_ENTRY(1, LNKJ), // INTB
+ ROOT_PRT_ENTRY(2, LNKK), // INTC
+ ROOT_PRT_ENTRY(3, LNKL), // INTD
+ })
+
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ 0, // AddressGranularity
+ FixedPcdGet32 (PcdPcieBusMin), // AddressMinimum - Minimum Bus Number
+ FixedPcdGet32 (PcdPcieBusMax), // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ FixedPcdGet32 (PcdPcieBusCount) // RangeLength - Number of Busses
+ )
+
+ QWordMemory ( // 32-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdPcieMmio32Base), // Min Base Address
+ FixedPcdGet32 (PcdPcieMmio32MaxBase), // Max Base Address
+ FixedPcdGet32 (PcdRemotePcieMmio32Translation), // Translate
+ FixedPcdGet32 (PcdPcieMmio32Size) // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ FixedPcdGet64 (PcdPcieMmio64Base), // Min Base Address
+ FixedPcdGet64 (PcdPcieMmio64MaxBase), // Max Base Address
+ FixedPcdGet64 (PcdRemotePcieMmio64Translation), // Translate
+ FixedPcdGet64 (PcdPcieMmio64Size) // Length
+ )
+
+ QWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ FixedPcdGet32 (PcdPcieIoBase), // Min Base Address
+ FixedPcdGet32 (PcdPcieIoMaxBase), // Max Base Address
+ FixedPcdGet64 (PcdRemotePcieIoTranslation), // Translate
+ FixedPcdGet32 (PcdPcieIoSize), // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ }) // Name(RBUF)
+
+ Return (RBUF)
+ } // Method (_CRS)
+ }
+ }
+}
--
2.17.1