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[PATCH] IntelFsp2Pkg: TempRamInit API should preserve EBX/RBX register.
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Chiu, Chasel
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4395
FSP specification defines the TempRamInit API preserved register list which including EBX/RBX, however current implementation unexpectedly overriding EBX/RBX register that should be fixed. Cc: Nate DeSimone <nathaniel.l.desimone@...> Cc: Star Zeng <star.zeng@...> Signed-off-by: Chasel Chiu <chasel.chiu@...> --- IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc | 7 +++++++ IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 21 +++++++++++++++++= +++- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp= 2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index a222f2e376..016f943b43 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -157,6 +157,9 @@ NextAddress: ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to t= est=0D ; whether the processor supports SSE instruction.=0D ;=0D + ; Save EBX to MM2=0D + ;=0D + movd mm2, ebx=0D mov eax, 1=0D cpuid=0D bt edx, 25=0D @@ -169,6 +172,10 @@ NextAddress: bt ecx, 19=0D jnc SseError=0D %endif=0D + ;=0D + ; Restore EBX from MM2=0D + ;=0D + movd ebx, mm2=0D =0D ;=0D ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)=0D diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pkg/= Include/SaveRestoreSseAvxNasm.inc index 38c807a311..002a5a1412 100644 --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc @@ -255,6 +255,10 @@ NextAddress: ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] =3D 1) to t= est=0D ; whether the processor supports SSE instruction.=0D ;=0D + ; Save RBX to R11=0D + ; Save RCX to R10=0D + ;=0D + mov r11, rbx=0D mov r10, rcx=0D mov rax, 1=0D cpuid=0D @@ -266,7 +270,12 @@ NextAddress: ;=0D bt ecx, 19=0D jnc SseError=0D - mov rcx, r10=0D + ;=0D + ; Restore RBX from R11=0D + ; Restore RCX from R10=0D + ;=0D + mov rbx, r11=0D + mov rcx, r10=0D =0D ;=0D ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10)=0D @@ -284,6 +293,11 @@ NextAddress: %endmacro=0D =0D %macro ENABLE_AVX 0=0D + ;=0D + ; Save RBX to R11=0D + ; Save RCX to R10=0D + ;=0D + mov r11, rbx=0D mov r10, rcx=0D mov eax, 1=0D cpuid=0D @@ -307,6 +321,11 @@ EnableAvx: xgetbv ; result in edx:eax=0D or eax, 00000006h ; Set XCR0 bit #1 and bit #2 to enable = SSE state and AVX state=0D xsetbv=0D + ;=0D + ; Restore RBX from R11=0D + ; Restore RCX from R10=0D + ;=0D + mov rbx, r11=0D mov rcx, r10=0D %endmacro=0D =0D --=20 2.35.0.windows.1 |
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Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...>
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-----Original Message-----
From: Chiu, Chasel <chasel.chiu@...> Sent: Friday, March 31, 2023 4:16 PM To: devel@edk2.groups.io Cc: Chiu, Chasel <chasel.chiu@...>; Desimone, Nathaniel L <nathaniel.l.desimone@...>; Zeng, Star <star.zeng@...> Subject: [PATCH] IntelFsp2Pkg: TempRamInit API should preserve EBX/RBX register. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4395 FSP specification defines the TempRamInit API preserved register list which including EBX/RBX, however current implementation unexpectedly overriding EBX/RBX register that should be fixed. Cc: Nate DeSimone <nathaniel.l.desimone@...> Cc: Star Zeng <star.zeng@...> Signed-off-by: Chasel Chiu <chasel.chiu@...> --- IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc | 7 +++++++ IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc | 21 ++++++++++++++++++++- 2 files changed, 27 insertions(+), 1 deletion(-) diff --git a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc index a222f2e376..016f943b43 100644 --- a/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc +++ b/IntelFsp2Pkg/FspSecCore/Ia32/SaveRestoreSseNasm.inc @@ -157,6 +157,9 @@ NextAddress: ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test ; whether the processor supports SSE instruction. ; + ; Save EBX to MM2 + ; + movd mm2, ebx mov eax, 1 cpuid bt edx, 25 @@ -169,6 +172,10 @@ NextAddress: bt ecx, 19 jnc SseError %endif + ; + ; Restore EBX from MM2 + ; + movd ebx, mm2 ; ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10) diff --git a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc index 38c807a311..002a5a1412 100644 --- a/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc +++ b/IntelFsp2Pkg/Include/SaveRestoreSseAvxNasm.inc @@ -255,6 +255,10 @@ NextAddress: ; Use CpuId instruction (CPUID.01H:EDX.SSE[bit 25] = 1) to test ; whether the processor supports SSE instruction. ; + ; Save RBX to R11 + ; Save RCX to R10 + ; + mov r11, rbx mov r10, rcx mov rax, 1 cpuid @@ -266,7 +270,12 @@ NextAddress: ; bt ecx, 19 jnc SseError - mov rcx, r10 + ; + ; Restore RBX from R11 + ; Restore RCX from R10 + ; + mov rbx, r11 + mov rcx, r10 ; ; Set OSFXSR bit (bit #9) & OSXMMEXCPT bit (bit #10) @@ -284,6 +293,11 @@ NextAddress: %endmacro %macro ENABLE_AVX 0 + ; + ; Save RBX to R11 + ; Save RCX to R10 + ; + mov r11, rbx mov r10, rcx mov eax, 1 cpuid @@ -307,6 +321,11 @@ EnableAvx: xgetbv ; result in edx:eax or eax, 00000006h ; Set XCR0 bit #1 and bit #2 to enable SSE state and AVX state xsetbv + ; + ; Restore RBX from R11 + ; Restore RCX from R10 + ; + mov rbx, r11 mov rcx, r10 %endmacro -- 2.35.0.windows.1 |
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Chiu, Chasel
Patch merged:
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https://github.com/tianocore/edk2/commit/af98f1fb0311d8e3cc52ab9fc544a8c8ff8f7546 Thanks, Chasel -----Original Message----- |
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Michael D Kinney
What compiler is being used for this IPU?
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Mike -----Original Message----- |
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