[PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from bootloader


Ni, Ray
 

The patch removes the dep on PcdUse5LevelPageTable.
Now the payload inherits the 5-level paging setting from
bootloader in IA-32e mode and uses 4-level paging in
legacy protected mode.

This fix the potential issue when bootloader enables 5-level paging
but 64bit payload sets 4-level page table to CR3 resulting CPU
exception because PcdUse5LevelPageTable is FALSE.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
---
.../UefiPayloadEntry/UefiPayloadEntry.inf | 1 -
.../UniversalPayloadEntry.inf | 1 -
.../UefiPayloadEntry/X64/VirtualMemory.c | 38 ++++++++-----------
3 files changed, 16 insertions(+), 24 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf b/UefiPay=
loadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
index 8d42925fcd..9b6fab66a1 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
@@ -80,7 +80,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ##=
CONSUMES=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##=
CONSUMES=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##=
CONSUMES=0D
- gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##=
SOMETIMES_CONSUMES=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ##=
CONSUMES=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ##=
CONSUMES=0D
=0D
diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf b/Ue=
fiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
index 416a620598..aae62126e9 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
@@ -85,7 +85,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ##=
CONSUMES=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##=
CONSUMES=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ##=
CONSUMES=0D
- gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##=
SOMETIMES_CONSUMES=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ##=
CONSUMES=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ##=
CONSUMES=0D
=0D
diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c b/UefiPayl=
oadPkg/UefiPayloadEntry/X64/VirtualMemory.c
index a1c4ad6ff4..9daa46c12c 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
@@ -15,7 +15,7 @@
2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:In=
struction Set Reference, Intel=0D
3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:Sy=
stem Programmer's Guide, Intel=0D
=0D
-Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>=0D
+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>=0D
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
@@ -668,7 +668,6 @@ CreateIdentityMappingPageTables (
)=0D
{=0D
UINT32 RegEax;=0D
- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX EcxFlags;=0D
UINT32 RegEdx;=0D
UINT8 PhysicalAddressBits;=0D
EFI_PHYSICAL_ADDRESS PageAddress;=0D
@@ -687,7 +686,7 @@ CreateIdentityMappingPageTables (
UINTN TotalPagesNum;=0D
UINTN BigPageAddress;=0D
VOID *Hob;=0D
- BOOLEAN Page5LevelSupport;=0D
+ BOOLEAN Enable5LevelPaging;=0D
BOOLEAN Page1GSupport;=0D
PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;=0D
UINT64 AddressEncMask;=0D
@@ -730,18 +729,16 @@ CreateIdentityMappingPageTables (
}=0D
}=0D
=0D
- Page5LevelSupport =3D FALSE;=0D
- if (PcdGetBool (PcdUse5LevelPageTable)) {=0D
- AsmCpuidEx (=0D
- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_F=
EATURE_FLAGS_SUB_LEAF_INFO, NULL,=0D
- &EcxFlags.Uint32, NULL, NULL=0D
- );=0D
- if (EcxFlags.Bits.FiveLevelPage !=3D 0) {=0D
- Page5LevelSupport =3D TRUE;=0D
- }=0D
- }=0D
+ //=0D
+ // Check CR4.LA57[bit12] to determin whether 5-Level Paging is enabled.=
=0D
+ // Because this code runs at both IA-32e (64bit) mode and legacy protect=
ed (32bit) mode,=0D
+ // below logic inherits the 5-level paging setting from bootloader in IA=
-32e mode=0D
+ // and uses 4-level paging in legacy protected mode.=0D
+ //=0D
+ Cr4.UintN =3D AsmReadCr4 ();=0D
+ Enable5LevelPaging =3D (BOOLEAN) (Cr4.Bits.LA57 =3D=3D 1);=0D
=0D
- DEBUG ((DEBUG_INFO, "AddressBits=3D%u 5LevelPaging=3D%u 1GPage=3D%u\n", =
PhysicalAddressBits, Page5LevelSupport, Page1GSupport));=0D
+ DEBUG ((DEBUG_INFO, "PayloadEntry: AddressBits=3D%u 5LevelPaging=3D%u 1G=
Page=3D%u\n", PhysicalAddressBits, Enable5LevelPaging, Page1GSupport));=0D
=0D
//=0D
// IA-32e paging translates 48-bit linear addresses to 52-bit physical a=
ddresses=0D
@@ -749,7 +746,7 @@ CreateIdentityMappingPageTables (
// due to either unsupported by HW, or disabled by PCD.=0D
//=0D
ASSERT (PhysicalAddressBits <=3D 52);=0D
- if (!Page5LevelSupport && PhysicalAddressBits > 48) {=0D
+ if (!Enable5LevelPaging && PhysicalAddressBits > 48) {=0D
PhysicalAddressBits =3D 48;=0D
}=0D
=0D
@@ -784,7 +781,7 @@ CreateIdentityMappingPageTables (
//=0D
// Substract the one page occupied by PML5 entries if 5-Level Paging is =
disabled.=0D
//=0D
- if (!Page5LevelSupport) {=0D
+ if (!Enable5LevelPaging) {=0D
TotalPagesNum--;=0D
}=0D
=0D
@@ -799,7 +796,7 @@ CreateIdentityMappingPageTables (
// By architecture only one PageMapLevel4 exists - so lets allocate stor=
age for it.=0D
//=0D
PageMap =3D (VOID *) BigPageAddress;=0D
- if (Page5LevelSupport) {=0D
+ if (Enable5LevelPaging) {=0D
//=0D
// By architecture only one PageMapLevel5 exists - so lets allocate st=
orage for it.=0D
//=0D
@@ -819,7 +816,7 @@ CreateIdentityMappingPageTables (
PageMapLevel4Entry =3D (VOID *) BigPageAddress;=0D
BigPageAddress +=3D SIZE_4KB;=0D
=0D
- if (Page5LevelSupport) {=0D
+ if (Enable5LevelPaging) {=0D
//=0D
// Make a PML5 Entry=0D
//=0D
@@ -911,10 +908,7 @@ CreateIdentityMappingPageTables (
ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PAGE=
_MAP_AND_DIRECTORY_POINTER));=0D
}=0D
=0D
- if (Page5LevelSupport) {=0D
- Cr4.UintN =3D AsmReadCr4 ();=0D
- Cr4.Bits.LA57 =3D 1;=0D
- AsmWriteCr4 (Cr4.UintN);=0D
+ if (Enable5LevelPaging) {=0D
//=0D
// For the PML5 entries we are not using fill in a null entry.=0D
//=0D
--=20
2.32.0.windows.1


Guo Dong
 

Reviewed-by: Guo Dong <guo.dong@intel.com>

-----Original Message-----
From: Ni, Ray <ray.ni@intel.com>
Sent: Friday, August 6, 2021 1:16 AM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>
Subject: [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from bootloader

The patch removes the dep on PcdUse5LevelPageTable.
Now the payload inherits the 5-level paging setting from bootloader in IA-32e mode and uses 4-level paging in legacy protected mode.

This fix the potential issue when bootloader enables 5-level paging but 64bit payload sets 4-level page table to CR3 resulting CPU exception because PcdUse5LevelPageTable is FALSE.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
---
.../UefiPayloadEntry/UefiPayloadEntry.inf | 1 -
.../UniversalPayloadEntry.inf | 1 -
.../UefiPayloadEntry/X64/VirtualMemory.c | 38 ++++++++-----------
3 files changed, 16 insertions(+), 24 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
index 8d42925fcd..9b6fab66a1 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
@@ -80,7 +80,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONSUMES- gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ## SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ## CONSUMES diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
index 416a620598..aae62126e9 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
@@ -85,7 +85,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONSUMES- gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ## SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ## CONSUMES diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
index a1c4ad6ff4..9daa46c12c 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
@@ -15,7 +15,7 @@
2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel -Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR> Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent@@ -668,7 +668,6 @@ CreateIdentityMappingPageTables (
) { UINT32 RegEax;- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX EcxFlags; UINT32 RegEdx; UINT8 PhysicalAddressBits; EFI_PHYSICAL_ADDRESS PageAddress;@@ -687,7 +686,7 @@ CreateIdentityMappingPageTables (
UINTN TotalPagesNum; UINTN BigPageAddress; VOID *Hob;- BOOLEAN Page5LevelSupport;+ BOOLEAN Enable5LevelPaging; BOOLEAN Page1GSupport; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; UINT64 AddressEncMask;@@ -730,18 +729,16 @@ CreateIdentityMappingPageTables (
} } - Page5LevelSupport = FALSE;- if (PcdGetBool (PcdUse5LevelPageTable)) {- AsmCpuidEx (- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL,- &EcxFlags.Uint32, NULL, NULL- );- if (EcxFlags.Bits.FiveLevelPage != 0) {- Page5LevelSupport = TRUE;- }- }+ //+ // Check CR4.LA57[bit12] to determin whether 5-Level Paging is enabled.+ // Because this code runs at both IA-32e (64bit) mode and legacy protected (32bit) mode,+ // below logic inherits the 5-level paging setting from bootloader in IA-32e mode+ // and uses 4-level paging in legacy protected mode.+ //+ Cr4.UintN = AsmReadCr4 ();+ Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); - DEBUG ((DEBUG_INFO, "AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Page5LevelSupport, Page1GSupport));+ DEBUG ((DEBUG_INFO, "PayloadEntry: AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Enable5LevelPaging, Page1GSupport)); // // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses@@ -749,7 +746,7 @@ CreateIdentityMappingPageTables (
// due to either unsupported by HW, or disabled by PCD. // ASSERT (PhysicalAddressBits <= 52);- if (!Page5LevelSupport && PhysicalAddressBits > 48) {+ if (!Enable5LevelPaging && PhysicalAddressBits > 48) { PhysicalAddressBits = 48; } @@ -784,7 +781,7 @@ CreateIdentityMappingPageTables (
// // Substract the one page occupied by PML5 entries if 5-Level Paging is disabled. //- if (!Page5LevelSupport) {+ if (!Enable5LevelPaging) { TotalPagesNum--; } @@ -799,7 +796,7 @@ CreateIdentityMappingPageTables (
// By architecture only one PageMapLevel4 exists - so lets allocate storage for it. // PageMap = (VOID *) BigPageAddress;- if (Page5LevelSupport) {+ if (Enable5LevelPaging) { // // By architecture only one PageMapLevel5 exists - so lets allocate storage for it. //@@ -819,7 +816,7 @@ CreateIdentityMappingPageTables (
PageMapLevel4Entry = (VOID *) BigPageAddress; BigPageAddress += SIZE_4KB; - if (Page5LevelSupport) {+ if (Enable5LevelPaging) { // // Make a PML5 Entry //@@ -911,10 +908,7 @@ CreateIdentityMappingPageTables (
ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)); } - if (Page5LevelSupport) {- Cr4.UintN = AsmReadCr4 ();- Cr4.Bits.LA57 = 1;- AsmWriteCr4 (Cr4.UintN);+ if (Enable5LevelPaging) { // // For the PML5 entries we are not using fill in a null entry. //--
2.32.0.windows.1


Ma, Maurice
 

Reviewed-by: Maurice Ma <maurice.ma@intel.com>

-----Original Message-----
From: Ni, Ray <ray.ni@intel.com>
Sent: Friday, August 6, 2021 1:16
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ma, Maurice
<maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>
Subject: [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from
bootloader

The patch removes the dep on PcdUse5LevelPageTable.
Now the payload inherits the 5-level paging setting from bootloader in IA-32e
mode and uses 4-level paging in legacy protected mode.

This fix the potential issue when bootloader enables 5-level paging but 64bit
payload sets 4-level page table to CR3 resulting CPU exception because
PcdUse5LevelPageTable is FALSE.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
---
.../UefiPayloadEntry/UefiPayloadEntry.inf | 1 -
.../UniversalPayloadEntry.inf | 1 -
.../UefiPayloadEntry/X64/VirtualMemory.c | 38 ++++++++-----------
3 files changed, 16 insertions(+), 24 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
index 8d42925fcd..9b6fab66a1 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
@@ -80,7 +80,6 @@

gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask
## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##
CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
## CONSUMES-
gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##
SOMETIMES_CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ##
CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize
## CONSUMES diff --git
a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
index 416a620598..aae62126e9 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
@@ -85,7 +85,6 @@

gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask
## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ##
CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard
## CONSUMES-
gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ##
SOMETIMES_CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ##
CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize
## CONSUMES diff --git
a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
index a1c4ad6ff4..9daa46c12c 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
@@ -15,7 +15,7 @@
2) IA-32 Intel(R) Architecture Software Developer's Manual Volume
2:Instruction Set Reference, Intel 3) IA-32 Intel(R) Architecture Software
Developer's Manual Volume 3:System Programmer's Guide, Intel -Copyright
(c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2006
- 2021, Intel Corporation. All rights reserved.<BR> Copyright (c) 2017, AMD
Incorporated. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-
Clause-Patent@@ -668,7 +668,6 @@ CreateIdentityMappingPageTables (
) { UINT32 RegEax;-
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX EcxFlags; UINT32
RegEdx; UINT8 PhysicalAddressBits;
EFI_PHYSICAL_ADDRESS PageAddress;@@ -687,7 +686,7 @@
CreateIdentityMappingPageTables (
UINTN TotalPagesNum; UINTN
BigPageAddress; VOID *Hob;- BOOLEAN
Page5LevelSupport;+ BOOLEAN Enable5LevelPaging;
BOOLEAN Page1GSupport; PAGE_TABLE_1G_ENTRY
*PageDirectory1GEntry; UINT64 AddressEncMask;@@ -
730,18 +729,16 @@ CreateIdentityMappingPageTables (
} } - Page5LevelSupport = FALSE;- if (PcdGetBool
(PcdUse5LevelPageTable)) {- AsmCpuidEx (-
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL,-
&EcxFlags.Uint32, NULL, NULL- );- if (EcxFlags.Bits.FiveLevelPage != 0) {-
Page5LevelSupport = TRUE;- }- }+ //+ // Check CR4.LA57[bit12] to
determin whether 5-Level Paging is enabled.+ // Because this code runs at
both IA-32e (64bit) mode and legacy protected (32bit) mode,+ // below logic
inherits the 5-level paging setting from bootloader in IA-32e mode+ // and
uses 4-level paging in legacy protected mode.+ //+ Cr4.UintN = AsmReadCr4
();+ Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); - DEBUG
((DEBUG_INFO, "AddressBits=%u 5LevelPaging=%u 1GPage=%u\n",
PhysicalAddressBits, Page5LevelSupport, Page1GSupport));+ DEBUG
((DEBUG_INFO, "PayloadEntry: AddressBits=%u 5LevelPaging=%u
1GPage=%u\n", PhysicalAddressBits, Enable5LevelPaging, Page1GSupport));
// // IA-32e paging translates 48-bit linear addresses to 52-bit physical
addresses@@ -749,7 +746,7 @@ CreateIdentityMappingPageTables (
// due to either unsupported by HW, or disabled by PCD. // ASSERT
(PhysicalAddressBits <= 52);- if (!Page5LevelSupport && PhysicalAddressBits >
48) {+ if (!Enable5LevelPaging && PhysicalAddressBits > 48)
{ PhysicalAddressBits = 48; } @@ -784,7 +781,7 @@
CreateIdentityMappingPageTables (
// // Substract the one page occupied by PML5 entries if 5-Level Paging is
disabled. //- if (!Page5LevelSupport) {+ if (!Enable5LevelPaging)
{ TotalPagesNum--; } @@ -799,7 +796,7 @@
CreateIdentityMappingPageTables (
// By architecture only one PageMapLevel4 exists - so lets allocate storage
for it. // PageMap = (VOID *) BigPageAddress;- if (Page5LevelSupport)
{+ if (Enable5LevelPaging) { // // By architecture only one
PageMapLevel5 exists - so lets allocate storage for it. //@@ -819,7 +816,7
@@ CreateIdentityMappingPageTables (
PageMapLevel4Entry = (VOID *) BigPageAddress; BigPageAddress +=
SIZE_4KB; - if (Page5LevelSupport) {+ if (Enable5LevelPaging) { // //
Make a PML5 Entry //@@ -911,10 +908,7 @@
CreateIdentityMappingPageTables (
ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof
(PAGE_MAP_AND_DIRECTORY_POINTER)); } - if (Page5LevelSupport) {-
Cr4.UintN = AsmReadCr4 ();- Cr4.Bits.LA57 = 1;- AsmWriteCr4
(Cr4.UintN);+ if (Enable5LevelPaging) { // // For the PML5 entries we are
not using fill in a null entry. //--
2.32.0.windows.1