[edk2-platforms][PATCH V4 7/9] Platform/Sgi: Update ACPI version to v6.4 for RD-V1-MC platform


Pranav Madhu
 

Update the RD-V1-MC platform specific ACPI tables to ACPI version
v6.4. Significant changes introduced are to add SPE overflow interrupt
number field to GICC structure of MADT table and adding cache ID field
to the cache structure of PPTT table.

Signed-off-by: Pranav Madhu <pranav.madhu@...>
Reviewed-by: Pierre Gondois <pierre.gondois@...>
Reviewed-by: Thomas Abraham <thomas.abraham@...>
---
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc | 64 ++++----
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc | 165 ++++++++++--------=
--
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc | 84 +++++-----
Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc | 82 +++++-----
4 files changed, 210 insertions(+), 185 deletions(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc b/Platform/A=
RM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
index c2dad0e137d5..b8485cd98ea4 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Hmat.aslc
@@ -1,17 +1,25 @@
/** @file
-* Heterogeneous Memory Attribute Table (HMAT)
-*
-* Copyright (c) 2020-2021, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Heterogeneous Memory Attribute Table (HMAT)
+
+ The (HMAT) describes the memory attributes, such as memory side cache
+ attributes and bandwidth and latency details, related to Memory Proxim=
ity
+ Domains. The software is expected to use this information as a hint fo=
r
+ optimization, or when the system has heterogeneous memory. The attribu=
tes of
+ the memory connected to the two chips on this platform are listed in t=
his
+ table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.27, Heterogeneous Memory Attribut=
e Table
**/
=20
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
-#include <SgiAcpiHeader.h>
-#include <SgiPlatform.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
=20
#define CHIP_CNT FixedPcdGet32 (PcdChipCount)
#define INITATOR_PROXIMITY_DOMAIN_CNT 4
@@ -29,14 +37,14 @@ typedef struct InitiatorTargetProximityMatrix {
} INITIATOR_TARGET_PROXIMITY_MATRIX;
=20
typedef struct {
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER =
Header;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES =
Proximity[CHIP_CNT];
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO=
LatencyInfo;
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_HEADER =
Header;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES =
Proximity[CHIP_CNT];
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO=
LatencyInfo;
INITIATOR_TARGET_PROXIMITY_MATRIX =
Matrix;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO =
MemSideCache0;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO =
MemSideCache1;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO =
MemSideCache2;
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO =
MemSideCache3;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO =
MemSideCache0;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO =
MemSideCache1;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO =
MemSideCache2;
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO =
MemSideCache3;
} EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE;
=20
#pragma pack ()
@@ -45,9 +53,9 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D =
{
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_SIGNATURE,
EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE,
- EFI_ACPI_6_3_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
+ EFI_ACPI_6_4_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE_REVISION
),
{
EFI_ACPI_RESERVED_BYTE,
@@ -59,19 +67,19 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D=
{
=20
// Memory Proximity Domain
{
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT =
(
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT =
(
1, 0x0, 0x0),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT =
(
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT =
(
1, 0x1, 0x1),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT =
(
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT =
(
1, 0x2, 0x2),
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT =
(
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_PROXIMITY_DOMAIN_ATTRIBUTES_INIT =
(
1, 0x3, 0x3),
},
=20
// Latency Info
- EFI_ACPI_6_3_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO=
_INIT (
- 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT, 10=
0),
+ EFI_ACPI_6_4_HMAT_STRUCTURE_SYSTEM_LOCALITY_LATENCY_AND_BANDWIDTH_INFO=
_INIT (
+ 0, 0, 0, INITATOR_PROXIMITY_DOMAIN_CNT, TARGET_PROXIMITY_DOMAIN_CNT,=
100),
{
{0, 1, 2, 3},
{0, 1, 2, 3},
@@ -90,7 +98,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D =
{
},
=20
// Memory Side Cache
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x0,
SIZE_1GB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
@@ -102,7 +110,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D=
{
),
0),
=20
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x1,
SIZE_1GB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
@@ -114,7 +122,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D=
{
),
0),
=20
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x2,
SIZE_1GB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
@@ -126,7 +134,7 @@ EFI_ACPI_HETEROGENEOUS_MEMORY_ATTRIBUTE_TABLE Hmat =3D=
{
),
0),
=20
- EFI_ACPI_6_3_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
+ EFI_ACPI_6_4_HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_INIT (
0x3,
SIZE_1GB,
HMAT_STRUCTURE_MEMORY_SIDE_CACHE_INFO_CACHE_ATTRIBUTES_INIT (
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc b/Platform/A=
RM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc
index 9b3e4f2be370..67687d627670 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Madt.aslc
@@ -1,18 +1,24 @@
/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2020, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Multiple APIC Description Table (MADT)
+
+ The MADT table provides OSPM with information necessary for operation =
on
+ systems with Generic interrupt controller (GIC). The information about=
the GIC
+ CPU interface, redistributor, distributor and ITS blocks on the Rd-V1
+ multichip platform is included in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.12, Multiple APIC Description Tab=
le
**/
=20
-#include "SgiPlatform.h"
-#include "SgiAcpiHeader.h"
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
=20
#define CORE_CNT (FixedPcdGet32 (PcdClusterCount) * \
FixedPcdGet32 (PcdCoreCount))
@@ -22,125 +28,126 @@
#pragma pack (1)
=20
typedef struct {
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_2_GIC_STRUCTURE GicInterfaces[COR=
E_CNT * CHIP_CNT];
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_2_GICR_STRUCTURE GicRedistributor[=
CHIP_CNT];
- EFI_ACPI_6_2_GIC_ITS_STRUCTURE GicIts[4];
-} EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE;
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
+ EFI_ACPI_6_4_GIC_STRUCTURE GicInterfaces[COR=
E_CNT * CHIP_CNT];
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
+ EFI_ACPI_6_4_GICR_STRUCTURE GicRedistributor[=
CHIP_CNT];
+ EFI_ACPI_6_4_GIC_ITS_STRUCTURE GicIts[4];
+} EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE;
=20
#pragma pack ()
=20
-STATIC EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D {
+STATIC EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE Madt =3D {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE,
+ EFI_ACPI_6_4_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
),
// MADT specific fields
0, // LocalApicAddress
0 // Flags
},
{
- // Format: EFI_ACPI_6_2_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr=
, Flags,
+ // Format: EFI_ACPI_6_4_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Mpidr=
, Flags,
// PmuIrq, GicBase, GicVBas=
e,
// GicHBase, GsivId, GicRBa=
se,
- // Efficiency)
+ // Efficiency,
+ // SpeOverflowInterrupt)
// Note: The GIC Structure of the primary CPU must be the first entr=
y
- // (see note in 5.2.12.14 GICC Structure of ACPI v6.2).
+ // (see note in 5.2.12.14 GICC Structure of ACPI v6.4).
//Chip 0
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
- 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 0, GET_MPID(0x0, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
- 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 1, GET_MPID(0x100, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
- 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 2, GET_MPID(0x200, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
- 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 3, GET_MPID(0x300, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
=20
// Chip 1
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
- 0, 4, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 4, GET_MPID(0x01000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
- 0, 5, GET_MPID(0x01000100ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 5, GET_MPID(0x01000100ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
- 0, 6, GET_MPID(0x01000200ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 6, GET_MPID(0x01000200ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
- 0, 7, GET_MPID(0x01000300ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 7, GET_MPID(0x01000300ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
=20
// Chip 2
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
- 0, 8, GET_MPID(0x02000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 8, GET_MPID(0x02000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
- 0, 9, GET_MPID(0x02000100ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 9, GET_MPID(0x02000100ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
- 0, 10, GET_MPID(0x02000200ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 10, GET_MPID(0x02000200ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
- 0, 11, GET_MPID(0x02000300ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 11, GET_MPID(0x02000300ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
=20
// Chip 3
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core0
- 0, 12, GET_MPID(0x03000000ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core0
+ 0, 12, GET_MPID(0x03000000ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core1
- 0, 13, GET_MPID(0x03000100ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core1
+ 0, 13, GET_MPID(0x03000100ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core2
- 0, 14, GET_MPID(0x03000200ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core2
+ 0, 14, GET_MPID(0x03000200ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
- EFI_ACPI_6_2_GICC_STRUCTURE_INIT( // Zeus core3
- 0, 15, GET_MPID(0x03000300ULL, 0x0), EFI_ACPI_6_2_GIC_ENABLED, 23,
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
+ EFI_ACPI_6_4_GICC_STRUCTURE_INIT( // Zeus core3
+ 0, 15, GET_MPID(0x03000300ULL, 0x0), EFI_ACPI_6_4_GIC_ENABLED, 23,
FixedPcdGet32 (PcdGicDistributorBase),
- 0x2c020000, 0x2c010000, 25, 0 /* GicRBase */, 0 /* Efficiency */),
+ 0x2c020000, 0x2c010000, 25, 0, 0, 0),
},
// GIC Distributor Entry
- EFI_ACPI_6_2_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorB=
ase),
+ EFI_ACPI_6_4_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet32 (PcdGicDistributorB=
ase),
0, 3),
{
// GIC Redistributor
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistribut=
orsBase) +
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistribut=
orsBase) +
SGI_REMOTE_CHIP_MEM_OFFSET(0), SIZE_16MB),
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistribut=
orsBase) +
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistribut=
orsBase) +
SGI_REMOTE_CHIP_MEM_OFFSET(1), SIZE_16MB),
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistribut=
orsBase) +
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistribut=
orsBase) +
SGI_REMOTE_CHIP_MEM_OFFSET(2), SIZE_16MB),
- EFI_ACPI_6_2_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistribut=
orsBase) +
+ EFI_ACPI_6_4_GIC_REDISTRIBUTOR_INIT(FixedPcdGet32 (PcdGicRedistribut=
orsBase) +
SGI_REMOTE_CHIP_MEM_OFFSET(3), SIZE_16MB)
},
// GIC ITS
{
- EFI_ACPI_6_2_GIC_ITS_INIT(0, 0x30040000),
- EFI_ACPI_6_2_GIC_ITS_INIT(1, 0x30080000),
- EFI_ACPI_6_2_GIC_ITS_INIT(2, 0x300C0000),
- EFI_ACPI_6_2_GIC_ITS_INIT(3, 0x30100000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(0, 0x30040000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(1, 0x30080000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(2, 0x300C0000),
+ EFI_ACPI_6_4_GIC_ITS_INIT(3, 0x30100000),
},
};
=20
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc b/Platform/A=
RM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
index 82124ca2ab65..a99b683eb66c 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Pptt.aslc
@@ -1,29 +1,27 @@
/** @file
-* Processor Properties Topology Table (PPTT) for RD-V1 quad-chip platfor=
m
-*
-* This file describes the topological structure of the processor block o=
n the
-* RD-V1 quad-chip platform in the form as defined by ACPI PPTT table. Th=
e RD-V1
-* quad-chip platform is composed of four identical chips connected over =
cache
-* coherent interconnect. Each of the chip on the platform includes four =
single
-* thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Inst=
ruction
-* cache and 1MB L2 cache. The platform also includes a system level cach=
e of
-* 16MB per chip.
-*
-* Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* @par Specification Reference:
-* - ACPI 6.3, Chapter 5, Section 5.2.29, Processor Properties Topology=
Table
+ Processor Properties Topology Table (PPTT) for RD-V1 quad-chip platfor=
m
+
+ This file describes the topological structure of the processor block o=
n the
+ RD-V1 quad-chip platform in the form as defined by ACPI PPTT table. Th=
e RD-V1
+ quad-chip platform is composed of four identical chips connected over =
cache
+ coherent interconnect. Each of the chip on the platform includes four =
single
+ thread CPUS. Each of the CPUs include 64KB L1 Data cache, 64KB L1 Inst=
ruction
+ cache and 1MB L2 cache. The platform also includes a system level cach=
e of
+ 16MB per chip.
+
+ Copyright (c) 2021 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.29, Processor Properties Topology=
Table
**/
=20
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
#include <Library/PcdLib.h>
-
-#include "SgiPlatform.h"
#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
=20
#define CHIP_COUNT FixedPcdGet32 (PcdChipCount)
=20
@@ -36,10 +34,10 @@
#define PPTT_CORE_INIT(PackageId, ClusterId, CpuId) =
\
{ =
\
/* Parameters for CPU Core */ =
\
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
OFFSET_OF (RD_PPTT_CORE, DCache), /* Length */ =
\
PPTT_PROCESSOR_CORE_FLAGS, /* Flag */ =
\
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
Package[PackageId].Cluster[ClusterId]), /* Parent */ =
\
((PackageId << 2) | ClusterId), /* ACPI Id */ =
\
2 /* Num of private resource *=
/ \
@@ -47,47 +45,53 @@
=
\
/* Offsets of the private resources */ =
\
{ =
\
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
Package[PackageId].Cluster[ClusterId].Core[CpuId].DCache), =
\
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
Package[PackageId].Cluster[ClusterId].Core[CpuId].ICache) =
\
}, =
\
=
\
/* L1 data cache parameters */ =
\
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( =
\
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), =
\
/* Next level of cache */ =
\
SIZE_64KB, /* Size */ =
\
256, /* Num of sets */ =
\
4, /* Associativity */ =
\
PPTT_DATA_CACHE_ATTR, /* Attributes */ =
\
- 64 /* Line size */ =
\
+ 64, /* Line size */ =
\
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1DataCache) =
\
+ /* Cache id */ =
\
), =
\
=
\
/* L1 instruction cache parameters */ =
\
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( =
\
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
Package[PackageId].Cluster[ClusterId].Core[CpuId].L2Cache), =
\
/* Next level of cache */ =
\
SIZE_64KB, /* Size */ =
\
256, /* Num of sets */ =
\
4, /* Associativity */ =
\
PPTT_INST_CACHE_ATTR, /* Attributes */ =
\
- 64 /* Line size */ =
\
+ 64, /* Line size */ =
\
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L1InstructionCache) =
\
+ /* Cache id */ =
\
), =
\
=
\
/* L2 cache parameters */ =
\
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE_INIT ( =
\
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_INIT ( =
\
PPTT_CACHE_STRUCTURE_FLAGS, /* Flag */ =
\
0, /* Next level of cache */ =
\
SIZE_1MB, /* Size */ =
\
2048, /* Num of sets */ =
\
8, /* Associativity */ =
\
PPTT_UNIFIED_CACHE_ATTR, /* Attributes */ =
\
- 64 /* Line size */ =
\
+ 64, /* Line size */ =
\
+ RD_PPTT_CACHE_ID(PackageId, ClusterId, CpuId, L2Cache) =
\
+ /* Cache id */ =
\
), =
\
}
=20
@@ -99,10 +103,10 @@
#define PPTT_CLUSTER_INIT(PackageId, ClusterId) =
\
{ =
\
/* Parameters for Cluster */ =
\
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
OFFSET_OF (RD_PPTT_MINIMAL_CLUSTER, Core), /* Length */ =
\
PPTT_PROCESSOR_CLUSTER_FLAGS, /* Flag */ =
\
- OFFSET_OF (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
+ OFFSET_OF (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE, =
\
Package[PackageId]), /* Parent */ =
\
((PackageId << 2) | ClusterId), /* ACPI Id */ =
\
0 /* Num of private resource *=
/ \
@@ -120,7 +124,7 @@
**/
#define PPTT_PACKAGE_INIT(PackageId) =
\
{ =
\
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR_INIT ( =
\
OFFSET_OF (RD_PPTT_PACKAGE, Cluster[0]), /* Length */ =
\
PPTT_PROCESSOR_PACKAGE_FLAGS, /* Flag */ =
\
0, /* Parent */ =
\
@@ -140,17 +144,17 @@
* Processor Properties Topology Table
*/
typedef struct {
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER Header;
RD_PPTT_PACKAGE Package[CHIP_=
COUNT];
-} EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
+} EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE;
#pragma pack ()
=20
-STATIC EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D {
+STATIC EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE Pptt =3D {
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU=
RE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATU=
RE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
)
},
=20
diff --git a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc b/Platform/A=
RM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc
index 2ad72e3878c2..b12db67dfe3f 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/RdV1Mc/Srat.aslc
@@ -1,17 +1,23 @@
/** @file
-* Static Resource Affinity Table (SRAT)
-*
-* Copyright (c) 2020, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
+ Static Resource Affinity Table (SRAT)
+
+ SRAT table provides information that allows OSPM to associate devices =
such as
+ processors with system locality / proximity domains and clock domains.=
The
+ memory attached to the two chips on this platform and its affinity to =
the
+ CPUs on its respective chips is listed in this table.
+
+ Copyright (c) 2020 - 2022, Arm Limited. All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.4, Chapter 5, Section 5.2.16, System Resource Affinity Tabl=
e
**/
=20
-#include "SgiAcpiHeader.h"
-#include "SgiPlatform.h"
-#include <IndustryStandard/Acpi.h>
#include <Library/AcpiLib.h>
#include <Library/ArmLib.h>
+#include "SgiAcpiHeader.h"
+#include "SgiPlatform.h"
=20
//
// Static Resource Affinity Table
@@ -19,9 +25,9 @@
#pragma pack (1)
=20
typedef struct {
- EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE Memory[8];
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE Gicc[16];
+ EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER Header;
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE Memory[8];
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE Gicc[16];
} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
=20
#pragma pack ()
@@ -30,9 +36,9 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat =3D {
// Header
{
ARM_ACPI_HEADER (
- EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
+ EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE,
- EFI_ACPI_6_3_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION
+ EFI_ACPI_6_4_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION
),
0x00000001,
EFI_ACPI_RESERVED_QWORD
@@ -40,70 +46,70 @@ EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat =3D {
// Memory Affinity
{
// Chip 0 (2GB and 6GB)
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x0, FixedPcdGet64 (PcdSystemMemoryBase),
FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x0, FixedPcdGet64 (PcdDramBlock2Base),
FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
=20
// Chip 1 (2GB and 6GB)
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x1, SYSTEM_MEMORY_BASE_REMOTE(1),
FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x1, DRAM_BLOCK2_BASE_REMOTE(1),
FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
=20
// Chip 2 (2GB and 6GB)
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x2, SYSTEM_MEMORY_BASE_REMOTE(2),
FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT (
0x2, DRAM_BLOCK2_BASE_REMOTE(2),
FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
=20
// Chip 3 (2GB and 6GB)
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT(
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT(
0x3, SYSTEM_MEMORY_BASE_REMOTE(3),
FixedPcdGet64 (PcdSystemMemorySize), 0x00000001),
- EFI_ACPI_6_3_MEMORY_AFFINITY_STRUCTURE_INIT(
+ EFI_ACPI_6_4_MEMORY_AFFINITY_STRUCTURE_INIT(
0x3, DRAM_BLOCK2_BASE_REMOTE(3),
FixedPcdGet64 (PcdDramBlock2Size), 0x00000001),
},
// Processor Affinity
{
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000000, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000001, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000002, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x0, 0x00000003, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x00000004, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x00000005, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x00000006, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x1, 0x00000007, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x2, 0x00000008, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x2, 0x00000009, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x2, 0x0000000A, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x2, 0x0000000B, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x3, 0x0000000C, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x3, 0x0000000D, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x3, 0x0000000E, 0x00000001, 0x00000000),
- EFI_ACPI_6_3_GICC_AFFINITY_STRUCTURE_INIT (
+ EFI_ACPI_6_4_GICC_AFFINITY_STRUCTURE_INIT (
0x3, 0x0000000F, 0x00000001, 0x00000000),
},
};
--=20
2.25.1