[edk2-platforms][PATCH V1 07/11] Platform/ARM/Morello: Port PCI Express library


chandni cherukuri
 

From: Anurag Koul <anurag.koul@arm.com>

Morello platform requires a custom platform-specific PCI Express
library because the native PCI Express Library only allows for a
single ECAM config address to be supplied to it. If there is more
than one PCIe root port, it expects the ECAM regions for all the
root ports to be contiguous. This is not the case with Morello where
the two RPs have their ECAM regions mapped to non-contiguous address
ranges and reside in separate PCIe segments.

This custom plaform-specific PCI Express library, inherited from
MdePkg/BasePciExpressLib, routes the ECAM accesses to the appropriate
ECAM region based on the PCIe segment number in the incoming PCIe
address.

Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
---
Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.inf | 49 +
Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.c | 1431 ++++++++++++++++++++
Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.uni | 18 +
3 files changed, 1498 insertions(+)

diff --git a/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.inf b/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.inf
new file mode 100644
index 000000000000..71a2cf3a6276
--- /dev/null
+++ b/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.inf
@@ -0,0 +1,49 @@
+## @file
+# Instance of PCI Express Library using the 256 MB PCI Express MMIO window.
+#
+# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform
+# PCI Configuration cycles. Layers on top of an I/O Library instance.
+#
+# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
+#
+# This library is inherited from MdePkg/Library/BasePciExpressLib to work with
+# non-contiguous ECAM regions for the two supported PCIe root ports. The
+# base PCI Express library expects the ECAM space for all the available root
+# ports to be contiguous and hence exposes only a single hook(variable) to
+# hold the ECAM base address informaion in.
+
+# This library reinterprets the ECAM accesses and routes them to the
+# appropriate Root Port Config based on the PCIe segment number in the
+# incoming PCIe address.
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = PciExpressLib
+ MODULE_UNI_FILE = PciExpressLib.uni
+ FILE_GUID = 795fad20-e353-45f8-b77f-c59eb7907370
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciExpressLib
+
+[Sources]
+ PciExpressLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/ARM/Morello/MorelloPlatform.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+ PcdLib
+
+[Pcd]
+ gArmMorelloTokenSpaceGuid.PcdCcixExpressBaseAddress ## CONSUMES
+ gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
diff --git a/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.c b/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.c
new file mode 100644
index 000000000000..8f0652dc6678
--- /dev/null
+++ b/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.c
@@ -0,0 +1,1431 @@
+/** @file
+ Functions in this library instance make use of MMIO functions in IoLib to
+ access memory mapped PCI configuration space.
+
+ All assertions for I/O operations are handled in MMIO functions in the IoLib
+ Library.
+
+ Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+
+ On Morello platform, the PCIe ECAM regions for the two supported Root Ports,
+ which lie in separate PCIe segments, are not contiguous. As such, any ECAM
+ access from the PCI Express library should ideally be routed based on the
+ segment number within the incoming address, which is configured in the
+ platform PCI Host Bridge library.
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciExpressLib.h>
+#include <Library/PcdLib.h>
+#include <MorelloPlatform.h>
+
+/**
+ Assert the validity of a PCI address. A valid PCI address may contain 1's
+ only in the low 33 bits. Bit 32 carries the segment number which could be
+ either 0 or 1.
+
+ @param A The address to validate.
+
+**/
+#define ASSERT_INVALID_PCI_ADDRESS(A) \
+ ASSERT (((A) & ~0x1ffffffffULL) == 0)
+
+#define GET_SEG_NUM(Address) ((Address >> 32ULL) & 0x1)
+
+/**
+ Registers a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ Registers the PCI device specified by Address so all the PCI configuration
+ registers associated with that PCI device may be accessed after
+ SetVirtualAddressMap() is called.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ The resources required to access the PCI
+ device at runtime could not be mapped.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciExpressRegisterForRuntimeAccess (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return RETURN_UNSUPPORTED;
+}
+
+/**
+ Gets the base address of PCI Express.
+
+ This internal functions retrieves PCI Express Base Address via a PCD entry.
+
+ @param [in] Address The address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+
+ @return The converted address relative to PCI Root's ECAM base address.
+
+**/
+STATIC
+VOID *
+GetPciExpressAddress (
+ IN UINTN Address
+ )
+{
+ UINTN ConvAddress;
+
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+
+ if (GET_SEG_NUM (Address) == 0) {
+ ConvAddress = PcdGet64 (PcdPciExpressBaseAddress) + (UINT32)Address;
+ } else if (GET_SEG_NUM (Address) == 1) {
+ ConvAddress = PcdGet64 (PcdCcixExpressBaseAddress) + (UINT32)Address;
+ } else {
+ DEBUG ((DEBUG_ERROR, "PciExpressLib: Invalid PCIe Address.\n"));
+ ASSERT (FALSE);
+ return NULL;
+ }
+
+ return (VOID *)ConvAddress;
+}
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressRead8 (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioRead8 ((UINTN)GetPciExpressAddress (Address));
+}
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressWrite8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+
+ return MmioWrite8 ((UINTN)GetPciExpressAddress (Address), Value);
+}
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with
+ an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressOr8 (
+ IN UINTN Address,
+ IN UINT8 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioOr8 ((UINTN)GetPciExpressAddress (Address), OrData);
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
+ value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressAnd8 (
+ IN UINTN Address,
+ IN UINT8 AndData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioAnd8 ((UINTN)GetPciExpressAddress (Address), AndData);
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
+ value, followed a bitwise OR with another 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] AndData The value to AND with the PCI configuration register.
+ @param [in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressAndThenOr8 (
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioAndThenOr8 (
+ (UINTN)GetPciExpressAddress (Address),
+ AndData,
+ OrData
+ );
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to read.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..7.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressBitFieldRead8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldRead8 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit
+ );
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..7.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..7.
+ @param [in] Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressBitFieldWrite8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldWrite8 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ Value
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..7.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..7.
+ @param [in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressBitFieldOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldOr8 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ OrData
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..7.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..7.
+ @param [in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressBitFieldAnd8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldAnd8 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ AndData
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..7.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..7.
+ @param [in] AndData The value to AND with the PCI configuration register.
+ @param [in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressBitFieldAndThenOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldAndThenOr8 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ AndData,
+ OrData
+ );
+}
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressRead16 (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioRead16 ((UINTN)GetPciExpressAddress (Address));
+}
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+
+ return MmioWrite16 ((UINTN)GetPciExpressAddress (Address), Value);
+}
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressOr16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioOr16 ((UINTN)GetPciExpressAddress (Address), OrData);
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressAnd16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioAnd16 ((UINTN)GetPciExpressAddress (Address), AndData);
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value, followed a bitwise OR with another 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] AndData The value to AND with the PCI configuration register.
+ @param [in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressAndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioAndThenOr16 (
+ (UINTN)GetPciExpressAddress (Address),
+ AndData,
+ OrData
+ );
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to read.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..15.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressBitFieldRead16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldRead16 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit
+ );
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..15.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..15.
+ @param [in] Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressBitFieldWrite16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldWrite16 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ Value
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..15.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..15.
+ @param [in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressBitFieldOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldOr16 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ OrData
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 16-bit register.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..15.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..15.
+ @param [in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressBitFieldAnd16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldAnd16 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ AndData
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..15.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..15.
+ @param [in] AndData The value to AND with the PCI configuration register.
+ @param [in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressBitFieldAndThenOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldAndThenOr16 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ AndData,
+ OrData
+ );
+}
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressRead32 (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioRead32 ((UINTN)GetPciExpressAddress (Address));
+}
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Value);
+}
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with
+ a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressOr32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioOr32 ((UINTN)GetPciExpressAddress (Address), OrData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
+ value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressAnd32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioAnd32 ((UINTN)GetPciExpressAddress (Address), AndData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
+ value, followed a bitwise OR with another 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] AndData The value to AND with the PCI configuration register.
+ @param [in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressAndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioAndThenOr32 (
+ (UINTN)GetPciExpressAddress (Address),
+ AndData,
+ OrData
+ );
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to read.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..31.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressBitFieldRead32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldRead32 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit
+ );
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..31.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..31.
+ @param [in] Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressBitFieldWrite32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldWrite32 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ Value
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..31.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..31.
+ @param [in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressBitFieldOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldOr32 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ OrData
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..31.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..31.
+ @param [in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressBitFieldAnd32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldAnd32 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ AndData
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..31.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..31.
+ @param [in] AndData The value to AND with the PCI configuration register.
+ @param [in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressBitFieldAndThenOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldAndThenOr32 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ AndData,
+ OrData
+ );
+}
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If StartAddress > 0x1FFFFFFFF, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param [in] StartAddress The starting address that encodes the PCI Bus,
+ Device, Function and Register.
+ @param [in] Size The size in bytes of the transfer.
+ @param [out] Buffer The pointer to a buffer receiving the data read.
+
+ @return Size read data from StartAddress.
+
+**/
+UINTN
+EFIAPI
+PciExpressReadBuffer (
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_ADDRESS (StartAddress);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return Size;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ // Save Size for return
+ ReturnValue = Size;
+
+ if ((StartAddress & 1) != 0) {
+ // Read a byte if StartAddress is byte aligned
+ *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
+ }
+
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {
+ // Read a word if StartAddress is word aligned
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));
+
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ // Read as many double words as possible
+ WriteUnaligned32 ((UINT32 *)Buffer, (UINT32)PciExpressRead32 (StartAddress));
+
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ // Read the last remaining word if exist
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ // Read the last remaining byte if exist
+ *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
+ }
+
+ return ReturnValue;
+}
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If StartAddress > 0x1FFFFFFFF, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param [in] StartAddress The starting address that encodes the PCI Bus,
+ Device, Function and Register.
+ @param [in] Size The size in bytes of the transfer.
+ @param [in] Buffer The pointer to a buffer containing the data to write.
+
+ @return Size written to StartAddress.
+
+**/
+UINTN
+EFIAPI
+PciExpressWriteBuffer (
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_ADDRESS (StartAddress);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return 0;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ // Save Size for return
+ ReturnValue = Size;
+
+ if ((StartAddress & 1) != 0) {
+ // Write a byte if StartAddress is byte aligned
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
+ }
+
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {
+ // Write a word if StartAddress is word aligned
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ // Write as many double words as possible
+ PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32 *)Buffer));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ // Write the last remaining word if exist
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ // Write the last remaining byte if exist
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);
+ }
+
+ return ReturnValue;
+}
diff --git a/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.uni b/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.uni
new file mode 100644
index 000000000000..540453d4a189
--- /dev/null
+++ b/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.uni
@@ -0,0 +1,18 @@
+// /** @file
+// Instance of PCI Express Library using the 256 MB PCI Express MMIO window.
+//
+// PCI Express Library that uses the 256 MB PCI Express MMIO window to perform
+// PCI Configuration cycles. Layers on top of an I/O Library instance.
+//
+// Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
+//
+// Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Instance of PCI Express Library using the 256 MB PCI Express MMIO window"
+
+#string STR_MODULE_DESCRIPTION #language en-US "PCI Express Library that uses the 256 MB PCI Express MMIO window to perform PCI Configuration cycles. Layers on top of an I/O Library instance."
--
2.17.1


Sami Mujawar
 

Hi Chandni,

Thank you for this patch.

Please find my feedback inline marked [SAMI].

With those addressed.

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar


On 04/12/2021 12:30 PM, Chandni Cherukuri wrote:
From: Anurag Koul <anurag.koul@arm.com>

Morello platform requires a custom platform-specific PCI Express
library because the native PCI Express Library only allows for a
single ECAM config address to be supplied to it. If there is more
than one PCIe root port, it expects the ECAM regions for all the
root ports to be contiguous. This is not the case with Morello where
the two RPs have their ECAM regions mapped to non-contiguous address
ranges and reside in separate PCIe segments.

This custom plaform-specific PCI Express library, inherited from
MdePkg/BasePciExpressLib, routes the ECAM accesses to the appropriate
ECAM region based on the PCIe segment number in the incoming PCIe
address.

Signed-off-by: Anurag Koul <anurag.koul@arm.com>
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
---
Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.inf | 49 +
Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.c | 1431 ++++++++++++++++++++
Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.uni | 18 +
3 files changed, 1498 insertions(+)

diff --git a/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.inf b/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.inf
new file mode 100644
index 000000000000..71a2cf3a6276
--- /dev/null
+++ b/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.inf
@@ -0,0 +1,49 @@
+## @file
+# Instance of PCI Express Library using the 256 MB PCI Express MMIO window.
+#
+# PCI Express Library that uses the 256 MB PCI Express MMIO window to perform
+# PCI Configuration cycles. Layers on top of an I/O Library instance.
+#
+# Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
+#
+# This library is inherited from MdePkg/Library/BasePciExpressLib to work with
+# non-contiguous ECAM regions for the two supported PCIe root ports. The
+# base PCI Express library expects the ECAM space for all the available root
+# ports to be contiguous and hence exposes only a single hook(variable) to
+# hold the ECAM base address informaion in.
+
+# This library reinterprets the ECAM accesses and routes them to the
+# appropriate Root Port Config based on the PCIe segment number in the
+# incoming PCIe address.
[SAMI] Is it possible to keep the copyright list together, please? Maybe
it would be good to move the comment above at the beginning of the file.
[/SAMI]
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = PciExpressLib
+ MODULE_UNI_FILE = PciExpressLib.uni
+ FILE_GUID = 795fad20-e353-45f8-b77f-c59eb7907370
+ MODULE_TYPE = BASE
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciExpressLib
+
+[Sources]
+ PciExpressLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ Platform/ARM/Morello/MorelloPlatform.dec
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ IoLib
+ PcdLib
+
+[Pcd]
+ gArmMorelloTokenSpaceGuid.PcdCcixExpressBaseAddress ## CONSUMES
+ gArmMorelloTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES
diff --git a/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.c b/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.c
new file mode 100644
index 000000000000..8f0652dc6678
--- /dev/null
+++ b/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.c
@@ -0,0 +1,1431 @@
+/** @file
+ Functions in this library instance make use of MMIO functions in IoLib to
+ access memory mapped PCI configuration space.
+
+ All assertions for I/O operations are handled in MMIO functions in the IoLib
+ Library.
+
+ Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+
+ On Morello platform, the PCIe ECAM regions for the two supported Root Ports,
+ which lie in separate PCIe segments, are not contiguous. As such, any ECAM
+ access from the PCI Express library should ideally be routed based on the
+ segment number within the incoming address, which is configured in the
+ platform PCI Host Bridge library.
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Base.h>
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciExpressLib.h>
+#include <Library/PcdLib.h>
+#include <MorelloPlatform.h>
+
+/**
+ Assert the validity of a PCI address. A valid PCI address may contain 1's
+ only in the low 33 bits. Bit 32 carries the segment number which could be
+ either 0 or 1.
+
+ @param A The address to validate.
+
+**/
+#define ASSERT_INVALID_PCI_ADDRESS(A) \
+ ASSERT (((A) & ~0x1ffffffffULL) == 0)
+
+#define GET_SEG_NUM(Address) ((Address >> 32ULL) & 0x1)
+
+/**
+ Registers a PCI device so PCI configuration registers may be accessed after
+ SetVirtualAddressMap().
+
+ Registers the PCI device specified by Address so all the PCI configuration
+ registers associated with that PCI device may be accessed after
+ SetVirtualAddressMap() is called.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @retval RETURN_UNSUPPORTED An attempt was made to call this function
+ after ExitBootServices().
+ The resources required to access the PCI
+ device at runtime could not be mapped.
+
+**/
+RETURN_STATUS
+EFIAPI
+PciExpressRegisterForRuntimeAccess (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return RETURN_UNSUPPORTED;
+}
+
+/**
+ Gets the base address of PCI Express.
+
+ This internal functions retrieves PCI Express Base Address via a PCD entry.
+
+ @param [in] Address The address that encodes the PCI Segment, Bus, Device,
+ Function and Register.
+
+ @return The converted address relative to PCI Root's ECAM base address.
+
+**/
+STATIC
+VOID *
[SAMI] Can the return type be changed to UINTN? It would remove the need
to typecase every time this function is used.
+GetPciExpressAddress (
+ IN UINTN Address
+ )
+{
+ UINTN ConvAddress;
+
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+
+ if (GET_SEG_NUM (Address) == 0) {
+ ConvAddress = PcdGet64 (PcdPciExpressBaseAddress) + (UINT32)Address;
+ } else if (GET_SEG_NUM (Address) == 1) {
+ ConvAddress = PcdGet64 (PcdCcixExpressBaseAddress) + (UINT32)Address;
+ } else {
+ DEBUG ((DEBUG_ERROR, "PciExpressLib: Invalid PCIe Address.\n"));
+ ASSERT (FALSE);
+ return NULL;
+ }
+
+ return (VOID *)ConvAddress;
+}
+
+/**
+ Reads an 8-bit PCI configuration register.
+
+ Reads and returns the 8-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressRead8 (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioRead8 ((UINTN)GetPciExpressAddress (Address));
+}
+
+/**
+ Writes an 8-bit PCI configuration register.
+
+ Writes the 8-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressWrite8 (
+ IN UINTN Address,
+ IN UINT8 Value
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+
+ return MmioWrite8 ((UINTN)GetPciExpressAddress (Address), Value);
+}
+
+/**
+ Performs a bitwise OR of an 8-bit PCI configuration register with
+ an 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressOr8 (
+ IN UINTN Address,
+ IN UINT8 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioOr8 ((UINTN)GetPciExpressAddress (Address), OrData);
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
+ value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressAnd8 (
+ IN UINTN Address,
+ IN UINT8 AndData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioAnd8 ((UINTN)GetPciExpressAddress (Address), AndData);
+}
+
+/**
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit
+ value, followed a bitwise OR with another 8-bit value.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] AndData The value to AND with the PCI configuration register.
+ @param [in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressAndThenOr8 (
+ IN UINTN Address,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioAndThenOr8 (
+ (UINTN)GetPciExpressAddress (Address),
+ AndData,
+ OrData
+ );
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to read.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..7.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..7.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressBitFieldRead8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldRead8 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit
+ );
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 8-bit register is returned.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..7.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..7.
+ @param [in] Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressBitFieldWrite8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 Value
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldWrite8 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ Value
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 8-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..7.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..7.
+ @param [in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressBitFieldOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldOr8 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ OrData
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 8-bit register.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 8-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..7.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..7.
+ @param [in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressBitFieldAnd8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldAnd8 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ AndData
+ );
+}
+
+/**
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 8-bit port.
+
+ Reads the 8-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 8-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If StartBit is greater than 7, then ASSERT().
+ If EndBit is greater than 7, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..7.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..7.
+ @param [in] AndData The value to AND with the PCI configuration register.
+ @param [in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT8
+EFIAPI
+PciExpressBitFieldAndThenOr8 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldAndThenOr8 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ AndData,
+ OrData
+ );
+}
+
+/**
+ Reads a 16-bit PCI configuration register.
+
+ Reads and returns the 16-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressRead16 (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioRead16 ((UINTN)GetPciExpressAddress (Address));
+}
+
+/**
+ Writes a 16-bit PCI configuration register.
+
+ Writes the 16-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressWrite16 (
+ IN UINTN Address,
+ IN UINT16 Value
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+
+ return MmioWrite16 ((UINTN)GetPciExpressAddress (Address), Value);
+}
+
+/**
+ Performs a bitwise OR of a 16-bit PCI configuration register with
+ a 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressOr16 (
+ IN UINTN Address,
+ IN UINT16 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioOr16 ((UINTN)GetPciExpressAddress (Address), OrData);
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressAnd16 (
+ IN UINTN Address,
+ IN UINT16 AndData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioAnd16 ((UINTN)GetPciExpressAddress (Address), AndData);
+}
+
+/**
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit
+ value, followed a bitwise OR with another 16-bit value.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] AndData The value to AND with the PCI configuration register.
+ @param [in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressAndThenOr16 (
+ IN UINTN Address,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioAndThenOr16 (
+ (UINTN)GetPciExpressAddress (Address),
+ AndData,
+ OrData
+ );
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to read.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..15.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..15.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressBitFieldRead16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldRead16 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit
+ );
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 16-bit register is returned.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..15.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..15.
+ @param [in] Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressBitFieldWrite16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 Value
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldWrite16 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ Value
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 16-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..15.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..15.
+ @param [in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressBitFieldOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldOr16 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ OrData
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 16-bit register.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 16-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..15.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..15.
+ @param [in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressBitFieldAnd16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldAnd16 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ AndData
+ );
+}
+
+/**
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 16-bit port.
+
+ Reads the 16-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 16-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 16-bit boundary, then ASSERT().
+ If StartBit is greater than 15, then ASSERT().
+ If EndBit is greater than 15, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..15.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..15.
+ @param [in] AndData The value to AND with the PCI configuration register.
+ @param [in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT16
+EFIAPI
+PciExpressBitFieldAndThenOr16 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldAndThenOr16 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ AndData,
+ OrData
+ );
+}
+
+/**
+ Reads a 32-bit PCI configuration register.
+
+ Reads and returns the 32-bit PCI configuration register specified by Address.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+
+ @return The read value from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressRead32 (
+ IN UINTN Address
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioRead32 ((UINTN)GetPciExpressAddress (Address));
+}
+
+/**
+ Writes a 32-bit PCI configuration register.
+
+ Writes the 32-bit PCI configuration register specified by Address with the
+ value specified by Value. Value is returned. This function must guarantee
+ that all PCI read and write operations are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] Value The value to write.
+
+ @return The value written to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressWrite32 (
+ IN UINTN Address,
+ IN UINT32 Value
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioWrite32 ((UINTN)GetPciExpressAddress (Address), Value);
+}
+
+/**
+ Performs a bitwise OR of a 32-bit PCI configuration register with
+ a 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressOr32 (
+ IN UINTN Address,
+ IN UINT32 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioOr32 ((UINTN)GetPciExpressAddress (Address), OrData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
+ value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressAnd32 (
+ IN UINTN Address,
+ IN UINT32 AndData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioAnd32 ((UINTN)GetPciExpressAddress (Address), AndData);
+}
+
+/**
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit
+ value, followed a bitwise OR with another 32-bit value.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData,
+ performs a bitwise OR between the result of the AND operation and
+ the value specified by OrData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+
+ @param [in] Address The address that encodes the PCI Bus, Device, Function and
+ Register.
+ @param [in] AndData The value to AND with the PCI configuration register.
+ @param [in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressAndThenOr32 (
+ IN UINTN Address,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioAndThenOr32 (
+ (UINTN)GetPciExpressAddress (Address),
+ AndData,
+ OrData
+ );
+}
+
+/**
+ Reads a bit field of a PCI configuration register.
+
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is
+ specified by the StartBit and the EndBit. The value of the bit field is
+ returned.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to read.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..31.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..31.
+
+ @return The value of the bit field read from the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressBitFieldRead32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldRead32 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit
+ );
+}
+
+/**
+ Writes a bit field to a PCI configuration register.
+
+ Writes Value to the bit field of the PCI configuration register. The bit
+ field is specified by the StartBit and the EndBit. All other bits in the
+ destination PCI configuration register are preserved. The new value of the
+ 32-bit register is returned.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If Value is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..31.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..31.
+ @param [in] Value The new value of the bit field.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressBitFieldWrite32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 Value
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldWrite32 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ Value
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and
+ writes the result back to the bit field in the 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise OR between the read result and the value specified by
+ OrData, and writes the result to the 32-bit PCI configuration register
+ specified by Address. The value written to the PCI configuration register is
+ returned. This function must guarantee that all PCI read and write operations
+ are serialized. Extra left bits in OrData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..31.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..31.
+ @param [in] OrData The value to OR with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressBitFieldOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldOr32 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ OrData
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise
+ AND, and writes the result back to the bit field in the 32-bit register.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND between the read result and the value specified by AndData, and
+ writes the result to the 32-bit PCI configuration register specified by
+ Address. The value written to the PCI configuration register is returned.
+ This function must guarantee that all PCI read and write operations are
+ serialized. Extra left bits in AndData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..31.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..31.
+ @param [in] AndData The value to AND with the PCI configuration register.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressBitFieldAnd32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldAnd32 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ AndData
+ );
+}
+
+/**
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a
+ bitwise OR, and writes the result back to the bit field in the
+ 32-bit port.
+
+ Reads the 32-bit PCI configuration register specified by Address, performs a
+ bitwise AND followed by a bitwise OR between the read result and
+ the value specified by AndData, and writes the result to the 32-bit PCI
+ configuration register specified by Address. The value written to the PCI
+ configuration register is returned. This function must guarantee that all PCI
+ read and write operations are serialized. Extra left bits in both AndData and
+ OrData are stripped.
+
+ If Address > 0x1FFFFFFFF, then ASSERT().
+ If Address is not aligned on a 32-bit boundary, then ASSERT().
+ If StartBit is greater than 31, then ASSERT().
+ If EndBit is greater than 31, then ASSERT().
+ If EndBit is less than StartBit, then ASSERT().
+ If AndData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+ If OrData is larger than the bitmask value range specified by StartBit and
+ EndBit, then ASSERT().
+
+ @param [in] Address The PCI configuration register to write.
+ @param [in] StartBit The ordinal of the least significant bit in the bit
+ field. Range 0..31.
+ @param [in] EndBit The ordinal of the most significant bit in the bit
+ field. Range 0..31.
+ @param [in] AndData The value to AND with the PCI configuration register.
+ @param [in] OrData The value to OR with the result of the AND operation.
+
+ @return The value written back to the PCI configuration register.
+
+**/
+UINT32
+EFIAPI
+PciExpressBitFieldAndThenOr32 (
+ IN UINTN Address,
+ IN UINTN StartBit,
+ IN UINTN EndBit,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ )
+{
+ ASSERT_INVALID_PCI_ADDRESS (Address);
+ return MmioBitFieldAndThenOr32 (
+ (UINTN)GetPciExpressAddress (Address),
+ StartBit,
+ EndBit,
+ AndData,
+ OrData
+ );
+}
+
+/**
+ Reads a range of PCI configuration registers into a caller supplied buffer.
+
+ Reads the range of PCI configuration registers specified by StartAddress and
+ Size into the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be read. Size is
+ returned. When possible 32-bit PCI configuration read cycles are used to read
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit
+ and 16-bit PCI configuration read cycles may be used at the beginning and the
+ end of the range.
+
+ If StartAddress > 0x1FFFFFFFF, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param [in] StartAddress The starting address that encodes the PCI Bus,
+ Device, Function and Register.
+ @param [in] Size The size in bytes of the transfer.
+ @param [out] Buffer The pointer to a buffer receiving the data read.
+
+ @return Size read data from StartAddress.
+
+**/
+UINTN
+EFIAPI
+PciExpressReadBuffer (
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ OUT VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_ADDRESS (StartAddress);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return Size;
[SAMI] return 0; ?
+ }
+
+ ASSERT (Buffer != NULL);
+
+ // Save Size for return
+ ReturnValue = Size;
+
+ if ((StartAddress & 1) != 0) {
+ // Read a byte if StartAddress is byte aligned
+ *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
+ }
+
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {
+ // Read a word if StartAddress is word aligned
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));
+
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ // Read as many double words as possible
+ WriteUnaligned32 ((UINT32 *)Buffer, (UINT32)PciExpressRead32 (StartAddress));
+
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ // Read the last remaining word if exist
+ WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ // Read the last remaining byte if exist
+ *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);
+ }
+
+ return ReturnValue;
+}
+
+/**
+ Copies the data in a caller supplied buffer to a specified range of PCI
+ configuration space.
+
+ Writes the range of PCI configuration registers specified by StartAddress and
+ Size from the buffer specified by Buffer. This function only allows the PCI
+ configuration registers from a single PCI function to be written. Size is
+ returned. When possible 32-bit PCI configuration write cycles are used to
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning
+ and the end of the range.
+
+ If StartAddress > 0x1FFFFFFFF, then ASSERT().
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().
+ If Size > 0 and Buffer is NULL, then ASSERT().
+
+ @param [in] StartAddress The starting address that encodes the PCI Bus,
+ Device, Function and Register.
+ @param [in] Size The size in bytes of the transfer.
+ @param [in] Buffer The pointer to a buffer containing the data to write.
+
+ @return Size written to StartAddress.
+
+**/
+UINTN
+EFIAPI
+PciExpressWriteBuffer (
+ IN UINTN StartAddress,
+ IN UINTN Size,
+ IN VOID *Buffer
+ )
+{
+ UINTN ReturnValue;
+
+ ASSERT_INVALID_PCI_ADDRESS (StartAddress);
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);
+
+ if (Size == 0) {
+ return 0;
+ }
+
+ ASSERT (Buffer != NULL);
+
+ // Save Size for return
+ ReturnValue = Size;
+
+ if ((StartAddress & 1) != 0) {
+ // Write a byte if StartAddress is byte aligned
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);
+ StartAddress += sizeof (UINT8);
+ Size -= sizeof (UINT8);
+ Buffer = (UINT8 *)Buffer + 1;
+ }
+
+ if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {
+ // Write a word if StartAddress is word aligned
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ while (Size >= sizeof (UINT32)) {
+ // Write as many double words as possible
+ PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32 *)Buffer));
+ StartAddress += sizeof (UINT32);
+ Size -= sizeof (UINT32);
+ Buffer = (UINT32 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT16)) {
+ // Write the last remaining word if exist
+ PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));
+ StartAddress += sizeof (UINT16);
+ Size -= sizeof (UINT16);
+ Buffer = (UINT16 *)Buffer + 1;
+ }
+
+ if (Size >= sizeof (UINT8)) {
+ // Write the last remaining byte if exist
+ PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);
+ }
+
+ return ReturnValue;
+}
diff --git a/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.uni b/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.uni
new file mode 100644
index 000000000000..540453d4a189
--- /dev/null
+++ b/Platform/ARM/Morello/Library/PciExpressLib/PciExpressLib.uni
@@ -0,0 +1,18 @@
+// /** @file
+// Instance of PCI Express Library using the 256 MB PCI Express MMIO window.
+//
+// PCI Express Library that uses the 256 MB PCI Express MMIO window to perform
+// PCI Configuration cycles. Layers on top of an I/O Library instance.
+//
+// Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>
+//
+// Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT #language en-US "Instance of PCI Express Library using the 256 MB PCI Express MMIO window"
+
+#string STR_MODULE_DESCRIPTION #language en-US "PCI Express Library that uses the 256 MB PCI Express MMIO window to perform PCI Configuration cycles. Layers on top of an I/O Library instance."
[SAMI] Does this comment need updating? Same for the file header
documentation.

IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.


Khasim Mohammed
 

Hi Sami, Chandni,

There was a suggestion from Pierre on a similar patch for N1SDP to remove PCIExpressLib.c and move to workarounds to PCISegmentLib.c,

https://edk2.groups.io/g/devel/message/84165?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3Arecentpostdate%2Fsticky%2C%2Ckhasim%2C20%2C2%2C0%2C87257273

I think we should discuss this implementation for both N1SDP and Morello as they have similar implementation.

Regards,
Khasim


chandni cherukuri
 

Hi Ard, Leif, Sami, Pierre,

For Morello platform, we created two custom libraries based on the
below two native libraries:
- https://github.com/tianocore/edk2/tree/master/MdePkg/Library/BasePciSegmentLibPci
- https://github.com/tianocore/edk2/tree/master/MdePkg/Library/BasePciExpressLib

because of the following reasons.
1. In Morello platform, the ECAM region of the two root ports
are placed in non-contiguous memory as per the memory map architecture
of the Morello platform. The native PCI Express Library expects both
the ECAM regions for all the root ports to be contiguous.
2. IORT and kernel currently require each root port to be in a
separate segment. You can refer to the code for more details -
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/acpi/arm64/iort.c#n307.
The native PCI Segment Library supports only a single segment.

Because of these reasons, the current patch series adapts the native
libraries as follows:

The custom PCI Segment Library passes the complete address which is
consumed by the custom PCI Express library where based on the Segment
number, the base address of the PCI Express is returned.

The rationale behind maintaining two separate libraries is that when
the software evolves and support for multiple segments is adapted in
the native PCI Segment Library the custom library could be removed.
Also, we might have other protocols which might try to use the PCI
Express library directly. However, there are some other platforms
where all the platform specific changes have gone in a single custom
PCI library

Could you please provide some inputs as to which of two approaches
would be better to follow as there is one more platform to follow
based on the decision taken?

Thanks
Chandni

On Wed, Dec 8, 2021 at 8:25 AM Khasim Mohammed <khasim.mohammed@arm.com> wrote:

Hi Sami, Chandni,

There was a suggestion from Pierre on a similar patch for N1SDP to remove PCIExpressLib.c and move to workarounds to PCISegmentLib.c,

https://edk2.groups.io/g/devel/message/84165?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3Arecentpostdate%2Fsticky%2C%2Ckhasim%2C20%2C2%2C0%2C87257273

I think we should discuss this implementation for both N1SDP and Morello as they have similar implementation.

Regards,
Khasim


Ard Biesheuvel
 

On Thu, 9 Dec 2021 at 13:30, chandni cherukuri <ch.chandni@gmail.com> wrote:

Hi Ard, Leif, Sami, Pierre,

For Morello platform, we created two custom libraries based on the
below two native libraries:
- https://github.com/tianocore/edk2/tree/master/MdePkg/Library/BasePciSegmentLibPci
- https://github.com/tianocore/edk2/tree/master/MdePkg/Library/BasePciExpressLib

because of the following reasons.
1. In Morello platform, the ECAM region of the two root ports
are placed in non-contiguous memory as per the memory map architecture
of the Morello platform. The native PCI Express Library expects both
the ECAM regions for all the root ports to be contiguous.
Do you mean root ports or host bridges? If root ports don't share the
MMIO resource windows provided by the respective host bridges, they
are really different host bridges and should be modeled as such.

Note that the Cadence and Synopsys IP usually does not implement a
root port at all, and gets away with this because it only implements a
single link.

2. IORT and kernel currently require each root port to be in a
separate segment. You can refer to the code for more details -
Please take a look at the SynQuaecer platform for inspiration. That
platform is very similar in this respect.

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/acpi/arm64/iort.c#n307.
The native PCI Segment Library supports only a single segment.

Because of these reasons, the current patch series adapts the native
libraries as follows:

The custom PCI Segment Library passes the complete address which is
consumed by the custom PCI Express library where based on the Segment
number, the base address of the PCI Express is returned.

The rationale behind maintaining two separate libraries is that when
the software evolves and support for multiple segments is adapted in
the native PCI Segment Library the custom library could be removed.
Also, we might have other protocols which might try to use the PCI
Express library directly. However, there are some other platforms
where all the platform specific changes have gone in a single custom
PCI library

Could you please provide some inputs as to which of two approaches
would be better to follow as there is one more platform to follow
based on the decision taken?

Thanks
Chandni

On Wed, Dec 8, 2021 at 8:25 AM Khasim Mohammed <khasim.mohammed@arm.com> wrote:

Hi Sami, Chandni,

There was a suggestion from Pierre on a similar patch for N1SDP to remove PCIExpressLib.c and move to workarounds to PCISegmentLib.c,

https://edk2.groups.io/g/devel/message/84165?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3Arecentpostdate%2Fsticky%2C%2Ckhasim%2C20%2C2%2C0%2C87257273

I think we should discuss this implementation for both N1SDP and Morello as they have similar implementation.

Regards,
Khasim


chandni cherukuri
 

Hi Ard,

Thanks for the response.

I had a look at the Synquacer platform where there is a single custom
PCIe library implemented.
So, is it better to implement a single custom PCIe library instead of
two custom PCIe libraries?

If that is the case then will implement a single custom PCIe library
for Morello.

Thanks
Chandni

On Fri, Dec 10, 2021 at 4:12 PM Ard Biesheuvel <ardb@kernel.org> wrote:

On Thu, 9 Dec 2021 at 13:30, chandni cherukuri <ch.chandni@gmail.com> wrote:

Hi Ard, Leif, Sami, Pierre,

For Morello platform, we created two custom libraries based on the
below two native libraries:
- https://github.com/tianocore/edk2/tree/master/MdePkg/Library/BasePciSegmentLibPci
- https://github.com/tianocore/edk2/tree/master/MdePkg/Library/BasePciExpressLib

because of the following reasons.
1. In Morello platform, the ECAM region of the two root ports
are placed in non-contiguous memory as per the memory map architecture
of the Morello platform. The native PCI Express Library expects both
the ECAM regions for all the root ports to be contiguous.
Do you mean root ports or host bridges? If root ports don't share the
MMIO resource windows provided by the respective host bridges, they
are really different host bridges and should be modeled as such.

Note that the Cadence and Synopsys IP usually does not implement a
root port at all, and gets away with this because it only implements a
single link.

2. IORT and kernel currently require each root port to be in a
separate segment. You can refer to the code for more details -
Please take a look at the SynQuaecer platform for inspiration. That
platform is very similar in this respect.

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/acpi/arm64/iort.c#n307.
The native PCI Segment Library supports only a single segment.

Because of these reasons, the current patch series adapts the native
libraries as follows:

The custom PCI Segment Library passes the complete address which is
consumed by the custom PCI Express library where based on the Segment
number, the base address of the PCI Express is returned.

The rationale behind maintaining two separate libraries is that when
the software evolves and support for multiple segments is adapted in
the native PCI Segment Library the custom library could be removed.
Also, we might have other protocols which might try to use the PCI
Express library directly. However, there are some other platforms
where all the platform specific changes have gone in a single custom
PCI library

Could you please provide some inputs as to which of two approaches
would be better to follow as there is one more platform to follow
based on the decision taken?

Thanks
Chandni

On Wed, Dec 8, 2021 at 8:25 AM Khasim Mohammed <khasim.mohammed@arm.com> wrote:

Hi Sami, Chandni,

There was a suggestion from Pierre on a similar patch for N1SDP to remove PCIExpressLib.c and move to workarounds to PCISegmentLib.c,

https://edk2.groups.io/g/devel/message/84165?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3Arecentpostdate%2Fsticky%2C%2Ckhasim%2C20%2C2%2C0%2C87257273

I think we should discuss this implementation for both N1SDP and Morello as they have similar implementation.

Regards,
Khasim


Ard Biesheuvel
 

On Mon, 13 Dec 2021 at 13:41, chandni cherukuri <ch.chandni@gmail.com> wrote:

Hi Ard,

Thanks for the response.

I had a look at the Synquacer platform where there is a single custom
PCIe library implemented.
So, is it better to implement a single custom PCIe library instead of
two custom PCIe libraries?
Yes, for two reasons:
- there is prior art for this solution, and solving the same problem
in two different ways in the same codebase is bad form;
- those two libraries are layered one on top of the other, which means
that your fix requires changes to two different layers, making the
interface between those two layers obviously unfit to represent the
hardware in question.


If that is the case then will implement a single custom PCIe library
for Morello.

Thanks
Chandni
On Fri, Dec 10, 2021 at 4:12 PM Ard Biesheuvel <ardb@kernel.org> wrote:

On Thu, 9 Dec 2021 at 13:30, chandni cherukuri <ch.chandni@gmail.com> wrote:

Hi Ard, Leif, Sami, Pierre,

For Morello platform, we created two custom libraries based on the
below two native libraries:
- https://github.com/tianocore/edk2/tree/master/MdePkg/Library/BasePciSegmentLibPci
- https://github.com/tianocore/edk2/tree/master/MdePkg/Library/BasePciExpressLib

because of the following reasons.
1. In Morello platform, the ECAM region of the two root ports
are placed in non-contiguous memory as per the memory map architecture
of the Morello platform. The native PCI Express Library expects both
the ECAM regions for all the root ports to be contiguous.
Do you mean root ports or host bridges? If root ports don't share the
MMIO resource windows provided by the respective host bridges, they
are really different host bridges and should be modeled as such.

Note that the Cadence and Synopsys IP usually does not implement a
root port at all, and gets away with this because it only implements a
single link.

2. IORT and kernel currently require each root port to be in a
separate segment. You can refer to the code for more details -
Please take a look at the SynQuaecer platform for inspiration. That
platform is very similar in this respect.

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/acpi/arm64/iort.c#n307.
The native PCI Segment Library supports only a single segment.

Because of these reasons, the current patch series adapts the native
libraries as follows:

The custom PCI Segment Library passes the complete address which is
consumed by the custom PCI Express library where based on the Segment
number, the base address of the PCI Express is returned.

The rationale behind maintaining two separate libraries is that when
the software evolves and support for multiple segments is adapted in
the native PCI Segment Library the custom library could be removed.
Also, we might have other protocols which might try to use the PCI
Express library directly. However, there are some other platforms
where all the platform specific changes have gone in a single custom
PCI library

Could you please provide some inputs as to which of two approaches
would be better to follow as there is one more platform to follow
based on the decision taken?

Thanks
Chandni

On Wed, Dec 8, 2021 at 8:25 AM Khasim Mohammed <khasim.mohammed@arm.com> wrote:

Hi Sami, Chandni,

There was a suggestion from Pierre on a similar patch for N1SDP to remove PCIExpressLib.c and move to workarounds to PCISegmentLib.c,

https://edk2.groups.io/g/devel/message/84165?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3Arecentpostdate%2Fsticky%2C%2Ckhasim%2C20%2C2%2C0%2C87257273

I think we should discuss this implementation for both N1SDP and Morello as they have similar implementation.

Regards,
Khasim


chandni cherukuri
 

On Mon, Dec 13, 2021 at 8:08 PM Ard Biesheuvel <ardb@kernel.org> wrote:

On Mon, 13 Dec 2021 at 13:41, chandni cherukuri <ch.chandni@gmail.com> wrote:

Hi Ard,

Thanks for the response.

I had a look at the Synquacer platform where there is a single custom
PCIe library implemented.
So, is it better to implement a single custom PCIe library instead of
two custom PCIe libraries?
Yes, for two reasons:
- there is prior art for this solution, and solving the same problem
in two different ways in the same codebase is bad form;
- those two libraries are layered one on top of the other, which means
that your fix requires changes to two different layers, making the
interface between those two layers obviously unfit to represent the
hardware in question.

Thanks for the response.
Will implement a single custom PCIe library and post a new patchset.

Thanks
Chandni

If that is the case then will implement a single custom PCIe library
for Morello.

Thanks
Chandni
On Fri, Dec 10, 2021 at 4:12 PM Ard Biesheuvel <ardb@kernel.org> wrote:

On Thu, 9 Dec 2021 at 13:30, chandni cherukuri <ch.chandni@gmail.com> wrote:

Hi Ard, Leif, Sami, Pierre,

For Morello platform, we created two custom libraries based on the
below two native libraries:
- https://github.com/tianocore/edk2/tree/master/MdePkg/Library/BasePciSegmentLibPci
- https://github.com/tianocore/edk2/tree/master/MdePkg/Library/BasePciExpressLib

because of the following reasons.
1. In Morello platform, the ECAM region of the two root ports
are placed in non-contiguous memory as per the memory map architecture
of the Morello platform. The native PCI Express Library expects both
the ECAM regions for all the root ports to be contiguous.
Do you mean root ports or host bridges? If root ports don't share the
MMIO resource windows provided by the respective host bridges, they
are really different host bridges and should be modeled as such.

Note that the Cadence and Synopsys IP usually does not implement a
root port at all, and gets away with this because it only implements a
single link.

2. IORT and kernel currently require each root port to be in a
separate segment. You can refer to the code for more details -
Please take a look at the SynQuaecer platform for inspiration. That
platform is very similar in this respect.

https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/acpi/arm64/iort.c#n307.
The native PCI Segment Library supports only a single segment.

Because of these reasons, the current patch series adapts the native
libraries as follows:

The custom PCI Segment Library passes the complete address which is
consumed by the custom PCI Express library where based on the Segment
number, the base address of the PCI Express is returned.

The rationale behind maintaining two separate libraries is that when
the software evolves and support for multiple segments is adapted in
the native PCI Segment Library the custom library could be removed.
Also, we might have other protocols which might try to use the PCI
Express library directly. However, there are some other platforms
where all the platform specific changes have gone in a single custom
PCI library

Could you please provide some inputs as to which of two approaches
would be better to follow as there is one more platform to follow
based on the decision taken?

Thanks
Chandni

On Wed, Dec 8, 2021 at 8:25 AM Khasim Mohammed <khasim.mohammed@arm.com> wrote:

Hi Sami, Chandni,

There was a suggestion from Pierre on a similar patch for N1SDP to remove PCIExpressLib.c and move to workarounds to PCISegmentLib.c,

https://edk2.groups.io/g/devel/message/84165?p=%2C%2C%2C20%2C0%2C0%2C0%3A%3Arecentpostdate%2Fsticky%2C%2Ckhasim%2C20%2C2%2C0%2C87257273

I think we should discuss this implementation for both N1SDP and Morello as they have similar implementation.

Regards,
Khasim