[edk2-platforms PATCH 4/6] Marvell: Armada7k8k/OcteonTx: Add multiple PCIE ports support


Marcin Wojtas
 

From: Kamil Koczurek <kek@semihalf.com>

In order to support more than one PCIE port, PciHostBridgeLib must
generate appropriate device paths according to the board description
and assign correct segment numbers instead of a hard-coded 0.

Additionally, PciSegmentLib has to operate on a proper
config spaces base address (depending on the segment number).
Add the library constructor routine and obtain the necessary
data from the Marvell board description protocol.

Remove unused PCIE-related PCD's.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc =
| 4 --
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc =
| 4 --
Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.i=
nf | 11 ++--
Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHostBridg=
eLib.c | 15 +++--
Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegmentLib.c=
| 69 +++++++++++++++++++-
5 files changed, 86 insertions(+), 17 deletions(-)

diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell=
/Cn913xDb/Cn9130DbA.dsc.inc
index 41d9cb9247..e4d4c8e073 100644
--- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
+++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
@@ -93,10 +93,6 @@
gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x1 }=0D
gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }=0D
=0D
- # PCIE=0D
- gArmTokenSpaceGuid.PcdPciIoTranslation|0xDFF00000=0D
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xD0000000=0D
-=0D
# RTC=0D
gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000=0D
=0D
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel=
l/Armada7k8k/Armada7k8k.dsc.inc
index b1aa0ae4d0..25f3fc8dd8 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -396,10 +396,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x0001000=
0=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000=
=0D
=0D
- # PCIE=0D
- gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFF00000=0D
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000=0D
-=0D
!if $(CAPSULE_ENABLE)=0D
[PcdsDynamicExDefault.common.DEFAULT]=0D
gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor=
|{0x0}|VOID*|0x100=0D
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/Pci=
SegmentLib.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib=
/PciSegmentLib.inf
index f5f1b8409b..d3876791e9 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegment=
Lib.inf
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegment=
Lib.inf
@@ -16,18 +16,21 @@
MODULE_TYPE =3D BASE=0D
VERSION_STRING =3D 1.0=0D
LIBRARY_CLASS =3D PciSegmentLib=0D
+ CONSTRUCTOR =3D Armada7k8kPciSegmentLibConstructor=0D
=0D
[Sources]=0D
PciSegmentLib.c=0D
=0D
[Packages]=0D
+ EmbeddedPkg/EmbeddedPkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
MdePkg/MdePkg.dec=0D
Silicon/Marvell/Marvell.dec=0D
=0D
[LibraryClasses]=0D
+ ArmadaBoardDescLib=0D
+ ArmadaSoCDescLib=0D
BaseLib=0D
- DebugLib=0D
- IoLib=0D
=0D
-[Pcd]=0D
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=0D
+[Protocols]=0D
+ gMarvellBoardDescProtocolGuid=0D
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/=
PciHostBridgeLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBr=
idgeLib/PciHostBridgeLib.c
index 52fa5a4c1a..ad52062d73 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost=
BridgeLib.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciHostBridgeLib/PciHost=
BridgeLib.c
@@ -9,6 +9,7 @@
**/=0D
#include <PiDxe.h>=0D
=0D
+#include <Library/BaseMemoryLib.h>=0D
#include <Library/DebugLib.h>=0D
#include <Library/DevicePathLib.h>=0D
#include <Library/MemoryAllocationLib.h>=0D
@@ -27,7 +28,7 @@ typedef struct {
} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;=0D
#pragma pack ()=0D
=0D
-STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath =3D {=0D
+STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePathTe=
mplate =3D {=0D
{=0D
{=0D
ACPI_DEVICE_PATH,=0D
@@ -38,7 +39,7 @@ STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeD=
evicePath =3D {
}=0D
},=0D
EISA_PNP_ID (0x0A08), // PCI Express=0D
- 0=0D
+ 0 // AcpiDevicePath.UID=0D
},=0D
=0D
{=0D
@@ -74,6 +75,7 @@ PciHostBridgeGetRootBridges (
{=0D
MV_BOARD_PCIE_DESCRIPTION CONST *BoardPcieDescription;=0D
MARVELL_BOARD_DESC_PROTOCOL *BoardDescriptionProtocol;=0D
+ EFI_PCI_ROOT_BRIDGE_DEVICE_PATH *EfiPciRootBridgeDevicePath;=0D
MV_PCIE_CONTROLLER CONST *PcieController;=0D
PCI_ROOT_BRIDGE *PciRootBridges;=0D
PCI_ROOT_BRIDGE *RootBridge;=0D
@@ -119,10 +121,15 @@ PciHostBridgeGetRootBridges (
=0D
/* Fill information of all root bridge instances */=0D
for (Index =3D 0; Index < *Count; Index++, RootBridge++) {=0D
+ EfiPciRootBridgeDevicePath =3D AllocateCopyPool (=0D
+ sizeof (EFI_PCI_ROOT_BRIDGE_DEVICE_PATH=
),=0D
+ &mEfiPciRootBridgeDevicePathTemplate=0D
+ );=0D
+ EfiPciRootBridgeDevicePath->AcpiDevicePath.UID =3D Index;=0D
=0D
PcieController =3D &(BoardPcieDescription->PcieControllers[Index]);=0D
=0D
- RootBridge->Segment =3D 0;=0D
+ RootBridge->Segment =3D Index;=0D
RootBridge->Supports =3D 0;=0D
RootBridge->Attributes =3D RootBridge->Supports;=0D
=0D
@@ -168,7 +175,7 @@ PciHostBridgeGetRootBridges (
=0D
RootBridge->NoExtendedConfigSpace =3D FALSE;=0D
=0D
- RootBridge->DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBri=
dgeDevicePath;=0D
+ RootBridge->DevicePath =3D (EFI_DEVICE_PATH_PROTOCOL *)EfiPciRootBridg=
eDevicePath;=0D
}=0D
=0D
return PciRootBridges;=0D
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/Pci=
SegmentLib.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/P=
ciSegmentLib.c
index 283190959e..02ceb17825 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegment=
Lib.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kPciSegmentLib/PciSegment=
Lib.c
@@ -9,12 +9,20 @@
=0D
**/=0D
=0D
+#include <Uefi.h>=0D
#include <Base.h>=0D
=0D
#include <Library/BaseLib.h>=0D
#include <Library/DebugLib.h>=0D
#include <Library/IoLib.h>=0D
+#include <Library/MemoryAllocationLib.h>=0D
#include <Library/PciSegmentLib.h>=0D
+#include <Library/UefiBootServicesTableLib.h>=0D
+=0D
+#include <Protocol/BoardDesc.h>=0D
+=0D
+UINT64 *mConfigSpaceAddresses;=0D
+UINTN mPcieControllerCount;=0D
=0D
typedef enum {=0D
PciCfgWidthUint8 =3D 0,=0D
@@ -34,6 +42,15 @@ typedef enum {
#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \=0D
ASSERT (((A) & (0xffff0000f0000000ULL | (M))) =3D=3D 0)=0D
=0D
+/**=0D
+ Extract segment number from PCI Segment address=0D
+=0D
+ @param A The address to process.=0D
+=0D
+**/=0D
+#define SEGMENT_INDEX(A) \=0D
+ (((A) & 0x0000ffff00000000) >> 32)=0D
+=0D
/**=0D
Internal worker function to obtain config space base address.=0D
=0D
@@ -49,7 +66,9 @@ PciSegmentLibGetConfigBase (
IN UINT64 Address=0D
)=0D
{=0D
- return PcdGet64 (PcdPciExpressBaseAddress);=0D
+ ASSERT (SEGMENT_INDEX (Address) < mPcieControllerCount);=0D
+=0D
+ return mConfigSpaceAddresses[SEGMENT_INDEX (Address)];=0D
}=0D
=0D
/**=0D
@@ -1388,3 +1407,51 @@ PciSegmentWriteBuffer (
=0D
return ReturnValue;=0D
}=0D
+=0D
+/**=0D
+ Obtain base addresses of PCIe configuration spaces.=0D
+=0D
+ @retval EFI_SUCEESS Routine executed properly.=0D
+ @retval Other Return error status.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+Armada7k8kPciSegmentLibConstructor (=0D
+ VOID=0D
+ )=0D
+{=0D
+ CONST MV_BOARD_PCIE_DESCRIPTION *PcieDesc;=0D
+ MARVELL_BOARD_DESC_PROTOCOL *Proto;=0D
+ EFI_STATUS Status;=0D
+ UINTN Index;=0D
+=0D
+ Status =3D gBS->LocateProtocol (=0D
+ &gMarvellBoardDescProtocolGuid,=0D
+ NULL,=0D
+ (VOID **)&Proto=0D
+ );=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ Status =3D Proto->PcieDescriptionGet (Proto, &PcieDesc);=0D
+ if (EFI_ERROR (Status)) {=0D
+ return Status;=0D
+ }=0D
+=0D
+ mConfigSpaceAddresses =3D AllocateZeroPool (=0D
+ PcieDesc->PcieControllerCount * sizeof (UINT64=
)=0D
+ );=0D
+ if (mConfigSpaceAddresses =3D=3D NULL) {=0D
+ return EFI_OUT_OF_RESOURCES;=0D
+ }=0D
+=0D
+ for (Index =3D 0; Index < PcieDesc->PcieControllerCount; Index++) {=0D
+ mConfigSpaceAddresses[Index] =3D PcieDesc->PcieControllers[Index].Conf=
igSpaceAddress;=0D
+ }=0D
+=0D
+ mPcieControllerCount =3D PcieDesc->PcieControllerCount;=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
--=20
2.29.0