[edk2-platforms PATCH 1/6] Marvell: Armada7k8k/OcteonTx: Allow memory mapping for more config spaces


Marcin Wojtas
 

Until now the virtual memory map for the single PCIE configuration space
was hardcoded via PCDs and assumed adjacency to the SoC MMIO region
(0xf0000000 - 4GB). Remove this limitation by splitting the regions
and allowing to obtain the PCIE configuration space settings
from ArmadaBoardDescLib. It is a preparation patch for adding
support for multiple PCIE controllers.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 3 -=
--
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 3 -=
--
Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf | 1 +
Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c | 16 +=
++++++++++++++-
4 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc b/Platform/Marvell=
/Cn913xDb/Cn9130DbA.dsc.inc
index 756d875f6c..41d9cb9247 100644
--- a/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
+++ b/Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc
@@ -100,8 +100,5 @@
# RTC=0D
gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000=0D
=0D
- # SoC Configuration Space=0D
- gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xD0000000=0D
-=0D
# Variable store=0D
gMarvellTokenSpaceGuid.PcdSpiMemoryMapped|FALSE=0D
diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel=
l/Armada7k8k/Armada7k8k.dsc.inc
index d398d9432f..b1aa0ae4d0 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -400,9 +400,6 @@
gArmTokenSpaceGuid.PcdPciIoTranslation|0xEFF00000=0D
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000=0D
=0D
- # SoC Configuration Space=0D
- gMarvellTokenSpaceGuid.PcdConfigSpaceBaseAddress|0xE0000000=0D
-=0D
!if $(CAPSULE_ENABLE)=0D
[PcdsDynamicExDefault.common.DEFAULT]=0D
gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor=
|{0x0}|VOID*|0x100=0D
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib=
.inf b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
index 94427177ef..8b77a07ab3 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib.inf
@@ -20,6 +20,7 @@
Silicon/Marvell/Marvell.dec=0D
=0D
[LibraryClasses]=0D
+ ArmadaBoardDescLib=0D
ArmadaSoCDescLib=0D
ArmLib=0D
ArmSmcLib=0D
diff --git a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLib=
Mem.c b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
index cc19694d37..853c1b4e56 100644
--- a/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
+++ b/Silicon/Marvell/Armada7k8k/Library/Armada7k8kLib/Armada7k8kLibMem.c
@@ -10,6 +10,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <IndustryStandard/ArmStdSmc.h>=0D
#include <IndustryStandard/MvSmc.h>=0D
=0D
+#include <Library/ArmadaBoardDescLib.h>=0D
#include <Library/ArmadaSoCDescLib.h>=0D
#include <Library/ArmPlatformLib.h>=0D
#include <Library/ArmSmcLib.h>=0D
@@ -81,6 +82,9 @@ ArmPlatformGetVirtualMemoryMap (
UINT64 MemHighStart;=0D
UINT64 MemHighSize;=0D
UINT64 ConfigSpaceBaseAddr;=0D
+ UINTN PcieControllerCount;=0D
+ UINTN PcieIndex;=0D
+ MV_PCIE_CONTROLLER CONST *PcieControllers;=0D
EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttributes;=0D
EFI_STATUS Status;=0D
=0D
@@ -125,12 +129,22 @@ ArmPlatformGetVirtualMemoryMap (
mVirtualMemoryTable[Index].Length =3D MemLowSize;=0D
mVirtualMemoryTable[Index].Attributes =3D DDR_ATTRIBUTES_CACHED;=0D
=0D
- // Configuration space=0D
+ // SoC MMIO configuration space=0D
mVirtualMemoryTable[++Index].PhysicalBase =3D ConfigSpaceBaseAddr;=0D
mVirtualMemoryTable[Index].VirtualBase =3D ConfigSpaceBaseAddr;=0D
mVirtualMemoryTable[Index].Length =3D SIZE_4GB - ConfigSpaceBas=
eAddr;=0D
mVirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIBU=
TE_DEVICE;=0D
=0D
+ // PCIE ECAM=0D
+ Status =3D ArmadaBoardPcieControllerGet (&PcieControllers, &PcieControll=
erCount);=0D
+ ASSERT_EFI_ERROR (Status);=0D
+ for (PcieIndex =3D 0; PcieIndex < PcieControllerCount; PcieIndex++) {=0D
+ mVirtualMemoryTable[++Index].PhysicalBase =3D PcieControllers[PcieInd=
ex].ConfigSpaceAddress;=0D
+ mVirtualMemoryTable[Index].VirtualBase =3D PcieControllers[PcieInd=
ex].ConfigSpaceAddress;=0D
+ mVirtualMemoryTable[Index].Length =3D SIZE_256MB;=0D
+ mVirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRI=
BUTE_DEVICE;=0D
+ }=0D
+=0D
if (MemSize > MemLowSize) {=0D
//=0D
// If we have more than MemLowSize worth of DRAM, the remainder will b=
e=0D
--=20
2.29.0