[edk2-platforms][PATCH 11/14] RISC-V/ProcessorPkg: Address Core CI Spelling errors.


Abner Chang
 

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 4 ++--
.../RiscVFirmwareContextSbiLib.inf | 6 +++---
.../RiscVFirmwareContextSscratchLib.inf | 4 ++--
.../Include/Library/RiscVEdk2SbiLib.h | 16 ++++++++--------
.../RISC-V/ProcessorPkg/Include/OpensbiTypes.h | 4 ++--
.../Include/ProcessorSpecificHobData.h | 2 +-
.../Include/SmbiosProcessorSpecificData.h | 4 ++--
.../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 16 ++++++++--------
.../RiscVFirmwareContextSbiLib.c | 4 ++--
.../RiscVFirmwareContextStvecLib.c | 4 ++--
10 files changed, 32 insertions(+), 32 deletions(-)

diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RI=
SC-V/ProcessorPkg/RiscVProcessorPkg.dec
index 59634f4413..177c1a710d 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
@@ -1,7 +1,7 @@
-## @file RiscVProcesssorPkg.dec=0D
+## @file RiscVProcessorPkg.dec=0D
# This Package provides UEFI RISC-V processor modules and libraries.=0D
#=0D
-# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+# Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All =
rights reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib=
/RiscVFirmwareContextSbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscV=
FirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
index 0edf781149..1e4f14724b 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVF=
irmwareContextSbiLib.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVF=
irmwareContextSbiLib.inf
@@ -1,9 +1,9 @@
## @file=0D
-# Instance of OpebSBI Firmware Conext Library=0D
+# Instance of OpenSBI Firmware Context Library=0D
#=0D
-# This iinstance uses RISC-V OpenSBI Firmware Extension SBI.=0D
+# This instance uses RISC-V OpenSBI Firmware Extension SBI.=0D
#=0D
-# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ=
ts reserved.<BR>=0D
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All=
rights reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscrat=
chLib/RiscVFirmwareContextSscratchLib.inf b/Silicon/RISC-V/ProcessorPkg/Lib=
rary/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
index 750c1cf51f..09e635fd1d 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/R=
iscVFirmwareContextSscratchLib.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/R=
iscVFirmwareContextSscratchLib.inf
@@ -1,9 +1,9 @@
## @file=0D
-# Instance of OpebSBI Firmware Conext Library=0D
+# Instance of OpenSBI Firmware Context Library=0D
#=0D
# This instance uses RISC-V Supervisor mode SCRATCH CSR=0D
#=0D
-# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ=
ts reserved.<BR>=0D
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All=
rights reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h =
b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
index 88d957f002..6089137373 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
@@ -1,7 +1,7 @@
/** @file=0D
Library to call the RISC-V SBI ecalls=0D
=0D
- Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.=
<BR>=0D
+ Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese=
rved.<BR>=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
@@ -54,7 +54,7 @@ SbiGetSpecVersion (
/**=0D
Get the SBI implementation ID=0D
=0D
- This ID is used to idenetify a specific SBI implementation in order to w=
ork=0D
+ This ID is used to identify a specific SBI implementation in order to wo=
rk=0D
around any quirks it might have.=0D
=0D
@param[out] ImplId The ID of the SBI implementation.=0D
@@ -275,7 +275,7 @@ SbiRemoteFenceI (
/**=0D
Instructs the remote harts to execute one or more SFENCE.VMA instruction=
s.=0D
=0D
- The SFENCE.VMA covers the range of virtual addresses between StartAaddr =
and Size.=0D
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr a=
nd Size.=0D
=0D
The remote fence function acts as a full tlb flush if * StartAddr and si=
ze=0D
are both 0 * size is equal to 2^XLEN-1=0D
@@ -305,7 +305,7 @@ SbiRemoteSfenceVma (
/**=0D
Instructs the remote harts to execute one or more SFENCE.VMA instruction=
s.=0D
=0D
- The SFENCE.VMA covers the range of virtual addresses between StartAaddr =
and Size.=0D
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr a=
nd Size.=0D
Covers only the given ASID.=0D
=0D
The remote fence function acts as a full tlb flush if * StartAddr and si=
ze=0D
@@ -337,7 +337,7 @@ SbiRemoteSfenceVmaAsid (
/**=0D
Instructs the remote harts to execute one or more SFENCE.GVMA instructio=
ns.=0D
=0D
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr=
and Size.=0D
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr =
and Size.=0D
Covers only the given VMID.=0D
This function call is only valid for harts implementing the hypervisor e=
xtension.=0D
=0D
@@ -373,7 +373,7 @@ SbiRemoteHfenceGvmaVmid (
/**=0D
Instructs the remote harts to execute one or more SFENCE.GVMA instructio=
ns.=0D
=0D
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr=
and Size.=0D
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr =
and Size.=0D
This function call is only valid for harts implementing the hypervisor e=
xtension.=0D
=0D
The remote fence function acts as a full tlb flush if * StartAddr and si=
ze=0D
@@ -407,7 +407,7 @@ SbiRemoteHfenceGvma (
/**=0D
Instructs the remote harts to execute one or more SFENCE.VVMA instructio=
ns.=0D
=0D
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr=
and Size.=0D
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr =
and Size.=0D
Covers only the given ASID.=0D
This function call is only valid for harts implementing the hypervisor e=
xtension.=0D
=0D
@@ -443,7 +443,7 @@ SbiRemoteHfenceVvmaAsid (
/**=0D
Instructs the remote harts to execute one or more SFENCE.VVMA instructio=
ns.=0D
=0D
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr=
and Size.=0D
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr =
and Size.=0D
This function call is only valid for harts implementing the hypervisor e=
xtension.=0D
=0D
The remote fence function acts as a full tlb flush if * StartAddr and si=
ze=0D
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/R=
ISC-V/ProcessorPkg/Include/OpensbiTypes.h
index 8a6ea97708..ca7fc7a4ac 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
@@ -1,7 +1,7 @@
/** @file=0D
- RISC-V OpesbSBI header file reference.=0D
+ RISC-V OpensbiSBI header file reference.=0D
=0D
- Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+ Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All =
rights reserved.<BR>=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h=
b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
index 97285289f7..4b2a92e2f2 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
@@ -29,7 +29,7 @@ typedef struct {
EFI_GUID CoreGuid;=0D
VOID *Context; // The additional information of this core whi=
ch=0D
// built in PEI phase and carried to DXE phase=
.=0D
- // The content is pocessor or platform specifi=
c.=0D
+ // The content is processor or platform specif=
ic.=0D
SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;=0D
} RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;=0D
=0D
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificDat=
a.h b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
index 81e48cd068..85b8dcbe20 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
@@ -1,9 +1,9 @@
/** @file=0D
Industry Standard Definitions of RISC-V Processor Specific data defined =
in=0D
- below link for complaiant with SMBIOS Table Specification v3.3.0.=0D
+ below link for compliant with SMBIOS Table Specification v3.3.0.=0D
https://github.com/riscv/riscv-smbios=0D
=0D
- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All =
rights reserved.<BR>=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2S=
biLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiL=
ib.c
index 319526ed8f..a51139542d 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
@@ -15,7 +15,7 @@
- SbiLegacyRemoteSfenceVmaAsid -> Use SbiRemoteSfenceVmaAsid=0D
- SbiLegacyShutdown -> Wait for new System Reset extension=0D
=0D
- Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.=
<BR>=0D
+ Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights rese=
rved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
@par Revision Reference:=0D
@@ -173,7 +173,7 @@ SbiGetSpecVersion (
/**=0D
Get the SBI implementation ID=0D
=0D
- This ID is used to idenetify a specific SBI implementation in order to w=
ork=0D
+ This ID is used to identify a specific SBI implementation in order to wo=
rk=0D
around any quirks it might have.=0D
=0D
@param[out] ImplId The ID of the SBI implementation.=0D
@@ -441,7 +441,7 @@ SbiRemoteFenceI (
/**=0D
Instructs the remote harts to execute one or more SFENCE.VMA instruction=
s.=0D
=0D
- The SFENCE.VMA covers the range of virtual addresses between StartAaddr =
and Size.=0D
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr a=
nd Size.=0D
=0D
The remote fence function acts as a full tlb flush if * StartAddr and si=
ze=0D
are both 0 * size is equal to 2^XLEN-1=0D
@@ -483,7 +483,7 @@ SbiRemoteSfenceVma (
/**=0D
Instructs the remote harts to execute one or more SFENCE.VMA instruction=
s.=0D
=0D
- The SFENCE.VMA covers the range of virtual addresses between StartAaddr =
and Size.=0D
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr a=
nd Size.=0D
Covers only the given ASID.=0D
=0D
The remote fence function acts as a full tlb flush if * StartAddr and si=
ze=0D
@@ -528,7 +528,7 @@ SbiRemoteSfenceVmaAsid (
/**=0D
Instructs the remote harts to execute one or more SFENCE.GVMA instructio=
ns.=0D
=0D
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr=
and Size.=0D
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr =
and Size.=0D
Covers only the given VMID.=0D
This function call is only valid for harts implementing the hypervisor e=
xtension.=0D
=0D
@@ -577,7 +577,7 @@ SbiRemoteHFenceGvmaVmid (
/**=0D
Instructs the remote harts to execute one or more SFENCE.GVMA instructio=
ns.=0D
=0D
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr=
and Size.=0D
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr =
and Size.=0D
This function call is only valid for harts implementing the hypervisor e=
xtension.=0D
=0D
The remote fence function acts as a full tlb flush if * StartAddr and si=
ze=0D
@@ -623,7 +623,7 @@ SbiRemoteHFenceGvma (
/**=0D
Instructs the remote harts to execute one or more SFENCE.VVMA instructio=
ns.=0D
=0D
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr=
and Size.=0D
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr =
and Size.=0D
Covers only the given ASID.=0D
This function call is only valid for harts implementing the hypervisor e=
xtension.=0D
=0D
@@ -672,7 +672,7 @@ SbiRemoteHFenceVvmaAsid (
/**=0D
Instructs the remote harts to execute one or more SFENCE.VVMA instructio=
ns.=0D
=0D
- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr=
and Size.=0D
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr =
and Size.=0D
This function call is only valid for harts implementing the hypervisor e=
xtension.=0D
=0D
The remote fence function acts as a full tlb flush if * StartAddr and si=
ze=0D
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib=
/RiscVFirmwareContextSbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFi=
rmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
index 6125618eaf..a2a18d3eb7 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVF=
irmwareContextSbiLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVF=
irmwareContextSbiLib.c
@@ -1,8 +1,8 @@
/** @file=0D
- This iinstance uses RISC-V OpenSBI Firmware Extension SBI to=0D
+ This instance uses RISC-V OpenSBI Firmware Extension SBI to=0D
get the pointer of firmware context.=0D
=0D
- Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights=
reserved.<BR>=0D
+ Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All r=
ights reserved.<BR>=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
**/=0D
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecL=
ib/RiscVFirmwareContextStvecLib.c b/Silicon/RISC-V/ProcessorPkg/Library/Ris=
cVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
index 7d1675355a..d08b51d3d9 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/Risc=
VFirmwareContextStvecLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/Risc=
VFirmwareContextStvecLib.c
@@ -1,8 +1,8 @@
/** @file=0D
- This instance uses This iinstance Supervisor mode STVEC CSR to=0D
+ This instance uses This instance Supervisor mode STVEC CSR to=0D
get/set the pointer of firmware context.=0D
=0D
- Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights=
reserved.<BR>=0D
+ Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All r=
ights reserved.<BR>=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
**/=0D
--=20
2.31.1


Sunil V L
 

On Fri, Jan 21, 2022 at 04:48:45PM +0800, Abner Chang wrote:
Signed-off-by: Abner Chang <abner.chang@hpe.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>
Cc: Sunil V L <sunilvl@ventanamicro.com>
---
.../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec | 4 ++--
.../RiscVFirmwareContextSbiLib.inf | 6 +++---
.../RiscVFirmwareContextSscratchLib.inf | 4 ++--
.../Include/Library/RiscVEdk2SbiLib.h | 16 ++++++++--------
.../RISC-V/ProcessorPkg/Include/OpensbiTypes.h | 4 ++--
.../Include/ProcessorSpecificHobData.h | 2 +-
.../Include/SmbiosProcessorSpecificData.h | 4 ++--
.../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c | 16 ++++++++--------
.../RiscVFirmwareContextSbiLib.c | 4 ++--
.../RiscVFirmwareContextStvecLib.c | 4 ++--
10 files changed, 32 insertions(+), 32 deletions(-)

diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
index 59634f4413..177c1a710d 100644
--- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
+++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
@@ -1,7 +1,7 @@
-## @file RiscVProcesssorPkg.dec
+## @file RiscVProcessorPkg.dec
# This Package provides UEFI RISC-V processor modules and libraries.
#
-# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
index 0edf781149..1e4f14724b 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
@@ -1,9 +1,9 @@
## @file
-# Instance of OpebSBI Firmware Conext Library
+# Instance of OpenSBI Firmware Context Library
#
-# This iinstance uses RISC-V OpenSBI Firmware Extension SBI.
+# This instance uses RISC-V OpenSBI Firmware Extension SBI.
#
-# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
index 750c1cf51f..09e635fd1d 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
@@ -1,9 +1,9 @@
## @file
-# Instance of OpebSBI Firmware Conext Library
+# Instance of OpenSBI Firmware Context Library
#
# This instance uses RISC-V Supervisor mode SCRATCH CSR
#
-# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+# Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
index 88d957f002..6089137373 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
@@ -1,7 +1,7 @@
/** @file
Library to call the RISC-V SBI ecalls

- Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -54,7 +54,7 @@ SbiGetSpecVersion (
/**
Get the SBI implementation ID

- This ID is used to idenetify a specific SBI implementation in order to work
+ This ID is used to identify a specific SBI implementation in order to work
around any quirks it might have.

@param[out] ImplId The ID of the SBI implementation.
@@ -275,7 +275,7 @@ SbiRemoteFenceI (
/**
Instructs the remote harts to execute one or more SFENCE.VMA instructions.

- The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.

The remote fence function acts as a full tlb flush if * StartAddr and size
are both 0 * size is equal to 2^XLEN-1
@@ -305,7 +305,7 @@ SbiRemoteSfenceVma (
/**
Instructs the remote harts to execute one or more SFENCE.VMA instructions.

- The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given ASID.

The remote fence function acts as a full tlb flush if * StartAddr and size
@@ -337,7 +337,7 @@ SbiRemoteSfenceVmaAsid (
/**
Instructs the remote harts to execute one or more SFENCE.GVMA instructions.

- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given VMID.
This function call is only valid for harts implementing the hypervisor extension.

@@ -373,7 +373,7 @@ SbiRemoteHfenceGvmaVmid (
/**
Instructs the remote harts to execute one or more SFENCE.GVMA instructions.

- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
This function call is only valid for harts implementing the hypervisor extension.

The remote fence function acts as a full tlb flush if * StartAddr and size
@@ -407,7 +407,7 @@ SbiRemoteHfenceGvma (
/**
Instructs the remote harts to execute one or more SFENCE.VVMA instructions.

- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given ASID.
This function call is only valid for harts implementing the hypervisor extension.

@@ -443,7 +443,7 @@ SbiRemoteHfenceVvmaAsid (
/**
Instructs the remote harts to execute one or more SFENCE.VVMA instructions.

- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
This function call is only valid for harts implementing the hypervisor extension.

The remote fence function acts as a full tlb flush if * StartAddr and size
diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
index 8a6ea97708..ca7fc7a4ac 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
@@ -1,7 +1,7 @@
/** @file
- RISC-V OpesbSBI header file reference.
+ RISC-V OpensbiSBI header file reference.
Please change to just OpenSBI.


- Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
index 97285289f7..4b2a92e2f2 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
@@ -29,7 +29,7 @@ typedef struct {
EFI_GUID CoreGuid;
VOID *Context; // The additional information of this core which
// built in PEI phase and carried to DXE phase.
- // The content is pocessor or platform specific.
+ // The content is processor or platform specific.
SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
} RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;

diff --git a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
index 81e48cd068..85b8dcbe20 100644
--- a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
+++ b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
@@ -1,9 +1,9 @@
/** @file
Industry Standard Definitions of RISC-V Processor Specific data defined in
- below link for complaiant with SMBIOS Table Specification v3.3.0.
+ below link for compliant with SMBIOS Table Specification v3.3.0.
https://github.com/riscv/riscv-smbios

- Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
index 319526ed8f..a51139542d 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
@@ -15,7 +15,7 @@
- SbiLegacyRemoteSfenceVmaAsid -> Use SbiRemoteSfenceVmaAsid
- SbiLegacyShutdown -> Wait for new System Reset extension

- Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent

@par Revision Reference:
@@ -173,7 +173,7 @@ SbiGetSpecVersion (
/**
Get the SBI implementation ID

- This ID is used to idenetify a specific SBI implementation in order to work
+ This ID is used to identify a specific SBI implementation in order to work
around any quirks it might have.

@param[out] ImplId The ID of the SBI implementation.
@@ -441,7 +441,7 @@ SbiRemoteFenceI (
/**
Instructs the remote harts to execute one or more SFENCE.VMA instructions.

- The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.

The remote fence function acts as a full tlb flush if * StartAddr and size
are both 0 * size is equal to 2^XLEN-1
@@ -483,7 +483,7 @@ SbiRemoteSfenceVma (
/**
Instructs the remote harts to execute one or more SFENCE.VMA instructions.

- The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given ASID.

The remote fence function acts as a full tlb flush if * StartAddr and size
@@ -528,7 +528,7 @@ SbiRemoteSfenceVmaAsid (
/**
Instructs the remote harts to execute one or more SFENCE.GVMA instructions.

- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given VMID.
This function call is only valid for harts implementing the hypervisor extension.

@@ -577,7 +577,7 @@ SbiRemoteHFenceGvmaVmid (
/**
Instructs the remote harts to execute one or more SFENCE.GVMA instructions.

- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
This function call is only valid for harts implementing the hypervisor extension.

The remote fence function acts as a full tlb flush if * StartAddr and size
@@ -623,7 +623,7 @@ SbiRemoteHFenceGvma (
/**
Instructs the remote harts to execute one or more SFENCE.VVMA instructions.

- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
Covers only the given ASID.
This function call is only valid for harts implementing the hypervisor extension.

@@ -672,7 +672,7 @@ SbiRemoteHFenceVvmaAsid (
/**
Instructs the remote harts to execute one or more SFENCE.VVMA instructions.

- The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
+ The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
This function call is only valid for harts implementing the hypervisor extension.

The remote fence function acts as a full tlb flush if * StartAddr and size
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
index 6125618eaf..a2a18d3eb7 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
@@ -1,8 +1,8 @@
/** @file
- This iinstance uses RISC-V OpenSBI Firmware Extension SBI to
+ This instance uses RISC-V OpenSBI Firmware Extension SBI to
get the pointer of firmware context.

- Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent
**/
diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
index 7d1675355a..d08b51d3d9 100644
--- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
+++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
@@ -1,8 +1,8 @@
/** @file
- This instance uses This iinstance Supervisor mode STVEC CSR to
+ This instance uses This instance Supervisor mode STVEC CSR to
Please remove extra "This instance"

Regards
Sunil
get/set the pointer of firmware context.

- Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
+ Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent
**/
--
2.31.1






Abner Chang
 

Hi Sunil, V2 sent.

Thanks for the review.
Abner


From: Sunil V L <sunilvl@...>
Sent: Friday, January 21, 2022 10:53 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>; Chang, Abner (HPS SW/FW Technologist) <abner.chang@...>
Cc: Schaefer, Daniel (ROM Janitor) <daniel.schaefer@...>
Subject: Re: [edk2-devel] [edk2-platforms][PATCH 11/14] RISC-V/ProcessorPkg: Address Core CI Spelling errors.
 
On Fri, Jan 21, 2022 at 04:48:45PM +0800, Abner Chang wrote:
> Signed-off-by: Abner Chang <abner.chang@...>
> Cc: Daniel Schaefer <daniel.schaefer@...>
> Cc: Sunil V L <sunilvl@...>
> ---
>  .../RISC-V/ProcessorPkg/RiscVProcessorPkg.dec    |  4 ++--
>  .../RiscVFirmwareContextSbiLib.inf               |  6 +++---
>  .../RiscVFirmwareContextSscratchLib.inf          |  4 ++--
>  .../Include/Library/RiscVEdk2SbiLib.h            | 16 ++++++++--------
>  .../RISC-V/ProcessorPkg/Include/OpensbiTypes.h   |  4 ++--
>  .../Include/ProcessorSpecificHobData.h           |  2 +-
>  .../Include/SmbiosProcessorSpecificData.h        |  4 ++--
>  .../Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c    | 16 ++++++++--------
>  .../RiscVFirmwareContextSbiLib.c                 |  4 ++--
>  .../RiscVFirmwareContextStvecLib.c               |  4 ++--
>  10 files changed, 32 insertions(+), 32 deletions(-)
>
> diff --git a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> index 59634f4413..177c1a710d 100644
> --- a/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> +++ b/Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec
> @@ -1,7 +1,7 @@
> -## @file  RiscVProcesssorPkg.dec
> +## @file  RiscVProcessorPkg.dec
>  # This Package provides UEFI RISC-V processor modules and libraries.
>  #
> -# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +# Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>  #
>  # SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> index 0edf781149..1e4f14724b 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.inf
> @@ -1,9 +1,9 @@
>  ## @file
> -# Instance of OpebSBI Firmware Conext Library
> +# Instance of OpenSBI Firmware Context Library
>  #
> -# This iinstance uses RISC-V OpenSBI Firmware Extension SBI.
> +# This instance uses RISC-V OpenSBI Firmware Extension SBI.
>  #
> -#  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#  Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>  #
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> index 750c1cf51f..09e635fd1d 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSscratchLib/RiscVFirmwareContextSscratchLib.inf
> @@ -1,9 +1,9 @@
>  ## @file
> -# Instance of OpebSBI Firmware Conext Library
> +# Instance of OpenSBI Firmware Context Library
>  #
>  # This instance uses RISC-V Supervisor mode SCRATCH CSR
>  #
> -#  Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +#  Copyright (c) 2021-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
>  #
>  #  SPDX-License-Identifier: BSD-2-Clause-Patent
>  #
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
> index 88d957f002..6089137373 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
> +++ b/Silicon/RISC-V/ProcessorPkg/Include/Library/RiscVEdk2SbiLib.h
> @@ -1,7 +1,7 @@
>  /** @file
>    Library to call the RISC-V SBI ecalls

> -  Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
> +  Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>

>    SPDX-License-Identifier: BSD-2-Clause-Patent

> @@ -54,7 +54,7 @@ SbiGetSpecVersion (
>  /**
>    Get the SBI implementation ID

> -  This ID is used to idenetify a specific SBI implementation in order to work
> +  This ID is used to identify a specific SBI implementation in order to work
>    around any quirks it might have.

>    @param[out] ImplId               The ID of the SBI implementation.
> @@ -275,7 +275,7 @@ SbiRemoteFenceI (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VMA instructions.

> -  The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.

>    The remote fence function acts as a full tlb flush if * StartAddr and size
>    are both 0 * size is equal to 2^XLEN-1
> @@ -305,7 +305,7 @@ SbiRemoteSfenceVma (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VMA instructions.

> -  The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
>    Covers only the given ASID.

>    The remote fence function acts as a full tlb flush if * StartAddr and size
> @@ -337,7 +337,7 @@ SbiRemoteSfenceVmaAsid (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.GVMA instructions.

> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    Covers only the given VMID.
>    This function call is only valid for harts implementing the hypervisor extension.

> @@ -373,7 +373,7 @@ SbiRemoteHfenceGvmaVmid (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.GVMA instructions.

> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    This function call is only valid for harts implementing the hypervisor extension.

>    The remote fence function acts as a full tlb flush if * StartAddr and size
> @@ -407,7 +407,7 @@ SbiRemoteHfenceGvma (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VVMA instructions.

> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    Covers only the given ASID.
>    This function call is only valid for harts implementing the hypervisor extension.

> @@ -443,7 +443,7 @@ SbiRemoteHfenceVvmaAsid (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VVMA instructions.

> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    This function call is only valid for harts implementing the hypervisor extension.

>    The remote fence function acts as a full tlb flush if * StartAddr and size
> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
> index 8a6ea97708..ca7fc7a4ac 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
> +++ b/Silicon/RISC-V/ProcessorPkg/Include/OpensbiTypes.h
> @@ -1,7 +1,7 @@
>  /** @file
> -  RISC-V OpesbSBI header file reference.
> +  RISC-V OpensbiSBI header file reference.

Please change to just OpenSBI.


> -  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +  Copyright (c) 2020-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>

>    SPDX-License-Identifier: BSD-2-Clause-Patent

> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
> index 97285289f7..4b2a92e2f2 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
> +++ b/Silicon/RISC-V/ProcessorPkg/Include/ProcessorSpecificHobData.h
> @@ -29,7 +29,7 @@ typedef struct {
>    EFI_GUID CoreGuid;
>    VOID     *Context;        // The additional information of this core which
>                              // built in PEI phase and carried to DXE phase.
> -                            // The content is pocessor or platform specific.
> +                            // The content is processor or platform specific.
>    SMBIOS_RISC_V_PROCESSOR_SPECIFIC_DATA ProcessorSpecificData;
>  } RISC_V_PROCESSOR_SPECIFIC_HOB_DATA;

> diff --git a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
> index 81e48cd068..85b8dcbe20 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
> +++ b/Silicon/RISC-V/ProcessorPkg/Include/SmbiosProcessorSpecificData.h
> @@ -1,9 +1,9 @@
>  /** @file
>    Industry Standard Definitions of RISC-V Processor Specific data defined in
> -  below link for complaiant with SMBIOS Table Specification v3.3.0.
> +  below link for compliant with SMBIOS Table Specification v3.3.0.
>    https://github.com/riscv/riscv-smbios

> -  Copyright (c) 2019, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +  Copyright (c) 2019-2022, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>

>    SPDX-License-Identifier: BSD-2-Clause-Patent

> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
> index 319526ed8f..a51139542d 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
> +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVEdk2SbiLib/RiscVEdk2SbiLib.c
> @@ -15,7 +15,7 @@
>    - SbiLegacyRemoteSfenceVmaAsid -> Use SbiRemoteSfenceVmaAsid
>    - SbiLegacyShutdown            -> Wait for new System Reset extension

> -  Copyright (c) 2021, Hewlett Packard Development LP. All rights reserved.<BR>
> +  Copyright (c) 2021-2022, Hewlett Packard Development LP. All rights reserved.<BR>
>    SPDX-License-Identifier: BSD-2-Clause-Patent

>    @par Revision Reference:
> @@ -173,7 +173,7 @@ SbiGetSpecVersion (
>  /**
>    Get the SBI implementation ID

> -  This ID is used to idenetify a specific SBI implementation in order to work
> +  This ID is used to identify a specific SBI implementation in order to work
>    around any quirks it might have.

>    @param[out] ImplId               The ID of the SBI implementation.
> @@ -441,7 +441,7 @@ SbiRemoteFenceI (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VMA instructions.

> -  The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.

>    The remote fence function acts as a full tlb flush if * StartAddr and size
>    are both 0 * size is equal to 2^XLEN-1
> @@ -483,7 +483,7 @@ SbiRemoteSfenceVma (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VMA instructions.

> -  The SFENCE.VMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.VMA covers the range of virtual addresses between StartAddr and Size.
>    Covers only the given ASID.

>    The remote fence function acts as a full tlb flush if * StartAddr and size
> @@ -528,7 +528,7 @@ SbiRemoteSfenceVmaAsid (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.GVMA instructions.

> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    Covers only the given VMID.
>    This function call is only valid for harts implementing the hypervisor extension.

> @@ -577,7 +577,7 @@ SbiRemoteHFenceGvmaVmid (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.GVMA instructions.

> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    This function call is only valid for harts implementing the hypervisor extension.

>    The remote fence function acts as a full tlb flush if * StartAddr and size
> @@ -623,7 +623,7 @@ SbiRemoteHFenceGvma (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VVMA instructions.

> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    Covers only the given ASID.
>    This function call is only valid for harts implementing the hypervisor extension.

> @@ -672,7 +672,7 @@ SbiRemoteHFenceVvmaAsid (
>  /**
>    Instructs the remote harts to execute one or more SFENCE.VVMA instructions.

> -  The SFENCE.GVMA covers the range of virtual addresses between StartAaddr and Size.
> +  The SFENCE.GVMA covers the range of virtual addresses between StartAddr and Size.
>    This function call is only valid for harts implementing the hypervisor extension.

>    The remote fence function acts as a full tlb flush if * StartAddr and size
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
> index 6125618eaf..a2a18d3eb7 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
> +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextSbiLib/RiscVFirmwareContextSbiLib.c
> @@ -1,8 +1,8 @@
>  /** @file
> -  This iinstance uses RISC-V OpenSBI Firmware Extension SBI to
> +  This instance uses RISC-V OpenSBI Firmware Extension SBI to
>    get the pointer of firmware context.

> -  Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +  Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>

>    SPDX-License-Identifier: BSD-2-Clause-Patent
>  **/
> diff --git a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
> index 7d1675355a..d08b51d3d9 100644
> --- a/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
> +++ b/Silicon/RISC-V/ProcessorPkg/Library/RiscVFirmwareContextStvecLib/RiscVFirmwareContextStvecLib.c
> @@ -1,8 +1,8 @@
>  /** @file
> -  This instance uses This iinstance Supervisor mode STVEC CSR to
> +  This instance uses This instance Supervisor mode STVEC CSR to

Please remove extra "This instance"

Regards
Sunil
>    get/set the pointer of firmware context.

> -  Copyright (c) 2021 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
> +  Copyright (c) 2021-2022 Hewlett Packard Enterprise Development LP. All rights reserved.<BR>

>    SPDX-License-Identifier: BSD-2-Clause-Patent
>  **/
> --
> 2.31.1
>
>
>
>
>
>