[edk2-platforms][PATCH 09/30] SiFive/U5SeriesPkg: Add CLINT to Device Tree


Abner Chang
 

Add CLINT to Device Tree on U540 platform for
M-mode timer and IPI.

Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>

Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../DeviceTree/fu540-c000.dtsi | 591 +++++++++---------
1 file changed, 304 insertions(+), 287 deletions(-)

diff --git a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/De=
viceTree/fu540-c000.dtsi b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnl=
eashedBoard/DeviceTree/fu540-c000.dtsi
index e44b6f7c56..1d8518cfb7 100644
--- a/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre=
e/fu540-c000.dtsi
+++ b/Platform/SiFive/U5SeriesPkg/FreedomU540HiFiveUnleashedBoard/DeviceTre=
e/fu540-c000.dtsi
@@ -1,287 +1,304 @@
-// SPDX-License-Identifier: (GPL-2.0 OR MIT)
-/* Copyright (c) 2018-2019 SiFive, Inc */
-
-/dts-v1/;
-
-/*#include <dt-bindings/clock/sifive-fu540-prci.h>*/
-#include "sifive-fu540-prci.h"
-
-/ {
- #address-cells =3D <2>;
- #size-cells =3D <2>;
- compatible =3D "sifive,fu540-c000", "sifive,fu540";
-
- aliases {
- serial0 =3D &uart0;
- serial1 =3D &uart1;
- ethernet0 =3D &eth0;
- };
-
- chosen {
- };
-
- cpus {
- #address-cells =3D <1>;
- #size-cells =3D <0>;
- cpu0: cpu@0 {
- compatible =3D "sifive,e51", "sifive,rocket0", "riscv";
- device_type =3D "cpu";
- i-cache-block-size =3D <64>;
- i-cache-sets =3D <128>;
- i-cache-size =3D <16384>;
- reg =3D <0>;
- riscv,isa =3D "rv64imac";
- status =3D "disabled";
- cpu0_intc: interrupt-controller {
- #interrupt-cells =3D <1>;
- compatible =3D "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu1: cpu@1 {
- compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size =3D <64>;
- d-cache-sets =3D <64>;
- d-cache-size =3D <32768>;
- d-tlb-sets =3D <1>;
- d-tlb-size =3D <32>;
- device_type =3D "cpu";
- i-cache-block-size =3D <64>;
- i-cache-sets =3D <64>;
- i-cache-size =3D <32768>;
- i-tlb-sets =3D <1>;
- i-tlb-size =3D <32>;
- mmu-type =3D "riscv,sv39";
- reg =3D <1>;
- riscv,isa =3D "rv64imafdc";
- tlb-split;
- next-level-cache =3D <&l2cache>;
- cpu1_intc: interrupt-controller {
- #interrupt-cells =3D <1>;
- compatible =3D "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu2: cpu@2 {
- compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size =3D <64>;
- d-cache-sets =3D <64>;
- d-cache-size =3D <32768>;
- d-tlb-sets =3D <1>;
- d-tlb-size =3D <32>;
- device_type =3D "cpu";
- i-cache-block-size =3D <64>;
- i-cache-sets =3D <64>;
- i-cache-size =3D <32768>;
- i-tlb-sets =3D <1>;
- i-tlb-size =3D <32>;
- mmu-type =3D "riscv,sv39";
- reg =3D <2>;
- riscv,isa =3D "rv64imafdc";
- tlb-split;
- next-level-cache =3D <&l2cache>;
- cpu2_intc: interrupt-controller {
- #interrupt-cells =3D <1>;
- compatible =3D "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu3: cpu@3 {
- compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size =3D <64>;
- d-cache-sets =3D <64>;
- d-cache-size =3D <32768>;
- d-tlb-sets =3D <1>;
- d-tlb-size =3D <32>;
- device_type =3D "cpu";
- i-cache-block-size =3D <64>;
- i-cache-sets =3D <64>;
- i-cache-size =3D <32768>;
- i-tlb-sets =3D <1>;
- i-tlb-size =3D <32>;
- mmu-type =3D "riscv,sv39";
- reg =3D <3>;
- riscv,isa =3D "rv64imafdc";
- tlb-split;
- next-level-cache =3D <&l2cache>;
- cpu3_intc: interrupt-controller {
- #interrupt-cells =3D <1>;
- compatible =3D "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu4: cpu@4 {
- compatible =3D "sifive,u54-mc", "sifive,rocket0", "riscv";
- d-cache-block-size =3D <64>;
- d-cache-sets =3D <64>;
- d-cache-size =3D <32768>;
- d-tlb-sets =3D <1>;
- d-tlb-size =3D <32>;
- device_type =3D "cpu";
- i-cache-block-size =3D <64>;
- i-cache-sets =3D <64>;
- i-cache-size =3D <32768>;
- i-tlb-sets =3D <1>;
- i-tlb-size =3D <32>;
- mmu-type =3D "riscv,sv39";
- reg =3D <4>;
- riscv,isa =3D "rv64imafdc";
- tlb-split;
- next-level-cache =3D <&l2cache>;
- cpu4_intc: interrupt-controller {
- #interrupt-cells =3D <1>;
- compatible =3D "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- };
- soc {
- #address-cells =3D <2>;
- #size-cells =3D <2>;
- compatible =3D "sifive,fu540-c000", "sifive,fu540", "simple-bus";
- ranges;
- plic0: interrupt-controller@c000000 {
- #interrupt-cells =3D <1>;
- compatible =3D "sifive,plic-1.0.0";
- reg =3D <0x0 0xc000000 0x0 0x4000000>;
- riscv,ndev =3D <53>;
- interrupt-controller;
- interrupts-extended =3D <
- &cpu0_intc 0xffffffff
- &cpu1_intc 0xffffffff &cpu1_intc 9
- &cpu2_intc 0xffffffff &cpu2_intc 9
- &cpu3_intc 0xffffffff &cpu3_intc 9
- &cpu4_intc 0xffffffff &cpu4_intc 9>;
- };
- prci: clock-controller@10000000 {
- compatible =3D "sifive,fu540-c000-prci";
- reg =3D <0x0 0x10000000 0x0 0x1000>;
- clocks =3D <&hfclk>, <&rtcclk>;
- #clock-cells =3D <1>;
- };
- uart0: serial@10010000 {
- compatible =3D "sifive,fu540-c000-uart", "sifive,uart0";
- reg =3D <0x0 0x10010000 0x0 0x1000>;
- interrupt-parent =3D <&plic0>;
- interrupts =3D <4>;
- clocks =3D <&prci PRCI_CLK_TLCLK>;
- status =3D "disabled";
- };
- dma: dma@3000000 {
- compatible =3D "sifive,fu540-c000-pdma";
- reg =3D <0x0 0x3000000 0x0 0x8000>;
- interrupt-parent =3D <&plic0>;
- interrupts =3D <23 24 25 26 27 28 29 30>;
- #dma-cells =3D <1>;
- };
- uart1: serial@10011000 {
- compatible =3D "sifive,fu540-c000-uart", "sifive,uart0";
- reg =3D <0x0 0x10011000 0x0 0x1000>;
- interrupt-parent =3D <&plic0>;
- interrupts =3D <5>;
- clocks =3D <&prci PRCI_CLK_TLCLK>;
- status =3D "disabled";
- };
- i2c0: i2c@10030000 {
- compatible =3D "sifive,fu540-c000-i2c", "sifive,i2c0";
- reg =3D <0x0 0x10030000 0x0 0x1000>;
- interrupt-parent =3D <&plic0>;
- interrupts =3D <50>;
- clocks =3D <&prci PRCI_CLK_TLCLK>;
- reg-shift =3D <2>;
- reg-io-width =3D <1>;
- #address-cells =3D <1>;
- #size-cells =3D <0>;
- status =3D "disabled";
- };
- qspi0: spi@10040000 {
- compatible =3D "sifive,fu540-c000-spi", "sifive,spi0";
- reg =3D <0x0 0x10040000 0x0 0x1000
- 0x0 0x20000000 0x0 0x10000000>;
- interrupt-parent =3D <&plic0>;
- interrupts =3D <51>;
- clocks =3D <&prci PRCI_CLK_TLCLK>;
- #address-cells =3D <1>;
- #size-cells =3D <0>;
- status =3D "disabled";
- };
- qspi1: spi@10041000 {
- compatible =3D "sifive,fu540-c000-spi", "sifive,spi0";
- reg =3D <0x0 0x10041000 0x0 0x1000
- 0x0 0x30000000 0x0 0x10000000>;
- interrupt-parent =3D <&plic0>;
- interrupts =3D <52>;
- clocks =3D <&prci PRCI_CLK_TLCLK>;
- #address-cells =3D <1>;
- #size-cells =3D <0>;
- status =3D "disabled";
- };
- qspi2: spi@10050000 {
- compatible =3D "sifive,fu540-c000-spi", "sifive,spi0";
- reg =3D <0x0 0x10050000 0x0 0x1000>;
- interrupt-parent =3D <&plic0>;
- interrupts =3D <6>;
- clocks =3D <&prci PRCI_CLK_TLCLK>;
- #address-cells =3D <1>;
- #size-cells =3D <0>;
- status =3D "disabled";
- };
- eth0: ethernet@10090000 {
- compatible =3D "sifive,fu540-c000-gem";
- interrupt-parent =3D <&plic0>;
- interrupts =3D <53>;
- reg =3D <0x0 0x10090000 0x0 0x2000
- 0x0 0x100a0000 0x0 0x1000>;
- local-mac-address =3D [00 00 00 00 00 00];
- clock-names =3D "pclk", "hclk";
- clocks =3D <&prci PRCI_CLK_GEMGXLPLL>,
- <&prci PRCI_CLK_GEMGXLPLL>;
- #address-cells =3D <1>;
- #size-cells =3D <0>;
- status =3D "disabled";
- };
- pwm0: pwm@10020000 {
- compatible =3D "sifive,fu540-c000-pwm", "sifive,pwm0";
- reg =3D <0x0 0x10020000 0x0 0x1000>;
- interrupt-parent =3D <&plic0>;
- interrupts =3D <42 43 44 45>;
- clocks =3D <&prci PRCI_CLK_TLCLK>;
- #pwm-cells =3D <3>;
- status =3D "disabled";
- };
- pwm1: pwm@10021000 {
- compatible =3D "sifive,fu540-c000-pwm", "sifive,pwm0";
- reg =3D <0x0 0x10021000 0x0 0x1000>;
- interrupt-parent =3D <&plic0>;
- interrupts =3D <46 47 48 49>;
- clocks =3D <&prci PRCI_CLK_TLCLK>;
- #pwm-cells =3D <3>;
- status =3D "disabled";
- };
- l2cache: cache-controller@2010000 {
- compatible =3D "sifive,fu540-c000-ccache", "cache";
- cache-block-size =3D <64>;
- cache-level =3D <2>;
- cache-sets =3D <1024>;
- cache-size =3D <2097152>;
- cache-unified;
- interrupt-parent =3D <&plic0>;
- interrupts =3D <1 2 3>;
- reg =3D <0x0 0x2010000 0x0 0x1000>;
- };
- gpio: gpio@10060000 {
- compatible =3D "sifive,fu540-c000-gpio", "sifive,gpio0";
- interrupt-parent =3D <&plic0>;
- interrupts =3D <7>, <8>, <9>, <10>, <11>, <12>, <13>,
- <14>, <15>, <16>, <17>, <18>, <19>, <20>,
- <21>, <22>;
- reg =3D <0x0 0x10060000 0x0 0x1000>;
- gpio-controller;
- #gpio-cells =3D <2>;
- interrupt-controller;
- #interrupt-cells =3D <2>;
- clocks =3D <&prci PRCI_CLK_TLCLK>;
- status =3D "disabled";
- };
- };
-};
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)=0D
+/* Copyright (c) 2018-2019 SiFive, Inc */=0D
+=0D
+/dts-v1/;=0D
+=0D
+/**@file=0D
+ SiFive U540 platform Device Tree=0D
+=0D
+ Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include "sifive-fu540-prci.h"=0D
+=0D
+/ {=0D
+ #address-cells =3D <2>;=0D
+ #size-cells =3D <2>;=0D
+ compatible =3D "sifive,fu540-c000", "sifive,fu540";=0D
+=0D
+ aliases {=0D
+ serial0 =3D &uart0;=0D
+ serial1 =3D &uart1;=0D
+ ethernet0 =3D &eth0;=0D
+ };=0D
+=0D
+ chosen {=0D
+ };=0D
+=0D
+ cpus {=0D
+ #address-cells =3D <1>;=0D
+ #size-cells =3D <0>;=0D
+ cpu0: cpu@0 {=0D
+ compatible =3D "sifive,e51", "sifive,rocket0", "ri=
scv";=0D
+ device_type =3D "cpu";=0D
+ i-cache-block-size =3D <64>;=0D
+ i-cache-sets =3D <128>;=0D
+ i-cache-size =3D <16384>;=0D
+ reg =3D <0>;=0D
+ riscv,isa =3D "rv64imac";=0D
+ status =3D "disabled";=0D
+ cpu0_intc: interrupt-controller {=0D
+ #interrupt-cells =3D <1>;=0D
+ compatible =3D "riscv,cpu-intc";=0D
+ interrupt-controller;=0D
+ };=0D
+ };=0D
+ cpu1: cpu@1 {=0D
+ compatible =3D "sifive,u54-mc", "sifive,rocket0", =
"riscv";=0D
+ d-cache-block-size =3D <64>;=0D
+ d-cache-sets =3D <64>;=0D
+ d-cache-size =3D <32768>;=0D
+ d-tlb-sets =3D <1>;=0D
+ d-tlb-size =3D <32>;=0D
+ device_type =3D "cpu";=0D
+ i-cache-block-size =3D <64>;=0D
+ i-cache-sets =3D <64>;=0D
+ i-cache-size =3D <32768>;=0D
+ i-tlb-sets =3D <1>;=0D
+ i-tlb-size =3D <32>;=0D
+ mmu-type =3D "riscv,sv39";=0D
+ reg =3D <1>;=0D
+ riscv,isa =3D "rv64imafdc";=0D
+ tlb-split;=0D
+ next-level-cache =3D <&l2cache>;=0D
+ cpu1_intc: interrupt-controller {=0D
+ #interrupt-cells =3D <1>;=0D
+ compatible =3D "riscv,cpu-intc";=0D
+ interrupt-controller;=0D
+ };=0D
+ };=0D
+ cpu2: cpu@2 {=0D
+ compatible =3D "sifive,u54-mc", "sifive,rocket0", =
"riscv";=0D
+ d-cache-block-size =3D <64>;=0D
+ d-cache-sets =3D <64>;=0D
+ d-cache-size =3D <32768>;=0D
+ d-tlb-sets =3D <1>;=0D
+ d-tlb-size =3D <32>;=0D
+ device_type =3D "cpu";=0D
+ i-cache-block-size =3D <64>;=0D
+ i-cache-sets =3D <64>;=0D
+ i-cache-size =3D <32768>;=0D
+ i-tlb-sets =3D <1>;=0D
+ i-tlb-size =3D <32>;=0D
+ mmu-type =3D "riscv,sv39";=0D
+ reg =3D <2>;=0D
+ riscv,isa =3D "rv64imafdc";=0D
+ tlb-split;=0D
+ next-level-cache =3D <&l2cache>;=0D
+ cpu2_intc: interrupt-controller {=0D
+ #interrupt-cells =3D <1>;=0D
+ compatible =3D "riscv,cpu-intc";=0D
+ interrupt-controller;=0D
+ };=0D
+ };=0D
+ cpu3: cpu@3 {=0D
+ compatible =3D "sifive,u54-mc", "sifive,rocket0", =
"riscv";=0D
+ d-cache-block-size =3D <64>;=0D
+ d-cache-sets =3D <64>;=0D
+ d-cache-size =3D <32768>;=0D
+ d-tlb-sets =3D <1>;=0D
+ d-tlb-size =3D <32>;=0D
+ device_type =3D "cpu";=0D
+ i-cache-block-size =3D <64>;=0D
+ i-cache-sets =3D <64>;=0D
+ i-cache-size =3D <32768>;=0D
+ i-tlb-sets =3D <1>;=0D
+ i-tlb-size =3D <32>;=0D
+ mmu-type =3D "riscv,sv39";=0D
+ reg =3D <3>;=0D
+ riscv,isa =3D "rv64imafdc";=0D
+ tlb-split;=0D
+ next-level-cache =3D <&l2cache>;=0D
+ cpu3_intc: interrupt-controller {=0D
+ #interrupt-cells =3D <1>;=0D
+ compatible =3D "riscv,cpu-intc";=0D
+ interrupt-controller;=0D
+ };=0D
+ };=0D
+ cpu4: cpu@4 {=0D
+ compatible =3D "sifive,u54-mc", "sifive,rocket0", =
"riscv";=0D
+ d-cache-block-size =3D <64>;=0D
+ d-cache-sets =3D <64>;=0D
+ d-cache-size =3D <32768>;=0D
+ d-tlb-sets =3D <1>;=0D
+ d-tlb-size =3D <32>;=0D
+ device_type =3D "cpu";=0D
+ i-cache-block-size =3D <64>;=0D
+ i-cache-sets =3D <64>;=0D
+ i-cache-size =3D <32768>;=0D
+ i-tlb-sets =3D <1>;=0D
+ i-tlb-size =3D <32>;=0D
+ mmu-type =3D "riscv,sv39";=0D
+ reg =3D <4>;=0D
+ riscv,isa =3D "rv64imafdc";=0D
+ tlb-split;=0D
+ next-level-cache =3D <&l2cache>;=0D
+ cpu4_intc: interrupt-controller {=0D
+ #interrupt-cells =3D <1>;=0D
+ compatible =3D "riscv,cpu-intc";=0D
+ interrupt-controller;=0D
+ };=0D
+ };=0D
+ };=0D
+ soc {=0D
+ #address-cells =3D <2>;=0D
+ #size-cells =3D <2>;=0D
+ compatible =3D "sifive,fu540-c000", "sifive,fu540", "simpl=
e-bus";=0D
+ ranges;=0D
+ plic0: interrupt-controller@c000000 {=0D
+ #interrupt-cells =3D <1>;=0D
+ compatible =3D "sifive,plic-1.0.0";=0D
+ reg =3D <0x0 0xc000000 0x0 0x4000000>;=0D
+ riscv,ndev =3D <53>;=0D
+ interrupt-controller;=0D
+ interrupts-extended =3D <=0D
+ &cpu0_intc 0xffffffff=0D
+ &cpu1_intc 0xffffffff &cpu1_intc 9=0D
+ &cpu2_intc 0xffffffff &cpu2_intc 9=0D
+ &cpu3_intc 0xffffffff &cpu3_intc 9=0D
+ &cpu4_intc 0xffffffff &cpu4_intc 9>;=0D
+ };=0D
+ prci: clock-controller@10000000 {=0D
+ compatible =3D "sifive,fu540-c000-prci";=0D
+ reg =3D <0x0 0x10000000 0x0 0x1000>;=0D
+ clocks =3D <&hfclk>, <&rtcclk>;=0D
+ #clock-cells =3D <1>;=0D
+ };=0D
+ uart0: serial@10010000 {=0D
+ compatible =3D "sifive,fu540-c000-uart", "sifive,u=
art0";=0D
+ reg =3D <0x0 0x10010000 0x0 0x1000>;=0D
+ interrupt-parent =3D <&plic0>;=0D
+ interrupts =3D <4>;=0D
+ clocks =3D <&prci PRCI_CLK_TLCLK>;=0D
+ status =3D "disabled";=0D
+ };=0D
+ dma: dma@3000000 {=0D
+ compatible =3D "sifive,fu540-c000-pdma";=0D
+ reg =3D <0x0 0x3000000 0x0 0x8000>;=0D
+ interrupt-parent =3D <&plic0>;=0D
+ interrupts =3D <23 24 25 26 27 28 29 30>;=0D
+ #dma-cells =3D <1>;=0D
+ };=0D
+ uart1: serial@10011000 {=0D
+ compatible =3D "sifive,fu540-c000-uart", "sifive,u=
art0";=0D
+ reg =3D <0x0 0x10011000 0x0 0x1000>;=0D
+ interrupt-parent =3D <&plic0>;=0D
+ interrupts =3D <5>;=0D
+ clocks =3D <&prci PRCI_CLK_TLCLK>;=0D
+ status =3D "disabled";=0D
+ };=0D
+ i2c0: i2c@10030000 {=0D
+ compatible =3D "sifive,fu540-c000-i2c", "sifive,i2=
c0";=0D
+ reg =3D <0x0 0x10030000 0x0 0x1000>;=0D
+ interrupt-parent =3D <&plic0>;=0D
+ interrupts =3D <50>;=0D
+ clocks =3D <&prci PRCI_CLK_TLCLK>;=0D
+ reg-shift =3D <2>;=0D
+ reg-io-width =3D <1>;=0D
+ #address-cells =3D <1>;=0D
+ #size-cells =3D <0>;=0D
+ status =3D "disabled";=0D
+ };=0D
+ qspi0: spi@10040000 {=0D
+ compatible =3D "sifive,fu540-c000-spi", "sifive,sp=
i0";=0D
+ reg =3D <0x0 0x10040000 0x0 0x1000=0D
+ 0x0 0x20000000 0x0 0x10000000>;=0D
+ interrupt-parent =3D <&plic0>;=0D
+ interrupts =3D <51>;=0D
+ clocks =3D <&prci PRCI_CLK_TLCLK>;=0D
+ #address-cells =3D <1>;=0D
+ #size-cells =3D <0>;=0D
+ status =3D "disabled";=0D
+ };=0D
+ qspi1: spi@10041000 {=0D
+ compatible =3D "sifive,fu540-c000-spi", "sifive,sp=
i0";=0D
+ reg =3D <0x0 0x10041000 0x0 0x1000=0D
+ 0x0 0x30000000 0x0 0x10000000>;=0D
+ interrupt-parent =3D <&plic0>;=0D
+ interrupts =3D <52>;=0D
+ clocks =3D <&prci PRCI_CLK_TLCLK>;=0D
+ #address-cells =3D <1>;=0D
+ #size-cells =3D <0>;=0D
+ status =3D "disabled";=0D
+ };=0D
+ qspi2: spi@10050000 {=0D
+ compatible =3D "sifive,fu540-c000-spi", "sifive,sp=
i0";=0D
+ reg =3D <0x0 0x10050000 0x0 0x1000>;=0D
+ interrupt-parent =3D <&plic0>;=0D
+ interrupts =3D <6>;=0D
+ clocks =3D <&prci PRCI_CLK_TLCLK>;=0D
+ #address-cells =3D <1>;=0D
+ #size-cells =3D <0>;=0D
+ status =3D "disabled";=0D
+ };=0D
+ eth0: ethernet@10090000 {=0D
+ compatible =3D "sifive,fu540-c000-gem";=0D
+ interrupt-parent =3D <&plic0>;=0D
+ interrupts =3D <53>;=0D
+ reg =3D <0x0 0x10090000 0x0 0x2000=0D
+ 0x0 0x100a0000 0x0 0x1000>;=0D
+ local-mac-address =3D [00 00 00 00 00 00];=0D
+ clock-names =3D "pclk", "hclk";=0D
+ clocks =3D <&prci PRCI_CLK_GEMGXLPLL>,=0D
+ <&prci PRCI_CLK_GEMGXLPLL>;=0D
+ #address-cells =3D <1>;=0D
+ #size-cells =3D <0>;=0D
+ status =3D "disabled";=0D
+ };=0D
+ pwm0: pwm@10020000 {=0D
+ compatible =3D "sifive,fu540-c000-pwm", "sifive,pw=
m0";=0D
+ reg =3D <0x0 0x10020000 0x0 0x1000>;=0D
+ interrupt-parent =3D <&plic0>;=0D
+ interrupts =3D <42 43 44 45>;=0D
+ clocks =3D <&prci PRCI_CLK_TLCLK>;=0D
+ #pwm-cells =3D <3>;=0D
+ status =3D "disabled";=0D
+ };=0D
+ pwm1: pwm@10021000 {=0D
+ compatible =3D "sifive,fu540-c000-pwm", "sifive,pw=
m0";=0D
+ reg =3D <0x0 0x10021000 0x0 0x1000>;=0D
+ interrupt-parent =3D <&plic0>;=0D
+ interrupts =3D <46 47 48 49>;=0D
+ clocks =3D <&prci PRCI_CLK_TLCLK>;=0D
+ #pwm-cells =3D <3>;=0D
+ status =3D "disabled";=0D
+ };=0D
+ l2cache: cache-controller@2010000 {=0D
+ compatible =3D "sifive,fu540-c000-ccache", "cache"=
;=0D
+ cache-block-size =3D <64>;=0D
+ cache-level =3D <2>;=0D
+ cache-sets =3D <1024>;=0D
+ cache-size =3D <2097152>;=0D
+ cache-unified;=0D
+ interrupt-parent =3D <&plic0>;=0D
+ interrupts =3D <1 2 3>;=0D
+ reg =3D <0x0 0x2010000 0x0 0x1000>;=0D
+ };=0D
+ gpio: gpio@10060000 {=0D
+ compatible =3D "sifive,fu540-c000-gpio", "sifive,g=
pio0";=0D
+ interrupt-parent =3D <&plic0>;=0D
+ interrupts =3D <7>, <8>, <9>, <10>, <11>, <12>, <1=
3>,=0D
+ <14>, <15>, <16>, <17>, <18>, <19>, <=
20>,=0D
+ <21>, <22>;=0D
+ reg =3D <0x0 0x10060000 0x0 0x1000>;=0D
+ gpio-controller;=0D
+ #gpio-cells =3D <2>;=0D
+ interrupt-controller;=0D
+ #interrupt-cells =3D <2>;=0D
+ clocks =3D <&prci PRCI_CLK_TLCLK>;=0D
+ status =3D "disabled";=0D
+ };=0D
+ clint: clint@2000000 {=0D
+ compatible =3D "riscv,clint0";=0D
+ interrupts-extended =3D <&cpu0_intc 3 &cpu0_intc 7=0D
+ &cpu1_intc 3 &cpu1_intc 7=0D
+ &cpu2_intc 3 &cpu2_intc 7=0D
+ &cpu3_intc 3 &cpu3_intc 7=0D
+ &cpu4_intc 3 &cpu4_intc 7>;=0D
+ reg =3D <0x0 0x2000000 0x0 0xc0000>;=0D
+ };=0D
+ };=0D
+};=0D
--=20
2.31.1