[edk2-platforms][PATCH 02/30] RISC-V: Add RISC-V PeiCoreEntryPoint library


Abner Chang
 

- Add RISC-V PeiCoreEntryPoint library that incorporates with
opensbi next phase switching mechanism.
- Use RiscVFirmwareContext library to get the pointer of
opensbi FirmwareContext.

Cc: Sunil V L <sunilvl@ventanamicro.com>
Cc: Daniel Schaefer <daniel.schaefer@hpe.com>

Signed-off-by: Abner Chang <abner.chang@hpe.com>
---
.../RISC-V/PlatformPkg/RiscVPlatformPkg.dsc | 7 +-
.../PeiCoreEntryPoint/PeiCoreEntryPoint.inf | 36 +++++++
.../PeiCoreEntryPoint/PeiCoreEntryPoint.c | 97 +++++++++++++++++++
.../PeiCoreEntryPoint/PeiCoreEntryPoint.uni | 14 +++
4 files changed, 153 insertions(+), 1 deletion(-)
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/P=
eiCoreEntryPoint.inf
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/P=
eiCoreEntryPoint.c
create mode 100644 Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/P=
eiCoreEntryPoint.uni

diff --git a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc b/Platform/RI=
SC-V/PlatformPkg/RiscVPlatformPkg.dsc
index 5d9674a965..8eec09549f 100644
--- a/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
+++ b/Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dsc
@@ -1,7 +1,7 @@
#/** @file=0D
# RISC-V platform package.=0D
#=0D
-# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -58,6 +58,10 @@
TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplat=
e.inf=0D
PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC=
offGetEntryPointLib.inf=0D
=0D
+[LibraryClasses.common.PEI_CORE]=0D
+ # RISC-V platform PEI core entry point.=0D
+ PeiCoreEntryPoint|Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/=
PeiCoreEntryPoint.inf=0D
+=0D
[LibraryClasses.common.PEIM]=0D
FirmwareContextProcessorSpecificLib|Platform/RISC-V/PlatformPkg/Library/=
FirmwareContextProcessorSpecificLib/FirmwareContextProcessorSpecificLib.inf=
=0D
HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D
@@ -77,6 +81,7 @@
Platform/RISC-V/PlatformPkg/Library/PlatformUpdateProgressLibNull/Platfo=
rmUpdateProgressLibNull.inf=0D
Platform/RISC-V/PlatformPkg/Library/FirmwareContextProcessorSpecificLib/=
FirmwareContextProcessorSpecificLib.inf=0D
Platform/RISC-V/PlatformPkg/Library/RiscVPlatformTempMemoryInitLibNull/R=
iscVPlatformTempMemoryInitLibNull.inf=0D
+ Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.=
inf=0D
=0D
[Components.common.SEC]=0D
Platform/RISC-V/PlatformPkg/Universal/Sec/SecMain.inf=0D
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreE=
ntryPoint.inf b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCo=
reEntryPoint.inf
new file mode 100644
index 0000000000..e16a974636
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoi=
nt.inf
@@ -0,0 +1,36 @@
+## @file=0D
+# Module entry point library for PEI core on RISC-V with RISC-V OpenSBI.=0D
+#=0D
+# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#=0D
+##=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x00010005=0D
+ BASE_NAME =3D PeiCoreEntryPoint=0D
+ MODULE_UNI_FILE =3D PeiCoreEntryPoint.uni=0D
+ FILE_GUID =3D 2EBF4D2C-99B2-4A09-8C5C-318FB0EF7250=
=0D
+ MODULE_TYPE =3D PEI_CORE=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D PeiCoreEntryPoint|PEI_CORE=0D
+=0D
+#=0D
+# VALID_ARCHITECTURES =3D RISCV64=0D
+#=0D
+=0D
+[Sources]=0D
+ PeiCoreEntryPoint.c=0D
+=0D
+[Packages]=0D
+ MdePkg/MdePkg.dec=0D
+ Platform/RISC-V/PlatformPkg/RiscVPlatformPkg.dec=0D
+ Silicon/RISC-V/ProcessorPkg/RiscVProcessorPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ BaseLib=0D
+ DebugLib=0D
+ RiscVFirmwareContextLib=0D
+=0D
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreE=
ntryPoint.c b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCore=
EntryPoint.c
new file mode 100644
index 0000000000..2fd0f2315b
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoi=
nt.c
@@ -0,0 +1,97 @@
+/** @file=0D
+ Entry point to a the PEI Core on RISC-V platform with RISC-V OpenSBI.=0D
+=0D
+Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>=0D
+Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All rights =
reserved.<BR>=0D
+=0D
+SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+=0D
+#include <PiPei.h>=0D
+#include <IndustryStandard/RiscVOpensbi.h>=0D
+//=0D
+// The Library classes this module produced=0D
+//=0D
+#include <Library/BaseLib.h>=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/PeiCoreEntryPoint.h>=0D
+#include <Library/RiscVFirmwareContextLib.h>=0D
+=0D
+/**=0D
+ The entry point of PE/COFF Image for the PEI Core.=0D
+=0D
+ This function is the entry point for the PEI Foundation, which allows th=
e SEC phase=0D
+ to pass information about the stack, temporary RAM and the Boot Firmware=
Volume.=0D
+ In addition, it also allows the SEC phase to pass services and data forw=
ard for use=0D
+ during the PEI phase in the form of one or more PPIs.=0D
+ There is no limit to the number of additional PPIs that can be passed fr=
om SEC into=0D
+ the PEI Foundation. As part of its initialization phase, the PEI Foundat=
ion will add=0D
+ these SEC-hosted PPIs to its PPI database such that both the PEI Foundat=
ion and any=0D
+ modules can leverage the associated service calls and/or code in these e=
arly PPIs.=0D
+ This function is required to call ProcessModuleEntryPointList() with the=
Context=0D
+ parameter set to NULL. ProcessModuleEntryPoint() is never expected to r=
eturn.=0D
+ The PEI Core is responsible for calling ProcessLibraryConstructorList() =
as soon as=0D
+ the PEI Services Table and the file handle for the PEI Core itself have =
been established.=0D
+ If ProcessModuleEntryPointList() returns, then ASSERT() and halt the sys=
tem.=0D
+=0D
+ @param SecCoreData This is actually the RISC-V boot HART ID passed in a=
0 register.=0D
+=0D
+ @param PpiList This is actually the EFI_RISCV_OPENSBI_FIRMWARE_CONT=
EXT passed=0D
+ in a1 register.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+_ModuleEntryPoint(=0D
+ IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,=0D
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList=0D
+)=0D
+{=0D
+ EFI_SEC_PEI_HAND_OFF *ThisSecCoreData;=0D
+ EFI_PEI_PPI_DESCRIPTOR *ThisPpiList;=0D
+ EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *FirmwareContext;=0D
+=0D
+ FirmwareContext =3D (EFI_RISCV_OPENSBI_FIRMWARE_CONTEXT *)PpiList;=0D
+ SetFirmwareContextPointer (FirmwareContext);=0D
+ ThisSecCoreData =3D (EFI_SEC_PEI_HAND_OFF *)FirmwareContext->SecPeiHandO=
ffData;=0D
+ ThisPpiList =3D (EFI_PEI_PPI_DESCRIPTOR *)FirmwareContext->SecPeiHandoff=
Ppi;=0D
+ ProcessModuleEntryPointList (ThisSecCoreData, ThisPpiList, NULL);=0D
+=0D
+ //=0D
+ // Should never return=0D
+ //=0D
+ ASSERT(FALSE);=0D
+ CpuDeadLoop ();=0D
+}=0D
+=0D
+=0D
+/**=0D
+ Required by the EBC compiler and identical in functionality to _ModuleEn=
tryPoint().=0D
+=0D
+ This function is required to call _ModuleEntryPoint() passing in SecCore=
Data and PpiList.=0D
+=0D
+ @param SecCoreData Points to a data structure containing information ab=
out the PEI core's=0D
+ operating environment, such as the size and location=
of temporary RAM,=0D
+ the stack location and the BFV location.=0D
+=0D
+ @param PpiList Points to a list of one or more PPI descriptors to b=
e installed=0D
+ initially by the PEI core. An empty PPI list consis=
ts of=0D
+ a single descriptor with the end-tag=0D
+ EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST.=0D
+ As part of its initialization phase, the PEI Foundat=
ion will=0D
+ add these SEC-hosted PPIs to its PPI database, such =
that both=0D
+ the PEI Foundationand any modules can leverage the a=
ssociated=0D
+ service calls and/or code in these early PPIs.=0D
+=0D
+**/=0D
+VOID=0D
+EFIAPI=0D
+EfiMain (=0D
+ IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,=0D
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList=0D
+ )=0D
+{=0D
+ _ModuleEntryPoint (SecCoreData, PpiList);=0D
+}=0D
diff --git a/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreE=
ntryPoint.uni b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCo=
reEntryPoint.uni
new file mode 100644
index 0000000000..1955b7a05b
--- /dev/null
+++ b/Platform/RISC-V/PlatformPkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoi=
nt.uni
@@ -0,0 +1,14 @@
+// /** @file=0D
+// Module entry point library for PEI core on RISC-V with RISC-V OpenSBI.=
=0D
+//=0D
+// Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ=
ts reserved.<BR>=0D
+//=0D
+// SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+//=0D
+// **/=0D
+=0D
+=0D
+#string STR_MODULE_ABSTRACT #language en-US "RISC-V module ent=
ry point library for PEI core"=0D
+=0D
+#string STR_MODULE_DESCRIPTION #language en-US "RISC-V module ent=
ry point library for PEI core."=0D
+=0D
--=20
2.31.1