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[PATCH v2 08/34] MdePkg/Include: Add LOONGARCH related definitions EDK2 CI.
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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
HTTP/PXE boot LOONGARCH64 related definitions for EDK2 CI. For the LOONGARCH values, please seeing following URL section "Processor Architecture Types": https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml Cc: Michael D Kinney <michael.d.kinney@...> Cc: Liming Gao <gaoliming@...> Cc: Zhiguang Liu <zhiguang.liu@...> Signed-off-by: Chao Li <lichao@...> --- MdePkg/Include/IndustryStandard/Dhcp.h | 45 ++++++++++++++------------ 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/Dhcp.h b/MdePkg/Include/Indust= ryStandard/Dhcp.h index f209f1b2eb..46ab4f8e75 100644 --- a/MdePkg/Include/IndustryStandard/Dhcp.h +++ b/MdePkg/Include/IndustryStandard/Dhcp.h @@ -4,6 +4,7 @@ =0D Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>=0D Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.<BR>=0D + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D **/=0D =0D @@ -256,27 +257,31 @@ typedef enum { =0D ///=0D /// Processor Architecture Types=0D -/// These identifiers are defined by IETF:=0D -/// http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xm= l=0D +/// These identifiers are defined by IANA:=0D +/// https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.x= html=0D ///=0D -#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE=0D -#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE=0D -#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE=0D -#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE=0D -#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE=0D -#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE= =0D -#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE= =0D -#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for = PXE=0D -#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for = PXE=0D -#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for= PXE=0D +#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE= =0D +#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE=0D +#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE= =0D +#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE= =0D +#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE=0D +#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for P= XE=0D +#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for P= XE=0D +#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 fo= r PXE=0D +#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 fo= r PXE=0D +#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 f= or PXE=0D +#define PXE_CLIENT_ARCH_LOONGARCH32 0x0025 /// LoongArch uefi 32= for PXE=0D +#define PXE_CLIENT_ARCH_LOONGARCH64 0x0027 /// LoongArch uefi 64= for PXE=0D =0D -#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from = http=0D -#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from = http=0D -#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http= =0D -#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot fr= om http=0D -#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot fr= om http=0D -#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot= from http=0D -#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot= from http=0D -#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boo= t from http=0D +#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot fr= om http=0D +#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot fr= om http=0D +#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from ht= tp=0D +#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot= from http=0D +#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot= from http=0D +#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 b= oot from http=0D +#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 b= oot from http=0D +#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 = boot from http=0D +#define HTTP_CLIENT_ARCH_LOONGARCH32 0x0026 /// LoongArch uefi 3= 2 boot from http=0D +#define HTTP_CLIENT_ARCH_LOONGARCH64 0x0028 /// LoongArch uefi 6= 4 boot from http=0D =0D #endif=0D --=20 2.27.0 |
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Hi Mike, In the V2, I updated the IANA URL link in Dhcp.h, can you review this patch again?
On 9ζ 14 2022, at 5:36 δΈε, Chao Li <lichao@...> wrote:
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Michael D Kinney
Reviewed-by: Michael D Kinney <michael.d.kinney@...>
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