[RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT relocations


Sunil V L <sunilvl@...>
 

Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3096

This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20
relocations generated by PIE enabled compiler. This also needed
changes to R_RISCV_32 and R_RISCV_64 relocations as explained in
https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682=
710

Changes in v2:
- Addressed Daniel's comment on formatting

Testing:
1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models.
2) Debian 10.2.0 and booted QEMU virt model.
3) riscv-gnu-tool chain 9.2 and booted QEMU virt model.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>

Acked-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Tested-by: <daniel.schaefer@hpe.com>

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++----
1 file changed, 38 insertions(+), 6 deletions(-)

diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/G=
enFw/Elf64Convert.c
index d097db8632..d684318269 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset;
STATIC UINT8 *mRiscVPass1Targ =3D NULL;=0D
STATIC Elf_Shdr *mRiscVPass1Sym =3D NULL;=0D
STATIC Elf64_Half mRiscVPass1SymSecIndex =3D 0;=0D
+STATIC INT32 mRiscVPass1Offset;=0D
+STATIC INT32 mRiscVPass1GotFixup;=0D
=0D
//=0D
// Initialization Function=0D
@@ -479,11 +481,11 @@ WriteSectionRiscV64 (
break;=0D
=0D
case R_RISCV_32:=0D
- *(UINT32 *)Targ =3D (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_a=
ddr + mCoffSectionsOffset[Sym->st_shndx]);=0D
+ *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend;=0D
break;=0D
=0D
case R_RISCV_64:=0D
- *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSections=
Offset[Sym->st_shndx];=0D
+ *(UINT64 *)Targ =3D Sym->st_value + Rel->r_addend;=0D
break;=0D
=0D
case R_RISCV_HI20:=0D
@@ -533,6 +535,18 @@ WriteSectionRiscV64 (
mRiscVPass1SymSecIndex =3D 0;=0D
break;=0D
=0D
+ case R_RISCV_GOT_HI20:=0D
+ Value =3D (Sym->st_value - Rel->r_offset);=0D
+ mRiscVPass1Offset =3D RV_X(Value, 0, 12);=0D
+ Value =3D RV_X(Value, 12, 20);=0D
+ *(UINT32 *)Targ =3D (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));=0D
+=0D
+ mRiscVPass1Targ =3D Targ;=0D
+ mRiscVPass1Sym =3D SymShdr;=0D
+ mRiscVPass1SymSecIndex =3D Sym->st_shndx;=0D
+ mRiscVPass1GotFixup =3D 1;=0D
+ break;=0D
+=0D
case R_RISCV_PCREL_HI20:=0D
mRiscVPass1Targ =3D Targ;=0D
mRiscVPass1Sym =3D SymShdr;=0D
@@ -545,11 +559,17 @@ WriteSectionRiscV64 (
if (mRiscVPass1Targ !=3D NULL && mRiscVPass1Sym !=3D NULL && mRiscVPas=
s1SymSecIndex !=3D 0) {=0D
int i;=0D
Value2 =3D (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));=0D
- Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));=0D
- if(Value & (RISCV_IMM_REACH/2)) {=0D
- Value |=3D ~(RISCV_IMM_REACH-1);=0D
+=0D
+ if(mRiscVPass1GotFixup) {=0D
+ Value =3D (UINT32)(mRiscVPass1Offset);=0D
+ } else {=0D
+ Value =3D (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));=0D
+ if(Value & (RISCV_IMM_REACH/2)) {=0D
+ Value |=3D ~(RISCV_IMM_REACH-1);=0D
+ }=0D
}=0D
Value =3D Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOff=
set[mRiscVPass1SymSecIndex];=0D
+=0D
if(-2048 > (INT32)Value) {=0D
i =3D (((INT32)Value * -1) / 4096);=0D
Value2 -=3D i;=0D
@@ -569,12 +589,21 @@ WriteSectionRiscV64 (
}=0D
}=0D
=0D
- *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Tar=
g, 0, 20));=0D
+ if(mRiscVPass1GotFixup) {=0D
+ *(UINT32 *)Targ =3D (RV_X((UINT32)Value, 0, 12) << 20)=0D
+ | (RV_X(*(UINT32*)Targ, 0, 20));=0D
+ /* Convert LD instruction to ADDI */=0D
+ *(UINT32 *)Targ =3D ((*(UINT32 *)Targ & ~0x707f) | 0x13);=0D
+ } else {=0D
+ *(UINT32 *)Targ =3D (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)T=
arg, 0, 20));=0D
+ }=0D
*(UINT32 *)mRiscVPass1Targ =3D (RV_X(Value2, 0, 20)<<12) | (RV_X(*(U=
INT32 *)mRiscVPass1Targ, 0, 12));=0D
}=0D
mRiscVPass1Sym =3D NULL;=0D
mRiscVPass1Targ =3D NULL;=0D
mRiscVPass1SymSecIndex =3D 0;=0D
+ mRiscVPass1Offset =3D 0;=0D
+ mRiscVPass1GotFixup =3D 0;=0D
break;=0D
=0D
case R_RISCV_ADD64:=0D
@@ -586,6 +615,7 @@ WriteSectionRiscV64 (
case R_RISCV_GPREL_I:=0D
case R_RISCV_GPREL_S:=0D
case R_RISCV_CALL:=0D
+ case R_RISCV_CALL_PLT:=0D
case R_RISCV_RVC_BRANCH:=0D
case R_RISCV_RVC_JUMP:=0D
case R_RISCV_RELAX:=0D
@@ -1528,6 +1558,7 @@ WriteRelocations64 (
case R_RISCV_GPREL_I:=0D
case R_RISCV_GPREL_S:=0D
case R_RISCV_CALL:=0D
+ case R_RISCV_CALL_PLT:=0D
case R_RISCV_RVC_BRANCH:=0D
case R_RISCV_RVC_JUMP:=0D
case R_RISCV_RELAX:=0D
@@ -1537,6 +1568,7 @@ WriteRelocations64 (
case R_RISCV_SET16:=0D
case R_RISCV_SET32:=0D
case R_RISCV_PCREL_HI20:=0D
+ case R_RISCV_GOT_HI20:=0D
case R_RISCV_PCREL_LO12_I:=0D
break;=0D
=0D
--=20
2.25.1


Sunil V L <sunilvl@...>
 

Hi,
I just edited the commit message to indicate the module and CC the
maintainers. Could I get the feedback please?
Thanks
Sunil

On Fri, Jun 11, 2021 at 07:35:03PM +0530, Sunil V L wrote:
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096

This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20
relocations generated by PIE enabled compiler. This also needed
changes to R_RISCV_32 and R_RISCV_64 relocations as explained in
https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710

Changes in v2:
- Addressed Daniel's comment on formatting

Testing:
1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models.
2) Debian 10.2.0 and booted QEMU virt model.
3) riscv-gnu-tool chain 9.2 and booted QEMU virt model.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>

Acked-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Tested-by: <daniel.schaefer@hpe.com>

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++----
1 file changed, 38 insertions(+), 6 deletions(-)

diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index d097db8632..d684318269 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset;
STATIC UINT8 *mRiscVPass1Targ = NULL;
STATIC Elf_Shdr *mRiscVPass1Sym = NULL;
STATIC Elf64_Half mRiscVPass1SymSecIndex = 0;
+STATIC INT32 mRiscVPass1Offset;
+STATIC INT32 mRiscVPass1GotFixup;

//
// Initialization Function
@@ -479,11 +481,11 @@ WriteSectionRiscV64 (
break;

case R_RISCV_32:
- *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);
+ *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
break;

case R_RISCV_64:
- *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
+ *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
break;

case R_RISCV_HI20:
@@ -533,6 +535,18 @@ WriteSectionRiscV64 (
mRiscVPass1SymSecIndex = 0;
break;

+ case R_RISCV_GOT_HI20:
+ Value = (Sym->st_value - Rel->r_offset);
+ mRiscVPass1Offset = RV_X(Value, 0, 12);
+ Value = RV_X(Value, 12, 20);
+ *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));
+
+ mRiscVPass1Targ = Targ;
+ mRiscVPass1Sym = SymShdr;
+ mRiscVPass1SymSecIndex = Sym->st_shndx;
+ mRiscVPass1GotFixup = 1;
+ break;
+
case R_RISCV_PCREL_HI20:
mRiscVPass1Targ = Targ;
mRiscVPass1Sym = SymShdr;
@@ -545,11 +559,17 @@ WriteSectionRiscV64 (
if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) {
int i;
Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));
- Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
- if(Value & (RISCV_IMM_REACH/2)) {
- Value |= ~(RISCV_IMM_REACH-1);
+
+ if(mRiscVPass1GotFixup) {
+ Value = (UINT32)(mRiscVPass1Offset);
+ } else {
+ Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
+ if(Value & (RISCV_IMM_REACH/2)) {
+ Value |= ~(RISCV_IMM_REACH-1);
+ }
}
Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex];
+
if(-2048 > (INT32)Value) {
i = (((INT32)Value * -1) / 4096);
Value2 -= i;
@@ -569,12 +589,21 @@ WriteSectionRiscV64 (
}
}

- *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
+ if(mRiscVPass1GotFixup) {
+ *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20)
+ | (RV_X(*(UINT32*)Targ, 0, 20));
+ /* Convert LD instruction to ADDI */
+ *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13);
+ } else {
+ *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
+ }
*(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12));
}
mRiscVPass1Sym = NULL;
mRiscVPass1Targ = NULL;
mRiscVPass1SymSecIndex = 0;
+ mRiscVPass1Offset = 0;
+ mRiscVPass1GotFixup = 0;
break;

case R_RISCV_ADD64:
@@ -586,6 +615,7 @@ WriteSectionRiscV64 (
case R_RISCV_GPREL_I:
case R_RISCV_GPREL_S:
case R_RISCV_CALL:
+ case R_RISCV_CALL_PLT:
case R_RISCV_RVC_BRANCH:
case R_RISCV_RVC_JUMP:
case R_RISCV_RELAX:
@@ -1528,6 +1558,7 @@ WriteRelocations64 (
case R_RISCV_GPREL_I:
case R_RISCV_GPREL_S:
case R_RISCV_CALL:
+ case R_RISCV_CALL_PLT:
case R_RISCV_RVC_BRANCH:
case R_RISCV_RVC_JUMP:
case R_RISCV_RELAX:
@@ -1537,6 +1568,7 @@ WriteRelocations64 (
case R_RISCV_SET16:
case R_RISCV_SET32:
case R_RISCV_PCREL_HI20:
+ case R_RISCV_GOT_HI20:
case R_RISCV_PCREL_LO12_I:
break;

--
2.25.1


Daniel Schaefer
 

Great commit message, thanks Sunil!
Maintainers, please take a look and let us know if there's any other concern.
This patch lets us build the RISC-V platforms using modern toolchains that are provided directly by the distributions, rather than building your own from source.

Thanks,
Daniel


From: Sunil V L <sunilvl@...>
Sent: Friday, June 11, 2021 22:08
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@...>; Schaefer, Daniel <daniel.schaefer@...>; Bob Feng <bob.c.feng@...>; Liming Gao <gaoliming@...>; Yuwei Chen <yuwei.chen@...>; Heinrich Schuchardt <xypron.glpk@...>
Subject: Re: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT relocations
 
Hi,
    I just edited the commit message to indicate the module and CC the
    maintainers. Could I get the feedback please?
Thanks
Sunil

On Fri, Jun 11, 2021 at 07:35:03PM +0530, Sunil V L wrote:
> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096
>
> This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20
> relocations generated by PIE enabled compiler. This also needed
> changes to R_RISCV_32 and R_RISCV_64 relocations as explained in
> https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710
>
> Changes in v2:
>   - Addressed Daniel's comment on formatting
>
> Testing:
> 1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models.
> 2) Debian 10.2.0 and booted QEMU virt model.
> 3) riscv-gnu-tool chain 9.2 and booted QEMU virt model.
>
> Signed-off-by: Sunil V L <sunilvl@...>
>
> Acked-by: Abner Chang <abner.chang@...>
> Reviewed-by: Daniel Schaefer <daniel.schaefer@...>
> Tested-by: <daniel.schaefer@...>
>
> Cc: Bob Feng <bob.c.feng@...>
> Cc: Liming Gao <gaoliming@...>
> Cc: Yuwei Chen <yuwei.chen@...>
> Cc: Heinrich Schuchardt <xypron.glpk@...>
> ---
>  BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++----
>  1 file changed, 38 insertions(+), 6 deletions(-)
>
> diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
> index d097db8632..d684318269 100644
> --- a/BaseTools/Source/C/GenFw/Elf64Convert.c
> +++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
> @@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset;
>  STATIC UINT8       *mRiscVPass1Targ = NULL;
>  STATIC Elf_Shdr    *mRiscVPass1Sym = NULL;
>  STATIC Elf64_Half  mRiscVPass1SymSecIndex = 0;
> +STATIC INT32       mRiscVPass1Offset;
> +STATIC INT32       mRiscVPass1GotFixup;

>  //
>  // Initialization Function
> @@ -479,11 +481,11 @@ WriteSectionRiscV64 (
>      break;

>    case R_RISCV_32:
> -    *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);
> +    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
>      break;

>    case R_RISCV_64:
> -    *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
> +    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
>      break;

>    case R_RISCV_HI20:
> @@ -533,6 +535,18 @@ WriteSectionRiscV64 (
>      mRiscVPass1SymSecIndex = 0;
>      break;

> +  case R_RISCV_GOT_HI20:
> +    Value = (Sym->st_value - Rel->r_offset);
> +    mRiscVPass1Offset = RV_X(Value, 0, 12);
> +    Value = RV_X(Value, 12, 20);
> +    *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));
> +
> +    mRiscVPass1Targ = Targ;
> +    mRiscVPass1Sym = SymShdr;
> +    mRiscVPass1SymSecIndex = Sym->st_shndx;
> +    mRiscVPass1GotFixup = 1;
> +    break;
> +
>    case R_RISCV_PCREL_HI20:
>      mRiscVPass1Targ = Targ;
>      mRiscVPass1Sym = SymShdr;
> @@ -545,11 +559,17 @@ WriteSectionRiscV64 (
>      if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) {
>        int i;
>        Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));
> -      Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
> -      if(Value & (RISCV_IMM_REACH/2)) {
> -        Value |= ~(RISCV_IMM_REACH-1);
> +
> +      if(mRiscVPass1GotFixup) {
> +        Value = (UINT32)(mRiscVPass1Offset);
> +      } else {
> +        Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
> +        if(Value & (RISCV_IMM_REACH/2)) {
> +          Value |= ~(RISCV_IMM_REACH-1);
> +        }
>        }
>        Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex];
> +
>        if(-2048 > (INT32)Value) {
>          i = (((INT32)Value * -1) / 4096);
>          Value2 -= i;
> @@ -569,12 +589,21 @@ WriteSectionRiscV64 (
>          }
>        }

> -      *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
> +      if(mRiscVPass1GotFixup) {
> +        *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20)
> +                            | (RV_X(*(UINT32*)Targ, 0, 20));
> +        /* Convert LD instruction to ADDI */
> +        *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13);
> +      } else {
> +        *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
> +      }
>        *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12));
>      }
>      mRiscVPass1Sym = NULL;
>      mRiscVPass1Targ = NULL;
>      mRiscVPass1SymSecIndex = 0;
> +    mRiscVPass1Offset = 0;
> +    mRiscVPass1GotFixup = 0;
>      break;

>    case R_RISCV_ADD64:
> @@ -586,6 +615,7 @@ WriteSectionRiscV64 (
>    case R_RISCV_GPREL_I:
>    case R_RISCV_GPREL_S:
>    case R_RISCV_CALL:
> +  case R_RISCV_CALL_PLT:
>    case R_RISCV_RVC_BRANCH:
>    case R_RISCV_RVC_JUMP:
>    case R_RISCV_RELAX:
> @@ -1528,6 +1558,7 @@ WriteRelocations64 (
>              case R_RISCV_GPREL_I:
>              case R_RISCV_GPREL_S:
>              case R_RISCV_CALL:
> +            case R_RISCV_CALL_PLT:
>              case R_RISCV_RVC_BRANCH:
>              case R_RISCV_RVC_JUMP:
>              case R_RISCV_RELAX:
> @@ -1537,6 +1568,7 @@ WriteRelocations64 (
>              case R_RISCV_SET16:
>              case R_RISCV_SET32:
>              case R_RISCV_PCREL_HI20:
> +            case R_RISCV_GOT_HI20:
>              case R_RISCV_PCREL_LO12_I:
>                break;

> --
> 2.25.1
>


Pete Batard
 

Sunil, Daniel, thanks for the patch.

I confirm that this addresses the 0x13 and 0x14 relocation issues that I was seeing.

However, this patch appears to introduces new R_RISCV_PCREL_LO12_S relocation errors that I was not seeing previously, so I still can't manage to get a successful compilation.

Especially the stream of 0x13 and 0x14 relocation errors I was getting at https://github.com/pbatard/ntfs-3g/runs/2278190652?check_suite_focus=true has now switched to (tested on up to date Ubuntu with latest EDK2):

-------------------------------------------------------------------------
"GenFw" -e UEFI_DRIVER -o /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/OUTPUT/ntfs.efi /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
GenFw: ERROR 3000: Invalid
WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll unsupported ELF EM_RISCV64 relocation 0x19.
make: *** [GNUmakefile:553: /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/OUTPUT/ntfs.efi] Error 2
-------------------------------------------------------------------------

So, in effect, some of the earlier relocation errors appear to have morphed into 0x19/R_RISCV_PCREL_LO12_S ones...

I can open a new bug for this issue if you prefer.

Regards,

/Pete

On 2021.06.15 03:26, Daniel Schaefer wrote:
Great commit message, thanks Sunil!
Maintainers, please take a look and let us know if there's any other concern.
This patch lets us build the RISC-V platforms using modern toolchains that are provided directly by the distributions, rather than building your own from source.
Thanks,
Daniel
------------------------------------------------------------------------
*From:* Sunil V L <sunilvl@ventanamicro.com>
*Sent:* Friday, June 11, 2021 22:08
*To:* devel@edk2.groups.io <devel@edk2.groups.io>
*Cc:* Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>; Schaefer, Daniel <daniel.schaefer@hpe.com>; Bob Feng <bob.c.feng@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>; Yuwei Chen <yuwei.chen@intel.com>; Heinrich Schuchardt <xypron.glpk@gmx.de>
*Subject:* Re: [RESEND PATCH v2] BaseTools: Add support for RISCV GOT/PLT relocations
Hi,
    I just edited the commit message to indicate the module and CC the
    maintainers. Could I get the feedback please?
Thanks
Sunil
On Fri, Jun 11, 2021 at 07:35:03PM +0530, Sunil V L wrote:
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096
<https://bugzilla.tianocore.org/show_bug.cgi?id=3096>
This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20
relocations generated by PIE enabled compiler. This also needed
changes to R_RISCV_32 and R_RISCV_64 relocations as explained in
https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710
<https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710>
Changes in v2:
   - Addressed Daniel's comment on formatting
Testing:
1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models.
2) Debian 10.2.0 and booted QEMU virt model.
3) riscv-gnu-tool chain 9.2 and booted QEMU virt model.
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
Acked-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Tested-by: <daniel.schaefer@hpe.com>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
  BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++----
  1 file changed, 38 insertions(+), 6 deletions(-)
diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index d097db8632..d684318269 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset;
  STATIC UINT8       *mRiscVPass1Targ = NULL;
  STATIC Elf_Shdr    *mRiscVPass1Sym = NULL;
  STATIC Elf64_Half  mRiscVPass1SymSecIndex = 0;
+STATIC INT32       mRiscVPass1Offset;
+STATIC INT32       mRiscVPass1GotFixup;
  //
  // Initialization Function
@@ -479,11 +481,11 @@ WriteSectionRiscV64 (
      break;
    case R_RISCV_32:
-    *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);
+    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
      break;
    case R_RISCV_64:
-    *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
+    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
      break;
    case R_RISCV_HI20:
@@ -533,6 +535,18 @@ WriteSectionRiscV64 (
      mRiscVPass1SymSecIndex = 0;
      break;
+  case R_RISCV_GOT_HI20:
+    Value = (Sym->st_value - Rel->r_offset);
+    mRiscVPass1Offset = RV_X(Value, 0, 12);
+    Value = RV_X(Value, 12, 20);
+    *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));
+
+    mRiscVPass1Targ = Targ;
+    mRiscVPass1Sym = SymShdr;
+    mRiscVPass1SymSecIndex = Sym->st_shndx;
+    mRiscVPass1GotFixup = 1;
+    break;
+
    case R_RISCV_PCREL_HI20:
      mRiscVPass1Targ = Targ;
      mRiscVPass1Sym = SymShdr;
@@ -545,11 +559,17 @@ WriteSectionRiscV64 (
      if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) {
        int i;
        Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));
-      Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
-      if(Value & (RISCV_IMM_REACH/2)) {
-        Value |= ~(RISCV_IMM_REACH-1);
+
+      if(mRiscVPass1GotFixup) {
+        Value = (UINT32)(mRiscVPass1Offset);
+      } else {
+        Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
+        if(Value & (RISCV_IMM_REACH/2)) {
+          Value |= ~(RISCV_IMM_REACH-1);
+        }
        }
        Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex];
+
        if(-2048 > (INT32)Value) {
          i = (((INT32)Value * -1) / 4096);
          Value2 -= i;
@@ -569,12 +589,21 @@ WriteSectionRiscV64 (
          }
        }
-      *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
+      if(mRiscVPass1GotFixup) {
+        *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20)
+                            | (RV_X(*(UINT32*)Targ, 0, 20));
+        /* Convert LD instruction to ADDI */
+        *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13);
+      } else {
+        *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
+      }
        *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12));
      }
      mRiscVPass1Sym = NULL;
      mRiscVPass1Targ = NULL;
      mRiscVPass1SymSecIndex = 0;
+    mRiscVPass1Offset = 0;
+    mRiscVPass1GotFixup = 0;
      break;
    case R_RISCV_ADD64:
@@ -586,6 +615,7 @@ WriteSectionRiscV64 (
    case R_RISCV_GPREL_I:
    case R_RISCV_GPREL_S:
    case R_RISCV_CALL:
+  case R_RISCV_CALL_PLT:
    case R_RISCV_RVC_BRANCH:
    case R_RISCV_RVC_JUMP:
    case R_RISCV_RELAX:
@@ -1528,6 +1558,7 @@ WriteRelocations64 (
              case R_RISCV_GPREL_I:
              case R_RISCV_GPREL_S:
              case R_RISCV_CALL:
+            case R_RISCV_CALL_PLT:
              case R_RISCV_RVC_BRANCH:
              case R_RISCV_RVC_JUMP:
              case R_RISCV_RELAX:
@@ -1537,6 +1568,7 @@ WriteRelocations64 (
              case R_RISCV_SET16:
              case R_RISCV_SET32:
              case R_RISCV_PCREL_HI20:
+            case R_RISCV_GOT_HI20:
              case R_RISCV_PCREL_LO12_I:
                break;
--
2.25.1


Sunil V L <sunilvl@...>
 

Hi Pete,
Thank you very much!.
On Wed, Jun 16, 2021 at 01:35:27PM +0100, Pete Batard wrote:
Sunil, Daniel, thanks for the patch.

I confirm that this addresses the 0x13 and 0x14 relocation issues that I was
seeing.

However, this patch appears to introduces new R_RISCV_PCREL_LO12_S
relocation errors that I was not seeing previously, so I still can't manage
to get a successful compilation.
It is not introduced by the patch but looks like one more new relocation
type is added by the latest tool chain you are using. Please raise a new
bug and I will add the support for it in next patch.

Thanks!
Sunil

Especially the stream of 0x13 and 0x14 relocation errors I was getting at
https://github.com/pbatard/ntfs-3g/runs/2278190652?check_suite_focus=true
has now switched to (tested on up to date Ubuntu with latest EDK2):

-------------------------------------------------------------------------
"GenFw" -e UEFI_DRIVER -o /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/OUTPUT/ntfs.efi /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
GenFw: ERROR 3000: Invalid
WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
make: *** [GNUmakefile:553: /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/OUTPUT/ntfs.efi]
Error 2
-------------------------------------------------------------------------

So, in effect, some of the earlier relocation errors appear to have morphed
into 0x19/R_RISCV_PCREL_LO12_S ones...

I can open a new bug for this issue if you prefer.

Regards,

/Pete

On 2021.06.15 03:26, Daniel Schaefer wrote:
Great commit message, thanks Sunil!
Maintainers, please take a look and let us know if there's any other
concern.
This patch lets us build the RISC-V platforms using modern toolchains
that are provided directly by the distributions, rather than building
your own from source.

Thanks,
Daniel
------------------------------------------------------------------------
*From:* Sunil V L <sunilvl@ventanamicro.com>
*Sent:* Friday, June 11, 2021 22:08
*To:* devel@edk2.groups.io <devel@edk2.groups.io>
*Cc:* Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>;
Schaefer, Daniel <daniel.schaefer@hpe.com>; Bob Feng
<bob.c.feng@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>; Yuwei
Chen <yuwei.chen@intel.com>; Heinrich Schuchardt <xypron.glpk@gmx.de>
*Subject:* Re: [RESEND PATCH v2] BaseTools: Add support for RISCV
GOT/PLT relocations
Hi,
    I just edited the commit message to indicate the module and CC the
    maintainers. Could I get the feedback please?
Thanks
Sunil

On Fri, Jun 11, 2021 at 07:35:03PM +0530, Sunil V L wrote:
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096
<https://bugzilla.tianocore.org/show_bug.cgi?id=3096>

This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20
relocations generated by PIE enabled compiler. This also needed
changes to R_RISCV_32 and R_RISCV_64 relocations as explained in
https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710
<https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710>

Changes in v2:
   - Addressed Daniel's comment on formatting

Testing:
1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models.
2) Debian 10.2.0 and booted QEMU virt model.
3) riscv-gnu-tool chain 9.2 and booted QEMU virt model.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>

Acked-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Tested-by: <daniel.schaefer@hpe.com>

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
  BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++----
  1 file changed, 38 insertions(+), 6 deletions(-)

diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index d097db8632..d684318269 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset;
  STATIC UINT8       *mRiscVPass1Targ = NULL;
  STATIC Elf_Shdr    *mRiscVPass1Sym = NULL;
  STATIC Elf64_Half  mRiscVPass1SymSecIndex = 0;
+STATIC INT32       mRiscVPass1Offset;
+STATIC INT32       mRiscVPass1GotFixup;
  //
  // Initialization Function
@@ -479,11 +481,11 @@ WriteSectionRiscV64 (
      break;
    case R_RISCV_32:
-    *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);
+    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
      break;
    case R_RISCV_64:
-    *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
+    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
      break;
    case R_RISCV_HI20:
@@ -533,6 +535,18 @@ WriteSectionRiscV64 (
      mRiscVPass1SymSecIndex = 0;
      break;
+  case R_RISCV_GOT_HI20:
+    Value = (Sym->st_value - Rel->r_offset);
+    mRiscVPass1Offset = RV_X(Value, 0, 12);
+    Value = RV_X(Value, 12, 20);
+    *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));
+
+    mRiscVPass1Targ = Targ;
+    mRiscVPass1Sym = SymShdr;
+    mRiscVPass1SymSecIndex = Sym->st_shndx;
+    mRiscVPass1GotFixup = 1;
+    break;
+
    case R_RISCV_PCREL_HI20:
      mRiscVPass1Targ = Targ;
      mRiscVPass1Sym = SymShdr;
@@ -545,11 +559,17 @@ WriteSectionRiscV64 (
      if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) {
        int i;
        Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));
-      Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
-      if(Value & (RISCV_IMM_REACH/2)) {
-        Value |= ~(RISCV_IMM_REACH-1);
+
+      if(mRiscVPass1GotFixup) {
+        Value = (UINT32)(mRiscVPass1Offset);
+      } else {
+        Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
+        if(Value & (RISCV_IMM_REACH/2)) {
+          Value |= ~(RISCV_IMM_REACH-1);
+        }
        }
        Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex];
+
        if(-2048 > (INT32)Value) {
          i = (((INT32)Value * -1) / 4096);
          Value2 -= i;
@@ -569,12 +589,21 @@ WriteSectionRiscV64 (
          }
        }
-      *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
+      if(mRiscVPass1GotFixup) {
+        *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20)
+                            | (RV_X(*(UINT32*)Targ, 0, 20));
+        /* Convert LD instruction to ADDI */
+        *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13);
+      } else {
+        *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
+      }
        *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12));
      }
      mRiscVPass1Sym = NULL;
      mRiscVPass1Targ = NULL;
      mRiscVPass1SymSecIndex = 0;
+    mRiscVPass1Offset = 0;
+    mRiscVPass1GotFixup = 0;
      break;
    case R_RISCV_ADD64:
@@ -586,6 +615,7 @@ WriteSectionRiscV64 (
    case R_RISCV_GPREL_I:
    case R_RISCV_GPREL_S:
    case R_RISCV_CALL:
+  case R_RISCV_CALL_PLT:
    case R_RISCV_RVC_BRANCH:
    case R_RISCV_RVC_JUMP:
    case R_RISCV_RELAX:
@@ -1528,6 +1558,7 @@ WriteRelocations64 (
              case R_RISCV_GPREL_I:
              case R_RISCV_GPREL_S:
              case R_RISCV_CALL:
+            case R_RISCV_CALL_PLT:
              case R_RISCV_RVC_BRANCH:
              case R_RISCV_RVC_JUMP:
              case R_RISCV_RELAX:
@@ -1537,6 +1568,7 @@ WriteRelocations64 (
              case R_RISCV_SET16:
              case R_RISCV_SET32:
              case R_RISCV_PCREL_HI20:
+            case R_RISCV_GOT_HI20:
              case R_RISCV_PCREL_LO12_I:
                break;
--
2.25.1


Pete Batard
 

I agree that this is unlikely to be a consequence of the current patch.

I logged new BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3459

Regards,

/Pete

On 2021.06.17 05:44, Sunil V L wrote:
Hi Pete,
Thank you very much!.
On Wed, Jun 16, 2021 at 01:35:27PM +0100, Pete Batard wrote:
Sunil, Daniel, thanks for the patch.

I confirm that this addresses the 0x13 and 0x14 relocation issues that I was
seeing.

However, this patch appears to introduces new R_RISCV_PCREL_LO12_S
relocation errors that I was not seeing previously, so I still can't manage
to get a successful compilation.
It is not introduced by the patch but looks like one more new relocation
type is added by the latest tool chain you are using. Please raise a new
bug and I will add the support for it in next patch.
Thanks!
Sunil

Especially the stream of 0x13 and 0x14 relocation errors I was getting at
https://github.com/pbatard/ntfs-3g/runs/2278190652?check_suite_focus=true
has now switched to (tested on up to date Ubuntu with latest EDK2):

-------------------------------------------------------------------------
"GenFw" -e UEFI_DRIVER -o /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/OUTPUT/ntfs.efi /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
GenFw: ERROR 3000: Invalid
WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteSections64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
GenFw: ERROR 3000: Invalid
WriteRelocations64(): /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/DEBUG/ntfs.dll
unsupported ELF EM_RISCV64 relocation 0x19.
make: *** [GNUmakefile:553: /usr/src/ntfs-3g/Build/RELEASE_GCC5/RISCV64/uefi-driver/uefi_driver/OUTPUT/ntfs.efi]
Error 2
-------------------------------------------------------------------------

So, in effect, some of the earlier relocation errors appear to have morphed
into 0x19/R_RISCV_PCREL_LO12_S ones...

I can open a new bug for this issue if you prefer.

Regards,

/Pete

On 2021.06.15 03:26, Daniel Schaefer wrote:
Great commit message, thanks Sunil!
Maintainers, please take a look and let us know if there's any other
concern.
This patch lets us build the RISC-V platforms using modern toolchains
that are provided directly by the distributions, rather than building
your own from source.

Thanks,
Daniel
------------------------------------------------------------------------
*From:* Sunil V L <sunilvl@ventanamicro.com>
*Sent:* Friday, June 11, 2021 22:08
*To:* devel@edk2.groups.io <devel@edk2.groups.io>
*Cc:* Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>;
Schaefer, Daniel <daniel.schaefer@hpe.com>; Bob Feng
<bob.c.feng@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>; Yuwei
Chen <yuwei.chen@intel.com>; Heinrich Schuchardt <xypron.glpk@gmx.de>
*Subject:* Re: [RESEND PATCH v2] BaseTools: Add support for RISCV
GOT/PLT relocations
Hi,
    I just edited the commit message to indicate the module and CC the
    maintainers. Could I get the feedback please?
Thanks
Sunil

On Fri, Jun 11, 2021 at 07:35:03PM +0530, Sunil V L wrote:
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=3096
<https://bugzilla.tianocore.org/show_bug.cgi?id=3096>

This patch adds support for R_RISCV_CALL_PLT and R_RISCV_GOT_HI20
relocations generated by PIE enabled compiler. This also needed
changes to R_RISCV_32 and R_RISCV_64 relocations as explained in
https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710
<https://github.com/riscv/riscv-gnu-toolchain/issues/905#issuecomment-846682710>

Changes in v2:
   - Addressed Daniel's comment on formatting

Testing:
1) Debian GCC 8.3.0 and booted sifive_u and QMEU virt models.
2) Debian 10.2.0 and booted QEMU virt model.
3) riscv-gnu-tool chain 9.2 and booted QEMU virt model.

Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>

Acked-by: Abner Chang <abner.chang@hpe.com>
Reviewed-by: Daniel Schaefer <daniel.schaefer@hpe.com>
Tested-by: <daniel.schaefer@hpe.com>

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
---
  BaseTools/Source/C/GenFw/Elf64Convert.c | 44 +++++++++++++++++++++----
  1 file changed, 38 insertions(+), 6 deletions(-)

diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/GenFw/Elf64Convert.c
index d097db8632..d684318269 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -129,6 +129,8 @@ STATIC UINT32 mDebugOffset;
  STATIC UINT8       *mRiscVPass1Targ = NULL;
  STATIC Elf_Shdr    *mRiscVPass1Sym = NULL;
  STATIC Elf64_Half  mRiscVPass1SymSecIndex = 0;
+STATIC INT32       mRiscVPass1Offset;
+STATIC INT32       mRiscVPass1GotFixup;
  //
  // Initialization Function
@@ -479,11 +481,11 @@ WriteSectionRiscV64 (
      break;
    case R_RISCV_32:
-    *(UINT32 *)Targ = (UINT32)((UINT64)(*(UINT32 *)Targ) - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx]);
+    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
      break;
    case R_RISCV_64:
-    *(UINT64 *)Targ = *(UINT64 *)Targ - SymShdr->sh_addr + mCoffSectionsOffset[Sym->st_shndx];
+    *(UINT64 *)Targ = Sym->st_value + Rel->r_addend;
      break;
    case R_RISCV_HI20:
@@ -533,6 +535,18 @@ WriteSectionRiscV64 (
      mRiscVPass1SymSecIndex = 0;
      break;
+  case R_RISCV_GOT_HI20:
+    Value = (Sym->st_value - Rel->r_offset);
+    mRiscVPass1Offset = RV_X(Value, 0, 12);
+    Value = RV_X(Value, 12, 20);
+    *(UINT32 *)Targ = (Value << 12) | (RV_X(*(UINT32*)Targ, 0, 12));
+
+    mRiscVPass1Targ = Targ;
+    mRiscVPass1Sym = SymShdr;
+    mRiscVPass1SymSecIndex = Sym->st_shndx;
+    mRiscVPass1GotFixup = 1;
+    break;
+
    case R_RISCV_PCREL_HI20:
      mRiscVPass1Targ = Targ;
      mRiscVPass1Sym = SymShdr;
@@ -545,11 +559,17 @@ WriteSectionRiscV64 (
      if (mRiscVPass1Targ != NULL && mRiscVPass1Sym != NULL && mRiscVPass1SymSecIndex != 0) {
        int i;
        Value2 = (UINT32)(RV_X(*(UINT32 *)mRiscVPass1Targ, 12, 20));
-      Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
-      if(Value & (RISCV_IMM_REACH/2)) {
-        Value |= ~(RISCV_IMM_REACH-1);
+
+      if(mRiscVPass1GotFixup) {
+        Value = (UINT32)(mRiscVPass1Offset);
+      } else {
+        Value = (UINT32)(RV_X(*(UINT32 *)Targ, 20, 12));
+        if(Value & (RISCV_IMM_REACH/2)) {
+          Value |= ~(RISCV_IMM_REACH-1);
+        }
        }
        Value = Value - (UINT32)mRiscVPass1Sym->sh_addr + mCoffSectionsOffset[mRiscVPass1SymSecIndex];
+
        if(-2048 > (INT32)Value) {
          i = (((INT32)Value * -1) / 4096);
          Value2 -= i;
@@ -569,12 +589,21 @@ WriteSectionRiscV64 (
          }
        }
-      *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
+      if(mRiscVPass1GotFixup) {
+        *(UINT32 *)Targ = (RV_X((UINT32)Value, 0, 12) << 20)
+                            | (RV_X(*(UINT32*)Targ, 0, 20));
+        /* Convert LD instruction to ADDI */
+        *(UINT32 *)Targ = ((*(UINT32 *)Targ & ~0x707f) | 0x13);
+      } else {
+        *(UINT32 *)Targ = (RV_X(Value, 0, 12) << 20) | (RV_X(*(UINT32*)Targ, 0, 20));
+      }
        *(UINT32 *)mRiscVPass1Targ = (RV_X(Value2, 0, 20)<<12) | (RV_X(*(UINT32 *)mRiscVPass1Targ, 0, 12));
      }
      mRiscVPass1Sym = NULL;
      mRiscVPass1Targ = NULL;
      mRiscVPass1SymSecIndex = 0;
+    mRiscVPass1Offset = 0;
+    mRiscVPass1GotFixup = 0;
      break;
    case R_RISCV_ADD64:
@@ -586,6 +615,7 @@ WriteSectionRiscV64 (
    case R_RISCV_GPREL_I:
    case R_RISCV_GPREL_S:
    case R_RISCV_CALL:
+  case R_RISCV_CALL_PLT:
    case R_RISCV_RVC_BRANCH:
    case R_RISCV_RVC_JUMP:
    case R_RISCV_RELAX:
@@ -1528,6 +1558,7 @@ WriteRelocations64 (
              case R_RISCV_GPREL_I:
              case R_RISCV_GPREL_S:
              case R_RISCV_CALL:
+            case R_RISCV_CALL_PLT:
              case R_RISCV_RVC_BRANCH:
              case R_RISCV_RVC_JUMP:
              case R_RISCV_RELAX:
@@ -1537,6 +1568,7 @@ WriteRelocations64 (
              case R_RISCV_SET16:
              case R_RISCV_SET32:
              case R_RISCV_PCREL_HI20:
+            case R_RISCV_GOT_HI20:
              case R_RISCV_PCREL_LO12_I:
                break;
--
2.25.1