OK. OK. I am preparing the patches to get the core/cluster info in NXP SOCs. I will move the version print in that code. it *does* set the FIRMWARE_VER environment variable. FIRMWARE_VER is just like

ping!!

Please don't merge this Patch. This patch needs update. The ReservedRam needs to be reported to UEFI. I will send v2 for this patch. other patches in this series can be reviewed. Regards, Pankaj Bansa

From: Pankaj Bansal <pankaj.bansal@...> This patch adds the Support for printing the git commit information in linux build environment. Ideal place of retrieving this information should be python

From: Pankaj Bansal <pankaj.bansal@...> Some NXP SOCs have some specialized IP blocks (like MC), which require DDR memory to operate. This DDR memory should not be managed by OS or UEFI. Moreover

From: Pankaj Bansal <pankaj.bansal@...> For DXE_RUNTIME_DRIVER runtime safe version of DebugLib should be used. Otherwise, any DEBUG print in code can result in abort in OS. Signed-off-by: Pankaj

From: Pankaj Bansal <pankaj.bansal@...> This patch series adds some useful features to NXP platforms. - runtime safe version of DebugLib - Add support for reserving a chunk from RAM - Add Support

From: Pankaj Bansal <pankaj.bansal@...> Add VarStore Fd. This Fd is used to store non volatile variables in flash. Signed-off-by: Pankaj Bansal <pankaj.bansal@...> Reviewed-by: Leif Lindholm <

From: Pankaj Bansal <pankaj.bansal@...> LS1046A Freeway (FRWY) is a high-performance development platform that supports the QorIQ LS1046A Layerscape Architecture SOCs. Co-authored-by: Pramod Kumar

From: Pankaj Bansal <pankaj.bansal@...> LS1046A is QorIq Layerscape multicore communications processor with four Arm Cortex-A72 cores. This SOC is based on Layerscape Chassis v2. Co-authored-by: V

From: Pankaj Bansal <pankaj.bansal@...> For LS1043A SOC the DCFG registers are read in big endian format. After Reading the registers in code we have the registers in Little Endian Bit format i.e.

From: Pankaj Bansal <pankaj.bansal@...> RCW bits parsing and their interpretation varies between various SOCs. Add the comments that explain this parsing scheme. Based on this explanation, fix the

From: Pankaj Bansal <pankaj.bansal@...> The Layerscape LS1046A Freeway (FRWY-LS1046A) board is a high-performance development platform that supports the QorIQ LS1046A architecture processor. The L

From: Pankaj Bansal <pankaj.bansal@...> Add VarStore Fd. This Fd is used to store non volatile variables in flash. Signed-off-by: Pankaj Bansal <pankaj.bansal@...> --- Platform/NXP/LS1046aFrwy

From: Pankaj Bansal <pankaj.bansal@...> LS1046A Freeway (FRWY) is a high-performance development platform that supports the QorIQ LS1046A Layerscape Architecture SOCs. Co-authored-by: Pramod Kumar

From: Pankaj Bansal <pankaj.bansal@...> Add ArmPlatformLib for LS1046AFRWY platform that is based on ArmPlatformPkg/Library/ArmPlatformLibNull. Signed-off-by: Pankaj Bansal <pankaj.bansal@...>

From: Pankaj Bansal <pankaj.bansal@...> LS1046A is QorIq Layerscape multicore communications processor with four Arm Cortex-A72 cores. This SOC is based on Layerscape Chassis v2. Co-authored-by: V

From: Pankaj Bansal <pankaj.bansal@...> For LS1043A SOC the DCFG registers are read in big endian format. After Reading the registers in code we have the registers in Little Endian Bit format i.e.

From: Pankaj Bansal <pankaj.bansal@...> RCW bits parsing and their interpretation varies between various SOCs. Add the comments that explain this parsing scheme. Based on this explanation, fix the

From: Pankaj Bansal <pankaj.bansal@...> The Layerscape LS1046A Freeway (FRWY-LS1046A) board is a high-performance development platform that supports the QorIQ LS1046A architecture processor. The L