Date   

[edk2-platforms PATCH 3/3] SolidRun/Cn913xCEx7Eval: Add platform support

Marcin Wojtas
 

This patch adds the required platform description files, along with
the hardware configuration libraries, for the SolidRun
CN913x CEx7 Evaluation Board. Supported interfaces:

* SPI flash & memory-mapped variable storage access
* uSD
* eMMC
* 7x PCIE root complex
* USB
* Networking:
* 1Gbps RGMII via PHY
* 2500Base-X via quad 1Gpbs switch
* 5Gbps via SFP cage and PHY

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc =
| 54 ++++
Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc =
| 64 +++++
Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc =
| 64 +++++
Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc =
| 68 +++++
Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc =
| 57 ++++
Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.i=
nf | 30 ++
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableIni=
tLib.inf | 38 +++
Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h=
| 30 ++
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableIni=
tLib.h | 13 +
Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c=
| 294 ++++++++++++++++++++
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableIni=
tLib.c | 89 ++++++
Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc =
| 17 ++
12 files changed, 818 insertions(+)
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/Bo=
ardDescriptionLib.inf
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib=
/NonDiscoverableInitLib.inf
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/Bo=
ardDescriptionLib.h
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib=
/NonDiscoverableInitLib.h
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/Bo=
ardDescriptionLib.c
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib=
/NonDiscoverableInitLib.c
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc

diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc b/Platform=
/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
new file mode 100644
index 0000000000..ad0983087d
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
@@ -0,0 +1,54 @@
+## @file=0D
+# Component description file for the CN9130 Development Board (variant A)=
=0D
+#=0D
+# Copyright (c) 2019 Marvell International Ltd.<BR>=0D
+# Copyright (c) 2021 Semihalf.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+##=0D
+=0D
+##########################################################################=
######=0D
+#=0D
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform=0D
+#=0D
+##########################################################################=
######=0D
+[PcdsFixedAtBuild.common]=0D
+ # ComPhy=0D
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1 }=0D
+ # ComPhy0=0D
+ # 0: PCIE0 5 Gbps=0D
+ # 1: PCIE0 5 Gbps=0D
+ # 2: PCIE0 5 Gbps=0D
+ # 3: PCIE0 5 Gbps=0D
+ # 4: SFI 10.31 Gbps=0D
+ # 5: SGMII2 3.125 Gbps=0D
+ gMarvellTokenSpaceGuid.PcdChip0ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $=
(CP_PCIE0), $(CP_PCIE0), $(CP_SFI), $(CP_SGMII2)}=0D
+ gMarvellTokenSpaceGuid.PcdChip0ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5=
G), $(CP_5G), $(CP_10_3125G), $(CP_3_125G) }=0D
+=0D
+ # UtmiPhy=0D
+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1 }=0D
+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H=
OST1) }=0D
+=0D
+ # MDIO=0D
+ gMarvellTokenSpaceGuid.PcdMdioControllersEnabled|{ 0x1 }=0D
+=0D
+ # PHY=0D
+ gMarvellTokenSpaceGuid.PcdPhy2MdioController|{ 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdPhyDeviceIds|{ 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdPhySmiAddresses|{ 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdPhyStartupAutoneg|FALSE=0D
+=0D
+ # NET=0D
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3 }=0D
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1 }=0D
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_=
SPEED_1000), $(PHY_SPEED_2500) }=0D
+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI=
I), $(PHY_SGMII) }=0D
+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF }=0D
+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2 }=0D
+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1 }=0D
+=0D
+ # NonDiscoverableDevices=0D
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1 }=0D
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }=0D
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc b/Platform=
/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
new file mode 100644
index 0000000000..c6b0cefa8d
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
@@ -0,0 +1,64 @@
+## @file=0D
+# Component description file for the CN9131 Development Board (variant A)=
=0D
+#=0D
+# Copyright (c) 2019 Marvell International Ltd.<BR>=0D
+# Copyright (c) 2021 Semihalf.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+##=0D
+=0D
+##########################################################################=
######=0D
+#=0D
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform=0D
+#=0D
+##########################################################################=
######=0D
+[PcdsFixedAtBuild.common]=0D
+ # CP115 count=0D
+ gMarvellTokenSpaceGuid.PcdMaxCpCount|2=0D
+=0D
+ # MPP=0D
+ gMarvellTokenSpaceGuid.PcdMppChipCount|3=0D
+=0D
+ # CP115 #1 MPP=0D
+ gMarvellTokenSpaceGuid.PcdChip2MppReverseFlag|FALSE=0D
+ gMarvellTokenSpaceGuid.PcdChip2MppBaseAddress|0xF4440000=0D
+ gMarvellTokenSpaceGuid.PcdChip2MppPinCount|64=0D
+ gMarvellTokenSpaceGuid.PcdChip2MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0=
x0, 0x0, 0x0, 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdChip2MppSel1|{ 0x0, 0x0, 0x0, 0x3, 0x3, 0x3, 0=
x3, 0x0, 0x0, 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdChip2MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0=
x0, 0x0, 0x7, 0x7 }=0D
+ gMarvellTokenSpaceGuid.PcdChip2MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x2, 0x2, 0=
x2, 0x8, 0x8, 0x9 }=0D
+ gMarvellTokenSpaceGuid.PcdChip2MppSel4|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0=
x0, 0x0, 0x0, 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdChip2MppSel5|{ 0x0, 0x0, 0x2, 0x0, 0x0, 0x0, 0=
x0, 0x0, 0x0, 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdChip2MppSel6|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0=
x0, 0x0, 0x0, 0x0 }=0D
+=0D
+ # ComPhy=0D
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1 }=0D
+ # ComPhy1=0D
+ # 0: PCIE0 5 Gbps=0D
+ # 1: PCIE0 5 Gbps=0D
+ # 2: SFI 5.15625 Gbps=0D
+ # 3: SATA1 5 Gbps=0D
+ # 4: PCIE1 5 Gbps=0D
+ # 5: PCIE2 5 Gbps=0D
+ gMarvellTokenSpaceGuid.PcdChip1ComPhyTypes|{ $(CP_PCIE0), $(CP_PCIE0), $=
(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)}=0D
+ gMarvellTokenSpaceGuid.PcdChip1ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5=
_15625G), $(CP_5G), $(CP_5G), $(CP_5G) }=0D
+=0D
+ # UtmiPhy=0D
+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1 }=
=0D
+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H=
OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1) }=0D
+=0D
+ # NET=0D
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_=
SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000) }=0D
+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI=
I), $(PHY_SGMII), $(PHY_SFI) }=0D
+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF }=0D
+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1 }=0D
+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1 }=0D
+=0D
+ # NonDiscoverableDevices=0D
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1 }=0D
+ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1 }=0D
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }=0D
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc b/Platform=
/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
new file mode 100644
index 0000000000..34f9a3f2fb
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
@@ -0,0 +1,64 @@
+## @file=0D
+# Component description file for the CN9132 Development Board (variant A)=
=0D
+#=0D
+# Copyright (c) 2019 Marvell International Ltd.<BR>=0D
+# Copyright (c) 2021 Semihalf.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+##=0D
+=0D
+##########################################################################=
######=0D
+#=0D
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform=0D
+#=0D
+##########################################################################=
######=0D
+[PcdsFixedAtBuild.common]=0D
+ # CP115 count=0D
+ gMarvellTokenSpaceGuid.PcdMaxCpCount|3=0D
+=0D
+ # MPP=0D
+ gMarvellTokenSpaceGuid.PcdMppChipCount|4=0D
+=0D
+ # CP115 #2 MPP=0D
+ gMarvellTokenSpaceGuid.PcdChip3MppReverseFlag|FALSE=0D
+ gMarvellTokenSpaceGuid.PcdChip3MppBaseAddress|0xF6440000=0D
+ gMarvellTokenSpaceGuid.PcdChip3MppPinCount|64=0D
+ gMarvellTokenSpaceGuid.PcdChip3MppSel0|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0=
x0, 0x0, 0x0, 0x0, 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdChip3MppSel1|{ 0x0, 0x0, 0xFF, 0xFF, 0xFF, 0=
xFF, 0xFF, 0xFF, 0xFF, 0xFF }=0D
+ gMarvellTokenSpaceGuid.PcdChip3MppSel2|{ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0=
xFF, 0xFF, 0x0, 0x7, 0x7 }=0D
+ gMarvellTokenSpaceGuid.PcdChip3MppSel3|{ 0x7, 0x0, 0x0, 0xFF, 0xFF, 0=
x2, 0x2, 0x8, 0x8, 0xFF }=0D
+ gMarvellTokenSpaceGuid.PcdChip3MppSel4|{ 0x0, 0xFF, 0x0, 0x0, 0xFF, 0=
xFF, 0xFF, 0xFF, 0xFF, 0xFF }=0D
+ gMarvellTokenSpaceGuid.PcdChip3MppSel5|{ 0x0, 0xFF, 0xFF, 0xFF, 0xFF, 0=
x0, 0x0, 0xFF, 0xFF, 0xFF }=0D
+ gMarvellTokenSpaceGuid.PcdChip3MppSel6|{ 0xFF, 0xFF, 0xFF, 0x0, 0x0, 0=
x0, 0x0, 0x0, 0x0, 0x0 }=0D
+=0D
+ # ComPhy=0D
+ gMarvellTokenSpaceGuid.PcdComPhyDevices|{ 0x1, 0x1, 0x1 }=0D
+ # ComPhy2=0D
+ # 0: PCIE0 5 Gbps=0D
+ # 1: USB3_HOST0 5 Gbps=0D
+ # 2: SFI 5.15625 Gbps=0D
+ # 3: SATA1 5 Gbps=0D
+ # 4: PCIE1 5 Gbps=0D
+ # 5: PCIE2 5 Gbps=0D
+ gMarvellTokenSpaceGuid.PcdChip2ComPhyTypes|{ $(CP_PCIE0), $(CP_USB3_HOST=
0), $(CP_SFI), $(CP_SATA1), $(CP_PCIE1), $(CP_PCIE2)}=0D
+ gMarvellTokenSpaceGuid.PcdChip2ComPhySpeeds|{ $(CP_5G), $(CP_5G), $(CP_5=
_15625G), $(CP_5G), $(CP_5G), $(CP_5G) }=0D
+=0D
+ # UtmiPhy=0D
+ gMarvellTokenSpaceGuid.PcdUtmiControllersEnabled|{ 0x1, 0x1, 0x0, 0x1, 0=
x1, 0x1 }=0D
+ gMarvellTokenSpaceGuid.PcdUtmiPortType|{ $(UTMI_USB_HOST0), $(UTMI_USB_H=
OST1), $(UTMI_USB_HOST0), $(UTMI_USB_HOST1), $(UTMI_USB_HOST0), $(UTMI_USB_=
HOST1) }=0D
+=0D
+ # NET=0D
+ gMarvellTokenSpaceGuid.PcdPp2GopIndexes|{ 0x0, 0x2, 0x3, 0x0, 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceAlwaysUp|{ 0x0, 0x0, 0x1, 0x0, 0x0=
}=0D
+ gMarvellTokenSpaceGuid.PcdPp2InterfaceSpeed|{ $(PHY_SPEED_10000), $(PHY_=
SPEED_1000), $(PHY_SPEED_2500), $(PHY_SPEED_10000), $(PHY_SPEED_10000) }=0D
+ gMarvellTokenSpaceGuid.PcdPp2PhyConnectionTypes|{ $(PHY_SFI), $(PHY_RGMI=
I), $(PHY_SGMII), $(PHY_SFI), $(PHY_SFI) }=0D
+ gMarvellTokenSpaceGuid.PcdPp2PhyIndexes|{ 0xFF, 0x0, 0xFF, 0xFF, 0xFF }=
=0D
+ gMarvellTokenSpaceGuid.PcdPp2Port2Controller|{ 0x0, 0x0, 0x0, 0x1, 0x2 }=
=0D
+ gMarvellTokenSpaceGuid.PcdPp2PortIds|{ 0x0, 0x1, 0x2, 0x0, 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdPp2Controllers|{ 0x1, 0x1, 0x1 }=0D
+=0D
+ # NonDiscoverableDevices=0D
+ gMarvellTokenSpaceGuid.PcdPciEXhci|{ 0x1, 0x1, 0x0, 0x1, 0x1, 0x1 }=0D
+ gMarvellTokenSpaceGuid.PcdPciEAhci|{ 0x0, 0x1, 0x1 }=0D
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1, 0x1 }=0D
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc b/Platform=
/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
new file mode 100644
index 0000000000..17463c09c6
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
@@ -0,0 +1,68 @@
+## @file=0D
+# Component description file for the CN9130 Development Board (variant A)=
=0D
+#=0D
+# Copyright (c) 2019 Marvell International Ltd.<BR>=0D
+# Copyright (c) 2021 Semihalf.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+##=0D
+=0D
+##########################################################################=
######=0D
+#=0D
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform=0D
+#=0D
+##########################################################################=
######=0D
+[PcdsFixedAtBuild.common]=0D
+ # CP115 count=0D
+ gMarvellTokenSpaceGuid.PcdMaxCpCount|1=0D
+=0D
+ # MPP=0D
+ gMarvellTokenSpaceGuid.PcdMppChipCount|2=0D
+=0D
+ # APN807 MPP=0D
+ gMarvellTokenSpaceGuid.PcdChip0MppReverseFlag|FALSE=0D
+ gMarvellTokenSpaceGuid.PcdChip0MppBaseAddress|0xF06F4000=0D
+ gMarvellTokenSpaceGuid.PcdChip0MppPinCount|20=0D
+ gMarvellTokenSpaceGuid.PcdChip0MppSel0|{ 0x1, 0x1, 0x1, 0x1, 0x1, 0x1, 0=
x1, 0x1, 0x1, 0x1 }=0D
+ gMarvellTokenSpaceGuid.PcdChip0MppSel1|{ 0x1, 0x3, 0x1, 0x0, 0x0, 0x0, 0=
x0, 0x0, 0x0, 0x3 }=0D
+=0D
+ # CP115 #0 MPP=0D
+ gMarvellTokenSpaceGuid.PcdChip1MppReverseFlag|FALSE=0D
+ gMarvellTokenSpaceGuid.PcdChip1MppBaseAddress|0xF2440000=0D
+ gMarvellTokenSpaceGuid.PcdChip1MppPinCount|64=0D
+ gMarvellTokenSpaceGuid.PcdChip1MppSel0|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0=
x3, 0x3, 0x3, 0x3 }=0D
+ gMarvellTokenSpaceGuid.PcdChip1MppSel1|{ 0x3, 0x3, 0x3, 0x3, 0x3, 0x3, 0=
x3, 0x0, 0x0, 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdChip1MppSel2|{ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0=
x0, 0x0, 0x7, 0x7 }=0D
+ gMarvellTokenSpaceGuid.PcdChip1MppSel3|{ 0x7, 0x0, 0x0, 0x0, 0x0, 0x2, 0=
x2, 0x2, 0x2, 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdChip1MppSel4|{ 0x8, 0x8, 0x8, 0x8, 0x0, 0x0, 0=
x0, 0x0, 0x0, 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdChip1MppSel5|{ 0x6, 0x6, 0x2, 0x0, 0x2, 0xB, 0=
xE, 0xE, 0xE, 0xE }=0D
+ gMarvellTokenSpaceGuid.PcdChip1MppSel6|{ 0xE, 0xE, 0x0, 0x0, 0x0, 0x0, 0=
x0, 0x0, 0x0, 0x0 }=0D
+=0D
+ # I2C=0D
+ gMarvellTokenSpaceGuid.PcdI2cSlaveAddresses|{ 0x50 }=0D
+ gMarvellTokenSpaceGuid.PcdI2cSlaveBuses|{ 0x0 }=0D
+ gMarvellTokenSpaceGuid.PcdI2cControllersEnabled|{ 0x0, 0x1 }=0D
+ gMarvellTokenSpaceGuid.PcdI2cClockFrequency|250000000=0D
+ gMarvellTokenSpaceGuid.PcdI2cBaudRate|100000=0D
+=0D
+ # SPI=0D
+ gMarvellTokenSpaceGuid.PcdSpiRegBase|0xF2700680=0D
+ gMarvellTokenSpaceGuid.PcdSpiMaxFrequency|10000000=0D
+ gMarvellTokenSpaceGuid.PcdSpiClockFrequency|200000000=0D
+=0D
+ gMarvellTokenSpaceGuid.PcdSpiFlashMode|3=0D
+ gMarvellTokenSpaceGuid.PcdSpiFlashCs|0=0D
+=0D
+ # NonDiscoverableDevices=0D
+ gMarvellTokenSpaceGuid.PcdPciESdhci|{ 0x1 }=0D
+=0D
+ # RTC=0D
+ gMarvellTokenSpaceGuid.PcdRtcBaseAddress|0xF2284000=0D
+=0D
+ # Variable store=0D
+ gMarvellTokenSpaceGuid.PcdSpiMemoryBase|0xEF000000=0D
+[PcdsDynamicDefault.common]=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0xEF3C000=
0=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xEF3E000=
0=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xEF3D0=
000=0D
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc b/Platform=
/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
new file mode 100644
index 0000000000..6cb82acb13
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
@@ -0,0 +1,57 @@
+## @file=0D
+# Component description file for the CN913x CEx7 Evaluation Board=0D
+#=0D
+# Copyright (c) 2021 Semihalf=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+##=0D
+=0D
+##########################################################################=
######=0D
+#=0D
+# Defines Section - statements that will be processed to create a Makefile=
.=0D
+#=0D
+##########################################################################=
######=0D
+[Defines]=0D
+ PLATFORM_NAME =3D Cn913xCEx7Eval=0D
+ PLATFORM_GUID =3D 4e2ffdd1-c82e-497e-936b-76217e54848a=
=0D
+ PLATFORM_VERSION =3D 0.1=0D
+ DSC_SPECIFICATION =3D 0x0001001B=0D
+ OUTPUT_DIRECTORY =3D Build/$(PLATFORM_NAME)-$(ARCH)=0D
+ SUPPORTED_ARCHITECTURES =3D AARCH64|ARM=0D
+ BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT=0D
+ SKUID_IDENTIFIER =3D DEFAULT=0D
+ FLASH_DEFINITION =3D Silicon/Marvell/Armada7k8k/Armada7k8k=
.fdf=0D
+ BOARD_DXE_FV_COMPONENTS =3D Platform/SolidRun/Cn913xCEx7Eval/Cn91=
3xCEx7Eval.fdf.inc=0D
+ CAPSULE_ENABLE =3D TRUE=0D
+=0D
+ #=0D
+ # Network definition=0D
+ #=0D
+ DEFINE NETWORK_IP6_ENABLE =3D FALSE=0D
+ DEFINE NETWORK_TLS_ENABLE =3D FALSE=0D
+ DEFINE NETWORK_HTTP_BOOT_ENABLE =3D FALSE=0D
+ DEFINE NETWORK_ISCSI_ENABLE =3D FALSE=0D
+=0D
+!include Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc=0D
+!include MdePkg/MdeLibs.dsc.inc=0D
+!include Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc=0D
+!include Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc=0D
+!include Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc=0D
+!include Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc=0D
+=0D
+[Components.common]=0D
+ Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATFORM_NAME).inf=0D
+=0D
+[Components.AARCH64]=0D
+ Silicon/Marvell/OcteonTx/AcpiTables/T91/$(PLATFORM_NAME).inf=0D
+=0D
+[LibraryClasses.common]=0D
+ NonDiscoverableInitLib|Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableI=
nitLib/NonDiscoverableInitLib.inf=0D
+ ArmadaBoardDescLib|Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/=
BoardDescriptionLib.inf=0D
+=0D
+[PcdsFixedAtBuild.common]=0D
+ #Platform description=0D
+ gMarvellTokenSpaceGuid.PcdProductManufacturer|"SolidRun"=0D
+ gMarvellTokenSpaceGuid.PcdProductPlatformName|"CN913x CEx7 Evaluation Bo=
ard"=0D
+ gMarvellTokenSpaceGuid.PcdProductVersion|"Rev. 1.1"=0D
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDesc=
riptionLib.inf b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/Board=
DescriptionLib.inf
new file mode 100644
index 0000000000..ea13ff7ad7
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescription=
Lib.inf
@@ -0,0 +1,30 @@
+## @file=0D
+#=0D
+# Copyright (C) 2019, Marvell International Ltd. and its affiliates<BR>=0D
+# Copyright (C) 2021, Semihalf<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#=0D
+##=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001B=0D
+ BASE_NAME =3D Cn913xCEx7EvalBoardDescriptionLib=0D
+ FILE_GUID =3D 97c47d82-b9b9-4bff-9175-3f26671efea6=
=0D
+ MODULE_TYPE =3D BASE=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D ArmadaBoardDescLib=0D
+=0D
+[Sources]=0D
+ BoardDescriptionLib.c=0D
+=0D
+[Packages]=0D
+ EmbeddedPkg/EmbeddedPkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ Silicon/Marvell/Marvell.dec=0D
+=0D
+[LibraryClasses]=0D
+ DebugLib=0D
+ IoLib=0D
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDis=
coverableInitLib.inf b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInit=
Lib/NonDiscoverableInitLib.inf
new file mode 100644
index 0000000000..c58ba8397a
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverab=
leInitLib.inf
@@ -0,0 +1,38 @@
+## @file=0D
+#=0D
+# Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>=0D
+# Copyright (c) 2019, Marvell International Ltd. All rights reserved.<BR>=
=0D
+# Copyright (c) 2021, Semihalf. All rights reserved.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+#=0D
+##=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001B=0D
+ BASE_NAME =3D Cn913xCExEvalNonDiscoverableInitLib=0D
+ FILE_GUID =3D 8e6a8766-df51-497f-9743-fc0d9170ced8=
=0D
+ MODULE_TYPE =3D BASE=0D
+ VERSION_STRING =3D 1.0=0D
+ LIBRARY_CLASS =3D NonDiscoverableInitLib=0D
+=0D
+[Sources]=0D
+ NonDiscoverableInitLib.c=0D
+=0D
+[Packages]=0D
+ EmbeddedPkg/EmbeddedPkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ Silicon/Marvell/Marvell.dec=0D
+=0D
+[LibraryClasses]=0D
+ DebugLib=0D
+ IoLib=0D
+ MvGpioLib=0D
+=0D
+[Protocols]=0D
+ gEmbeddedGpioProtocolGuid=0D
+=0D
+[Depex]=0D
+ gMarvellPlatformInitCompleteProtocolGuid=0D
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDesc=
riptionLib.h b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDe=
scriptionLib.h
new file mode 100644
index 0000000000..d5d96e1e49
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescription=
Lib.h
@@ -0,0 +1,30 @@
+/**=0D
+*=0D
+* Copyright (C) 2021, Semihalf.=0D
+*=0D
+* SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+*=0D
+**/=0D
+#ifndef BOARD_DESCRIPTION_LIB_H__=0D
+#define BOARD_DESCRIPTION_LIB_H__=0D
+=0D
+#define IO_WIN_ALR_OFFSET(WinId) (0xF06F0000 + 0x0 + (0x10 * (WinId=
)))=0D
+#define IO_WIN_AHR_OFFSET(WinId) (0xF06F0000 + 0x8 + (0x10 * (WinId=
)))=0D
+#define IO_WIN_CR_OFFSET(WinId) (0xF06F0000 + 0xC + (0x10 * (WinId=
)))=0D
+#define IO_WIN_ENABLE_BIT 0x1=0D
+#define IO_WIN_ADDRESS_SHIFT 16=0D
+#define IO_WIN_ADDRESS_MASK 0xFFFFFFF0=0D
+=0D
+#define MCI1_TARGET_ID 0x1=0D
+#define CP2_PCIE_WIN32_BASE 0xe9000000=0D
+#define CP2_PCIE_WIN32_SIZE 0x6000000=0D
+#define CP2_PCIE_WIN32_ID 0x5=0D
+#define CP2_PCIE_WIN64_BASE 0x8c0000000=0D
+#define CP2_PCIE_WIN64_SIZE 0x30000000=0D
+#define CP2_PCIE_WIN64_ID 0x6=0D
+=0D
+#define CP0_GPIO1_DATA_OUT_REG 0xF2440140=0D
+#define CP0_GPIO1_OUT_EN_REG 0xF2440144=0D
+#define CP0_GPIO1_PIN_MASK (1 << 7)=0D
+=0D
+#endif=0D
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDis=
coverableInitLib.h b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLi=
b/NonDiscoverableInitLib.h
new file mode 100644
index 0000000000..937b84b99d
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverab=
leInitLib.h
@@ -0,0 +1,13 @@
+/**=0D
+*=0D
+* Copyright (c) 2021, Semihalf. All rights reserved.=0D
+*=0D
+* SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+*=0D
+**/=0D
+#ifndef NON_DISCOVERABLE_INIT_LIB_H__=0D
+#define NON_DISCOVERABLE_INIT_LIB_H__=0D
+=0D
+#define CN913X_CEX7_AP_SDMMC_VCCQ_PIN 26=0D
+=0D
+#endif=0D
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDesc=
riptionLib.c b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDe=
scriptionLib.c
new file mode 100644
index 0000000000..8c336b4fd5
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescription=
Lib.c
@@ -0,0 +1,294 @@
+/**=0D
+*=0D
+* Copyright (C) 2021, Semihalf.=0D
+*=0D
+* SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+*=0D
+**/=0D
+=0D
+#include <Uefi.h>=0D
+=0D
+#include <Library/ArmadaBoardDescLib.h>=0D
+#include <Library/BaseMemoryLib.h>=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/IoLib.h>=0D
+#include <Library/MemoryAllocationLib.h>=0D
+#include <Library/MvGpioLib.h>=0D
+#include <Library/UefiBootServicesTableLib.h>=0D
+=0D
+#include "BoardDescriptionLib.h"=0D
+=0D
+STATIC=0D
+VOID=0D
+ConfigureIoWindow (=0D
+ UINT64 WinBaseAddress,=0D
+ UINT64 WinSize,=0D
+ UINTN WinId,=0D
+ UINT32 WinTargetId=0D
+ )=0D
+{=0D
+ UINT32 AddressHigh;=0D
+ UINT32 AddressLow;=0D
+ UINT64 MaxAddress;=0D
+=0D
+ /* Disable IO window. */=0D
+ MmioWrite32 (IO_WIN_ALR_OFFSET(WinId), 0);=0D
+=0D
+ /* Calculate the end address. */=0D
+ MaxAddress =3D (WinBaseAddress + WinSize - 1);=0D
+=0D
+ AddressLow =3D (UINT32)((WinBaseAddress >> IO_WIN_ADDRESS_SHIFT) & IO_WI=
N_ADDRESS_MASK);=0D
+ AddressLow |=3D IO_WIN_ENABLE_BIT;=0D
+ AddressHigh =3D (UINT32)((MaxAddress >> IO_WIN_ADDRESS_SHIFT) & IO_WIN_A=
DDRESS_MASK);=0D
+=0D
+ /* Write start address and end address for IO window. */=0D
+ MmioWrite32 (IO_WIN_ALR_OFFSET(WinId), AddressLow);=0D
+ MmioWrite32 (IO_WIN_AHR_OFFSET(WinId), AddressHigh);=0D
+=0D
+ /* Write window target. */=0D
+ MmioWrite32 (IO_WIN_CR_OFFSET(WinId), WinTargetId);=0D
+}=0D
+=0D
+//=0D
+// General purpose routine for per-board initalization=0D
+//=0D
+EFI_STATUS=0D
+ArmadaBoardInit (=0D
+ VOID=0D
+ )=0D
+{=0D
+ /*=0D
+ * Due to lack of sufficient number of IO windows registers,=0D
+ * the CP2 PCIE configuration must be performed after the=0D
+ * early firmware stages. Replace the MCI 0/1 indirect=0D
+ * windows, which are no longer needed.=0D
+ */=0D
+ ConfigureIoWindow (=0D
+ CP2_PCIE_WIN32_BASE,=0D
+ CP2_PCIE_WIN32_SIZE,=0D
+ CP2_PCIE_WIN32_ID,=0D
+ MCI1_TARGET_ID=0D
+ );=0D
+=0D
+ ConfigureIoWindow (=0D
+ CP2_PCIE_WIN64_BASE,=0D
+ CP2_PCIE_WIN64_SIZE,=0D
+ CP2_PCIE_WIN64_ID,=0D
+ MCI1_TARGET_ID=0D
+ );=0D
+=0D
+ /* Enable FAN */=0D
+ MmioAnd32 (CP0_GPIO1_DATA_OUT_REG, ~CP0_GPIO1_PIN_MASK);=0D
+ MmioAnd32 (CP0_GPIO1_OUT_EN_REG, ~CP0_GPIO1_PIN_MASK);=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+//=0D
+// GPIO Expander=0D
+//=0D
+EFI_STATUS=0D
+EFIAPI=0D
+ArmadaBoardGpioExpanderGet (=0D
+ IN OUT MV_GPIO_EXPANDER **GpioExpanders,=0D
+ IN OUT UINTN *GpioExpanderCount=0D
+ )=0D
+{=0D
+ /* No GPIO expanders on board */=0D
+ *GpioExpanders =3D NULL;=0D
+ *GpioExpanderCount =3D 0;=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+//=0D
+// PCIE=0D
+//=0D
+STATIC=0D
+MV_PCIE_CONTROLLER mPcieController[] =3D {=0D
+ { /* CP0 PCIE0 @0xF2600000 */=0D
+ .PcieDbiAddress =3D 0xF2600000,=0D
+ .ConfigSpaceAddress =3D 0x800000000,=0D
+ .HaveResetGpio =3D FALSE,=0D
+ .PcieResetGpio =3D { 0 },=0D
+ .PcieBusMin =3D 0,=0D
+ .PcieBusMax =3D 0xFE,=0D
+ .PcieIoTranslation =3D 0x80FF00000,=0D
+ .PcieIoWinBase =3D 0x0,=0D
+ .PcieIoWinSize =3D 0x10000,=0D
+ .PcieMmio32Translation =3D 0,=0D
+ .PcieMmio32WinBase =3D 0xC0000000,=0D
+ .PcieMmio32WinSize =3D 0x20000000,=0D
+ .PcieMmio64Translation =3D 0,=0D
+ .PcieMmio64WinBase =3D 0x810000000,=0D
+ .PcieMmio64WinSize =3D 0x80000000,=0D
+ },=0D
+ { /* CP1 PCIE0 @0xF4600000 */=0D
+ .PcieDbiAddress =3D 0xF4600000,=0D
+ .ConfigSpaceAddress =3D 0xE2000000,=0D
+ .HaveResetGpio =3D FALSE,=0D
+ .PcieResetGpio =3D { 0 },=0D
+ .PcieBusMin =3D 0,=0D
+ .PcieBusMax =3D 0xE,=0D
+ .PcieIoTranslation =3D 0xE2F00000,=0D
+ .PcieIoWinBase =3D 0x0,=0D
+ .PcieIoWinSize =3D 0x10000,=0D
+ .PcieMmio32Translation =3D 0,=0D
+ .PcieMmio32WinBase =3D 0xE3000000,=0D
+ .PcieMmio32WinSize =3D 0x1000000,=0D
+ .PcieMmio64Translation =3D 0,=0D
+ .PcieMmio64WinBase =3D 0x890000000,=0D
+ .PcieMmio64WinSize =3D 0x10000000,=0D
+ },=0D
+ { /* CP1 PCIE1 @0xF4620000 */=0D
+ .PcieDbiAddress =3D 0xF4620000,=0D
+ .ConfigSpaceAddress =3D 0xE4000000,=0D
+ .HaveResetGpio =3D FALSE,=0D
+ .PcieResetGpio =3D { 0 },=0D
+ .PcieBusMin =3D 0,=0D
+ .PcieBusMax =3D 0xE,=0D
+ .PcieIoTranslation =3D 0xE4F00000,=0D
+ .PcieIoWinBase =3D 0x0,=0D
+ .PcieIoWinSize =3D 0x10000,=0D
+ .PcieMmio32Translation =3D 0,=0D
+ .PcieMmio32WinBase =3D 0xE5000000,=0D
+ .PcieMmio32WinSize =3D 0x1000000,=0D
+ .PcieMmio64Translation =3D 0,=0D
+ .PcieMmio64WinBase =3D 0x8A0000000,=0D
+ .PcieMmio64WinSize =3D 0x10000000,=0D
+ },=0D
+ { /* CP1 PCIE2 @0xF4640000 */=0D
+ .PcieDbiAddress =3D 0xF4640000,=0D
+ .ConfigSpaceAddress =3D 0xE6000000,=0D
+ .HaveResetGpio =3D FALSE,=0D
+ .PcieResetGpio =3D { 0 },=0D
+ .PcieBusMin =3D 0,=0D
+ .PcieBusMax =3D 0xE,=0D
+ .PcieIoTranslation =3D 0xE6F00000,=0D
+ .PcieIoWinBase =3D 0x0,=0D
+ .PcieIoWinSize =3D 0x10000,=0D
+ .PcieMmio32Translation =3D 0,=0D
+ .PcieMmio32WinBase =3D 0xE7000000,=0D
+ .PcieMmio32WinSize =3D 0x1000000,=0D
+ .PcieMmio64Translation =3D 0,=0D
+ .PcieMmio64WinBase =3D 0x8B0000000,=0D
+ .PcieMmio64WinSize =3D 0x10000000,=0D
+ },=0D
+ { /* CP2 PCIE0 @0xF6600000 */=0D
+ .PcieDbiAddress =3D 0xF6600000,=0D
+ .ConfigSpaceAddress =3D 0xE9000000,=0D
+ .HaveResetGpio =3D FALSE,=0D
+ .PcieResetGpio =3D { 0 },=0D
+ .PcieBusMin =3D 0,=0D
+ .PcieBusMax =3D 0xE,=0D
+ .PcieIoTranslation =3D 0xE9F00000,=0D
+ .PcieIoWinBase =3D 0x0,=0D
+ .PcieIoWinSize =3D 0x10000,=0D
+ .PcieMmio32Translation =3D 0,=0D
+ .PcieMmio32WinBase =3D 0xEA000000,=0D
+ .PcieMmio32WinSize =3D 0x1000000,=0D
+ .PcieMmio64Translation =3D 0,=0D
+ .PcieMmio64WinBase =3D 0x8C0000000,=0D
+ .PcieMmio64WinSize =3D 0x10000000,=0D
+ },=0D
+ { /* CP2 PCIE1 @0xF6620000 */=0D
+ .PcieDbiAddress =3D 0xF6620000,=0D
+ .ConfigSpaceAddress =3D 0xEB000000,=0D
+ .HaveResetGpio =3D FALSE,=0D
+ .PcieResetGpio =3D { 0 },=0D
+ .PcieBusMin =3D 0,=0D
+ .PcieBusMax =3D 0xE,=0D
+ .PcieIoTranslation =3D 0xEBF00000,=0D
+ .PcieIoWinBase =3D 0x0,=0D
+ .PcieIoWinSize =3D 0x10000,=0D
+ .PcieMmio32Translation =3D 0,=0D
+ .PcieMmio32WinBase =3D 0xEC000000,=0D
+ .PcieMmio32WinSize =3D 0x1000000,=0D
+ .PcieMmio64Translation =3D 0,=0D
+ .PcieMmio64WinBase =3D 0x8D0000000,=0D
+ .PcieMmio64WinSize =3D 0x10000000,=0D
+ },=0D
+ { /* CP2 PCIE2 @0xF6640000 */=0D
+ .PcieDbiAddress =3D 0xF6640000,=0D
+ .ConfigSpaceAddress =3D 0xED000000,=0D
+ .HaveResetGpio =3D FALSE,=0D
+ .PcieResetGpio =3D { 0 },=0D
+ .PcieBusMin =3D 0,=0D
+ .PcieBusMax =3D 0xE,=0D
+ .PcieIoTranslation =3D 0xEDF00000,=0D
+ .PcieIoWinBase =3D 0x0,=0D
+ .PcieIoWinSize =3D 0x10000,=0D
+ .PcieMmio32Translation =3D 0,=0D
+ .PcieMmio32WinBase =3D 0xEE000000,=0D
+ .PcieMmio32WinSize =3D 0x1000000,=0D
+ .PcieMmio64Translation =3D 0,=0D
+ .PcieMmio64WinBase =3D 0x8E0000000,=0D
+ .PcieMmio64WinSize =3D 0x10000000,=0D
+ },=0D
+};=0D
+=0D
+/**=0D
+ Return the number and description of PCIE controllers used on the platfo=
rm.=0D
+=0D
+ @param[in out] **PcieControllers Array containing PCIE controllers'=
=0D
+ description.=0D
+ @param[in out] *PcieControllerCount Amount of used PCIE controllers.=0D
+=0D
+ @retval EFI_SUCCESS The data were obtained successfull=
y.=0D
+ @retval other Return error status.=0D
+=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+ArmadaBoardPcieControllerGet (=0D
+ IN OUT MV_PCIE_CONTROLLER CONST **PcieControllers,=0D
+ IN OUT UINTN *PcieControllerCount=0D
+ )=0D
+{=0D
+ *PcieControllers =3D mPcieController;=0D
+ *PcieControllerCount =3D ARRAY_SIZE (mPcieController);=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+//=0D
+// Order of devices in SdMmcDescTemplate has to be in par with ArmadaSoCDe=
scLib=0D
+//=0D
+STATIC=0D
+MV_BOARD_SDMMC_DESC mSdMmcDescTemplate[] =3D {=0D
+ { /* eMMC 0xF06E0000 */=0D
+ 0, /* SOC will be filled by MvBoardDescDxe */=0D
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */=0D
+ TRUE, /* Xenon1v8Enabled */=0D
+ /*=0D
+ * Force 4-bit bus width - work-around for non=0D
+ * functional HS400 mode.=0D
+ */=0D
+ FALSE, /* Xenon8BitBusEnabled */=0D
+ FALSE, /* XenonSlowModeEnabled */=0D
+ 0x40, /* XenonTuningStepDivisor */=0D
+ EmbeddedSlot /* SlotType */=0D
+ },=0D
+ { /* SD/MMC 0xF2780000 */=0D
+ 0, /* SOC will be filled by MvBoardDescDxe */=0D
+ 0, /* SdMmcDevCount will be filled by MvBoardDescDxe */=0D
+ FALSE, /* Xenon1v8Enabled */=0D
+ FALSE, /* Xenon8BitBusEnabled */=0D
+ FALSE, /* XenonSlowModeEnabled */=0D
+ 0x19, /* XenonTuningStepDivisor */=0D
+ EmbeddedSlot /* SlotType */=0D
+ },=0D
+};=0D
+=0D
+EFI_STATUS=0D
+EFIAPI=0D
+ArmadaBoardDescSdMmcGet (=0D
+ OUT UINTN *SdMmcDevCount,=0D
+ OUT MV_BOARD_SDMMC_DESC **SdMmcDesc=0D
+ )=0D
+{=0D
+ *SdMmcDesc =3D mSdMmcDescTemplate;=0D
+ *SdMmcDevCount =3D ARRAY_SIZE (mSdMmcDescTemplate);=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDis=
coverableInitLib.c b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLi=
b/NonDiscoverableInitLib.c
new file mode 100644
index 0000000000..18312ac403
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverab=
leInitLib.c
@@ -0,0 +1,89 @@
+/**=0D
+*=0D
+* Copyright (c) 2017, Linaro Ltd. All rights reserved.=0D
+* Copyright (c) 2019, Marvell International Ltd. All rights reserved.=0D
+* Copyright (c) 2021, Semihalf. All rights reserved.=0D
+*=0D
+* SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+*=0D
+**/=0D
+=0D
+#include <Uefi.h>=0D
+=0D
+#include <Library/DebugLib.h>=0D
+#include <Library/DevicePathLib.h>=0D
+#include <Library/IoLib.h>=0D
+#include <Library/MemoryAllocationLib.h>=0D
+#include <Library/MvGpioLib.h>=0D
+#include <Library/NonDiscoverableDeviceRegistrationLib.h>=0D
+#include <Library/UefiBootServicesTableLib.h>=0D
+=0D
+#include <Protocol/NonDiscoverableDevice.h>=0D
+=0D
+#include "NonDiscoverableInitLib.h"=0D
+=0D
+STATIC=0D
+EFI_STATUS=0D
+EFIAPI=0D
+ConfigurePins (=0D
+ IN CONST MV_GPIO_PIN *VbusPin,=0D
+ IN UINTN PinCount,=0D
+ IN MV_GPIO_DRIVER_TYPE DriverType=0D
+ )=0D
+{=0D
+ EMBEDDED_GPIO_MODE Mode;=0D
+ EMBEDDED_GPIO_PIN Gpio;=0D
+ EMBEDDED_GPIO *GpioProtocol;=0D
+ EFI_STATUS Status;=0D
+ UINTN Index;=0D
+=0D
+ Status =3D MvGpioGetProtocol (DriverType, &GpioProtocol);=0D
+ if (EFI_ERROR (Status)) {=0D
+ DEBUG ((DEBUG_ERROR, "%a: Unable to find GPIO protocol\n", __FUNCTION_=
_));=0D
+ return Status;=0D
+ }=0D
+=0D
+ for (Index =3D 0; Index < PinCount; Index++) {=0D
+ Mode =3D VbusPin->ActiveHigh ? GPIO_MODE_OUTPUT_1 : GPIO_MODE_OUTPUT_0=
;=0D
+ Gpio =3D GPIO (VbusPin->ControllerId, VbusPin->PinNumber);=0D
+ GpioProtocol->Set (GpioProtocol, Gpio, Mode);=0D
+ VbusPin++;=0D
+ }=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+STATIC CONST MV_GPIO_PIN mApSdMmcPins[] =3D {=0D
+ {=0D
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER,=0D
+ MV_GPIO_CP0_CONTROLLER0,=0D
+ CN913X_CEX7_AP_SDMMC_VCCQ_PIN,=0D
+ TRUE,=0D
+ },=0D
+};=0D
+=0D
+STATIC=0D
+EFI_STATUS=0D
+EFIAPI=0D
+ApSdMmcInit (=0D
+ IN NON_DISCOVERABLE_DEVICE *This=0D
+ )=0D
+{=0D
+ return ConfigurePins (mApSdMmcPins,=0D
+ ARRAY_SIZE (mApSdMmcPins),=0D
+ MV_GPIO_DRIVER_TYPE_SOC_CONTROLLER);=0D
+}=0D
+=0D
+NON_DISCOVERABLE_DEVICE_INIT=0D
+EFIAPI=0D
+NonDiscoverableDeviceInitializerGet (=0D
+ IN NON_DISCOVERABLE_DEVICE_TYPE Type,=0D
+ IN UINTN Index=0D
+ )=0D
+{=0D
+ if (Type =3D=3D NonDiscoverableDeviceTypeSdhci && Index =3D=3D 0) {=0D
+ return ApSdMmcInit;=0D
+ }=0D
+=0D
+ return NULL;=0D
+}=0D
diff --git a/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc b/Plat=
form/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc
new file mode 100644
index 0000000000..6cf2be0b1e
--- /dev/null
+++ b/Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc
@@ -0,0 +1,17 @@
+#=0D
+# Copyright (c) 2021 Semihalf=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+=0D
+# Per-board additional content of the DXE phase firmware volume=0D
+=0D
+ INF Silicon/Marvell/Drivers/Gpio/MvGpioDxe/MvGpioDxe.inf=0D
+=0D
+ # DTB=0D
+ INF RuleOverride =3D DTB Silicon/Marvell/OcteonTx/DeviceTree/T91/$(PLATF=
ORM_NAME).inf=0D
+=0D
+ # ACPI support=0D
+!if $(ARCH) =3D=3D AARCH64=0D
+ INF RuleOverride =3D ACPITABLE Silicon/Marvell/OcteonTx/AcpiTables/T91/$=
(PLATFORM_NAME).inf=0D
+!endif=0D
--=20
2.29.0


[edk2-platforms PATCH 2/3] SolidRun/Cn913xCEx7Eval: Add ACPI support

Marcin Wojtas
 

This patch adds ACPI tables description for the SolidRun
CN913x CEx7 Evaluation Board platform.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf =
| 61 +++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h =
| 9 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h =
| 114 +++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl =
| 383 +++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl =
| 493 +++++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl =
| 515 ++++++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl =
| 120 +++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc =
| 74 +++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc =
| 87 ++++
9 files changed, 1856 insertions(+)
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.=
inf
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/=
Dbg2.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/=
Pcie.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/=
Cn9130EvalSsdt.asl
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/=
Cn9131EvalSsdt.asl
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/=
Cn9132EvalSsdt.asl
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/=
Cn913xCEx7Dsdt.asl
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/=
Dbg2.aslc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/=
Mcfg.aslc

diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf b/S=
ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf
new file mode 100644
index 0000000000..27e7294014
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf
@@ -0,0 +1,61 @@
+## @file=0D
+# Component description file for PlatformAcpiTables module.=0D
+#=0D
+# ACPI table data and ASL sources required to boot the platform.=0D
+#=0D
+# Copyright (c) 2018, Linaro, Ltd. All rights reserved.<BR>=0D
+# Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>=
=0D
+# Copyright (c) 2021, Semihalf.<BR>=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+#=0D
+##=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x0001001B=0D
+ BASE_NAME =3D PlatformAcpiTables=0D
+ FILE_GUID =3D 7E374E25-8E01-4FEE-87F2-390C23C606CD=
=0D
+ MODULE_TYPE =3D USER_DEFINED=0D
+ VERSION_STRING =3D 1.0=0D
+=0D
+[Sources]=0D
+ Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl=0D
+ Cn913xCEx7Eval/Cn9130EvalSsdt.asl=0D
+ Cn913xCEx7Eval/Cn9131EvalSsdt.asl=0D
+ Cn913xCEx7Eval/Cn9132EvalSsdt.asl=0D
+ Cn913xCEx7Eval/Dbg2.aslc=0D
+ Cn913xCEx7Eval/Mcfg.aslc=0D
+ Fadt.aslc=0D
+ Gtdt.aslc=0D
+ Madt.aslc=0D
+ Pptt.aslc=0D
+ Spcr.aslc=0D
+=0D
+[Packages]=0D
+ ArmPkg/ArmPkg.dec=0D
+ ArmPlatformPkg/ArmPlatformPkg.dec=0D
+ EmbeddedPkg/EmbeddedPkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ Silicon/Marvell/Marvell.dec=0D
+=0D
+[FixedPcd]=0D
+ gArmPlatformTokenSpaceGuid.PcdCoreCount=0D
+=0D
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum=0D
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum=0D
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum=0D
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum=0D
+=0D
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase=0D
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum=0D
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase=0D
+=0D
+ gArmTokenSpaceGuid.PcdGicDistributorBase=0D
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase=0D
+=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate=0D
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase=0D
+=0D
+[BuildOptions]=0D
+ *_*_*_ASLCC_FLAGS =3D -DCN9131=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h =
b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h
new file mode 100644
index 0000000000..a18b7c1396
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h
@@ -0,0 +1,9 @@
+/**=0D
+=0D
+ Copyright (C) 2021, Semihalf.=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#define CN913X_DBG2_UART_REG_BASE 0xF2702200=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h =
b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h
new file mode 100644
index 0000000000..592e47d0c4
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h
@@ -0,0 +1,114 @@
+/**=0D
+=0D
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.=0D
+ Copyright (C) 2021, Semihalf.=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#define CP0_PCI0_BUS_MIN 0x0=0D
+#define CP0_PCI0_BUS_MAX 0x0=0D
+#define CP0_PCI0_BUS_COUNT 0x1=0D
+#define CP0_PCI0_MMIO32_BASE 0xC0000000=0D
+#define CP0_PCI0_MMIO32_SIZE 0x20000000=0D
+#define CP0_PCI0_MMIO32_MAX 0xDFFFFFFF=0D
+#define CP0_PCI0_MMIO64_BASE 0x810000000=0D
+#define CP0_PCI0_MMIO64_SIZE 0x80000000=0D
+#define CP0_PCI0_MMIO64_MAX 0x88FFFFFFF=0D
+#define CP0_PCI0_IO_BASE 0x0=0D
+#define CP0_PCI0_IO_SIZE 0x10000=0D
+#define CP0_PCI0_IO_TRANSLATION 0x80FF00000=0D
+#define CP0_PCI0_ECAM_BASE 0x800008000=0D
+#define CP0_PCI0_ECAM_SIZE 0x100000=0D
+#define CP0_PCI0_ECAM_MAX 0x800107FFF=0D
+=0D
+#define CP1_PCI0_BUS_MIN 0x0=0D
+#define CP1_PCI0_BUS_MAX 0x0=0D
+#define CP1_PCI0_BUS_COUNT 0x1=0D
+#define CP1_PCI0_MMIO32_BASE 0xE3000000=0D
+#define CP1_PCI0_MMIO32_SIZE 0x1000000=0D
+#define CP1_PCI0_MMIO32_MAX 0xE3FFFFFF=0D
+#define CP1_PCI0_MMIO64_BASE 0x890000000=0D
+#define CP1_PCI0_MMIO64_SIZE 0x10000000=0D
+#define CP1_PCI0_MMIO64_MAX 0x89FFFFFFF=0D
+#define CP1_PCI0_IO_BASE 0x0=0D
+#define CP1_PCI0_IO_SIZE 0x10000=0D
+#define CP1_PCI0_IO_TRANSLATION 0xE2F00000=0D
+#define CP1_PCI0_ECAM_BASE 0xE2008000=0D
+#define CP1_PCI0_ECAM_SIZE 0x100000=0D
+=0D
+#define CP1_PCI1_BUS_MIN 0x0=0D
+#define CP1_PCI1_BUS_MAX 0x0=0D
+#define CP1_PCI1_BUS_COUNT 0x1=0D
+#define CP1_PCI1_MMIO32_BASE 0xE5000000=0D
+#define CP1_PCI1_MMIO32_SIZE 0x1000000=0D
+#define CP1_PCI1_MMIO32_MAX 0xE5FFFFFF=0D
+#define CP1_PCI1_MMIO64_BASE 0x8A0000000=0D
+#define CP1_PCI1_MMIO64_SIZE 0x10000000=0D
+#define CP1_PCI1_MMIO64_MAX 0x8AFFFFFFF=0D
+#define CP1_PCI1_IO_BASE 0x0=0D
+#define CP1_PCI1_IO_SIZE 0x10000=0D
+#define CP1_PCI1_IO_TRANSLATION 0xE4F00000=0D
+#define CP1_PCI1_ECAM_BASE 0xE4008000=0D
+#define CP1_PCI1_ECAM_SIZE 0x100000=0D
+=0D
+#define CP1_PCI2_BUS_MIN 0x0=0D
+#define CP1_PCI2_BUS_MAX 0x0=0D
+#define CP1_PCI2_BUS_COUNT 0x1=0D
+#define CP1_PCI2_MMIO32_BASE 0xE7000000=0D
+#define CP1_PCI2_MMIO32_SIZE 0x1000000=0D
+#define CP1_PCI2_MMIO32_MAX 0xE7FFFFFF=0D
+#define CP1_PCI2_MMIO64_BASE 0x8B0000000=0D
+#define CP1_PCI2_MMIO64_SIZE 0x10000000=0D
+#define CP1_PCI2_MMIO64_MAX 0x8BFFFFFFF=0D
+#define CP1_PCI2_IO_BASE 0x0=0D
+#define CP1_PCI2_IO_SIZE 0x10000=0D
+#define CP1_PCI2_IO_TRANSLATION 0xE6F00000=0D
+#define CP1_PCI2_ECAM_BASE 0xE6008000=0D
+#define CP1_PCI2_ECAM_SIZE 0x100000=0D
+=0D
+#define CP2_PCI0_BUS_MIN 0x0=0D
+#define CP2_PCI0_BUS_MAX 0x0=0D
+#define CP2_PCI0_BUS_COUNT 0x1=0D
+#define CP2_PCI0_MMIO32_BASE 0xEA000000=0D
+#define CP2_PCI0_MMIO32_SIZE 0x1000000=0D
+#define CP2_PCI0_MMIO32_MAX 0xEAFFFFFF=0D
+#define CP2_PCI0_MMIO64_BASE 0x8C0000000=0D
+#define CP2_PCI0_MMIO64_SIZE 0x10000000=0D
+#define CP2_PCI0_MMIO64_MAX 0x8CFFFFFFF=0D
+#define CP2_PCI0_IO_BASE 0x0=0D
+#define CP2_PCI0_IO_SIZE 0x10000=0D
+#define CP2_PCI0_IO_TRANSLATION 0xE9F00000=0D
+#define CP2_PCI0_ECAM_BASE 0xE9008000=0D
+#define CP2_PCI0_ECAM_SIZE 0x100000=0D
+=0D
+#define CP2_PCI1_BUS_MIN 0x0=0D
+#define CP2_PCI1_BUS_MAX 0x0=0D
+#define CP2_PCI1_BUS_COUNT 0x1=0D
+#define CP2_PCI1_MMIO32_BASE 0xEC000000=0D
+#define CP2_PCI1_MMIO32_SIZE 0x1000000=0D
+#define CP2_PCI1_MMIO32_MAX 0xECFFFFFF=0D
+#define CP2_PCI1_MMIO64_BASE 0x8D0000000=0D
+#define CP2_PCI1_MMIO64_SIZE 0x10000000=0D
+#define CP2_PCI1_MMIO64_MAX 0x8DFFFFFFF=0D
+#define CP2_PCI1_IO_BASE 0x0=0D
+#define CP2_PCI1_IO_SIZE 0x10000=0D
+#define CP2_PCI1_IO_TRANSLATION 0xEBF00000=0D
+#define CP2_PCI1_ECAM_BASE 0xEB008000=0D
+#define CP2_PCI1_ECAM_SIZE 0x100000=0D
+=0D
+#define CP2_PCI2_BUS_MIN 0x0=0D
+#define CP2_PCI2_BUS_MAX 0x0=0D
+#define CP2_PCI2_BUS_COUNT 0x1=0D
+#define CP2_PCI2_MMIO32_BASE 0xEE000000=0D
+#define CP2_PCI2_MMIO32_SIZE 0x1000000=0D
+#define CP2_PCI2_MMIO32_MAX 0xEEFFFFFF=0D
+#define CP2_PCI2_MMIO64_BASE 0x8E0000000=0D
+#define CP2_PCI2_MMIO64_SIZE 0x10000000=0D
+#define CP2_PCI2_MMIO64_MAX 0x8EFFFFFFF=0D
+#define CP2_PCI2_IO_BASE 0x0=0D
+#define CP2_PCI2_IO_SIZE 0x10000=0D
+#define CP2_PCI2_IO_TRANSLATION 0xEDF00000=0D
+#define CP2_PCI2_ECAM_BASE 0xED008000=0D
+#define CP2_PCI2_ECAM_SIZE 0x100000=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130E=
valSsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130=
EvalSsdt.asl
new file mode 100644
index 0000000000..70bdecb620
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt=
.asl
@@ -0,0 +1,383 @@
+/** @file=0D
+=0D
+ Differentiated System Description Table Fields (DSDT)=0D
+=0D
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>=0D
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR>=0D
+ Copyright (C) 2021, Semihalf.<BR>=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include "Cn913xCEx7Eval/Dbg2.h"=0D
+#include "Cn913xCEx7Eval/Pcie.h"=0D
+#include "IcuInterrupts.h"=0D
+=0D
+DefinitionBlock ("Cn9130CEx7EvalSsdt.aml", "SSDT", 2, "MRVL", "CN913X", 3)=
=0D
+{=0D
+ Scope (_SB)=0D
+ {=0D
+ Device (MMC1)=0D
+ {=0D
+ Name (_HID, "MRVL0004") // _HID: Hardware ID=0D
+ Name (_UID, 0x01) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+=0D
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ 0xF2780000, // Address Base (MMIO)=0D
+ 0x00000300, // Address Length=0D
+ )=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,=
,, )=0D
+ {=0D
+ CP_GIC_SPI_CP0_SDMMC=0D
+ }=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "clock-frequency", 400000000 },=0D
+ Package () { "bus-width", 4 },=0D
+ Package () { "no-1-8-v", 0x1 },=0D
+ Package () { "broken-cd", 0x1 },=0D
+ }=0D
+ })=0D
+ }=0D
+=0D
+ Device (XHC0)=0D
+ {=0D
+ Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
+ Name (_UID, 0x00) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+=0D
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ 0xF2500000, // Address Base (MMIO)=0D
+ 0x00004000, // Address Length=0D
+ )=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,=
,, )=0D
+ {=0D
+ CP_GIC_SPI_CP0_USB_H0=0D
+ }=0D
+ })=0D
+ }=0D
+=0D
+ Device (XHC1)=0D
+ {=0D
+ Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
+ Name (_UID, 0x01) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+=0D
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ 0xF2510000, // Address Base (MMIO)=0D
+ 0x00004000, // Address Length=0D
+ )=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,=
,, )=0D
+ {=0D
+ CP_GIC_SPI_CP0_USB_H1=0D
+ }=0D
+ })=0D
+ }=0D
+=0D
+ Device (COM2)=0D
+ {=0D
+ Name (_HID, "MRVL0001") // _HID: H=
ardware ID=0D
+ Name (_CID, "HISI0031") // _CID: C=
ompatible ID=0D
+ Name (_UID, 0x01) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_ADR, CN913X_DBG2_UART_REG_BASE) // _ADR: A=
ddress=0D
+ Name (_CRS, ResourceTemplate () // _CRS: C=
urrent Resource Settings=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ CN913X_DBG2_UART_REG_BASE, // Address=
Base=0D
+ 0x00000100, // Address=
Length=0D
+ )=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,=
,, )=0D
+ {=0D
+ CP_GIC_SPI_CP0_UART2=0D
+ }=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "clock-frequency", FixedPcdGet32 (PcdSe=
rialClockRate) },=0D
+ Package () { "reg-io-width", 1 },=0D
+ Package () { "reg-shift", 2 },=0D
+ }=0D
+ })=0D
+ }=0D
+=0D
+ Device (SMI0)=0D
+ {=0D
+ Name (_HID, "MRVL0100") // _HID: H=
ardware ID=0D
+ Name (_UID, 0x00) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ 0xf212a200, // Address=
Base=0D
+ 0x00000010, // Address=
Length=0D
+ )=0D
+ })=0D
+ Device (PHY0)=0D
+ {=0D
+ Name (_ADR, 0x0)=0D
+ }=0D
+ }=0D
+=0D
+ Device (PP20)=0D
+ {=0D
+ Name (_HID, "MRVL0110") // _HID: H=
ardware ID=0D
+ Name (_CCA, 0x01) // Cache-c=
oherent controller=0D
+ Name (_UID, 0x00) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D
+ Memory32Fixed (ReadWrite, 0xf2129000 , 0xb000)=0D
+ Memory32Fixed (ReadWrite, 0xf2220000 , 0x800)=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "clock-frequency", 333333333 },=0D
+ }=0D
+ })=0D
+ Device (ETH0)=0D
+ {=0D
+ Name (_ADR, 0x0)=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv=
e, ,, )=0D
+ {=0D
+ CP_GIC_SPI_PP2_CP0_PORT0=0D
+ }=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "port-id", 0 },=0D
+ Package () { "gop-port-id", 0 },=0D
+ Package () { "phy-mode", "10gbase-kr"},=0D
+ Package () { "managed", "in-band-status"},=0D
+ }=0D
+ })=0D
+ }=0D
+ Device (ETH1)=0D
+ {=0D
+ Name (_ADR, 0x0)=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv=
e, ,, )=0D
+ {=0D
+ CP_GIC_SPI_PP2_CP0_PORT1=0D
+ }=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "port-id", 1 },=0D
+ Package () { "gop-port-id", 2 },=0D
+ Package () { "phy-mode", "rgmii-id"},=0D
+ Package () { "phy-handle", \_SB.SMI0.PHY0},=0D
+ }=0D
+ })=0D
+ }=0D
+ Device (ETH2)=0D
+ {=0D
+ Name (_ADR, 0x0)=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv=
e, ,, )=0D
+ {=0D
+ CP_GIC_SPI_PP2_CP0_PORT2=0D
+ }=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "port-id", 2 },=0D
+ Package () { "gop-port-id", 3 },=0D
+ Package () { "phy-mode", "2500base-x"},=0D
+ },=0D
+ ToUUID("dbb8e3e6-5886-4ba6-8795-1319f52a966b"),=0D
+ Package () {=0D
+ Package () {"fixed-link", "LNK0"}=0D
+ }=0D
+ })=0D
+ Name (LNK0, Package(){ // Data-only subnode of port=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () {"speed", 2500},=0D
+ Package () {"full-duplex", 1}=0D
+ }=0D
+ })=0D
+ }=0D
+ }=0D
+=0D
+ Device (RNG0)=0D
+ {=0D
+ Name (_HID, "PRP0001") // _HID=
: Hardware ID=0D
+ Name (_UID, 0x00) // _UID=
: Unique ID=0D
+ Method (_STA) // _STA=
: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)=0D
+ {=0D
+ CP_GIC_SPI_CP0_EIP_RNG0=0D
+ }=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "compatible", "inside-secure,safexcel-eip=
76" },=0D
+ }=0D
+ })=0D
+ }=0D
+=0D
+ //=0D
+ // PCIe Root Bus=0D
+ //=0D
+ Device (PCI0)=0D
+ {=0D
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar=
e ID=0D
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID=0D
+ Name (_SEG, 0x00) // _SEG: PCI Segment=0D
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D
+ Name (_UID, 0x00) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_PRT, Package () // _PRT: PCI Routing Table=0D
+ {=0D
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }=0D
+ })=0D
+=0D
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin=
gs=0D
+ {=0D
+ Name (RBUF, ResourceTemplate ()=0D
+ {=0D
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P=
osDecode,=0D
+ 0x0000, // Granularity=
=0D
+ CP0_PCI0_BUS_MIN, // Range Minim=
um=0D
+ CP0_PCI0_BUS_MAX, // Range Maxim=
um=0D
+ 0x0000, // Translation=
Offset=0D
+ CP0_PCI0_BUS_COUNT // Length=0D
+ )=0D
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma=
xFixed, NonCacheable, ReadWrite,=0D
+ 0x00000000, // Granularity=
=0D
+ CP0_PCI0_MMIO32_BASE, // Range Minim=
um=0D
+ CP0_PCI0_MMIO32_MAX, // Range Maxim=
um=0D
+ 0x00000000, // Translation=
Offset=0D
+ CP0_PCI0_MMIO32_SIZE // Length=0D
+ )=0D
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma=
xFixed, NonCacheable, ReadWrite,=0D
+ 0x0000000000000000, // Granularity=
=0D
+ CP0_PCI0_MMIO64_BASE, // Range Minim=
um=0D
+ CP0_PCI0_MMIO64_MAX, // Range Maxim=
um=0D
+ 0x00000000, // Translation=
Offset=0D
+ CP0_PCI0_MMIO64_SIZE // Length=0D
+ )=0D
+ QWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco=
de, EntireRange,=0D
+ 0x00000000, // Granularity=
=0D
+ CP0_PCI0_IO_BASE, // Range Minim=
um=0D
+ 0x0000FFFF, // Range Maxim=
um=0D
+ CP0_PCI0_IO_TRANSLATION, // Translation=
Address=0D
+ CP0_PCI0_IO_SIZE, // Length=0D
+ ,=0D
+ ,=0D
+ ,=0D
+ TypeTranslation=0D
+ )=0D
+ })=0D
+ Return (RBUF) /* \_SB_.PCI0._CRS.RBUF */=0D
+ } // Method(_CRS)=0D
+=0D
+ Device (RES0)=0D
+ {=0D
+ Name (_HID, "PNP0C02")=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma=
xFixed, NonCacheable, ReadWrite,=0D
+ 0x0000000000000000, // Granularity=
=0D
+ CP0_PCI0_ECAM_BASE, // Range Minim=
um=0D
+ CP0_PCI0_ECAM_MAX, // Range Maxim=
um=0D
+ 0x00000000, // Translation=
Offset=0D
+ CP0_PCI0_ECAM_SIZE // Length=0D
+ )=0D
+ })=0D
+ }=0D
+ Name (SUPP, 0x00)=0D
+ Name (CTRL, 0x00)=0D
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap=
abilities=0D
+ {=0D
+ CreateDWordField (Arg3, 0x00, CDW1)=0D
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03=
dd766") /* PCI Host Bridge Device */))=0D
+ {=0D
+ CreateDWordField (Arg3, 0x04, CDW2)=0D
+ CreateDWordField (Arg3, 0x08, CDW3)=0D
+ Store (CDW2, SUPP) /* \_SB_.PCI0.SUPP */=0D
+ Store (CDW3, CTRL) /* \_SB_.PCI0.CTRL */=0D
+ If (LNotEqual (And (SUPP, 0x16), 0x16))=0D
+ {=0D
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI0.CTRL */=0D
+ }=0D
+=0D
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI0.CTRL */=0D
+ If (LNotEqual (Arg1, One))=0D
+ {=0D
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI0._OSC.CDW1 */=0D
+ }=0D
+=0D
+ If (LNotEqual (CDW3, CTRL))=0D
+ {=0D
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI0._OSC.CDW1 */=0D
+ }=0D
+=0D
+ Store (CTRL, CDW3) /* \_SB_.PCI0._OSC.CDW3 */=0D
+ Return (Arg3)=0D
+ }=0D
+ Else=0D
+ {=0D
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI0._OSC.CDW1 */=0D
+ Return (Arg3)=0D
+ }=0D
+ } // Method(_OSC)=0D
+ }=0D
+ }=0D
+}=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131E=
valSsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131=
EvalSsdt.asl
new file mode 100644
index 0000000000..930134b86f
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt=
.asl
@@ -0,0 +1,493 @@
+/** @file=0D
+=0D
+ Secondary System Description Table Fields (SSDT)=0D
+=0D
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>=0D
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>=0D
+ Copyright (C) 2021, Semihalf.<BR>=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include "Cn913xCEx7Eval/Pcie.h"=0D
+#include "IcuInterrupts.h"=0D
+=0D
+DefinitionBlock ("Cn9131CEx7EvalSsdt.aml", "SSDT", 2, "MRVL", "CN913X", 3)=
=0D
+{=0D
+ Scope (_SB)=0D
+ {=0D
+ Device (AHC0)=0D
+ {=0D
+ Name (_HID, "LNRO001E") // _HID: Hardware ID=0D
+ Name (_UID, 0x00) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_CLS, Package (0x03) // _CLS: Class Code=0D
+ {=0D
+ 0x01,=0D
+ 0x06,=0D
+ 0x01=0D
+ })=0D
+=0D
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ 0xF4540000, // Address Base (MMIO)=0D
+ 0x00030000, // Address Length=0D
+ )=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,=
,, )=0D
+ {=0D
+ CP_GIC_SPI_CP1_SATA_H0=0D
+ }=0D
+ })=0D
+ }=0D
+=0D
+ Device (XHC2)=0D
+ {=0D
+ Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
+ Name (_UID, 0x02) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+=0D
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ 0xF4510000, // Address Base (MMIO)=0D
+ 0x00004000, // Address Length=0D
+ )=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,=
,, )=0D
+ {=0D
+ CP_GIC_SPI_CP1_USB_H1=0D
+ }=0D
+ })=0D
+ }=0D
+=0D
+ Device (XSM1)=0D
+ {=0D
+ Name (_HID, "MRVL0101") // _HID: H=
ardware ID=0D
+ Name (_UID, 0x00) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ 0xf412a600, // Address=
Base=0D
+ 0x00000010, // Address=
Length=0D
+ )=0D
+ })=0D
+ Device (PHY0)=0D
+ {=0D
+ Name (_ADR, 0x0)=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "compatible", "ethernet-phy-ieee802.3=
-c45" },=0D
+ }=0D
+ })=0D
+ }=0D
+ }=0D
+=0D
+ Device (PP21)=0D
+ {=0D
+ Name (_HID, "MRVL0110") // _HID: H=
ardware ID=0D
+ Name (_CCA, 0x01) // Cache-c=
oherent controller=0D
+ Name (_UID, 0x01) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)=0D
+ Memory32Fixed (ReadWrite, 0xf4129000 , 0xb000)=0D
+ Memory32Fixed (ReadWrite, 0xf4220000 , 0x800)=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "clock-frequency", 333333333 },=0D
+ }=0D
+ })=0D
+ Device (ETH0)=0D
+ {=0D
+ Name (_ADR, 0x0)=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv=
e, ,, )=0D
+ {=0D
+ CP_GIC_SPI_PP2_CP1_PORT0=0D
+ }=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "port-id", 0 },=0D
+ Package () { "gop-port-id", 0 },=0D
+ Package () { "phy-mode", "5gbase-r"},=0D
+ Package () { "phy-handle", \_SB.XSM1.PHY0},=0D
+ }=0D
+ })=0D
+ }=0D
+ }=0D
+=0D
+ Device (RNG1)=0D
+ {=0D
+ Name (_HID, "PRP0001") // _HID=
: Hardware ID=0D
+ Name (_UID, 0x01) // _UID=
: Unique ID=0D
+ Method (_STA) // _STA=
: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)=0D
+ {=0D
+ CP_GIC_SPI_CP1_EIP_RNG0=0D
+ }=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "compatible", "inside-secure,safexcel-eip=
76" },=0D
+ }=0D
+ })=0D
+ }=0D
+=0D
+ Device (PCI1)=0D
+ {=0D
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar=
e ID=0D
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID=0D
+ Name (_SEG, 0x01) // _SEG: PCI Segment=0D
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D
+ Name (_UID, 0x01) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_PRT, Package () // _PRT: PCI Routing Table=0D
+ {=0D
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }=0D
+ })=0D
+=0D
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin=
gs=0D
+ {=0D
+ Name (RBUF, ResourceTemplate ()=0D
+ {=0D
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P=
osDecode,=0D
+ 0x0000, // Granularity=
=0D
+ CP1_PCI0_BUS_MIN, // Range Minim=
um=0D
+ CP1_PCI0_BUS_MAX, // Range Maxim=
um=0D
+ 0x0000, // Translation=
Offset=0D
+ CP1_PCI0_BUS_COUNT // Length=0D
+ )=0D
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma=
xFixed, NonCacheable, ReadWrite,=0D
+ 0x00000000, // Granularity=
=0D
+ CP1_PCI0_MMIO32_BASE, // Range Minim=
um=0D
+ CP1_PCI0_MMIO32_MAX, // Range Maxim=
um=0D
+ 0x00000000, // Translation=
Offset=0D
+ CP1_PCI0_MMIO32_SIZE // Length=0D
+ )=0D
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma=
xFixed, NonCacheable, ReadWrite,=0D
+ 0x0000000000000000, // Granularity=
=0D
+ CP1_PCI0_MMIO64_BASE, // Range Minim=
um=0D
+ CP1_PCI0_MMIO64_MAX, // Range Maxim=
um=0D
+ 0x00000000, // Translation=
Offset=0D
+ CP1_PCI0_MMIO64_SIZE // Length=0D
+ )=0D
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco=
de, EntireRange,=0D
+ 0x00000000, // Granularity=
=0D
+ CP1_PCI0_IO_BASE, // Range Minim=
um=0D
+ 0x0000FFFF, // Range Maxim=
um=0D
+ CP1_PCI0_IO_TRANSLATION, // Translation=
Address=0D
+ CP1_PCI0_IO_SIZE, // Length=0D
+ ,=0D
+ ,=0D
+ ,=0D
+ TypeTranslation=0D
+ )=0D
+ })=0D
+ Return (RBUF) /* \_SB_.PCI1._CRS.RBUF */=0D
+ } // Method(_CRS)=0D
+=0D
+ Device (RES0)=0D
+ {=0D
+ Name (_HID, "PNP0C02")=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ CP1_PCI0_ECAM_BASE, // Range Minim=
um=0D
+ CP1_PCI0_ECAM_SIZE // Length=0D
+ )=0D
+ })=0D
+ }=0D
+ Name (SUPP, 0x00)=0D
+ Name (CTRL, 0x00)=0D
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap=
abilities=0D
+ {=0D
+ CreateDWordField (Arg3, 0x00, CDW1)=0D
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03=
dd766") /* PCI Host Bridge Device */))=0D
+ {=0D
+ CreateDWordField (Arg3, 0x04, CDW2)=0D
+ CreateDWordField (Arg3, 0x08, CDW3)=0D
+ Store (CDW2, SUPP) /* \_SB_.PCI1.SUPP */=0D
+ Store (CDW3, CTRL) /* \_SB_.PCI1.CTRL */=0D
+ If (LNotEqual (And (SUPP, 0x16), 0x16))=0D
+ {=0D
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI1.CTRL */=0D
+ }=0D
+=0D
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI1.CTRL */=0D
+ If (LNotEqual (Arg1, One))=0D
+ {=0D
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI1._OSC.CDW1 */=0D
+ }=0D
+=0D
+ If (LNotEqual (CDW3, CTRL))=0D
+ {=0D
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI1._OSC.CDW1 */=0D
+ }=0D
+=0D
+ Store (CTRL, CDW3) /* \_SB_.PCI1._OSC.CDW3 */=0D
+ Return (Arg3)=0D
+ }=0D
+ Else=0D
+ {=0D
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI1._OSC.CDW1 */=0D
+ Return (Arg3)=0D
+ }=0D
+ } // Method(_OSC)=0D
+ }=0D
+=0D
+ Device (PCI2)=0D
+ {=0D
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar=
e ID=0D
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID=0D
+ Name (_SEG, 0x02) // _SEG: PCI Segment=0D
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D
+ Name (_UID, 0x02) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_PRT, Package () // _PRT: PCI Routing Table=0D
+ {=0D
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }=0D
+ })=0D
+=0D
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin=
gs=0D
+ {=0D
+ Name (RBUF, ResourceTemplate ()=0D
+ {=0D
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P=
osDecode,=0D
+ 0x0000, // Granularity=
=0D
+ CP1_PCI1_BUS_MIN, // Range Minim=
um=0D
+ CP1_PCI1_BUS_MAX, // Range Maxim=
um=0D
+ 0x0000, // Translation=
Offset=0D
+ CP1_PCI1_BUS_COUNT // Length=0D
+ )=0D
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma=
xFixed, NonCacheable, ReadWrite,=0D
+ 0x00000000, // Granularity=
=0D
+ CP1_PCI1_MMIO32_BASE, // Range Minim=
um=0D
+ CP1_PCI1_MMIO32_MAX, // Range Maxim=
um=0D
+ 0x00000000, // Translation=
Offset=0D
+ CP1_PCI1_MMIO32_SIZE // Length=0D
+ )=0D
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma=
xFixed, NonCacheable, ReadWrite,=0D
+ 0x0000000000000000, // Granularity=
=0D
+ CP1_PCI1_MMIO64_BASE, // Range Minim=
um=0D
+ CP1_PCI1_MMIO64_MAX, // Range Maxim=
um=0D
+ 0x00000000, // Translation=
Offset=0D
+ CP1_PCI1_MMIO64_SIZE // Length=0D
+ )=0D
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco=
de, EntireRange,=0D
+ 0x00000000, // Granularity=
=0D
+ CP1_PCI1_IO_BASE, // Range Minim=
um=0D
+ 0x0000FFFF, // Range Maxim=
um=0D
+ CP1_PCI1_IO_TRANSLATION, // Translation=
Address=0D
+ CP1_PCI1_IO_SIZE, // Length=0D
+ ,=0D
+ ,=0D
+ ,=0D
+ TypeTranslation=0D
+ )=0D
+ })=0D
+ Return (RBUF) /* \_SB_.PCI2._CRS.RBUF */=0D
+ } // Method(_CRS)=0D
+=0D
+ Device (RES0)=0D
+ {=0D
+ Name (_HID, "PNP0C02")=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ CP1_PCI1_ECAM_BASE, // Range Minim=
um=0D
+ CP1_PCI1_ECAM_SIZE // Length=0D
+ )=0D
+ })=0D
+ }=0D
+ Name (SUPP, 0x00)=0D
+ Name (CTRL, 0x00)=0D
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap=
abilities=0D
+ {=0D
+ CreateDWordField (Arg3, 0x00, CDW1)=0D
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03=
dd766") /* PCI Host Bridge Device */))=0D
+ {=0D
+ CreateDWordField (Arg3, 0x04, CDW2)=0D
+ CreateDWordField (Arg3, 0x08, CDW3)=0D
+ Store (CDW2, SUPP) /* \_SB_.PCI2.SUPP */=0D
+ Store (CDW3, CTRL) /* \_SB_.PCI2.CTRL */=0D
+ If (LNotEqual (And (SUPP, 0x16), 0x16))=0D
+ {=0D
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI2.CTRL */=0D
+ }=0D
+=0D
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI2.CTRL */=0D
+ If (LNotEqual (Arg1, One))=0D
+ {=0D
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI2._OSC.CDW1 */=0D
+ }=0D
+=0D
+ If (LNotEqual (CDW3, CTRL))=0D
+ {=0D
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI2._OSC.CDW1 */=0D
+ }=0D
+=0D
+ Store (CTRL, CDW3) /* \_SB_.PCI2._OSC.CDW3 */=0D
+ Return (Arg3)=0D
+ }=0D
+ Else=0D
+ {=0D
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI2._OSC.CDW1 */=0D
+ Return (Arg3)=0D
+ }=0D
+ } // Method(_OSC)=0D
+ }=0D
+=0D
+ Device (PCI3)=0D
+ {=0D
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar=
e ID=0D
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID=0D
+ Name (_SEG, 0x03) // _SEG: PCI Segment=0D
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D
+ Name (_UID, 0x03) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_PRT, Package () // _PRT: PCI Routing Table=0D
+ {=0D
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }=0D
+ })=0D
+=0D
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin=
gs=0D
+ {=0D
+ Name (RBUF, ResourceTemplate ()=0D
+ {=0D
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P=
osDecode,=0D
+ 0x0000, // Granularity=
=0D
+ CP1_PCI2_BUS_MIN, // Range Minim=
um=0D
+ CP1_PCI2_BUS_MAX, // Range Maxim=
um=0D
+ 0x0000, // Translation=
Offset=0D
+ CP1_PCI2_BUS_COUNT // Length=0D
+ )=0D
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma=
xFixed, NonCacheable, ReadWrite,=0D
+ 0x00000000, // Granularity=
=0D
+ CP1_PCI2_MMIO32_BASE, // Range Minim=
um=0D
+ CP1_PCI2_MMIO32_MAX, // Range Maxim=
um=0D
+ 0x00000000, // Translation=
Offset=0D
+ CP1_PCI2_MMIO32_SIZE // Length=0D
+ )=0D
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma=
xFixed, NonCacheable, ReadWrite,=0D
+ 0x0000000000000000, // Granularity=
=0D
+ CP1_PCI2_MMIO64_BASE, // Range Minim=
um=0D
+ CP1_PCI2_MMIO64_MAX, // Range Maxim=
um=0D
+ 0x00000000, // Translation=
Offset=0D
+ CP1_PCI2_MMIO64_SIZE // Length=0D
+ )=0D
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco=
de, EntireRange,=0D
+ 0x00000000, // Granularity=
=0D
+ CP1_PCI2_IO_BASE, // Range Minim=
um=0D
+ 0x0000FFFF, // Range Maxim=
um=0D
+ CP1_PCI2_IO_TRANSLATION, // Translation=
Address=0D
+ CP1_PCI2_IO_SIZE, // Length=0D
+ ,=0D
+ ,=0D
+ ,=0D
+ TypeTranslation=0D
+ )=0D
+ })=0D
+ Return (RBUF) /* \_SB_.PCI3._CRS.RBUF */=0D
+ } // Method(_CRS)=0D
+=0D
+ Device (RES0)=0D
+ {=0D
+ Name (_HID, "PNP0C02")=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ CP1_PCI2_ECAM_BASE, // Range Minim=
um=0D
+ CP1_PCI2_ECAM_SIZE // Length=0D
+ )=0D
+ })=0D
+ }=0D
+ Name (SUPP, 0x00)=0D
+ Name (CTRL, 0x00)=0D
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap=
abilities=0D
+ {=0D
+ CreateDWordField (Arg3, 0x00, CDW1)=0D
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03=
dd766") /* PCI Host Bridge Device */))=0D
+ {=0D
+ CreateDWordField (Arg3, 0x04, CDW2)=0D
+ CreateDWordField (Arg3, 0x08, CDW3)=0D
+ Store (CDW2, SUPP) /* \_SB_.PCI3.SUPP */=0D
+ Store (CDW3, CTRL) /* \_SB_.PCI3.CTRL */=0D
+ If (LNotEqual (And (SUPP, 0x16), 0x16))=0D
+ {=0D
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI3.CTRL */=0D
+ }=0D
+=0D
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI3.CTRL */=0D
+ If (LNotEqual (Arg1, One))=0D
+ {=0D
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI3._OSC.CDW1 */=0D
+ }=0D
+=0D
+ If (LNotEqual (CDW3, CTRL))=0D
+ {=0D
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI3._OSC.CDW1 */=0D
+ }=0D
+=0D
+ Store (CTRL, CDW3) /* \_SB_.PCI3._OSC.CDW3 */=0D
+ Return (Arg3)=0D
+ }=0D
+ Else=0D
+ {=0D
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI3._OSC.CDW1 */=0D
+ Return (Arg3)=0D
+ }=0D
+ } // Method(_OSC)=0D
+ }=0D
+ }=0D
+}=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132E=
valSsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132=
EvalSsdt.asl
new file mode 100644
index 0000000000..64341095b1
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt=
.asl
@@ -0,0 +1,515 @@
+/** @file=0D
+=0D
+ Secondary System Description Table Fields (SSDT)=0D
+=0D
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>=0D
+ Copyright (c) 2019, Marvell International Ltd. and its affiliates.<BR>=0D
+ Copyright (C) 2021, Semihalf.<BR>=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include "Cn913xCEx7Eval/Pcie.h"=0D
+#include "IcuInterrupts.h"=0D
+=0D
+DefinitionBlock ("Cn9132CEx7EvalSsdt.aml", "SSDT", 2, "MRVL", "CN913X", 3)=
=0D
+{=0D
+ Scope (_SB)=0D
+ {=0D
+ Device (AHC1)=0D
+ {=0D
+ Name (_HID, "LNRO001E") // _HID: Hardware ID=0D
+ Name (_UID, 0x01) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_CLS, Package (0x03) // _CLS: Class Code=0D
+ {=0D
+ 0x01,=0D
+ 0x06,=0D
+ 0x01=0D
+ })=0D
+=0D
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ 0xF6540000, // Address Base (MMIO)=0D
+ 0x00030000, // Address Length=0D
+ )=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,=
,, )=0D
+ {=0D
+ CP_GIC_SPI_CP2_SATA_H0=0D
+ }=0D
+ })=0D
+ }=0D
+=0D
+ Device (XHC3)=0D
+ {=0D
+ Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
+ Name (_UID, 0x03) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+=0D
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ 0xF6500000, // Address Base (MMIO)=0D
+ 0x00004000, // Address Length=0D
+ )=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,=
,, )=0D
+ {=0D
+ CP_GIC_SPI_CP2_USB_H0=0D
+ }=0D
+ })=0D
+ }=0D
+ Device (XHC4)=0D
+ {=0D
+ Name (_HID, "PNP0D10") // _HID: Hardware ID=0D
+ Name (_UID, 0x04) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+=0D
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ 0xF6510000, // Address Base (MMIO)=0D
+ 0x00004000, // Address Length=0D
+ )=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,=
,, )=0D
+ {=0D
+ CP_GIC_SPI_CP2_USB_H1=0D
+ }=0D
+ })=0D
+ }=0D
+=0D
+ Device (XSM2)=0D
+ {=0D
+ Name (_HID, "MRVL0101") // _HID: H=
ardware ID=0D
+ Name (_UID, 0x01) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ 0xf412a600, // Address=
Base=0D
+ 0x00000010, // Address=
Length=0D
+ )=0D
+ })=0D
+ Device (PHY0)=0D
+ {=0D
+ Name (_ADR, 0x0)=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "compatible", "ethernet-phy-ieee802.3=
-c45" },=0D
+ }=0D
+ })=0D
+ }=0D
+ }=0D
+=0D
+ Device (PP22)=0D
+ {=0D
+ Name (_HID, "MRVL0110") // _HID: H=
ardware ID=0D
+ Name (_CCA, 0x01) // Cache-c=
oherent controller=0D
+ Name (_UID, 0x02) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Memory32Fixed (ReadWrite, 0xf6000000 , 0x100000)=0D
+ Memory32Fixed (ReadWrite, 0xf6129000 , 0xb000)=0D
+ Memory32Fixed (ReadWrite, 0xf6220000 , 0x800)=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "clock-frequency", 333333333 },=0D
+ }=0D
+ })=0D
+ Device (ETH0)=0D
+ {=0D
+ Name (_ADR, 0x0)=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusiv=
e, ,, )=0D
+ {=0D
+ CP_GIC_SPI_PP2_CP2_PORT0=0D
+ }=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "port-id", 0 },=0D
+ Package () { "gop-port-id", 0 },=0D
+ Package () { "phy-mode", "5gbase-r"},=0D
+ Package () { "phy-handle", \_SB.XSM2.PHY0},=0D
+ }=0D
+ })=0D
+ }=0D
+ }=0D
+=0D
+ Device (RNG2)=0D
+ {=0D
+ Name (_HID, "PRP0001") // _HID=
: Hardware ID=0D
+ Name (_UID, 0x02) // _UID=
: Unique ID=0D
+ Method (_STA) // _STA=
: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Memory32Fixed (ReadWrite, 0xF6760000, 0x7D)=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Shared)=0D
+ {=0D
+ CP_GIC_SPI_CP2_EIP_RNG0=0D
+ }=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "compatible", "inside-secure,safexcel-eip=
76" },=0D
+ }=0D
+ })=0D
+ }=0D
+=0D
+ Device (PCI4)=0D
+ {=0D
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar=
e ID=0D
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID=0D
+ Name (_SEG, 0x04) // _SEG: PCI Segment=0D
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D
+ Name (_UID, 0x04) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_PRT, Package () // _PRT: PCI Routing Table=0D
+ {=0D
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }=0D
+ })=0D
+=0D
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin=
gs=0D
+ {=0D
+ Name (RBUF, ResourceTemplate ()=0D
+ {=0D
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P=
osDecode,=0D
+ 0x0000, // Granularity=
=0D
+ CP2_PCI0_BUS_MIN, // Range Minim=
um=0D
+ CP2_PCI0_BUS_MAX, // Range Maxim=
um=0D
+ 0x0000, // Translation=
Offset=0D
+ CP2_PCI0_BUS_COUNT // Length=0D
+ )=0D
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma=
xFixed, NonCacheable, ReadWrite,=0D
+ 0x00000000, // Granularity=
=0D
+ CP2_PCI0_MMIO32_BASE, // Range Minim=
um=0D
+ CP2_PCI0_MMIO32_MAX, // Range Maxim=
um=0D
+ 0x00000000, // Translation=
Offset=0D
+ CP2_PCI0_MMIO32_SIZE // Length=0D
+ )=0D
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma=
xFixed, NonCacheable, ReadWrite,=0D
+ 0x0000000000000000, // Granularity=
=0D
+ CP2_PCI0_MMIO64_BASE, // Range Minim=
um=0D
+ CP2_PCI0_MMIO64_MAX, // Range Maxim=
um=0D
+ 0x00000000, // Translation=
Offset=0D
+ CP2_PCI0_MMIO64_SIZE // Length=0D
+ )=0D
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco=
de, EntireRange,=0D
+ 0x00000000, // Granularity=
=0D
+ CP2_PCI0_IO_BASE, // Range Minim=
um=0D
+ 0x0000FFFF, // Range Maxim=
um=0D
+ CP2_PCI0_IO_TRANSLATION, // Translation=
Address=0D
+ CP2_PCI0_IO_SIZE, // Length=0D
+ ,=0D
+ ,=0D
+ ,=0D
+ TypeTranslation=0D
+ )=0D
+ })=0D
+ Return (RBUF) /* \_SB_.PCI4._CRS.RBUF */=0D
+ } // Method(_CRS)=0D
+=0D
+ Device (RES0)=0D
+ {=0D
+ Name (_HID, "PNP0C02")=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ CP2_PCI0_ECAM_BASE, // Range Minim=
um=0D
+ CP2_PCI0_ECAM_SIZE // Length=0D
+ )=0D
+ })=0D
+ }=0D
+ Name (SUPP, 0x00)=0D
+ Name (CTRL, 0x00)=0D
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap=
abilities=0D
+ {=0D
+ CreateDWordField (Arg3, 0x00, CDW1)=0D
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03=
dd766") /* PCI Host Bridge Device */))=0D
+ {=0D
+ CreateDWordField (Arg3, 0x04, CDW2)=0D
+ CreateDWordField (Arg3, 0x08, CDW3)=0D
+ Store (CDW2, SUPP) /* \_SB_.PCI4.SUPP */=0D
+ Store (CDW3, CTRL) /* \_SB_.PCI4.CTRL */=0D
+ If (LNotEqual (And (SUPP, 0x16), 0x16))=0D
+ {=0D
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI4.CTRL */=0D
+ }=0D
+=0D
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI4.CTRL */=0D
+ If (LNotEqual (Arg1, One))=0D
+ {=0D
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI4._OSC.CDW1 */=0D
+ }=0D
+=0D
+ If (LNotEqual (CDW3, CTRL))=0D
+ {=0D
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI4._OSC.CDW1 */=0D
+ }=0D
+=0D
+ Store (CTRL, CDW3) /* \_SB_.PCI4._OSC.CDW3 */=0D
+ Return (Arg3)=0D
+ }=0D
+ Else=0D
+ {=0D
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI4._OSC.CDW1 */=0D
+ Return (Arg3)=0D
+ }=0D
+ } // Method(_OSC)=0D
+ }=0D
+=0D
+ Device (PCI5)=0D
+ {=0D
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar=
e ID=0D
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID=0D
+ Name (_SEG, 0x05) // _SEG: PCI Segment=0D
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D
+ Name (_UID, 0x05) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_PRT, Package () // _PRT: PCI Routing Table=0D
+ {=0D
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }=0D
+ })=0D
+=0D
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin=
gs=0D
+ {=0D
+ Name (RBUF, ResourceTemplate ()=0D
+ {=0D
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P=
osDecode,=0D
+ 0x0000, // Granularity=
=0D
+ CP2_PCI1_BUS_MIN, // Range Minim=
um=0D
+ CP2_PCI1_BUS_MAX, // Range Maxim=
um=0D
+ 0x0000, // Translation=
Offset=0D
+ CP2_PCI1_BUS_COUNT // Length=0D
+ )=0D
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma=
xFixed, NonCacheable, ReadWrite,=0D
+ 0x00000000, // Granularity=
=0D
+ CP2_PCI1_MMIO32_BASE, // Range Minim=
um=0D
+ CP2_PCI1_MMIO32_MAX, // Range Maxim=
um=0D
+ 0x00000000, // Translation=
Offset=0D
+ CP2_PCI1_MMIO32_SIZE // Length=0D
+ )=0D
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma=
xFixed, NonCacheable, ReadWrite,=0D
+ 0x0000000000000000, // Granularity=
=0D
+ CP2_PCI1_MMIO64_BASE, // Range Minim=
um=0D
+ CP2_PCI1_MMIO64_MAX, // Range Maxim=
um=0D
+ 0x00000000, // Translation=
Offset=0D
+ CP2_PCI1_MMIO64_SIZE // Length=0D
+ )=0D
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco=
de, EntireRange,=0D
+ 0x00000000, // Granularity=
=0D
+ CP2_PCI1_IO_BASE, // Range Minim=
um=0D
+ 0x0000FFFF, // Range Maxim=
um=0D
+ CP2_PCI1_IO_TRANSLATION, // Translation=
Address=0D
+ CP2_PCI1_IO_SIZE, // Length=0D
+ ,=0D
+ ,=0D
+ ,=0D
+ TypeTranslation=0D
+ )=0D
+ })=0D
+ Return (RBUF) /* \_SB_.PCI5._CRS.RBUF */=0D
+ } // Method(_CRS)=0D
+=0D
+ Device (RES0)=0D
+ {=0D
+ Name (_HID, "PNP0C02")=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ CP2_PCI1_ECAM_BASE, // Range Minim=
um=0D
+ CP2_PCI1_ECAM_SIZE // Length=0D
+ )=0D
+ })=0D
+ }=0D
+ Name (SUPP, 0x00)=0D
+ Name (CTRL, 0x00)=0D
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap=
abilities=0D
+ {=0D
+ CreateDWordField (Arg3, 0x00, CDW1)=0D
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03=
dd766") /* PCI Host Bridge Device */))=0D
+ {=0D
+ CreateDWordField (Arg3, 0x04, CDW2)=0D
+ CreateDWordField (Arg3, 0x08, CDW3)=0D
+ Store (CDW2, SUPP) /* \_SB_.PCI5.SUPP */=0D
+ Store (CDW3, CTRL) /* \_SB_.PCI5.CTRL */=0D
+ If (LNotEqual (And (SUPP, 0x16), 0x16))=0D
+ {=0D
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI5.CTRL */=0D
+ }=0D
+=0D
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI5.CTRL */=0D
+ If (LNotEqual (Arg1, One))=0D
+ {=0D
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI5._OSC.CDW1 */=0D
+ }=0D
+=0D
+ If (LNotEqual (CDW3, CTRL))=0D
+ {=0D
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI5._OSC.CDW1 */=0D
+ }=0D
+=0D
+ Store (CTRL, CDW3) /* \_SB_.PCI5._OSC.CDW3 */=0D
+ Return (Arg3)=0D
+ }=0D
+ Else=0D
+ {=0D
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI5._OSC.CDW1 */=0D
+ Return (Arg3)=0D
+ }=0D
+ } // Method(_OSC)=0D
+ }=0D
+=0D
+ Device (PCI6)=0D
+ {=0D
+ Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar=
e ID=0D
+ Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID=0D
+ Name (_SEG, 0x06) // _SEG: PCI Segment=0D
+ Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D
+ Name (_UID, 0x06) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_PRT, Package () // _PRT: PCI Routing Table=0D
+ {=0D
+ Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x1, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x2, 0x0, 0x40 },=0D
+ Package () { 0xFFFF, 0x3, 0x0, 0x40 }=0D
+ })=0D
+=0D
+ Method (_CRS, 0, Serialized) // _CRS: Current Resource Settin=
gs=0D
+ {=0D
+ Name (RBUF, ResourceTemplate ()=0D
+ {=0D
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P=
osDecode,=0D
+ 0x0000, // Granularity=
=0D
+ CP2_PCI2_BUS_MIN, // Range Minim=
um=0D
+ CP2_PCI2_BUS_MAX, // Range Maxim=
um=0D
+ 0x0000, // Translation=
Offset=0D
+ CP2_PCI2_BUS_COUNT // Length=0D
+ )=0D
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, Ma=
xFixed, NonCacheable, ReadWrite,=0D
+ 0x00000000, // Granularity=
=0D
+ CP2_PCI2_MMIO32_BASE, // Range Minim=
um=0D
+ CP2_PCI2_MMIO32_MAX, // Range Maxim=
um=0D
+ 0x00000000, // Translation=
Offset=0D
+ CP2_PCI2_MMIO32_SIZE // Length=0D
+ )=0D
+ QWordMemory (ResourceProducer, PosDecode, MinFixed, Ma=
xFixed, NonCacheable, ReadWrite,=0D
+ 0x0000000000000000, // Granularity=
=0D
+ CP2_PCI2_MMIO64_BASE, // Range Minim=
um=0D
+ CP2_PCI2_MMIO64_MAX, // Range Maxim=
um=0D
+ 0x00000000, // Translation=
Offset=0D
+ CP2_PCI2_MMIO64_SIZE // Length=0D
+ )=0D
+ DWordIo (ResourceProducer, MinFixed, MaxFixed, PosDeco=
de, EntireRange,=0D
+ 0x00000000, // Granularity=
=0D
+ CP2_PCI2_IO_BASE, // Range Minim=
um=0D
+ 0x0000FFFF, // Range Maxim=
um=0D
+ CP2_PCI2_IO_TRANSLATION, // Translation=
Address=0D
+ CP2_PCI2_IO_SIZE, // Length=0D
+ ,=0D
+ ,=0D
+ ,=0D
+ TypeTranslation=0D
+ )=0D
+ })=0D
+ Return (RBUF) /* \_SB_.PCI6._CRS.RBUF */=0D
+ } // Method(_CRS)=0D
+=0D
+ Device (RES0)=0D
+ {=0D
+ Name (_HID, "PNP0C02")=0D
+ Name (_CRS, ResourceTemplate ()=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ CP2_PCI2_ECAM_BASE, // Range Minim=
um=0D
+ CP2_PCI2_ECAM_SIZE // Length=0D
+ )=0D
+ })=0D
+ }=0D
+ Name (SUPP, 0x00)=0D
+ Name (CTRL, 0x00)=0D
+ Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap=
abilities=0D
+ {=0D
+ CreateDWordField (Arg3, 0x00, CDW1)=0D
+ If (LEqual (Arg0, ToUUID ("33db4d5b-1ff7-401c-9657-7441c03=
dd766") /* PCI Host Bridge Device */))=0D
+ {=0D
+ CreateDWordField (Arg3, 0x04, CDW2)=0D
+ CreateDWordField (Arg3, 0x08, CDW3)=0D
+ Store (CDW2, SUPP) /* \_SB_.PCI6.SUPP */=0D
+ Store (CDW3, CTRL) /* \_SB_.PCI6.CTRL */=0D
+ If (LNotEqual (And (SUPP, 0x16), 0x16))=0D
+ {=0D
+ And (CTRL, 0x1E, CTRL) /* \_SB_.PCI6.CTRL */=0D
+ }=0D
+=0D
+ And (CTRL, 0x1D, CTRL) /* \_SB_.PCI6.CTRL */=0D
+ If (LNotEqual (Arg1, One))=0D
+ {=0D
+ Or (CDW1, 0x08, CDW1) /* \_SB_.PCI6._OSC.CDW1 */=0D
+ }=0D
+=0D
+ If (LNotEqual (CDW3, CTRL))=0D
+ {=0D
+ Or (CDW1, 0x10, CDW1) /* \_SB_.PCI6._OSC.CDW1 */=0D
+ }=0D
+=0D
+ Store (CTRL, CDW3) /* \_SB_.PCI6._OSC.CDW3 */=0D
+ Return (Arg3)=0D
+ }=0D
+ Else=0D
+ {=0D
+ Or (CDW1, 0x04, CDW1) /* \_SB_.PCI6._OSC.CDW1 */=0D
+ Return (Arg3)=0D
+ }=0D
+ } // Method(_OSC)=0D
+ }=0D
+ }=0D
+}=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xC=
Ex7Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913x=
CEx7Dsdt.asl
new file mode 100644
index 0000000000..c54937fc7b
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt=
.asl
@@ -0,0 +1,120 @@
+/** @file=0D
+=0D
+ Differentiated System Description Table Fields (DSDT)=0D
+=0D
+ Copyright (c) 2018, Linaro Ltd. All rights reserved.<BR>=0D
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR>=0D
+ Copyright (C) 2021, Semihalf.<BR>=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+DefinitionBlock ("Cn913xCEx7.aml", "DSDT", 2, "MRVL", "CN9130", 3)=0D
+{=0D
+ Scope (_SB)=0D
+ {=0D
+ Device (CPU0)=0D
+ {=0D
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
+ Name (_UID, 0x000) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ }=0D
+ Device (CPU1)=0D
+ {=0D
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
+ Name (_UID, 0x001) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ }=0D
+ Device (CPU2)=0D
+ {=0D
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
+ Name (_UID, 0x100) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ }=0D
+ Device (CPU3)=0D
+ {=0D
+ Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw=
are ID=0D
+ Name (_UID, 0x101) // _UID: Unique ID=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ }=0D
+=0D
+ Device (MMC0)=0D
+ {=0D
+ Name (_HID, "MRVL0003") // _HID: Hardware ID=0D
+ Name (_UID, 0x00) // _UID: Unique ID=0D
+ Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=
=0D
+ Method (_STA) // _STA: Device status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+=0D
+ Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set=
tings=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ 0xF06E0000, // Address Base (MMIO)=0D
+ 0x00000300, // Address Length=0D
+ )=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,=
,, )=0D
+ {=0D
+ 48=0D
+ }=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "clock-frequency", 400000000 },=0D
+ Package () { "bus-width", 8 },=0D
+ Package () { "no-sd", 0x1 },=0D
+ Package () { "no-sdio", 0x1 },=0D
+ Package () { "mmc-ddr-1_8v", 0x1 },=0D
+ Package () { "mmc-hs400-1_8v", 0x1 },=0D
+ Package () { "non-removable", 0x1 },=0D
+ }=0D
+ })=0D
+ }=0D
+=0D
+ Device (COM1)=0D
+ {=0D
+ Name (_HID, "MRVL0001") // _HID: H=
ardware ID=0D
+ Name (_CID, "HISI0031") // _CID: C=
ompatible ID=0D
+ Name (_UID, 0x00) // _UID: U=
nique ID=0D
+ Method (_STA) // _STA: D=
evice status=0D
+ {=0D
+ Return (0xF)=0D
+ }=0D
+ Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A=
ddress=0D
+ Name (_CRS, ResourceTemplate () // _CRS: C=
urrent Resource Settings=0D
+ {=0D
+ Memory32Fixed (ReadWrite,=0D
+ FixedPcdGet64(PcdSerialRegisterBase), // Address=
Base=0D
+ 0x00000100, // Address=
Length=0D
+ )=0D
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive,=
,, )=0D
+ {=0D
+ 51=0D
+ }=0D
+ })=0D
+ Name (_DSD, Package () {=0D
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),=0D
+ Package () {=0D
+ Package () { "clock-frequency", FixedPcdGet32 (PcdSe=
rialClockRate) },=0D
+ Package () { "reg-io-width", 1 },=0D
+ Package () { "reg-shift", 2 },=0D
+ }=0D
+ })=0D
+ }=0D
+ }=0D
+}=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.as=
lc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc
new file mode 100644
index 0000000000..143da73f5c
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc
@@ -0,0 +1,74 @@
+/** @file=0D
+* Debug Port Table (DBG2)=0D
+*=0D
+* Copyright (c) 2020 Linaro Ltd. All rights reserved.=0D
+* Copyright (c) 2021 ARM Ltd. All rights reserved.=0D
+* Copyright (c) 2021 Semihalf. All rights reserved.=0D
+*=0D
+* SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+*=0D
+**/=0D
+#include <IndustryStandard/Acpi.h>=0D
+#include <IndustryStandard/DebugPort2Table.h>=0D
+#include <Library/AcpiLib.h>=0D
+#include <Library/PcdLib.h>=0D
+=0D
+#include "AcpiHeader.h"=0D
+#include "Cn913xCEx7Eval/Dbg2.h"=0D
+=0D
+#pragma pack(1)=0D
+=0D
+#define CN913X_UART_STR { '\\', '_', 'S', 'B', '.', 'C', 'O', 'M', '2', 0x=
00 }=0D
+=0D
+typedef struct {=0D
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT Dbg2Device;=0D
+ EFI_ACPI_6_3_GENERIC_ADDRESS_STRUCTURE BaseAddressRegister;=0D
+ UINT32 AddressSize;=0D
+ UINT8 NameSpaceString[10];=0D
+} DBG2_DEBUG_DEVICE_INFORMATION;=0D
+=0D
+typedef struct {=0D
+ EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Description;=0D
+ DBG2_DEBUG_DEVICE_INFORMATION Dbg2DeviceInfo;=0D
+} DBG2_TABLE;=0D
+=0D
+=0D
+STATIC DBG2_TABLE Dbg2 =3D {=0D
+ {=0D
+ __ACPI_HEADER (=0D
+ EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,=0D
+ DBG2_TABLE,=0D
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION=0D
+ ),=0D
+ OFFSET_OF (DBG2_TABLE, Dbg2DeviceInfo),=0D
+ 1 /* NumberOfDebugPorts */=0D
+ },=0D
+ {=0D
+ {=0D
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,=0D
+ sizeof (DBG2_DEBUG_DEVICE_INFORMATION),=0D
+ 1, /* NumberofGenericAddressRegist=
ers */=0D
+ 10, /* NameSpaceStringLength */=0D
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, NameSpaceString),=0D
+ 0, /* OemDataLength */=0D
+ 0, /* OemDataOffset */=0D
+ EFI_ACPI_DBG2_PORT_TYPE_SERIAL,=0D
+ EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_16550_SUBSET_COMPATIBLE_WITH_MS_DB=
GP_SPEC,=0D
+ {=0D
+ EFI_ACPI_RESERVED_BYTE,=0D
+ EFI_ACPI_RESERVED_BYTE=0D
+ },=0D
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, BaseAddressRegister),=0D
+ OFFSET_OF (DBG2_DEBUG_DEVICE_INFORMATION, AddressSize)=0D
+ },=0D
+ MV_UART_AS32 (CN913X_DBG2_UART_REG_BASE), /* BaseAddress */=
=0D
+ SIZE_4KB, /* AddressSize */=
=0D
+ CN913X_UART_STR, /* NameSpaceStrin=
g */=0D
+ }=0D
+};=0D
+=0D
+#pragma pack()=0D
+=0D
+// Reference the table being generated to prevent the optimizer from remov=
ing=0D
+// the data structure from the executable=0D
+VOID* CONST ReferenceAcpiTable =3D &Dbg2;=0D
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.as=
lc b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc
new file mode 100644
index 0000000000..181bbe5530
--- /dev/null
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc
@@ -0,0 +1,87 @@
+/** @file=0D
+=0D
+ Memory mapped config space base address table (MCFG)=0D
+=0D
+ Copyright (c) 2017, Linaro Ltd. All rights reserved.<BR>=0D
+ Copyright (C) 2019, Marvell International Ltd. and its affiliates.<BR>=0D
+ Copyright (C) 2021, Semihalf.<BR>=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <Library/AcpiLib.h>=0D
+=0D
+#include "AcpiHeader.h"=0D
+#include "Cn913xCEx7Eval/Pcie.h"=0D
+=0D
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>=0D
+=0D
+#pragma pack(1)=0D
+typedef struct {=0D
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER Header;=0D
+ EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCAT=
ION_STRUCTURE Structure[7];=0D
+} ACPI_6_0_MCFG_STRUCTURE;=0D
+#pragma pack()=0D
+=0D
+STATIC ACPI_6_0_MCFG_STRUCTURE Mcfg =3D {=0D
+ {=0D
+ __ACPI_HEADER (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SP=
ACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,=0D
+ ACPI_6_0_MCFG_STRUCTURE,=0D
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE=
_REVISION),=0D
+ EFI_ACPI_RESERVED_QWORD=0D
+ },=0D
+ {=0D
+ {=0D
+ CP0_PCI0_ECAM_BASE, // BaseAddress=0D
+ 0, // PciSegmentGroupNumber=0D
+ CP0_PCI0_BUS_MIN, // StartBusNumber=0D
+ CP0_PCI0_BUS_MAX, // EndBusNumber=0D
+ EFI_ACPI_RESERVED_DWORD // Reserved=0D
+ },=0D
+ {=0D
+ CP1_PCI0_ECAM_BASE, // BaseAddress=0D
+ 1, // PciSegmentGroupNumber=0D
+ CP1_PCI0_BUS_MIN, // StartBusNumber=0D
+ CP1_PCI0_BUS_MAX, // EndBusNumber=0D
+ EFI_ACPI_RESERVED_DWORD // Reserved=0D
+ },=0D
+ {=0D
+ CP1_PCI1_ECAM_BASE, // BaseAddress=0D
+ 2, // PciSegmentGroupNumber=0D
+ CP1_PCI1_BUS_MIN, // StartBusNumber=0D
+ CP1_PCI1_BUS_MAX, // EndBusNumber=0D
+ EFI_ACPI_RESERVED_DWORD // Reserved=0D
+ },=0D
+ {=0D
+ CP1_PCI2_ECAM_BASE, // BaseAddress=0D
+ 3, // PciSegmentGroupNumber=0D
+ CP1_PCI2_BUS_MIN, // StartBusNumber=0D
+ CP1_PCI2_BUS_MAX, // EndBusNumber=0D
+ EFI_ACPI_RESERVED_DWORD // Reserved=0D
+ },=0D
+ {=0D
+ CP2_PCI0_ECAM_BASE, // BaseAddress=0D
+ 4, // PciSegmentGroupNumber=0D
+ CP2_PCI0_BUS_MIN, // StartBusNumber=0D
+ CP2_PCI0_BUS_MAX, // EndBusNumber=0D
+ EFI_ACPI_RESERVED_DWORD // Reserved=0D
+ },=0D
+ {=0D
+ CP2_PCI1_ECAM_BASE, // BaseAddress=0D
+ 5, // PciSegmentGroupNumber=0D
+ CP2_PCI1_BUS_MIN, // StartBusNumber=0D
+ CP2_PCI1_BUS_MAX, // EndBusNumber=0D
+ EFI_ACPI_RESERVED_DWORD // Reserved=0D
+ },=0D
+ {=0D
+ CP2_PCI2_ECAM_BASE, // BaseAddress=0D
+ 6, // PciSegmentGroupNumber=0D
+ CP2_PCI2_BUS_MIN, // StartBusNumber=0D
+ CP2_PCI2_BUS_MAX, // EndBusNumber=0D
+ EFI_ACPI_RESERVED_DWORD // Reserved=0D
+ }=0D
+ }=0D
+};=0D
+=0D
+VOID CONST * CONST ReferenceAcpiTable =3D &Mcfg;=0D
--=20
2.29.0


[edk2-platforms PATCH 1/3] Marvell: Armada7k8k/OcteonTx: Select ACPI description as a default

Marcin Wojtas
 

All currently supported platforms based on the Marvell SoCs offer
both DT and ACPI. Reverse the default setting and pick ACPI as the main
HW description.

Signed-off-by: Marcin Wojtas <mw@semihalf.com>
---
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel=
l/Armada7k8k/Armada7k8k.dsc.inc
index 25f3fc8dd8..d27e582b54 100644
--- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
+++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc
@@ -240,6 +240,13 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|0xF93E000=
0=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|0xF93D0=
000=0D
=0D
+ #=0D
+ # Select ACPI as a default HW description=0D
+ #=0D
+!if $(ARCH) =3D=3D AARCH64=0D
+ gEmbeddedTokenSpaceGuid.PcdDefaultDtPref|FALSE=0D
+!endif=0D
+=0D
[PcdsFixedAtBuild.common]=0D
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"EDK2 SH 1.0"=0D
gArmPlatformTokenSpaceGuid.PcdCoreCount|4=0D
--=20
2.29.0


[edk2-platforms PATCH 0/4] SolidRun CEx7 Evaluation Board support

Marcin Wojtas
 

Hi,

This patchset introduces support for the CEx7 Evaluation Board
Support, together with the ACPI tables and DT (edk2-non-osi patch).
Additional patch toggles the default HW description to ACPI for
all platforms based on SoCs.

Supported interaces:
* SPI flash & memory-mapped variable storage access
* uSD
* eMMC
* 7x PCIE root complex
* USB
* Networking:
* 1Gbps RGMII via PHY
* 2500Base-X via quad 1Gpbs switch
* 5Gbps via SFP cage and PHY

The patches are also available on public branches:
https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/cex7-r20210806
https://github.com/semihalf-wojtas-marcin/edk2-non-osi/commits/cex7-r20210806

I would appreciate any comments or remarks.

Best regards,
Marcin

Marcin Wojtas (3):
edk2-platforms:
Marvell: Armada7k8k/OcteonTx: Select ACPI description as a default
SolidRun/Cn913xCEx7Eval: Add ACPI support
SolidRun/Cn913xCEx7Eval: Add platform support

edk2-non-osi:
SolidRun/Cn913xCEx7Eval: Add DeviceTree

Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc | 54 ++
Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc | 64 +++
Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc | 64 +++
Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc | 68 +++
Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 7 +
Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc | 57 +++
Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf | 30 ++
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf | 38 ++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf | 61 +++
Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h | 30 ++
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h | 13 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h | 9 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h | 114 +++++
Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c | 294 +++++++++++
Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c | 89 ++++
Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc | 17 +
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl | 383 +++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl | 493 +++++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl | 515 ++++++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl | 120 +++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc | 74 +++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc | 87 ++++
22 files changed, 2681 insertions(+)
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9130Eval.dsc.inc
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9131Eval.dsc.inc
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn9132Eval.dsc.inc
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7.dsc.inc
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.dsc
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.inf
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.inf
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval.inf
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.h
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.h
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Pcie.h
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/BoardDescriptionLib/BoardDescriptionLib.c
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/NonDiscoverableInitLib/NonDiscoverableInitLib.c
create mode 100644 Platform/SolidRun/Cn913xCEx7Eval/Cn913xCEx7Eval.fdf.inc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9130EvalSsdt.asl
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9131EvalSsdt.asl
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn9132EvalSsdt.asl
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Cn913xCEx7Dsdt.asl
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Dbg2.aslc
create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xCEx7Eval/Mcfg.aslc

--
2.29.0


Re: [PATCH 1/1] Platform/RaspberryPi: Add linux quirk support

Jeremy Linton
 

Hi,

On 8/6/21 10:47 AM, Andrei Warkentin wrote:
Hi Jeremy,
Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
MADT -> MCFG
Yah, I have to start thinking about what I'm typing :)

Root port registers would be NonCacheable just like the outbound mapping. (Also, with https://mantis.uefi.org/mantis/view.php?id=2220, _MEM attributes aside from NonCacheable and Prefetchable are effectively deprecated).
Note: I really wish we had sorted out the HID/CID story for the PCIe RC... i.e. at least to make the HID custom for non-ECAM implementations and push PNP0A08/PNP0A03 in the CID... this would make linux,pcie-quirk unnecessary, using standard ACPI driver binding mechanisms to separate quirks from proper ECAM. Sadly, I think the train to do that has long left the station (with so many ACPI Arm systems out there and non-ECAM or not-quite-ECAM RCs using PNP0A08/PNP0A03 alone. ESXi, for example, ends up keying on the Table Ids (which is arguably even worse than the DT props)
This isn't a bad idea (changing the HID), but I think your right that ship might have sailed, although it might be still be an alternative for the SMC.


Note 2: Given that DT has users in U-Boot and the BSDs (and potentially anywhere else), there's a long term hope to make DT bindings separate from Linux. To that end "linux,pcie-quirk" and "linux,pcie-nomsi" should probably be named something else (although I recognise that you're probably just wiring up something that already exists).
Well I want this one to be linux specific, because hopefully everyone else realizes that the SMC is a better plan and ignores the property. Its not set anywhere so I can potentially change it. The linux posting is here:

https://lkml.org/lkml/2021/8/5/1109

(where I apparently typed MCFG instead of MADT correctly, well at least most of the time :) .

But I don't have a problem dropping the linux bit, although I would like that part to be generic so future SMC+quirked platforms don't have to modify the quirk detection code. Although lets see what Lorenzo/etc say about what i'm doing in that patch. Thats why I left this patch off the other set.



--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware
________________________________
From: Jeremy Linton <jeremy.linton@arm.com>
Sent: Thursday, August 5, 2021 7:40 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>
Subject: [PATCH 1/1] Platform/RaspberryPi: Add linux quirk support
Linux, for the time being has refused to support the Arm
standard SMCCC for PCIe configuration. Instead they
want to continue to maintain per device "quirks".
As the RPI isn't really ECAM this is a bit more
involved because the MADT can't really describe
the root port+config registers situation. Further
platforms which support the SMCCC shouldn't have
a MADT, so we need an additional way to tell linux
what it needs to know about this platform.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/Pci.asl | 21 +++++++++++++++++++++
1 file changed, 21 insertions(+)
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
index 34474f13ef..3e7fd0d5b7 100644
--- a/Platform/RaspberryPi/AcpiTables/Pci.asl
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -123,6 +123,15 @@ DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
Name(_BBN, Zero) // PCI Base Bus Number
Name(_CCA, 0) // Mark the PCI noncoherent
+ Name (_DSD, Package () {
+ ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+ Package () {
+ Package () { "linux,pcie-quirk", "bcm2711" },
+ Package () { "linux,pcie-nomsi", 1 },
+ }
+ })
+
+
// Root Complex 0
Device (RP0) {
Name(_ADR, 0xF0000000) // Dev 0, Func 0
@@ -176,6 +185,18 @@ DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
2 // SANITIZED_PCIE_MMIO_LEN + 1
,,,MMI1,,TypeTranslation
)
+
+ QWordMemory ( // Root port registers, not to be used if SMCCC is utilized
+ ResourceConsumer, ,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, // cacheable? is that right?
+ 0x00000000, // Granularity
+ 0xFD500000, // Root port begin
+ 0xFD509FFF, // Root port end
+ 0x00000000, // no translation
+ 0x0000A000, // size
+ ,,
+ )
}) // end Name(RBUF)
// Work around ASL's inability to add in a resource definition
--
2.13.7


Re: [RFC] MemoryProtectionLib for Dynamic Memory Guard Settings

Andrew Fish
 



On Aug 1, 2021, at 7:35 PM, Ni, Ray <ray.ni@...> wrote:

I also vote "using HOB passing policy". This design helps the new bootloader/payload architecture.

EDKII library class design was a good design which mimics C++ class to provide same interface for:
1. different phases (PEI, DXE, runtime. E.g.: HobLib, PcdLib, MemoryAllocationLib)
2. different source of policy (e.g.: DebugLib.)
3. different optimization mechanism (e.g.: BaseMemoryLib)
4. more...


I also like to think of this in terms on static and dynamic linking. For things that would be statically linked we use EDKII library classes. For dynamic linking we use Protocol/PPI and the required the coder to write code, vs having a dynamic linker resolve it for you. 

However, the extensive usage of lib class brings difficulty of understanding the code. There are so many instances of a library class and it's hard to know which one is being used by a certain module by just looking at the source code. (Sometimes even I need to build the code base and check the files in build directory to understand which lib instance is used for which module.)


The build log that can optionally be created by the tools is very useful for figuring all this kind of stuff out. Maybe we should come up with a best practice place to put those and turn it one for platforms that have scripts wrapping the build?

We could also build tooling to help with this? It is possible to add custom git commands to help in grepping code etc. So if people have ideas about tools we should discuss them….

Thanks,

Andrew Fish

It's a common issue in projects using OO programing language. But most of these projects are for application level needs and the app debugger is very easy to use. This is the difference between EDKII projects and other OO projects.

Thanks,
Ray

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Sean
Sent: Saturday, July 31, 2021 2:42 AM
To: devel@edk2.groups.io; Yao, Jiewen <jiewen.yao@...>; Taylor Beebe <t@...>; Wang, Jian J <jian.j.wang@...>
Cc: Dong, Eric <eric.dong@...>; Ni, Ray <ray.ni@...>; Kumar, Rahul1 <rahul1.kumar@...>; mikuback@...; Wu, Hao A <hao.a.wu@...>; Bi, Dandan <dandan.bi@...>; gaoliming@...; Dong, Guo <guo.dong@...>; Ma, Maurice <maurice.ma@...>; You, Benjamin <benjamin.you@...>
Subject: Re: [edk2-devel] [RFC] MemoryProtectionLib for Dynamic Memory Guard Settings

Jiewen,

**Slight rant**

I agree with libraries as an effective abstraction method.  But I think there needs to be a broad discussion about the order of preference for methods of abstraction.  Today the edk2 code base is a mix and often there are numerous methods abstracting the same thing which leads to confusion, misconfiguration, and error.

In the UEFI specification we have PPIs/Protocols/Events for functional abstraction.  We have variables, guided config tables, and HII for data abstraction.

In the PI specification we add HOBs and PCDs for data abstractions.

Finally, in EDKII we add the library class concept and leverage it heavily for arch, phase, and platform/behavioral abstractions.

Without clear guidance for how and when to use the above it is hard to keep code being developed by the larger community consistent.

**End**

I was leaning towards something closer to

Option 1: 
https://github.com/TaylorBeebe/edk2/tree/memory_protection_lib_2

the HOB method and internally as we develop more code we are preferring HOB and data abstractions more than functional abstraction.  Data abstractions can be used to control functional differences as well if needed.  Data abstractions allow for easier validation and support diverse code environments.  For example standalone MM and payloadpkg/payload concepts.  Finally, data abstractions break the need 
for a monolithic code base.   But as you can see in option 1 it actually 
uses a library class abstraction as well because no one wants to write the same code over and over again to get the HOB.  The contract of the library is just data but it still requires library mappings.  Maybe these types of libraries need to be treated differently.

Anyway it would be great to hear from other members of the community around not just the memory protections RFC (this RFC) but around preferences for abstraction techniques (pro/con).  If an actual discussion starts it could move to design meeting.

Thanks
Sean







On 7/29/2021 7:34 PM, Yao, Jiewen wrote:
Thanks. Code talks better.

I prefer option 2, which is a generic way for abstraction.

And you may enable option 1 under the cover of option 2, just create a lib instance to get config from Hob.

Thank you
Yao Jiewen

-----Original Message-----
From: Taylor Beebe <t@...>
Sent: Friday, July 30, 2021 10:07 AM
To: Yao, Jiewen <jiewen.yao@...>; Wang, Jian J 
<jian.j.wang@...>; devel@edk2.groups.io
Cc: spbrogan@...; Dong, Eric <eric.dong@...>; Ni, Ray 
<ray.ni@...>; Kumar, Rahul1 <rahul1.kumar@...>; 
mikuback@...; Wu, Hao A <hao.a.wu@...>; Bi, 
Dandan <dandan.bi@...>; gaoliming@...; Dong, Guo 
<guo.dong@...>; Ma, Maurice <maurice.ma@...>; You, 
Benjamin <benjamin.you@...>
Subject: Re: [RFC] MemoryProtectionLib for Dynamic Memory Guard 
Settings

Of course - here are a couple of rough drafts:

Option 1: 
https://github.com/TaylorBeebe/edk2/tree/memory_protection_lib_2
Option 2: 
https://github.com/TaylorBeebe/edk2/tree/memory_protection_lib

On 7/29/2021 6:57 PM, Yao, Jiewen wrote:
Hi
Sorry, I am not able to follow the discussion.

Is there any sample or POC code to show the concept?

-----Original Message-----
From: Taylor Beebe <t@...>
Sent: Friday, July 30, 2021 9:55 AM
To: Wang, Jian J <jian.j.wang@...>; devel@edk2.groups.io
Cc: spbrogan@...; Dong, Eric <eric.dong@...>; Ni, Ray 
<ray.ni@...>; Kumar, Rahul1 <rahul1.kumar@...>; 
mikuback@...; Wu, Hao A <hao.a.wu@...>; Bi,
Dandan
<dandan.bi@...>; gaoliming@...; Dong, Guo 
<guo.dong@...>; Ma, Maurice <maurice.ma@...>; You,
Benjamin
<benjamin.you@...>; Yao, Jiewen <jiewen.yao@...>
Subject: Re: [RFC] MemoryProtectionLib for Dynamic Memory Guard 
Settings

Thanks for your feedback, Jian.

In option 2, a most basic implementation would returning the 
current FixedAtBuild PCDs assuming they are kept. If they aren't, 
the library implementer could simply hard-code the return value for 
each memory protection setting.

In option 1, the HOB would be published in pre-mem and I'm not an 
expert on exploiting the pre-mem environment. Jiewen may have more 
to say on
this.

-Taylor

On 7/28/2021 7:18 PM, Wang, Jian J wrote:
Thanks for the RFC. I'm not object to this idea. The only concern 
from me is the potential security holes introduced by the changes. 
According to your description, it allows 3rd party software to 
violate memory protection
policy.
I'd like to see more explanations on how to avoid it to be exploited.

+Jiewen, what's current process to evaluate the security threat?

Regards,
Jian

-----Original Message-----
From: Taylor Beebe <t@...>
Sent: Friday, July 23, 2021 8:33 AM
To: devel@edk2.groups.io
Cc: spbrogan@...; Dong, Eric <eric.dong@...>; Ni, 
Ray <ray.ni@...>; Kumar, Rahul1 <Rahul1.Kumar@...>; 
mikuback@...; Wang, Jian J 
<jian.j.wang@...>;
Wu,
Hao A <hao.a.wu@...>; Bi, Dandan <dandan.bi@...>; 
gaoliming@...; Dong, Guo <guo.dong@...>; Ma,
Maurice
<maurice.ma@...>; You, Benjamin <benjamin.you@...>
Subject: [RFC] MemoryProtectionLib for Dynamic Memory Guard 
Settings

Current memory protection settings rely on FixedAtBuild PCD 
values (minus PcdSetNxForStack). Because of this, the memory 
protection configuration interface is fixed in nature. Cases 
arise in which memory protections might need to be adjusted 
between boots (if platform design
allows) to avoid disabling a system. For example, platforms might 
choose to allow the user to control their protection policies 
such as allow execution of critical 3rd party software that might 
violate memory protections.

This RFC seeks your feedback regarding introducing an interface 
that allows dynamic configuration of memory protection settings.

I would like to propose two options:
1. Describing the memory protection setting configuration in a 
HOB that is produced by the platform.
2. Introducing a library class (e.g. MemoryProtectionLib) that 
allows abstraction of the memory protection setting configuration data source.

In addition, I would like to know if the memory protection 
FixedAtBuild PCDs currently in MdeModulePkg can be removed so we 
can move the configuration interface entirely to an option above.

In any case, I would like the settings to be visible to 
environments such as Standalone MM where dynamic PCDs are not accessible.

I am seeking your feedback on this proposal in preparation for 
sending an edk2 patch series.

--
Taylor Beebe
Software Engineer @ Microsoft

--
Taylor Beebe
Software Engineer @ Microsoft

--
Taylor Beebe
Software Engineer @ Microsoft














Re: [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4

Jeremy Linton
 

Hi,

On 8/6/21 11:04 AM, Andrei Warkentin wrote:
Ok, I misunderstood the patch set (I thought the PciHostBridgeLib itself would eventually move to DEN0115).
I still think that (in general) would be a good idea - if not for the benefit of the Pi, then for the next upstreamed platform where you could avoid implementing custom config access code...
Right, the only bit that goes away is the PciSegmentLibGetConfigBase() code to be replaced by the SMC call. Which I will do, but I think its better to fix to this one and make that a separate patch-set ideally with another platform in parallel.


Reviewed-by: Andrei Warkentin <awarkentin@vmware.com>
--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware
________________________________
From: Andrei Warkentin <awarkentin@vmware.com>
Sent: Friday, August 6, 2021 7:02 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>; jeremy.linton@arm.com <jeremy.linton@arm.com>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; René Treffer <treffer+groups.io@measite.de>
Subject: Re: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
Hi Jeremy,
Is any of this still conceptually necessary if we adopt the SMCCC interface within UEFI?
Instead of assuming the first downstream bus is bus 1, could you read the secondary BN from the RP?
--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware
________________________________
From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <jeremy.linton=arm.com@groups.io>
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>; René Treffer <treffer+groups.io@measite.de>
Subject: [edk2-devel] [PATCH 4/5] Silicon/Broadcom/Bcm27xx: Tweak PCIe for CM4
The CM4 has an actual pcie slot, so we need to move the linkup
check to the configuration probe logic. Further the device
restriction logic needs to be relaxed to support downstream
PCIe switches.
Suggested-by: René Treffer <treffer+groups.io@measite.de>
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
.../Bcm2711PciHostBridgeLibConstructor.c | 5 -----
.../Library/Bcm2711PciSegmentLib/PciSegmentLib.c | 24 +++++++++++++++-------
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
index 8587d2d36d..4d4c584726 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciHostBridgeLib/Bcm2711PciHostBridgeLibConstructor.c
@@ -204,11 +204,6 @@ Bcm2711PciHostBridgeLibConstructor (
} while (((Data & 0x30) != 0x030) && (Timeout));
DEBUG ((DEBUG_VERBOSE, "PCIe link ready (status=%x) Timeout=%d\n", Data, Timeout));
- if ((Data & 0x30) != 0x30) {
- DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
- return EFI_DEVICE_ERROR;
- }
-
if ((Data & 0x80) != 0x80) {
DEBUG ((DEBUG_ERROR, "PCIe link not in RC mode (status=%x)\n", Data));
return EFI_UNSUPPORTED;
diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..3ccc131eab 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -78,6 +78,8 @@ PciSegmentLibGetConfigBase (
UINT64 Base;
UINT64 Offset;
UINT32 Dev;
+ UINT32 Bus;
+ UINT32 Data;
Base = PCIE_REG_BASE;
Offset = Address & 0xFFF; /* Pick off the 4k register offset */
@@ -89,17 +91,25 @@ PciSegmentLibGetConfigBase (
Base += PCIE_EXT_CFG_DATA;
if (mPciSegmentLastAccess != Address) {
Dev = EFI_PCI_ADDR_DEV (Address);
+ Bus = EFI_PCI_ADDR_BUS (Address);
+
/*
- * Scan things out directly rather than translating the "bus" to a device, etc..
- * only we need to limit each bus to a single device.
+ * There can only be a single device on bus 1 (downstream of root).
+ * Subsequent busses (behind a PCIe switch) can have more.
*/
- if (Dev < 1) {
- MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
- mPciSegmentLastAccess = Address;
- } else {
- mPciSegmentLastAccess = 0;
+ if (Dev > 0 && (Bus < 2)) {
return 0xFFFFFFFF;
}
+
+ /* Don't probe slots if the link is down */
+ Data = MmioRead32 (PCIE_REG_BASE + PCIE_MISC_PCIE_STATUS);
+ if ((Data & 0x30) != 0x30) {
+ DEBUG ((DEBUG_ERROR, "PCIe link not ready (status=%x)\n", Data));
+ return 0xFFFFFFFF;
+ }
+
+ MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+ mPciSegmentLastAccess = Address;
}
}
return Base + Offset;
--
2.13.7


Re: [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT

Jeremy Linton
 

Hi,


So I've tested with all the comments below and everything seems to be working fine, so no issues there. I will re-post RSN.

Thanks,

On 8/6/21 8:42 AM, Ard Biesheuvel via groups.io wrote:
On Thu, 5 Aug 2021 at 18:36, Jeremy Linton <jeremy.linton@arm.com> wrote:

Since we plan on toggling between XHCI and PCI the PCI
root needs to be in its own SSDT. This is all thats needed
of UEFI. The SMC conduit is provided directly to the running
OS. When the OS detects this PCIe port, on a machine without
a MADT it attempts to connect to the SMC conduit. The RPi
definition doesn't have any power mgmt, and only provides
a description of the root port.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 +
Platform/RaspberryPi/AcpiTables/Pci.asl | 237 +++++++++++++++++++++
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 +
3 files changed, 246 insertions(+)
create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl

diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index f3e8d950c1..da2a6db85f 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -39,6 +39,7 @@
Pptt.aslc
SsdtThermal.asl
Xhci.asl
+ Pci.asl

[Packages]
ArmPkg/ArmPkg.dec
@@ -59,6 +60,8 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
new file mode 100644
index 0000000000..34474f13ef
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -0,0 +1,237 @@
+/** @file
+ *
+ * Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ * Copyright (c) 2021 Arm
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <IndustryStandard/Bcm2711.h>
+
+#include "AcpiTables.h"
+
+/*
+ * The following can be used to remove parenthesis from
+ * defined macros that the compiler complains about.
+ */
+#define ISOLATE_ARGS(...) __VA_ARGS__
+#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x
+
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
+#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
+
+/*
+ * According to UEFI boot log for the VLI device on Pi 4.
+ */
+#define RT_REG_LENGTH 0x1000
+
+// copy paste job from juno
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+ Device(Link_Name) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, Unique_Id) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+ }
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, /* uses the same format as _ADR */ \
+ Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
+ Link, /* Interrupt allocated via Link device. */ \
+ Zero /* global system interrupt number (no used) */ \
+ }
+#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link)
+
This can be done in a much simpler way - SynQuacer uses this, for instance
Name (_PRT, Package () {
Package () { 0xFFFF, 0, Zero, 222 }, // INTA
Package () { 0xFFFF, 1, Zero, 222 }, // INTB
Package () { 0xFFFF, 2, Zero, 222 }, // INTC
Package () { 0xFFFF, 3, Zero, 222 }, // INTD
})

+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
+{
+ Scope (\_SB_)
+ {
+
+ Device (SCB0) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x0)
Even if this file and the xhci one should never be exposed to the OS
at the same time, can we please use unique UIDs?

+ Name (_CCA, 0x0)
+
+ Method (_CRS, 0, Serialized) {
+ // Container devices with _DMA must have _CRS,
+ // meaning SCB0 to provide all resources that
+ // PCI0 consumes (except interrupts).
+ Name (RBUF, ResourceTemplate () {
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX
+ 0x0,
+ 0x1, // LEN
+ ,
+ ,
+ MMIO
+ )
+ })
+ CreateQwordField (RBUF, MMIO._MAX, MMBE)
+ CreateQwordField (RBUF, MMIO._LEN, MMLE)
+ Add (MMBE, RT_REG_LENGTH - 1, MMBE)
+ Add (MMLE, RT_REG_LENGTH - 1, MMLE)
+ Return (RBUF)
+ }
+
+ Name (_DMA, ResourceTemplate() {
+ // PCIe can only DMA to first 3GB with early SOC's
+ // But we keep the restriction on the later ones
+ // To avoid DMA translation problems.
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ //
+ // PCI Root Complex
+ //
+ LNK_DEVICE(1, LNKA, 175)
+ LNK_DEVICE(2, LNKB, 176)
+ LNK_DEVICE(3, LNKC, 177)
+ LNK_DEVICE(4, LNKD, 178)
+
+ Device(PCI0)
+ {
+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name(_SEG, Zero) // PCI Segment Group number
+ Name(_BBN, Zero) // PCI Base Bus Number
+ Name(_CCA, 0) // Mark the PCI noncoherent
+
+ // Root Complex 0
+ Device (RP0) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
Can we just drop this?

+ Name (_DMA, ResourceTemplate() {
+ QWordMemory (ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
Do we need this method on the host bridge device as well as on the container?

+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKA), // INTA
+ ROOT_PRT_ENTRY(1, LNKB), // INTB
+ ROOT_PRT_ENTRY(2, LNKC), // INTC
+ ROOT_PRT_ENTRY(3, LNKD), // INTD
+ })
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ QWordMemory ( // 32-bit BAR Windows in 64-bit addr
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, //cacheable? is that right?
+ 0x00000000, // Granularity
+ 0, // SANITIZED_PCIE_PCI_MMIO_BEGIN
+ 1, // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW
+ 2 // SANITIZED_PCIE_MMIO_LEN + 1
+ ,,,MMI1,,TypeTranslation
+ )
+ }) // end Name(RBUF)
+
+ // Work around ASL's inability to add in a resource definition
+ // or for that matter compute the min,max,len properly
+ CreateQwordField (RBUF, MMI1._MIN, MMIB)
+ CreateQwordField (RBUF, MMI1._MAX, MMIE)
+ CreateQwordField (RBUF, MMI1._TRA, MMIT)
+ CreateQwordField (RBUF, MMI1._LEN, MMIL)
+ Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)
+ Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
+ Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
+ Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)
+
+ Return (RBUF)
+ } // end Method(_CRS)
+ //
+ // OS Control Handoff
+ //
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ // See [1] 6.2.10, [2] 4.5
+ Method(_OSC,4) {
+ // Note, This code is very similar to the code in the PCIe firmware
+ // specification which can be used as a reference
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+ // Mask out Native HotPlug
+ And(CTRL,0x1E,CTRL)
+ // Always allow native PME, AER (no dependencies)
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ } // End _OSC
+ } // PCI0
+ } //end SCB0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 7c5786303d..4c40820858 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {Yah, I will fix that.
PcdToken(PcdXhciPci),
NULL
},
+ {
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),
+ PcdToken(PcdXhciPci),
+ 0,
+ NULL
+ },
#endif
{ // DSDT
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
--
2.13.7


Re: [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT

Jeremy Linton
 

Hi,

On 8/6/21 10:37 AM, Andrei Warkentin wrote:
Hi Jeremy,
MADT -> MCFG (and in other patches as well, where you refer to MADT)
I will take 4 letter acronyms that start with an M... <chuckle>

Thanks,


The other feedback that Ard provided makes sense to me as well.
A
--
Andrei Warkentin,
Arm Enablement Architect,
Cloud Platform Business Unit, VMware
________________________________
From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Jeremy Linton via groups.io <jeremy.linton=arm.com@groups.io>
Sent: Thursday, August 5, 2021 7:35 PM
To: devel@edk2.groups.io <devel@edk2.groups.io>
Cc: pete@akeo.ie <pete@akeo.ie>; ardb+tianocore@kernel.org <ardb+tianocore@kernel.org>; Andrei Warkentin <awarkentin@vmware.com>; Sunny.Wang@arm.com <Sunny.Wang@arm.com>; samer.el-haj-mahmoud@arm.com <samer.el-haj-mahmoud@arm.com>; Jeremy Linton <jeremy.linton@arm.com>
Subject: [edk2-devel] [PATCH 3/5] Platform/RaspberryPi: Add PCIe SSDT
Since we plan on toggling between XHCI and PCI the PCI
root needs to be in its own SSDT. This is all thats needed
of UEFI. The SMC conduit is provided directly to the running
OS. When the OS detects this PCIe port, on a machine without
a MADT it attempts to connect to the SMC conduit. The RPi
definition doesn't have any power mgmt, and only provides
a description of the root port.
Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
---
Platform/RaspberryPi/AcpiTables/AcpiTables.inf | 3 +
Platform/RaspberryPi/AcpiTables/Pci.asl | 237 +++++++++++++++++++++
Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c | 6 +
3 files changed, 246 insertions(+)
create mode 100644 Platform/RaspberryPi/AcpiTables/Pci.asl
diff --git a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
index f3e8d950c1..da2a6db85f 100644
--- a/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
+++ b/Platform/RaspberryPi/AcpiTables/AcpiTables.inf
@@ -39,6 +39,7 @@
Pptt.aslc
SsdtThermal.asl
Xhci.asl
+ Pci.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -59,6 +60,8 @@
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
gArmTokenSpaceGuid.PcdGicDistributorBase
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciCpuMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioAdr
+ gBcm27xxTokenSpaceGuid.PcdBcm27xxPciBusMmioLen
gBcm27xxTokenSpaceGuid.PcdBcm27xxPciRegBase
gBcm27xxTokenSpaceGuid.PcdBcmGenetRegistersAddress
gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress
diff --git a/Platform/RaspberryPi/AcpiTables/Pci.asl b/Platform/RaspberryPi/AcpiTables/Pci.asl
new file mode 100644
index 0000000000..34474f13ef
--- /dev/null
+++ b/Platform/RaspberryPi/AcpiTables/Pci.asl
@@ -0,0 +1,237 @@
+/** @file
+ *
+ * Copyright (c) 2019 Linaro, Limited. All rights reserved.
+ * Copyright (c) 2021 Arm
+ *
+ * SPDX-License-Identifier: BSD-2-Clause-Patent
+ *
+ **/
+
+#include <IndustryStandard/Bcm2711.h>
+
+#include "AcpiTables.h"
+
+/*
+ * The following can be used to remove parenthesis from
+ * defined macros that the compiler complains about.
+ */
+#define ISOLATE_ARGS(...) __VA_ARGS__
+#define REMOVE_PARENTHESES(x) ISOLATE_ARGS x
+
+#define SANITIZED_PCIE_CPU_MMIO_WINDOW REMOVE_PARENTHESES(PCIE_CPU_MMIO_WINDOW)
+#define SANITIZED_PCIE_MMIO_LEN REMOVE_PARENTHESES(PCIE_BRIDGE_MMIO_LEN)
+#define SANITIZED_PCIE_PCI_MMIO_BEGIN REMOVE_PARENTHESES(PCIE_TOP_OF_MEM_WIN)
+
+/*
+ * According to UEFI boot log for the VLI device on Pi 4.
+ */
+#define RT_REG_LENGTH 0x1000
+
+// copy paste job from juno
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+ Device(Link_Name) { \
+ Name(_HID, EISAID("PNP0C0F")) \
+ Name(_UID, Unique_Id) \
+ Name(_PRS, ResourceTemplate() { \
+ Interrupt(ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+ }
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, /* uses the same format as _ADR */ \
+ Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD). */ \
+ Link, /* Interrupt allocated via Link device. */ \
+ Zero /* global system interrupt number (no used) */ \
+ }
+#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY(0x0000FFFF, Pin, Link)
+
+DefinitionBlock (__FILE__, "SSDT", 5, "RPIFDN", "RPI4PCIE", 2)
+{
+ Scope (\_SB_)
+ {
+
+ Device (SCB0) {
+ Name (_HID, "ACPI0004")
+ Name (_UID, 0x0)
+ Name (_CCA, 0x0)
+
+ Method (_CRS, 0, Serialized) {
+ // Container devices with _DMA must have _CRS,
+ // meaning SCB0 to provide all resources that
+ // PCI0 consumes (except interrupts).
+ Name (RBUF, ResourceTemplate () {
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // MIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // MAX
+ 0x0,
+ 0x1, // LEN
+ ,
+ ,
+ MMIO
+ )
+ })
+ CreateQwordField (RBUF, MMIO._MAX, MMBE)
+ CreateQwordField (RBUF, MMIO._LEN, MMLE)
+ Add (MMBE, RT_REG_LENGTH - 1, MMBE)
+ Add (MMLE, RT_REG_LENGTH - 1, MMLE)
+ Return (RBUF)
+ }
+
+ Name (_DMA, ResourceTemplate() {
+ // PCIe can only DMA to first 3GB with early SOC's
+ // But we keep the restriction on the later ones
+ // To avoid DMA translation problems.
+ QWordMemory (ResourceProducer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ //
+ // PCI Root Complex
+ //
+ LNK_DEVICE(1, LNKA, 175)
+ LNK_DEVICE(2, LNKB, 176)
+ LNK_DEVICE(3, LNKC, 177)
+ LNK_DEVICE(4, LNKD, 178)
+
+ Device(PCI0)
+ {
+ Name(_HID, EISAID("PNP0A08")) // PCI Express Root Bridge
+ Name(_CID, EISAID("PNP0A03")) // Compatible PCI Root Bridge
+ Name(_SEG, Zero) // PCI Segment Group number
+ Name(_BBN, Zero) // PCI Base Bus Number
+ Name(_CCA, 0) // Mark the PCI noncoherent
+
+ // Root Complex 0
+ Device (RP0) {
+ Name(_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
+ Name (_DMA, ResourceTemplate() {
+ QWordMemory (ResourceConsumer,
+ ,
+ MinFixed,
+ MaxFixed,
+ NonCacheable,
+ ReadWrite,
+ 0x0,
+ 0x0, // MIN
+ 0xbfffffff, // MAX
+ 0x0, // TRA
+ 0xc0000000, // LEN
+ ,
+ ,
+ )
+ })
+
+ // PCI Routing Table
+ Name(_PRT, Package() {
+ ROOT_PRT_ENTRY(0, LNKA), // INTA
+ ROOT_PRT_ENTRY(1, LNKB), // INTB
+ ROOT_PRT_ENTRY(2, LNKC), // INTC
+ ROOT_PRT_ENTRY(3, LNKD), // INTD
+ })
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ QWordMemory ( // 32-bit BAR Windows in 64-bit addr
+ ResourceProducer, PosDecode,
+ MinFixed, MaxFixed,
+ NonCacheable, ReadWrite, //cacheable? is that right?
+ 0x00000000, // Granularity
+ 0, // SANITIZED_PCIE_PCI_MMIO_BEGIN
+ 1, // SANITIZED_PCIE_MMIO_LEN + SANITIZED_PCIE_PCI_MMIO_BEGIN
+ SANITIZED_PCIE_CPU_MMIO_WINDOW, // SANITIZED_PCIE_PCI_MMIO_BEGIN - SANITIZED_PCIE_CPU_MMIO_WINDOW
+ 2 // SANITIZED_PCIE_MMIO_LEN + 1
+ ,,,MMI1,,TypeTranslation
+ )
+ }) // end Name(RBUF)
+
+ // Work around ASL's inability to add in a resource definition
+ // or for that matter compute the min,max,len properly
+ CreateQwordField (RBUF, MMI1._MIN, MMIB)
+ CreateQwordField (RBUF, MMI1._MAX, MMIE)
+ CreateQwordField (RBUF, MMI1._TRA, MMIT)
+ CreateQwordField (RBUF, MMI1._LEN, MMIL)
+ Add (MMIB, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIB)
+ Add (SANITIZED_PCIE_MMIO_LEN, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIE)
+ Subtract (MMIT, SANITIZED_PCIE_PCI_MMIO_BEGIN, MMIT)
+ Add (SANITIZED_PCIE_MMIO_LEN, 1 , MMIL)
+
+ Return (RBUF)
+ } // end Method(_CRS)
+ //
+ // OS Control Handoff
+ //
+ Name(SUPP, Zero) // PCI _OSC Support Field value
+ Name(CTRL, Zero) // PCI _OSC Control Field value
+
+ // See [1] 6.2.10, [2] 4.5
+ Method(_OSC,4) {
+ // Note, This code is very similar to the code in the PCIe firmware
+ // specification which can be used as a reference
+ // Check for proper UUID
+ If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField(Arg3,0,CDW1)
+ CreateDWordField(Arg3,4,CDW2)
+ CreateDWordField(Arg3,8,CDW3)
+ // Save Capabilities DWord2 & 3
+ Store(CDW2,SUPP)
+ Store(CDW3,CTRL)
+ // Mask out Native HotPlug
+ And(CTRL,0x1E,CTRL)
+ // Always allow native PME, AER (no dependencies)
+ // Never allow SHPC (no SHPC controller in this system)
+ And(CTRL,0x1D,CTRL)
+
+ If(LNotEqual(Arg1,One)) { // Unknown revision
+ Or(CDW1,0x08,CDW1)
+ }
+
+ If(LNotEqual(CDW3,CTRL)) { // Capabilities bits were masked
+ Or(CDW1,0x10,CDW1)
+ }
+ // Update DWORD3 in the buffer
+ Store(CTRL,CDW3)
+ Return(Arg3)
+ } Else {
+ Or(CDW1,4,CDW1) // Unrecognized UUID
+ Return(Arg3)
+ }
+ } // End _OSC
+ } // PCI0
+ } //end SCB0
+ } //end scope sb
+} //end definition block
diff --git a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
index 7c5786303d..4c40820858 100644
--- a/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
+++ b/Platform/RaspberryPi/Drivers/ConfigDxe/ConfigDxe.c
@@ -821,6 +821,12 @@ STATIC CONST NAMESPACE_TABLES SdtTables[] = {
PcdToken(PcdXhciPci),
NULL
},
+ {
+ SIGNATURE_64 ('R', 'P', 'I', '4', 'P', 'C', 'I', 'E'),
+ PcdToken(PcdXhciPci),
+ 0,
+ NULL
+ },
#endif
{ // DSDT
SIGNATURE_64 ('R', 'P', 'I', 0, 0, 0, 0, 0),
--
2.13.7
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Re: [PATCH v7 1/3] BaseTools: Remove COMMON section from the GCC discard list

Christopher Zurcher
 

Ard,
Is the removal of the COMMON section during the build not redundant to the -fno-common option? Do you expect cases where we will still see the undesired variable collisions?

Thanks,
Christopher Zurcher

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of gaoliming
Sent: Wednesday, August 4, 2021 22:04
To: 'Ard Biesheuvel' <ardb@kernel.org>; 'Yao, Jiewen' <jiewen.yao@intel.com>
Cc: devel@edk2.groups.io; christopher.zurcher@outlook.com; 'Feng, Bob C' <bob.c.feng@intel.com>
Subject: 回复: [edk2-devel] [PATCH v7 1/3] BaseTools: Remove COMMON section from the GCC discard list

Ard:
Chris explains this change in https://edk2.groups.io/g/devel/message/77662. And, he also verifies the patch in OVMF with GCC5 tool chain.

Thanks
Liming
-----邮件原件-----
发件人: Ard Biesheuvel <ardb@kernel.org>
发送时间: 2021年8月4日 20:27
收件人: Yao, Jiewen <jiewen.yao@intel.com>
抄送: devel@edk2.groups.io; christopher.zurcher@outlook.com; Feng, Bob C
<bob.c.feng@intel.com>; Liming Gao <gaoliming@byosoft.com.cn>
主题: Re: [edk2-devel] [PATCH v7 1/3] BaseTools: Remove COMMON section
from the GCC discard list

On Wed, 21 Jul 2021 at 13:44, Yao, Jiewen <jiewen.yao@intel.com> wrote:

Acked-by: Jiewen Yao <Jiewen.yao@intel.com>
I don't think this is a good idea tbh. We have already identified that
EDK2 code often fails to use the STATIC keyword when possible for
global variables, and that unrelated variables that happen to have the
same name will be collapsed into the same storage unit in the program
image. (see commit 214a3b79417f64bf2faae74af42c1b9d23f50dc8 for
details)

Was this considered? Is this no longer an issue?



-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
Christopher
Zurcher
Sent: Wednesday, July 21, 2021 6:07 AM
To: devel@edk2.groups.io
Cc: Ard Biesheuvel <ardb@kernel.org>; Feng, Bob C
<bob.c.feng@intel.com>;
Liming Gao <gaoliming@byosoft.com.cn>
Subject: [edk2-devel] [PATCH v7 1/3] BaseTools: Remove COMMON
section
from the GCC discard list

From: Christopher Zurcher <christopher.zurcher@microsoft.com>

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=2507

The COMMON section is used by OpenSSL assembly-optimized crypto
functions. OpenSSL assembly code is auto-generated from the
submodule and cannot be modified to remove dependence on the COMMON section.
The default -fno-common compiler flag should still prevent
variable from being emitted into the COMMON section.

Cc: Ard Biesheuvel <ardb@kernel.org>
Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Christopher Zurcher
<christopher.zurcher@microsoft.com>
---
BaseTools/Scripts/GccBase.lds | 1 -
1 file changed, 1 deletion(-)

diff --git a/BaseTools/Scripts/GccBase.lds
b/BaseTools/Scripts/GccBase.lds
index a9dd2138d4..83cebd29d5 100644
--- a/BaseTools/Scripts/GccBase.lds
+++ b/BaseTools/Scripts/GccBase.lds
@@ -74,6 +74,5 @@ SECTIONS {
*(.dynamic)
*(.hash .gnu.hash)
*(.comment)
- *(COMMON)
}
}
--
2.32.0.windows.1





[edk2-platforms][PATCH v1 1/1] MinPlatformPkg/AcpiTables: Update structures for ACPI 6.3

Michael Kubacki
 

From: Daniel Maddy <danmad@microsoft.com>

REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3535

Updates ACPI table structures in MinPlatformPkg for ACPI 6.3.

Cc: Chasel Chiu <chasel.chiu@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Daniel Maddy <danmad@microsoft.com>
Co-authored-by: Michael Kubacki <michael.kubacki@microsoft.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 203 +++++=
+++++----------
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Facs/Facs.c | 11 +-
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c | 74 ++++-=
--
3 files changed, 150 insertions(+), 138 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c=
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index 2b51c34ef2fd..5e3c4c0672f9 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -2,6 +2,7 @@
ACPI Platform Driver
=20
Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
=20
**/
@@ -13,7 +14,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#pragma pack(1)
=20
typedef struct {
- UINT32 AcpiProcessorId;
+ UINT32 AcpiProcessorUid;
UINT32 ApicId;
UINT32 Flags;
UINT32 SwProcApicId;
@@ -27,9 +28,9 @@ typedef struct {
// Define Union of IO APIC & Local APIC structure;
//
typedef union {
- EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE AcpiLocalApic;
- EFI_ACPI_4_0_IO_APIC_STRUCTURE AcpiIoApic;
- EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE AcpiLocalx2Apic;
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE AcpiLocalApic;
+ EFI_ACPI_6_3_IO_APIC_STRUCTURE AcpiIoApic;
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE AcpiLocalx2Apic;
struct {
UINT8 Type;
UINT8 Length;
@@ -38,9 +39,9 @@ typedef union {
=20
#pragma pack()
=20
-extern EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs;
-extern EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt;
-extern EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER Hpet;
+extern EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs;
+extern EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE Fadt;
+extern EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER Hpet;
extern EFI_ACPI_WSMT_TABLE Wsmt;
=20
VOID *mLocalTable[] =3D {
@@ -217,7 +218,7 @@ DebugDisplayReOrderTable(
DEBUG ((EFI_D_ERROR, "Index AcpiProcId ApicId Flags SwApicId Skt\=
n"));
for (Index=3D0; Index<MAX_CPU_NUM; Index++) {
DEBUG ((EFI_D_ERROR, " %02d 0x%02X 0x%02X %d 0x=
%02X %d\n",
- Index, mCpuApicIdOrderTable[Index].AcpiProces=
sorId,
+ Index, mCpuApicIdOrderTable[Index].AcpiProces=
sorUid,
mCpuApicIdOrderTable[Index].ApicId,
mCpuApicIdOrderTable[Index].Flags,
mCpuApicIdOrderTable[Index].SwProcApicId,
@@ -232,31 +233,31 @@ AppendCpuMapTableEntry (
)
{
EFI_STATUS Status;
- EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE *LocalApicPtr;
- EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE *LocalX2ApicPtr;
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE *LocalApicPtr;
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE *LocalX2ApicPtr;
UINT8 Type;
=20
Status =3D EFI_SUCCESS;
Type =3D ((ACPI_APIC_STRUCTURE_PTR *)ApicPtr)->AcpiApicCommon.Type;
- LocalApicPtr =3D (EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE *)(&((AC=
PI_APIC_STRUCTURE_PTR *)ApicPtr)->AcpiLocalApic);
- LocalX2ApicPtr =3D (EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE *)(&=
((ACPI_APIC_STRUCTURE_PTR *)ApicPtr)->AcpiLocalx2Apic);
+ LocalApicPtr =3D (EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE *)(&((AC=
PI_APIC_STRUCTURE_PTR *)ApicPtr)->AcpiLocalApic);
+ LocalX2ApicPtr =3D (EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE *)(&=
((ACPI_APIC_STRUCTURE_PTR *)ApicPtr)->AcpiLocalx2Apic);
=20
- if(Type =3D=3D EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC) {
+ if(Type =3D=3D EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC) {
if(!mX2ApicEnabled) {
- LocalApicPtr->Flags =3D (UINT8)mCpuApicIdOrderTable[Loca=
lApicCounter].Flags;
- LocalApicPtr->ApicId =3D (UINT8)mCpuApicIdOrderTable[Loca=
lApicCounter].ApicId;
- LocalApicPtr->AcpiProcessorId =3D (UINT8)mCpuApicIdOrderTable[Loca=
lApicCounter].AcpiProcessorId;
+ LocalApicPtr->Flags =3D (UINT8)mCpuApicIdOrderTable[Loc=
alApicCounter].Flags;
+ LocalApicPtr->ApicId =3D (UINT8)mCpuApicIdOrderTable[Loc=
alApicCounter].ApicId;
+ LocalApicPtr->AcpiProcessorUid =3D (UINT8)mCpuApicIdOrderTable[Loc=
alApicCounter].AcpiProcessorUid;
} else {
- LocalApicPtr->Flags =3D 0;
- LocalApicPtr->ApicId =3D 0xFF;
- LocalApicPtr->AcpiProcessorId =3D (UINT8)0xFF;
+ LocalApicPtr->Flags =3D 0;
+ LocalApicPtr->ApicId =3D 0xFF;
+ LocalApicPtr->AcpiProcessorUid =3D (UINT8)0xFF;
Status =3D EFI_UNSUPPORTED;
}
- } else if(Type =3D=3D EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC) {
+ } else if(Type =3D=3D EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC) {
if(mX2ApicEnabled) {
LocalX2ApicPtr->Flags =3D (UINT8)mCpuApicIdOrderTable[L=
ocalApicCounter].Flags;
LocalX2ApicPtr->X2ApicId =3D mCpuApicIdOrderTable[LocalApi=
cCounter].ApicId;
- LocalX2ApicPtr->AcpiProcessorUid =3D mCpuApicIdOrderTable[LocalApi=
cCounter].AcpiProcessorId;
+ LocalX2ApicPtr->AcpiProcessorUid =3D mCpuApicIdOrderTable[LocalApi=
cCounter].AcpiProcessorUid;
} else {
LocalX2ApicPtr->Flags =3D 0;
LocalX2ApicPtr->X2ApicId =3D (UINT32)-1;
@@ -311,8 +312,8 @@ SortCpuLocalApicInTable (
CpuIdMapPtr->ApicId =3D (UINT32)ProcessorInfoBuffer.ProcessorId=
;
CpuIdMapPtr->Flags =3D ((ProcessorInfoBuffer.StatusFlag & PROC=
ESSOR_ENABLED_BIT) !=3D 0);
CpuIdMapPtr->SocketNum =3D (UINT32)ProcessorInfoBuffer.Location.=
Package;
- CpuIdMapPtr->AcpiProcessorId =3D (CpuIdMapPtr->SocketNum * Fixed=
PcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuThreadCount)) + Get=
IndexFromApicId(CpuIdMapPtr->ApicId); //CpuIdMapPtr->ApicId;
- CpuIdMapPtr->SwProcApicId =3D ((UINT32)(ProcessorInfoBuffer.Loca=
tion.Package << mNumOfBitShift) + (((UINT32)ProcessorInfoBuffer.Processor=
Id) & CoreThreadMask));
+ CpuIdMapPtr->AcpiProcessorUid =3D (CpuIdMapPtr->SocketNum * Fixe=
dPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuThreadCount)) + Ge=
tIndexFromApicId(CpuIdMapPtr->ApicId); //CpuIdMapPtr->ApicId;
+ CpuIdMapPtr->SwProcApicId =3D ((UINT32)(ProcessorInfoBuffer.=
Location.Package << mNumOfBitShift) + (((UINT32)ProcessorInfoBuffer.Proce=
ssorId) & CoreThreadMask));
if(mX2ApicEnabled) { //if X2Apic, re-order the socket # so it st=
arts from base 0 and contiguous
//may not necessory!!!!!
}
@@ -321,18 +322,18 @@ SortCpuLocalApicInTable (
if (CpuIdMapPtr->Flags =3D=3D 1) {
=20
if(mForceX2ApicId) {
- CpuIdMapPtr->SocketNum &=3D 0x7;
- CpuIdMapPtr->AcpiProcessorId &=3D 0xFF; //keep lower 8bit du=
e to use Proc obj in dsdt
- CpuIdMapPtr->SwProcApicId &=3D 0xFF;
+ CpuIdMapPtr->SocketNum &=3D 0x7;
+ CpuIdMapPtr->AcpiProcessorUid &=3D 0xFF; //keep lower 8bit d=
ue to use Proc obj in dsdt
+ CpuIdMapPtr->SwProcApicId &=3D 0xFF;
}
}
} else { //not enabled
- CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[In=
dex];
- CpuIdMapPtr->ApicId =3D (UINT32)-1;
- CpuIdMapPtr->Flags =3D 0;
- CpuIdMapPtr->AcpiProcessorId =3D (UINT32)-1;
- CpuIdMapPtr->SwProcApicId =3D (UINT32)-1;
- CpuIdMapPtr->SocketNum =3D (UINT32)-1;
+ CpuIdMapPtr =3D (EFI_CPU_ID_ORDER_MAP *)&mCpuA=
picIdOrderTable[Index];
+ CpuIdMapPtr->ApicId =3D (UINT32)-1;
+ CpuIdMapPtr->Flags =3D 0;
+ CpuIdMapPtr->AcpiProcessorUid =3D (UINT32)-1;
+ CpuIdMapPtr->SwProcApicId =3D (UINT32)-1;
+ CpuIdMapPtr->SocketNum =3D (UINT32)-1;
} //end if PROC ENABLE
} //end for CurrentProcessor
=20
@@ -366,9 +367,9 @@ SortCpuLocalApicInTable (
mCpuApicIdOrderTable[Index].SwProcApicId =3D mCpuApicIdOrderTable[=
0].SwProcApicId;
mCpuApicIdOrderTable[0].SwProcApicId =3D TempVal;
//swap AcpiProcId
- TempVal =3D mCpuApicIdOrderTable[Index].AcpiProcessorId;
- mCpuApicIdOrderTable[Index].AcpiProcessorId =3D mCpuApicIdOrderTab=
le[0].AcpiProcessorId;
- mCpuApicIdOrderTable[0].AcpiProcessorId =3D TempVal;
+ TempVal =3D mCpuApicIdOrderTable[Index].AcpiProcessorUid;
+ mCpuApicIdOrderTable[Index].AcpiProcessorUid =3D mCpuApicIdOrderTa=
ble[0].AcpiProcessorUid;
+ mCpuApicIdOrderTable[0].AcpiProcessorUid =3D TempVal;
=20
}
=20
@@ -377,23 +378,23 @@ SortCpuLocalApicInTable (
=20
if(mCpuApicIdOrderTable[CurrProcessor].Flags =3D=3D 0) {
//make sure disabled entry has ProcId set to FFs
- mCpuApicIdOrderTable[CurrProcessor].ApicId =3D (UINT32)-1;
- mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId =3D (UINT32)=
-1;
- mCpuApicIdOrderTable[CurrProcessor].SwProcApicId =3D (UINT32)-1;
+ mCpuApicIdOrderTable[CurrProcessor].ApicId =3D (UINT32=
)-1;
+ mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorUid =3D (UINT32=
)-1;
+ mCpuApicIdOrderTable[CurrProcessor].SwProcApicId =3D (UINT32=
)-1;
=20
for(Index =3D CurrProcessor+1; Index < MAX_CPU_NUM; Index++) {
if(mCpuApicIdOrderTable[Index].Flags =3D=3D 1) {
//move enabled entry up
- mCpuApicIdOrderTable[CurrProcessor].Flags =3D 1;
- mCpuApicIdOrderTable[CurrProcessor].ApicId =3D mCpuApicIdOrd=
erTable[Index].ApicId;
- mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId =3D mCpu=
ApicIdOrderTable[Index].AcpiProcessorId;
- mCpuApicIdOrderTable[CurrProcessor].SwProcApicId =3D mCpuApi=
cIdOrderTable[Index].SwProcApicId;
- mCpuApicIdOrderTable[CurrProcessor].SocketNum =3D mCpuApicId=
OrderTable[Index].SocketNum;
+ mCpuApicIdOrderTable[CurrProcessor].Flags =3D 1;
+ mCpuApicIdOrderTable[CurrProcessor].ApicId =3D mCp=
uApicIdOrderTable[Index].ApicId;
+ mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorUid =3D mCp=
uApicIdOrderTable[Index].AcpiProcessorUid;
+ mCpuApicIdOrderTable[CurrProcessor].SwProcApicId =3D mCp=
uApicIdOrderTable[Index].SwProcApicId;
+ mCpuApicIdOrderTable[CurrProcessor].SocketNum =3D mCp=
uApicIdOrderTable[Index].SocketNum;
//disable moved entry
- mCpuApicIdOrderTable[Index].Flags =3D 0;
- mCpuApicIdOrderTable[Index].ApicId =3D (UINT32)-1;
- mCpuApicIdOrderTable[Index].AcpiProcessorId =3D (UINT32)-1;
- mCpuApicIdOrderTable[Index].SwProcApicId =3D (UINT32)-1;
+ mCpuApicIdOrderTable[Index].Flags =3D 0;
+ mCpuApicIdOrderTable[Index].ApicId =3D (UINT32)-1;
+ mCpuApicIdOrderTable[Index].AcpiProcessorUid =3D (UINT32)-1;
+ mCpuApicIdOrderTable[Index].SwProcApicId =3D (UINT32)-1;
break;
}
}
@@ -422,17 +423,17 @@ typedef struct {
} STRUCTURE_HEADER;
=20
STRUCTURE_HEADER mMadtStructureTable[] =3D {
- {EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC, sizeof (EFI_ACPI_4_0_PROC=
ESSOR_LOCAL_APIC_STRUCTURE)},
- {EFI_ACPI_4_0_IO_APIC, sizeof (EFI_ACPI_4_0_IO_A=
PIC_STRUCTURE)},
- {EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE, sizeof (EFI_ACPI_4_0_INTE=
RRUPT_SOURCE_OVERRIDE_STRUCTURE)},
- {EFI_ACPI_4_0_NON_MASKABLE_INTERRUPT_SOURCE, sizeof (EFI_ACPI_4_0_NON_=
MASKABLE_INTERRUPT_SOURCE_STRUCTURE)},
- {EFI_ACPI_4_0_LOCAL_APIC_NMI, sizeof (EFI_ACPI_4_0_LOCA=
L_APIC_NMI_STRUCTURE)},
- {EFI_ACPI_4_0_LOCAL_APIC_ADDRESS_OVERRIDE, sizeof (EFI_ACPI_4_0_LOCA=
L_APIC_ADDRESS_OVERRIDE_STRUCTURE)},
- {EFI_ACPI_4_0_IO_SAPIC, sizeof (EFI_ACPI_4_0_IO_S=
APIC_STRUCTURE)},
- {EFI_ACPI_4_0_LOCAL_SAPIC, sizeof (EFI_ACPI_4_0_PROC=
ESSOR_LOCAL_SAPIC_STRUCTURE)},
- {EFI_ACPI_4_0_PLATFORM_INTERRUPT_SOURCES, sizeof (EFI_ACPI_4_0_PLAT=
FORM_INTERRUPT_SOURCES_STRUCTURE)},
- {EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC, sizeof (EFI_ACPI_4_0_PROC=
ESSOR_LOCAL_X2APIC_STRUCTURE)},
- {EFI_ACPI_4_0_LOCAL_X2APIC_NMI, sizeof (EFI_ACPI_4_0_LOCA=
L_X2APIC_NMI_STRUCTURE)}
+ {EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC, sizeof (EFI_ACPI_6_3_PROC=
ESSOR_LOCAL_APIC_STRUCTURE)},
+ {EFI_ACPI_6_3_IO_APIC, sizeof (EFI_ACPI_6_3_IO_A=
PIC_STRUCTURE)},
+ {EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE, sizeof (EFI_ACPI_6_3_INTE=
RRUPT_SOURCE_OVERRIDE_STRUCTURE)},
+ {EFI_ACPI_6_3_NON_MASKABLE_INTERRUPT_SOURCE, sizeof (EFI_ACPI_6_3_NON_=
MASKABLE_INTERRUPT_SOURCE_STRUCTURE)},
+ {EFI_ACPI_6_3_LOCAL_APIC_NMI, sizeof (EFI_ACPI_6_3_LOCA=
L_APIC_NMI_STRUCTURE)},
+ {EFI_ACPI_6_3_LOCAL_APIC_ADDRESS_OVERRIDE, sizeof (EFI_ACPI_6_3_LOCA=
L_APIC_ADDRESS_OVERRIDE_STRUCTURE)},
+ {EFI_ACPI_6_3_IO_SAPIC, sizeof (EFI_ACPI_6_3_IO_S=
APIC_STRUCTURE)},
+ {EFI_ACPI_6_3_LOCAL_SAPIC, sizeof (EFI_ACPI_6_3_PROC=
ESSOR_LOCAL_SAPIC_STRUCTURE)},
+ {EFI_ACPI_6_3_PLATFORM_INTERRUPT_SOURCES, sizeof (EFI_ACPI_6_3_PLAT=
FORM_INTERRUPT_SOURCES_STRUCTURE)},
+ {EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC, sizeof (EFI_ACPI_6_3_PROC=
ESSOR_LOCAL_X2APIC_STRUCTURE)},
+ {EFI_ACPI_6_3_LOCAL_X2APIC_NMI, sizeof (EFI_ACPI_6_3_LOCA=
L_X2APIC_NMI_STRUCTURE)}
};
=20
/**
@@ -591,7 +592,7 @@ InitializeHeader (
**/
EFI_STATUS
InitializeMadtHeader (
- IN OUT EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *MadtHeader
+ IN OUT EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *MadtHeader
)
{
EFI_STATUS Status;
@@ -603,8 +604,8 @@ InitializeMadtHeader (
=20
Status =3D InitializeHeader (
&MadtHeader->Header,
- EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
0
);
if (EFI_ERROR (Status)) {
@@ -612,7 +613,7 @@ InitializeMadtHeader (
}
=20
MadtHeader->LocalApicAddress =3D PcdGet32(PcdLocalApicAddress);
- MadtHeader->Flags =3D EFI_ACPI_4_0_PCAT_COMPAT;
+ MadtHeader->Flags =3D EFI_ACPI_6_3_PCAT_COMPAT;
=20
return EFI_SUCCESS;
}
@@ -649,7 +650,7 @@ CopyStructure (
//
// Initialize the number of table entries and the table based on the t=
able header passed in.
//
- if (Header->Signature =3D=3D EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TA=
BLE_SIGNATURE) {
+ if (Header->Signature =3D=3D EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TA=
BLE_SIGNATURE) {
TableNumEntries =3D sizeof (mMadtStructureTable) / sizeof (STRUCTURE=
_HEADER);
StructureTable =3D mMadtStructureTable;
} else {
@@ -759,7 +760,7 @@ BuildAcpiTable (
return EFI_INVALID_PARAMETER;
}
=20
- if (AcpiHeader->Signature !=3D EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_=
TABLE_SIGNATURE) {
+ if (AcpiHeader->Signature !=3D EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_=
TABLE_SIGNATURE) {
DEBUG ((
DEBUG_ERROR,
"MADT header signature is expected, actually 0x%08x\n",
@@ -850,15 +851,15 @@ InstallMadtFromScratch (
{
EFI_STATUS Status;
UINTN Index;
- EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *NewMadtTable;
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER *NewMadtTable;
UINTN TableHandle;
- EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER MadtTableHeader;
- EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC_STRUCTURE ProcLocalApicStruc=
t;
- EFI_ACPI_4_0_IO_APIC_STRUCTURE IoApicStruct;
- EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE IntSrcOverrideStru=
ct;
- EFI_ACPI_4_0_LOCAL_APIC_NMI_STRUCTURE LocalApciNmiStruct=
;
- EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC_STRUCTURE ProcLocalX2ApicStr=
uct;
- EFI_ACPI_4_0_LOCAL_X2APIC_NMI_STRUCTURE LocalX2ApicNmiStru=
ct;
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER MadtTableHeader;
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC_STRUCTURE ProcLocalApicStruc=
t;
+ EFI_ACPI_6_3_IO_APIC_STRUCTURE IoApicStruct;
+ EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE IntSrcOverrideStru=
ct;
+ EFI_ACPI_6_3_LOCAL_APIC_NMI_STRUCTURE LocalApciNmiStruct=
;
+ EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC_STRUCTURE ProcLocalX2ApicStr=
uct;
+ EFI_ACPI_6_3_LOCAL_X2APIC_NMI_STRUCTURE LocalX2ApicNmiStru=
ct;
STRUCTURE_HEADER **MadtStructs;
UINTN MaxMadtStructCount=
;
UINTN MadtStructsIndex;
@@ -915,11 +916,11 @@ InstallMadtFromScratch (
//
// Build Processor Local APIC Structures and Processor Local X2APIC St=
ructures
//
- ProcLocalApicStruct.Type =3D EFI_ACPI_4_0_PROCESSOR_LOCAL_APIC;
- ProcLocalApicStruct.Length =3D sizeof (EFI_ACPI_4_0_PROCESSOR_LOCAL_AP=
IC_STRUCTURE);
+ ProcLocalApicStruct.Type =3D EFI_ACPI_6_3_PROCESSOR_LOCAL_APIC;
+ ProcLocalApicStruct.Length =3D sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_AP=
IC_STRUCTURE);
=20
- ProcLocalX2ApicStruct.Type =3D EFI_ACPI_4_0_PROCESSOR_LOCAL_X2APIC;
- ProcLocalX2ApicStruct.Length =3D sizeof (EFI_ACPI_4_0_PROCESSOR_LOCAL_=
X2APIC_STRUCTURE);
+ ProcLocalX2ApicStruct.Type =3D EFI_ACPI_6_3_PROCESSOR_LOCAL_X2APIC;
+ ProcLocalX2ApicStruct.Length =3D sizeof (EFI_ACPI_6_3_PROCESSOR_LOCAL_=
X2APIC_STRUCTURE);
ProcLocalX2ApicStruct.Reserved[0] =3D 0;
ProcLocalX2ApicStruct.Reserved[1] =3D 0;
=20
@@ -930,9 +931,9 @@ InstallMadtFromScratch (
// use a processor local x2APIC structure.
//
if (!mX2ApicEnabled && mCpuApicIdOrderTable[Index].ApicId < MAX_UINT=
8) {
- ProcLocalApicStruct.Flags =3D (UINT8) mCpuApicIdOrderTab=
le[Index].Flags;
- ProcLocalApicStruct.ApicId =3D (UINT8) mCpuApicIdOrderTab=
le[Index].ApicId;
- ProcLocalApicStruct.AcpiProcessorId =3D (UINT8) mCpuApicIdOrderTab=
le[Index].AcpiProcessorId;
+ ProcLocalApicStruct.Flags =3D (UINT8) mCpuApicIdOrderTa=
ble[Index].Flags;
+ ProcLocalApicStruct.ApicId =3D (UINT8) mCpuApicIdOrderTa=
ble[Index].ApicId;
+ ProcLocalApicStruct.AcpiProcessorUid =3D (UINT8) mCpuApicIdOrderTa=
ble[Index].AcpiProcessorUid;
=20
ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status =3D CopyStructure (
@@ -943,7 +944,7 @@ InstallMadtFromScratch (
} else if (mCpuApicIdOrderTable[Index].ApicId !=3D 0xFFFFFFFF) {
ProcLocalX2ApicStruct.Flags =3D (UINT8) mCpuApicIdOrder=
Table[Index].Flags;
ProcLocalX2ApicStruct.X2ApicId =3D mCpuApicIdOrderTable[In=
dex].ApicId;
- ProcLocalX2ApicStruct.AcpiProcessorUid =3D mCpuApicIdOrderTable[In=
dex].AcpiProcessorId;
+ ProcLocalX2ApicStruct.AcpiProcessorUid =3D mCpuApicIdOrderTable[In=
dex].AcpiProcessorUid;
=20
ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status =3D CopyStructure (
@@ -961,8 +962,8 @@ InstallMadtFromScratch (
//
// Build I/O APIC Structures
//
- IoApicStruct.Type =3D EFI_ACPI_4_0_IO_APIC;
- IoApicStruct.Length =3D sizeof (EFI_ACPI_4_0_IO_APIC_STRUCTURE);
+ IoApicStruct.Type =3D EFI_ACPI_6_3_IO_APIC;
+ IoApicStruct.Length =3D sizeof (EFI_ACPI_6_3_IO_APIC_STRUCTURE);
IoApicStruct.Reserved =3D 0;
=20
PcIoApicEnable =3D PcdGet32(PcdPcIoApicEnable);
@@ -1008,8 +1009,8 @@ InstallMadtFromScratch (
//
// Build Interrupt Source Override Structures
//
- IntSrcOverrideStruct.Type =3D EFI_ACPI_4_0_INTERRUPT_SOURCE_OVERRIDE;
- IntSrcOverrideStruct.Length =3D sizeof (EFI_ACPI_4_0_INTERRUPT_SOURCE_=
OVERRIDE_STRUCTURE);
+ IntSrcOverrideStruct.Type =3D EFI_ACPI_6_3_INTERRUPT_SOURCE_OVERRIDE;
+ IntSrcOverrideStruct.Length =3D sizeof (EFI_ACPI_6_3_INTERRUPT_SOURCE_=
OVERRIDE_STRUCTURE);
=20
//
// IRQ0=3D>IRQ2 Interrupt Source Override Structure
@@ -1052,11 +1053,11 @@ InstallMadtFromScratch (
//
// Build Local APIC NMI Structures
//
- LocalApciNmiStruct.Type =3D EFI_ACPI_4_0_LOCAL_APIC_NMI;
- LocalApciNmiStruct.Length =3D sizeof (EFI_ACPI_4_0_LOCAL_APIC_NMI_STRU=
CTURE);
- LocalApciNmiStruct.AcpiProcessorId =3D 0xFF; // Applies to all pr=
ocessors
- LocalApciNmiStruct.Flags =3D 0x0005; // Flags - Edge-tigg=
ered, Active High
- LocalApciNmiStruct.LocalApicLint =3D 0x1;
+ LocalApciNmiStruct.Type =3D EFI_ACPI_6_3_LOCAL_APIC_NMI;
+ LocalApciNmiStruct.Length =3D sizeof (EFI_ACPI_6_3_LOCAL_APIC_NMI_STRU=
CTURE);
+ LocalApciNmiStruct.AcpiProcessorUid =3D 0xFF; // Applies to all p=
rocessors
+ LocalApciNmiStruct.Flags =3D 0x0005; // Flags - Edge-tig=
gered, Active High
+ LocalApciNmiStruct.LocalApicLint =3D 0x1;
=20
ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status =3D CopyStructure (
@@ -1073,8 +1074,8 @@ InstallMadtFromScratch (
// Build Local x2APIC NMI Structure
//
if (mX2ApicEnabled) {
- LocalX2ApicNmiStruct.Type =3D EFI_ACPI_4_0_LOCAL_X2APIC_NMI;
- LocalX2ApicNmiStruct.Length =3D sizeof (EFI_ACPI_4_0_LOCAL_X2APIC_NM=
I_STRUCTURE);
+ LocalX2ApicNmiStruct.Type =3D EFI_ACPI_6_3_LOCAL_X2APIC_NMI;
+ LocalX2ApicNmiStruct.Length =3D sizeof (EFI_ACPI_6_3_LOCAL_X2APIC_NM=
I_STRUCTURE);
LocalX2ApicNmiStruct.Flags =3D 0x000D; // Flags - Le=
vel-tiggered, Active High
LocalX2ApicNmiStruct.AcpiProcessorUid =3D 0xFFFFFFFF; // Applies to=
all processors
LocalX2ApicNmiStruct.LocalX2ApicLint =3D 0x01;
@@ -1099,7 +1100,7 @@ InstallMadtFromScratch (
//
Status =3D BuildAcpiTable (
(EFI_ACPI_DESCRIPTION_HEADER *) &MadtTableHeader,
- sizeof (EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER),
+ sizeof (EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER),
MadtStructs,
MadtStructsIndex,
(UINT8 **)&NewMadtTable
@@ -1222,7 +1223,7 @@ PlatformUpdateTables (
EFI_ACPI_DESCRIPTION_HEADER *TableHeader;
UINT8 *TempOemId;
UINT64 TempOemTableId;
- EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader;
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *FadtHeader;
EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER *HpetTable;
UINT32 HpetBaseAddress;
EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_BLOCK_ID HpetBlockId;
@@ -1279,12 +1280,12 @@ PlatformUpdateTables (
//
switch (Table->Signature) {
=20
- case EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE:
+ case EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE:
ASSERT(FALSE);
break;
=20
- case EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:
- FadtHeader =3D (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE *) Tabl=
e;
+ case EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:
+ FadtHeader =3D (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *) Table;
=20
FadtHeader->PreferredPmProfile =3D PcdGet8 (PcdFadtPreferredPmProfil=
e);
FadtHeader->IaPcBootArch =3D PcdGet16 (PcdFadtIaPcBootArch);
@@ -1329,7 +1330,7 @@ PlatformUpdateTables (
DEBUG(( EFI_D_ERROR, " Flags 0x%x\n", FadtHeader->Flags ));
break;
=20
- case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:
+ case EFI_ACPI_6_3_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:
HpetTable =3D (EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER *)Ta=
ble;
HpetBaseAddress =3D PcdGet32 (PcdHpetBaseAddress);
HpetTable->BaseAddressLower32Bit.Address =3D HpetBaseAddress;
@@ -1381,8 +1382,8 @@ IsHardwareChange (
UINTN HWChangeSize;
UINT32 PciId;
UINTN Handle;
- EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *FacsPtr;
- EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *pFADT;
+ EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE *FacsPtr;
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE *pFADT;
=20
HandleCount =3D 0;
HandleBuffer =3D NULL;
@@ -1428,7 +1429,7 @@ IsHardwareChange (
//
Handle =3D 0;
Status =3D LocateAcpiTableBySignature (
- EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
(EFI_ACPI_DESCRIPTION_HEADER **) &pFADT,
&Handle
);
@@ -1450,7 +1451,7 @@ IsHardwareChange (
//
// Set HardwareSignature value based on CRC value.
//
- FacsPtr =3D (EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)(UINTN)pFA=
DT->FirmwareCtrl;
+ FacsPtr =3D (EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE *)(UINTN)pFA=
DT->FirmwareCtrl;
FacsPtr->HardwareSignature =3D CRC;
FreePool( HWChange );
}
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Facs/Facs.c b/=
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Facs/Facs.c
index cde6e478c6b9..8700c44e633d 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Facs/Facs.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Facs/Facs.c
@@ -1,9 +1,10 @@
/** @file
- This file contains a structure definition for the ACPI 5.0 Firmware AC=
PI
+ This file contains a structure definition for the ACPI 6.3 Firmware AC=
PI
Control Structure (FACS). The contents of this file should only be mo=
dified
for bug fixes, no porting is required.
=20
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
=20
**/
@@ -35,9 +36,9 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Please modify all values in Facs.h only.
//
=20
-EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs =3D {
- EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,
- sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),
+EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs =3D {
+ EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,
+ sizeof (EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE),
=20
//
// Hardware Signature will be updated at runtime
@@ -48,7 +49,7 @@ EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs =3D {
EFI_ACPI_GLOBAL_LOCK,
EFI_ACPI_FIRMWARE_CONTROL_STRUCTURE_FLAGS,
EFI_ACPI_X_FIRMWARE_WAKING_VECTOR,
- EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,
+ EFI_ACPI_6_3_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,
{
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_RESERVED_BYTE,
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c b/=
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c
index 6efb38cda40d..38e767856de7 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.c
@@ -1,9 +1,10 @@
/** @file
- This file contains a structure definition for the ACPI 5.0 Fixed ACPI
+ This file contains a structure definition for the ACPI 6.3 Fixed ACPI
Description Table (FADT). The contents of this file should only be mo=
dified
for bug fixes, no porting is required.
=20
Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
=20
**/
@@ -47,6 +48,12 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
=20
#define EFI_ACPI_IAPC_BOOT_ARCH 0 // To be fixed
=20
+//
+// ARM Boot Architecture Flags
+//
+
+#define EFI_ACPI_ARM_BOOT_ARCH 0 // To be fixed
+
//
// Fixed Feature Flags
//
@@ -55,7 +62,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// PM1A Event Register Block Generic Address Information
//
-#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH 0x20
#define EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET 0x00
#define EFI_ACPI_PM1A_EVT_BLK_ADDRESS 0 // To be fixed
@@ -63,7 +70,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// PM1B Event Register Block Generic Address Information
//
-#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH 0x00
#define EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET 0x00
#define EFI_ACPI_PM1B_EVT_BLK_ADDRESS 0 // To be fixed
@@ -71,7 +78,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// PM1A Control Register Block Generic Address Information
//
-#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH 0x10
#define EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET 0x00
#define EFI_ACPI_PM1A_CNT_BLK_ADDRESS 0 // To be fixed
@@ -79,7 +86,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// PM1B Control Register Block Generic Address Information
//
-#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH 0x00
#define EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET 0x00
#define EFI_ACPI_PM1B_CNT_BLK_ADDRESS 0 // To be fixed
@@ -87,7 +94,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//
// PM2 Control Register Block Generic Address Information
//
-#define EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH 0x08
#define EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET 0x00
#define EFI_ACPI_PM2_CNT_BLK_ADDRESS 0 // To be fixed
@@ -96,7 +103,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Power Management Timer Control Register Block Generic Address
// Information
//
-#define EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_PM_TMR_BLK_BIT_WIDTH 0x20
#define EFI_ACPI_PM_TMR_BLK_BIT_OFFSET 0x00
#define EFI_ACPI_PM_TMR_BLK_ADDRESS 0 // To be fixed
@@ -105,7 +112,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// General Purpose Event 0 Register Block Generic Address
// Information
//
-#define EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_GPE0_BLK_BIT_WIDTH 0 // size of R_PCH_ACPI_GPE=
0_STS_127_96 + R_PCH_ACPI_GPE0_EN_127_96
#define EFI_ACPI_GPE0_BLK_BIT_OFFSET 0x00
#define EFI_ACPI_GPE0_BLK_ADDRESS 0 // To be fixed
@@ -114,14 +121,14 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// General Purpose Event 1 Register Block Generic Address
// Information
//
-#define EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_GPE1_BLK_BIT_WIDTH 0x0
#define EFI_ACPI_GPE1_BLK_BIT_OFFSET 0x0
#define EFI_ACPI_GPE1_BLK_ADDRESS 0 // To be fixed
//
// Reset Register Generic Address Information
//
-#define EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID EFI_ACPI_2_0_SYSTEM_IO
+#define EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID EFI_ACPI_6_3_SYSTEM_IO
#define EFI_ACPI_RESET_REG_BIT_WIDTH 0x08
#define EFI_ACPI_RESET_REG_BIT_OFFSET 0x00
#define EFI_ACPI_RESET_REG_ADDRESS 0x00000CF9
@@ -162,11 +169,11 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
// Please modify all values in Fadt.h only.
//
=20
-EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
+EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
{
- EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
- sizeof (EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE),
- EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ sizeof (EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE),
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
=20
//
// Checksum will be updated at runtime
@@ -187,9 +194,9 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
//
// These addresses will be updated at runtime
//
- 0x00000000,=20
0x00000000,
- =20
+ 0x00000000,
+
EFI_ACPI_RESERVED_BYTE,
EFI_ACPI_PREFERRED_PM_PROFILE,
EFI_ACPI_SCI_INT,
@@ -198,7 +205,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_ACPI_DISABLE,
EFI_ACPI_S4_BIOS_REQ,
EFI_ACPI_PSTATE_CNT,
- =20
+
EFI_ACPI_PM1A_EVT_BLK_ADDRESS,
EFI_ACPI_PM1B_EVT_BLK_ADDRESS,
EFI_ACPI_PM1A_CNT_BLK_ADDRESS,
@@ -240,15 +247,13 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D =
{
EFI_ACPI_RESET_REG_ADDRESS_SPACE_ID,
EFI_ACPI_RESET_REG_BIT_WIDTH,
EFI_ACPI_RESET_REG_BIT_OFFSET,
- EFI_ACPI_5_0_BYTE,
+ EFI_ACPI_6_3_BYTE,
EFI_ACPI_RESET_REG_ADDRESS
},
EFI_ACPI_RESET_VALUE,
- {
- EFI_ACPI_RESERVED_BYTE,
- EFI_ACPI_RESERVED_BYTE,
- EFI_ACPI_RESERVED_BYTE
- },
+
+ EFI_ACPI_ARM_BOOT_ARCH,
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,
=20
//
// These addresses will be updated at runtime
@@ -263,7 +268,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_PM1A_EVT_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_PM1A_EVT_BLK_BIT_WIDTH,
EFI_ACPI_PM1A_EVT_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_WORD,
+ EFI_ACPI_6_3_WORD,
EFI_ACPI_PM1A_EVT_BLK_ADDRESS
},
{
@@ -273,7 +278,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_PM1B_EVT_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_PM1B_EVT_BLK_BIT_WIDTH,
EFI_ACPI_PM1B_EVT_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_WORD,
+ EFI_ACPI_6_3_WORD,
EFI_ACPI_PM1B_EVT_BLK_ADDRESS
},
{
@@ -283,7 +288,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_PM1A_CNT_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_PM1A_CNT_BLK_BIT_WIDTH,
EFI_ACPI_PM1A_CNT_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_WORD,
+ EFI_ACPI_6_3_WORD,
EFI_ACPI_PM1A_CNT_BLK_ADDRESS
},
{
@@ -293,7 +298,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_PM1B_CNT_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_PM1B_CNT_BLK_BIT_WIDTH,
EFI_ACPI_PM1B_CNT_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_WORD,
+ EFI_ACPI_6_3_WORD,
EFI_ACPI_PM1B_CNT_BLK_ADDRESS
},
{
@@ -303,7 +308,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_PM2_CNT_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_PM2_CNT_BLK_BIT_WIDTH,
EFI_ACPI_PM2_CNT_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_BYTE,
+ EFI_ACPI_6_3_BYTE,
EFI_ACPI_PM2_CNT_BLK_ADDRESS
},
{
@@ -313,7 +318,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_PM_TMR_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_PM_TMR_BLK_BIT_WIDTH,
EFI_ACPI_PM_TMR_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_DWORD,
+ EFI_ACPI_6_3_DWORD,
EFI_ACPI_PM_TMR_BLK_ADDRESS
},
{
@@ -323,7 +328,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_GPE0_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_GPE0_BLK_BIT_WIDTH,
EFI_ACPI_GPE0_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_BYTE,
+ EFI_ACPI_6_3_BYTE,
EFI_ACPI_GPE0_BLK_ADDRESS
},
{
@@ -333,7 +338,7 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
EFI_ACPI_GPE1_BLK_ADDRESS_SPACE_ID,
EFI_ACPI_GPE1_BLK_BIT_WIDTH,
EFI_ACPI_GPE1_BLK_BIT_OFFSET,
- EFI_ACPI_5_0_BYTE,
+ EFI_ACPI_6_3_BYTE,
EFI_ACPI_GPE1_BLK_ADDRESS
},
{
@@ -355,5 +360,10 @@ EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE Fadt =3D {
0,
0,
0
- }
+ },
+
+ //
+ // Hypervisor Vendor Identity
+ //
+ 0x0000000000000000,
};
--=20
2.28.0.windows.1


Re: [PATCH 1/4] UefiPayloadPkg: Add Fixed PCDs and use Macro to define the default value.

Guo Dong
 

Reviewed-by: Guo Dong <guo.dong@intel.com>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Zhiguang Liu
Sent: Thursday, August 5, 2021 9:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>
Subject: [edk2-devel] [PATCH 1/4] UefiPayloadPkg: Add Fixed PCDs and use Macro to define the default value.

Add the three PCDs as fixed at build PCD:
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule
gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister
gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister
The default value is defined as Macro, so it can be passed in at build command.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index bcedf1c746..ba54f2057f 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -91,6 +91,13 @@
DEFINE EMU_VARIABLE_ENABLE = TRUE DEFINE DISABLE_RESET_SYSTEM = FALSE + # Dfine the maximum size of the capsule image without a reset flag that the platform can support.+ DEFINE MAX_SIZE_NON_POPULATE_CAPSULE = 0xa00000++ # Define RTC related register.+ DEFINE RTC_INDEX_REGISTER = 0x70+ DEFINE RTC_TARGET_REGISTER = 0x71+ [BuildOptions] *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES GCC:*_UNIXGCC_*_CC_FLAGS = -DMDEPKG_NDEBUG@@ -324,7 +331,9 @@
!else gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F !endif-+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|$(MAX_SIZE_NON_POPULATE_CAPSULE)+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|$(RTC_INDEX_REGISTER)+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|$(RTC_TARGET_REGISTER) # # The following parameters are set by Library/PlatformHookLib #--
2.32.0.windows.2



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Re: [PATCH 2/4] UefiPayloadPkg: define some PCD as DynamicEX PCD

Guo Dong
 

Reviewed-by: Guo Dong <guo.dong@intel.com>

-----Original Message-----
From: Liu, Zhiguang <zhiguang.liu@intel.com>
Sent: Thursday, August 5, 2021 9:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>
Subject: [PATCH 2/4] UefiPayloadPkg: define some PCD as DynamicEX PCD

Define some PCDs as DynamicEX PCD to be used as global variable.
Because PcdUartDefaultBaudRate is defined as DynamicEX, remove the code to set it in platformlib. That code was actually redundant.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c | 5 -----
UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf | 1 -
UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c | 4 ----
UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf | 1 -
UefiPayloadPkg/UefiPayloadPkg.dsc | 28 ++++++++++++++++++----------
5 files changed, 18 insertions(+), 21 deletions(-)

diff --git a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
index 72a17dc8a7..d8453e5957 100644
--- a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
+++ b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.c
@@ -75,11 +75,6 @@ PlatformHookSerialPortInitialize (
return Status; } - Status = PcdSet64S (PcdUartDefaultBaudRate, SerialPortInfo.Baud);- if (RETURN_ERROR (Status)) {- return Status;- }- Status = PcdSet32S (PcdSerialClockRate, SerialPortInfo.InputHertz); if (RETURN_ERROR (Status)) { return Status;diff --git a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
index 2415d99c64..3eeb94d8fa 100644
--- a/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
+++ b/UefiPayloadPkg/Library/PlatformHookLib/PlatformHookLib.inf
@@ -35,5 +35,4 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## PRODUCES gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## PRODUCES gEfiMdeModulePkgTokenSpaceGuid.PcdSerialClockRate ## PRODUCES- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCES gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters ## PRODUCESdiff --git a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c
index 6705f29505..bd433bdbe0 100644
--- a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.c
+++ b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHoo
+++ kLib.c
@@ -70,10 +70,6 @@ PlatformHookSerialPortInitialize (
if (RETURN_ERROR (Status)) { return Status; }- Status = PcdSet64S (PcdUartDefaultBaudRate, SerialPortInfo->BaudRate);- if (RETURN_ERROR (Status)) {- return Status;- } return RETURN_SUCCESS; }diff --git a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf
index 41e05ddf54..2dfd8b1216 100644
--- a/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHookLib.inf
+++ b/UefiPayloadPkg/Library/UniversalPayloadPlatformHookLib/PlatformHoo
+++ kLib.inf
@@ -38,4 +38,3 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase ## PRODUCES gEfiMdeModulePkgTokenSpaceGuid.PcdSerialBaudRate ## PRODUCES gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterStride ## PRODUCES- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate ## PRODUCESdiff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index ba54f2057f..d293211e46 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -308,11 +308,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvModeEnable|TRUE gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0-!if $(TARGET) == DEBUG- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE-!else- gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE-!endif gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|TRUE @@ -352,11 +347,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialFifoControl|$(SERIAL_FIFO_CONTROL) gEfiMdeModulePkgTokenSpaceGuid.PcdSerialExtendedTxFifoSize|$(SERIAL_EXTENDED_TX_FIFO_SIZE) - gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|$(UART_DEFAULT_STOP_BITS)- gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE) gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS) gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS)@@ -369,6 +359,24 @@
################################################################################ [PcdsDynamicExDefault]+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|$(UART_DEFAULT_BAUD_RATE)+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|$(UART_DEFAULT_DATA_BITS)+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|$(UART_DEFAULT_PARITY)+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|$(UART_DEFAULT_STOP_BITS)+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|$(DEFAULT_TERMINAL_TYPE)+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport+ gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize+!if $(TARGET) == DEBUG+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE+!else+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE+!endif gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved|0 gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|0--
2.32.0.windows.2


Re: [PATCH 3/4] UefiPayloadPkg: change the default value of some PCDs.

Guo Dong
 

Reviewed-by: Guo Dong <guo.dong@intel.com>

-----Original Message-----
From: Liu, Zhiguang <zhiguang.liu@intel.com>
Sent: Thursday, August 5, 2021 9:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>
Subject: [PATCH 3/4] UefiPayloadPkg: change the default value of some PCDs.

Change the default value of the below PCDs to diable some legacy feature.
gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE
gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index d293211e46..002d2a8fa7 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -297,6 +297,8 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE

## This PCD specified whether ACPI SDT protocol is installed.

gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE

+ gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE

+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE



[PcdsFixedAtBuild]

gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000

@@ -350,7 +352,7 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdPciSerialParameters|$(PCI_SERIAL_PARAMETERS)



gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|$(MAX_LOGICAL_PROCESSORS)

-

+ gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0



################################################################################

#

--
2.32.0.windows.2


Re: [PATCH 4/4] UefiPayloadPkg: Add a macro to enable or diable the serial driver.

Guo Dong
 

Reviewed-by: Guo Dong <guo.dong@intel.com>

-----Original Message-----
From: Liu, Zhiguang <zhiguang.liu@intel.com>
Sent: Thursday, August 5, 2021 9:31 PM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>
Subject: [PATCH 4/4] UefiPayloadPkg: Add a macro to enable or diable the serial driver.

This patch doesn't change the default behavior.

Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>

Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/UefiPayloadPkg.dsc | 4 ++++ UefiPayloadPkg/UefiPayloadPkg.fdf | 2 ++
2 files changed, 6 insertions(+)

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc
index 002d2a8fa7..b4a30be381 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dsc
+++ b/UefiPayloadPkg/UefiPayloadPkg.dsc
@@ -98,6 +98,8 @@
DEFINE RTC_INDEX_REGISTER = 0x70 DEFINE RTC_TARGET_REGISTER = 0x71 + DEFINE SERIAL_DRIVER_ENABLE = TRUE+ [BuildOptions] *_*_*_CC_FLAGS = -D DISABLE_NEW_DEPRECATED_INTERFACES GCC:*_UNIXGCC_*_CC_FLAGS = -DMDEPKG_NDEBUG@@ -536,7 +538,9 @@
# # ISA Support #+!if $(SERIAL_DRIVER_ENABLE) == TRUE MdeModulePkg/Universal/SerialDxe/SerialDxe.inf+!endif !if $(PS2_KEYBOARD_ENABLE) == TRUE OvmfPkg/SioBusDxe/SioBusDxe.inf MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.infdiff --git a/UefiPayloadPkg/UefiPayloadPkg.fdf b/UefiPayloadPkg/UefiPayloadPkg.fdf
index 041fed842c..b2cfb6b405 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.fdf
+++ b/UefiPayloadPkg/UefiPayloadPkg.fdf
@@ -136,7 +136,9 @@ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
# # ISA Support #+!if $(SERIAL_DRIVER_ENABLE) == TRUE INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf+!endif !if $(PS2_KEYBOARD_ENABLE) == TRUE INF OvmfPkg/SioBusDxe/SioBusDxe.inf INF MdeModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2KeyboardDxe.inf--
2.32.0.windows.2


Re: [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from bootloader

Guo Dong
 

Reviewed-by: Guo Dong <guo.dong@intel.com>

-----Original Message-----
From: Ni, Ray <ray.ni@intel.com>
Sent: Friday, August 6, 2021 1:16 AM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@intel.com>; Ma, Maurice <maurice.ma@intel.com>; You, Benjamin <benjamin.you@intel.com>
Subject: [PATCH] UefiPayloadPkg/PayloadEntry: Inherit 4/5-level paging from bootloader

The patch removes the dep on PcdUse5LevelPageTable.
Now the payload inherits the 5-level paging setting from bootloader in IA-32e mode and uses 4-level paging in legacy protected mode.

This fix the potential issue when bootloader enables 5-level paging but 64bit payload sets 4-level page table to CR3 resulting CPU exception because PcdUse5LevelPageTable is FALSE.

Signed-off-by: Ray Ni <ray.ni@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
---
.../UefiPayloadEntry/UefiPayloadEntry.inf | 1 -
.../UniversalPayloadEntry.inf | 1 -
.../UefiPayloadEntry/X64/VirtualMemory.c | 38 ++++++++-----------
3 files changed, 16 insertions(+), 24 deletions(-)

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
index 8d42925fcd..9b6fab66a1 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
@@ -80,7 +80,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONSUMES- gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ## SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ## CONSUMES diff --git a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
index 416a620598..aae62126e9 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UniversalPayloadEntry.inf
@@ -85,7 +85,6 @@
gEfiMdeModulePkgTokenSpaceGuid.PcdNullPointerDetectionPropertyMask ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdHeapGuardPropertyMask ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdCpuStackGuard ## CONSUMES- gEfiMdeModulePkgTokenSpaceGuid.PcdUse5LevelPageTable ## SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbBase ## CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdGhcbSize ## CONSUMES diff --git a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
index a1c4ad6ff4..9daa46c12c 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/X64/VirtualMemory.c
@@ -15,7 +15,7 @@
2) IA-32 Intel(R) Architecture Software Developer's Manual Volume 2:Instruction Set Reference, Intel 3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel -Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR> Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> SPDX-License-Identifier: BSD-2-Clause-Patent@@ -668,7 +668,6 @@ CreateIdentityMappingPageTables (
) { UINT32 RegEax;- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX EcxFlags; UINT32 RegEdx; UINT8 PhysicalAddressBits; EFI_PHYSICAL_ADDRESS PageAddress;@@ -687,7 +686,7 @@ CreateIdentityMappingPageTables (
UINTN TotalPagesNum; UINTN BigPageAddress; VOID *Hob;- BOOLEAN Page5LevelSupport;+ BOOLEAN Enable5LevelPaging; BOOLEAN Page1GSupport; PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; UINT64 AddressEncMask;@@ -730,18 +729,16 @@ CreateIdentityMappingPageTables (
} } - Page5LevelSupport = FALSE;- if (PcdGetBool (PcdUse5LevelPageTable)) {- AsmCpuidEx (- CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL,- &EcxFlags.Uint32, NULL, NULL- );- if (EcxFlags.Bits.FiveLevelPage != 0) {- Page5LevelSupport = TRUE;- }- }+ //+ // Check CR4.LA57[bit12] to determin whether 5-Level Paging is enabled.+ // Because this code runs at both IA-32e (64bit) mode and legacy protected (32bit) mode,+ // below logic inherits the 5-level paging setting from bootloader in IA-32e mode+ // and uses 4-level paging in legacy protected mode.+ //+ Cr4.UintN = AsmReadCr4 ();+ Enable5LevelPaging = (BOOLEAN) (Cr4.Bits.LA57 == 1); - DEBUG ((DEBUG_INFO, "AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Page5LevelSupport, Page1GSupport));+ DEBUG ((DEBUG_INFO, "PayloadEntry: AddressBits=%u 5LevelPaging=%u 1GPage=%u\n", PhysicalAddressBits, Enable5LevelPaging, Page1GSupport)); // // IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses@@ -749,7 +746,7 @@ CreateIdentityMappingPageTables (
// due to either unsupported by HW, or disabled by PCD. // ASSERT (PhysicalAddressBits <= 52);- if (!Page5LevelSupport && PhysicalAddressBits > 48) {+ if (!Enable5LevelPaging && PhysicalAddressBits > 48) { PhysicalAddressBits = 48; } @@ -784,7 +781,7 @@ CreateIdentityMappingPageTables (
// // Substract the one page occupied by PML5 entries if 5-Level Paging is disabled. //- if (!Page5LevelSupport) {+ if (!Enable5LevelPaging) { TotalPagesNum--; } @@ -799,7 +796,7 @@ CreateIdentityMappingPageTables (
// By architecture only one PageMapLevel4 exists - so lets allocate storage for it. // PageMap = (VOID *) BigPageAddress;- if (Page5LevelSupport) {+ if (Enable5LevelPaging) { // // By architecture only one PageMapLevel5 exists - so lets allocate storage for it. //@@ -819,7 +816,7 @@ CreateIdentityMappingPageTables (
PageMapLevel4Entry = (VOID *) BigPageAddress; BigPageAddress += SIZE_4KB; - if (Page5LevelSupport) {+ if (Enable5LevelPaging) { // // Make a PML5 Entry //@@ -911,10 +908,7 @@ CreateIdentityMappingPageTables (
ZeroMem (PageMapLevel4Entry, (512 - IndexOfPml4Entries) * sizeof (PAGE_MAP_AND_DIRECTORY_POINTER)); } - if (Page5LevelSupport) {- Cr4.UintN = AsmReadCr4 ();- Cr4.Bits.LA57 = 1;- AsmWriteCr4 (Cr4.UintN);+ if (Enable5LevelPaging) { // // For the PML5 entries we are not using fill in a null entry. //--
2.32.0.windows.1


[RFC PATCH 6/7] OVMF: Reference new classes in the build system for compilation

Stefan Berger <stefanb@...>
 

Compile the added code now.

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
OvmfPkg/AmdSev/AmdSevX64.dsc | 3 +++
.../Library/PlatformBootManagerLib/PlatformBootManagerLib.inf | 1 +
OvmfPkg/OvmfPkgIa32.dsc | 3 +++
OvmfPkg/OvmfPkgIa32X64.dsc | 3 +++
OvmfPkg/OvmfPkgX64.dsc | 3 +++
5 files changed, 13 insertions(+)

diff --git a/OvmfPkg/AmdSev/AmdSevX64.dsc b/OvmfPkg/AmdSev/AmdSevX64.dsc
index e6cd10b759..6b582626ff 100644
--- a/OvmfPkg/AmdSev/AmdSevX64.dsc
+++ b/OvmfPkg/AmdSev/AmdSevX64.dsc
@@ -209,9 +209,11 @@
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeT=
cg2PhysicalPresenceLib.inf=0D
Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibN=
ull.inf=0D
TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure=
mentLib.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
b/PeiDxeTpmPlatformHierarchyLib.inf=0D
!else=0D
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibNull/DxeT=
cg2PhysicalPresenceLib.inf=0D
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem=
entLibNull.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
bNull/PeiDxeTpmPlatformHierarchyLib.inf=0D
!endif=0D
=0D
[LibraryClasses.common]=0D
@@ -836,6 +838,7 @@
SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf {=0D
<LibraryClasses>=0D
Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibR=
outerDxe.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarc=
hyLib/PeiDxeTpmPlatformHierarchyLib.inf=0D
NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf=0D
HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCrypt=
oRouterDxe.inf=0D
NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf=
=0D
diff --git a/OvmfPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.=
inf b/OvmfPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
index e470b9a6a3..e7d1917022 100644
--- a/OvmfPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+++ b/OvmfPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
@@ -56,6 +56,7 @@
PlatformBmPrintScLib=0D
Tcg2PhysicalPresenceLib=0D
XenPlatformLib=0D
+ TpmPlatformHierarchyLib=0D
=0D
[Pcd]=0D
gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent=0D
diff --git a/OvmfPkg/OvmfPkgIa32.dsc b/OvmfPkg/OvmfPkgIa32.dsc
index d1d92c97ba..374a1ea652 100644
--- a/OvmfPkg/OvmfPkgIa32.dsc
+++ b/OvmfPkg/OvmfPkgIa32.dsc
@@ -235,9 +235,11 @@
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeT=
cg2PhysicalPresenceLib.inf=0D
Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibN=
ull.inf=0D
TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure=
mentLib.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
b/PeiDxeTpmPlatformHierarchyLib.inf=0D
!else=0D
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibNull/DxeT=
cg2PhysicalPresenceLib.inf=0D
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem=
entLibNull.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
bNull/PeiDxeTpmPlatformHierarchyLib.inf=0D
!endif=0D
=0D
[LibraryClasses.common]=0D
@@ -711,6 +713,7 @@
SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf {=0D
<LibraryClasses>=0D
HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCrypt=
oRouterPei.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarc=
hyLib/PeiDxeTpmPlatformHierarchyLib.inf=0D
NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf=
=0D
NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256=
.inf=0D
NULL|SecurityPkg/Library/HashInstanceLibSha384/HashInstanceLibSha384=
.inf=0D
diff --git a/OvmfPkg/OvmfPkgIa32X64.dsc b/OvmfPkg/OvmfPkgIa32X64.dsc
index a467ab7090..7b7dffcd94 100644
--- a/OvmfPkg/OvmfPkgIa32X64.dsc
+++ b/OvmfPkg/OvmfPkgIa32X64.dsc
@@ -239,9 +239,11 @@
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeT=
cg2PhysicalPresenceLib.inf=0D
Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibN=
ull.inf=0D
TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure=
mentLib.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
b/PeiDxeTpmPlatformHierarchyLib.inf=0D
!else=0D
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibNull/DxeT=
cg2PhysicalPresenceLib.inf=0D
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem=
entLibNull.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
bNull/PeiDxeTpmPlatformHierarchyLib.inf=0D
!endif=0D
=0D
[LibraryClasses.common]=0D
@@ -1034,6 +1036,7 @@
SecurityPkg/Tcg/Tcg2Dxe/Tcg2Dxe.inf {=0D
<LibraryClasses>=0D
Tpm2DeviceLib|SecurityPkg/Library/Tpm2DeviceLibRouter/Tpm2DeviceLibR=
outerDxe.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarc=
hyLib/PeiDxeTpmPlatformHierarchyLib.inf=0D
NULL|SecurityPkg/Library/Tpm2DeviceLibDTpm/Tpm2InstanceLibDTpm.inf=0D
HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCrypt=
oRouterDxe.inf=0D
NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf=
=0D
diff --git a/OvmfPkg/OvmfPkgX64.dsc b/OvmfPkg/OvmfPkgX64.dsc
index e56b83d95e..34c6e833e4 100644
--- a/OvmfPkg/OvmfPkgX64.dsc
+++ b/OvmfPkg/OvmfPkgX64.dsc
@@ -239,9 +239,11 @@
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibQemu/DxeT=
cg2PhysicalPresenceLib.inf=0D
Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibN=
ull.inf=0D
TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasure=
mentLib.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
b/PeiDxeTpmPlatformHierarchyLib.inf=0D
!else=0D
Tcg2PhysicalPresenceLib|OvmfPkg/Library/Tcg2PhysicalPresenceLibNull/DxeT=
cg2PhysicalPresenceLib.inf=0D
TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeasurem=
entLibNull.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLi=
bNull/PeiDxeTpmPlatformHierarchyLib.inf=0D
!endif=0D
=0D
[LibraryClasses.common]=0D
@@ -723,6 +725,7 @@
SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf {=0D
<LibraryClasses>=0D
HashLib|SecurityPkg/Library/HashLibBaseCryptoRouter/HashLibBaseCrypt=
oRouterPei.inf=0D
+ TpmPlatformHierarchyLib|SecurityPkg/Library/PeiDxeTpmPlatformHierarc=
hyLib/PeiDxeTpmPlatformHierarchyLib.inf=0D
NULL|SecurityPkg/Library/HashInstanceLibSha1/HashInstanceLibSha1.inf=
=0D
NULL|SecurityPkg/Library/HashInstanceLibSha256/HashInstanceLibSha256=
.inf=0D
NULL|SecurityPkg/Library/HashInstanceLibSha384/HashInstanceLibSha384=
.inf=0D
--=20
2.31.1


[RFC PATCH 3/7] SecurityPkg/TPM: Disable PcdGetBool (PcdRandomizePlatformHierarchy)

Stefan Berger <stefanb@...>
 

To avoid this type of build errors, disable
'PcdGetBool (PcdRandomizePlatformHierarchy)'.

Building ... /home/stefanb/dev/edk2/SecurityPkg/Library/SecureBootVariableProvisionLib/SecureBootVariableProvisionLib.inf [X64]
In file included from /home/stefanb/dev/edk2/Build/OvmfX64/DEBUG_GCC5/X64/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib/DEBUG/AutoGen.h:17,
from <command-line>:
/home/stefanb/dev/edk2/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c: In function ‘ConfigureTpmPlatformHierarchy’:
/home/stefanb/dev/edk2/MdePkg/Include/Library/PcdLib.h:424:45: error: ‘_PCD_GET_MODE_BOOL_PcdRandomizePlatformHierarchy’ undeclared (first use in this function)
424 | #define PcdGetBool(TokenName) _PCD_GET_MODE_BOOL_##TokenName
| ^~~~~~~~~~~~~~~~~~~

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
.../PeiDxeTpmPlatformHierarchyLib.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
index 9812ab99ab..bea10d37a4 100644
--- a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
+++ b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLib/PeiDxeTpmPlatformHierarchyLib.c
@@ -252,7 +252,7 @@ EFIAPI
ConfigureTpmPlatformHierarchy (
)
{
- if (PcdGetBool (PcdRandomizePlatformHierarchy)) {
+ if (1 /*PcdGetBool (PcdRandomizePlatformHierarchy)*/) {
//
// Send Tpm2HierarchyChange Auth with random value to avoid PlatformAuth being null
//
--
2.31.1


[RFC PATCH 7/7] OVMF: Disable the TPM2 platform hierarchy

Stefan Berger <stefanb@...>
 

Use the newly added functions to disable the TPM2 platform hierarchy.

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c | 6 ++++++
OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c | 6 ++++++
OvmfPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c | 6 ++++++
3 files changed, 18 insertions(+)

diff --git a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c b/OvmfPkg=
/Library/PlatformBootManagerLib/BdsPlatform.c
index b0e9742937..5bf145ba25 100644
--- a/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBootManagerLib/BdsPlatform.c
@@ -11,6 +11,7 @@
#include <Protocol/FirmwareVolume2.h>=0D
#include <Library/PlatformBmPrintScLib.h>=0D
#include <Library/Tcg2PhysicalPresenceLib.h>=0D
+#include <Library/TpmPlatformHierarchyLib.h>
#include <Library/XenPlatformLib.h>=0D
=0D
=0D
@@ -1516,6 +1517,11 @@ PlatformBootManagerAfterConsole (
//=0D
Tcg2PhysicalPresenceLibProcessRequest (NULL);=0D
=0D
+ //=0D
+ // Disable the TPM 2 platform hierarchy=0D
+ //=0D
+ ConfigureTpmPlatformHierarchy ();
+=0D
//=0D
// Process QEMU's -kernel command line option=0D
//=0D
diff --git a/OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c b/Ov=
mfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c
index eaade4adea..09418dc4ff 100644
--- a/OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBootManagerLibBhyve/BdsPlatform.c
@@ -12,6 +12,7 @@
#include <Protocol/FirmwareVolume2.h>=0D
#include <Library/PlatformBmPrintScLib.h>=0D
#include <Library/Tcg2PhysicalPresenceLib.h>=0D
+#include <Library/TpmPlatformHierarchyLib.h>
=0D
#include <Protocol/BlockIo.h>=0D
=0D
@@ -1450,6 +1451,11 @@ PlatformBootManagerAfterConsole (
//=0D
Tcg2PhysicalPresenceLibProcessRequest (NULL);=0D
=0D
+ //=0D
+ // Disable the TPM 2 platform hierarchy=0D
+ //=0D
+ ConfigureTpmPlatformHierarchy ();
+=0D
//=0D
// Perform some platform specific connect sequence=0D
//=0D
diff --git a/OvmfPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c b/Ovm=
fPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c
index 7cceeea487..508e2b6403 100644
--- a/OvmfPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c
+++ b/OvmfPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c
@@ -12,6 +12,7 @@
#include <Protocol/FirmwareVolume2.h>=0D
#include <Library/PlatformBmPrintScLib.h>=0D
#include <Library/Tcg2PhysicalPresenceLib.h>=0D
+#include <Library/TpmPlatformHierarchyLib.h>
=0D
=0D
//=0D
@@ -1315,6 +1316,11 @@ PlatformBootManagerAfterConsole (
//=0D
Tcg2PhysicalPresenceLibProcessRequest (NULL);=0D
=0D
+ //=0D
+ // Disable the TPM 2 platform hierachy=0D
+ //=0D
+ ConfigureTpmPlatformHierarchy ();
+=0D
//=0D
// Process QEMU's -kernel command line option=0D
//=0D
--=20
2.31.1


[RFC PATCH 5/7] SecurityPkg/TPM: Add a NULL implementation of PeiDxeTpmPlatformHierarchyLib

Stefan Berger <stefanb@...>
 

Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
---
.../PeiDxeTpmPlatformHierarchyLib.c | 23 +++++++++++
.../PeiDxeTpmPlatformHierarchyLib.inf | 39 +++++++++++++++++++
2 files changed, 62 insertions(+)
create mode 100644 SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.c
create mode 100644 SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf

diff --git a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.c b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.c
new file mode 100644
index 0000000000..e871ada230
--- /dev/null
+++ b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.c
@@ -0,0 +1,23 @@
+/** @file
+ Null TPM Platform Hierarchy configuration library.
+
+ This library provides stub functions for customizing the TPM's Platform Hierarchy
+ Authorization Value (platformAuth) and Platform Hierarchy Authorization
+ Policy (platformPolicy) can be defined through this function.
+
+ Copyright (c) 2021, IBM Corporation.
+ Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) Microsoft Corporation.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+
+VOID
+EFIAPI
+ConfigureTpmPlatformHierarchy (
+ )
+{
+ /* no nothing */
+}
diff --git a/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf
new file mode 100644
index 0000000000..678f38410a
--- /dev/null
+++ b/SecurityPkg/Library/PeiDxeTpmPlatformHierarchyLibNull/PeiDxeTpmPlatformHierarchyLib.inf
@@ -0,0 +1,39 @@
+### @file
+#
+# TPM Platform Hierarchy configuration library.
+#
+# This library provides functions for customizing the TPM's Platform Hierarchy
+# Authorization Value (platformAuth) and Platform Hierarchy Authorization
+# Policy (platformPolicy) can be defined through this function.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) Microsoft Corporation.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiDxeTpmPlatformHierarchyLibNull
+ FILE_GUID = 7794F92C-4E8E-4E57-9E4A-49A0764C7D73
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = TpmPlatformHierarchyLib|PEIM DXE_DRIVER
+
+[LibraryClasses]
+ BaseLib
+# BaseMemoryLib
+# DebugLib
+# MemoryAllocationLib
+# PcdLib
+# RngLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ SecurityPkg/SecurityPkg.dec
+ CryptoPkg/CryptoPkg.dec
+
+[Sources]
+ PeiDxeTpmPlatformHierarchyLib.c
--
2.31.1

2101 - 2120 of 80865