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[PATCH v6 0/1] Add function QuickSort into MdePkg/BaseLib
From: IanX Kuo <ianx.kuo@...>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3675 First change 1. MdePkg/BaseLib: Add QuickSort function It need to seperate to second change 2. MdeModulePkg/SortLib: Use QuickSort instead of QuickSortWorker 3. CryptLib/CryptLib: Remove duplicate QuickSortWorker 4. CpuCacheInfoLib: Remove MdeModulePkg dependency IanX Kuo (1): MdePkg/BaseLib: Add QuickSort function on BaseLib MdePkg/Include/Library/BaseLib.h | 49 ++++++++ MdePkg/Library/BaseLib/BaseLib.inf | 1 + MdePkg/Library/BaseLib/QuickSort.c | 116 ++++++++++++++++++ .../Library/BaseLib/UnitTestHostBaseLib.inf | 3 +- 4 files changed, 168 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Library/BaseLib/QuickSort.c -- 2.30.0.windows.1 |
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[edk2-platforms][PATCH V2 5/5] WhitleyOpenBoardPkg: Enable VT-D support
Isaac Oram
From: "Oram, Isaac W" <isaac.w.oram@...>
Implements VT-D DMAR table functionality. VT-D is currently implemented as an OpenBoardPkg feature. More work would be needed to promote to an Advanced Feature. Specifically reducing dependencies and improving API and integration with OpenBoardPkg ACPI implementation. This fix depends on FvOpenBoardPkg providing extended ACPI tables and AcpiPlatform binaries. Cc: Nate DeSimone <nathaniel.l.desimone@...> Cc: Chasel Chiu <chasel.chiu@...> Signed-off-by: Isaac Oram <isaac.w.oram@...> --- Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.c | 604 ++++++++++++++++++++ Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf | 66 +++ Platform/Intel/WhitleyOpenBoardPkg/Include/AcpiVtd.h | 53 ++ Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/DmaRemap.h | 109 ++++ Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 4 + Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 1 + Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf | 1 + Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinitions.h | 4 + 8 files changed, 842 insertions(+) diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.c b/Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.c new file mode 100644 index 0000000000..310d15b9ad --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.c @@ -0,0 +1,604 @@ +/** @file AcpiVtd.c + + @copyright + Copyright 1996 - 2021 Intel Corporation. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +// +// Statements that include other files +// +#include <AcpiVtd.h> +#include <Library/SetupLib.h> +#include <IioRegs.h> +#include <IioSetupDefinitions.h> +#include <Protocol/Tcg2Protocol.h> +#include <Library/TpmMeasurementLib.h> + +VTD_SUPPORT_INSTANCE mPrivateData; + +#define MAX_BUS_ADDR_WIDTH 45 + +/** + + Add DMAR entry + + @param This - DMA Remap protocol pointer + @param RemapType - Type of DMA remapping structure to add + @param RemapEntry - Entry to add + + @retval EFI_INVALID_PARAMETER - DMA remapping support not initialized or entry is malformed + @retval EFI_UNSUPPORTED - Adding entries is not supported + @retval EFI_SUCCESS - The entry was inserted successfully. + +**/ +EFI_STATUS +EFIAPI +InsertDmaRemap ( + IN DMA_REMAP_PROTOCOL *This, + IN REMAP_TYPE RemapType, + IN VOID *RemapEntry + ) +{ + UINTN DevIndex; + EFI_ACPI_DMAR_HEADER *Dmar; + EFI_ACPI_DMAR_DRHD_HEADER *Drhd; + EFI_ACPI_DMAR_RMRR_HEADER *Rmrr; + EFI_ACPI_DMAR_SATC_HEADER *Atsr; + EFI_ACPI_DMAR_RHSA_HEADER *Rhsa; + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *DevScope; + DMAR_DRHD *DmaRemap; + DMAR_RMRR *RevMemRegion; + DMAR_ATSR *AtsrRegion; + DMAR_RHSA *RhsaRegion; + EFI_ACPI_DMAR_PCI_PATH *PciPath; + EFI_ACPI_DMAR_PCI_PATH *PciInputPath; + + if (mPrivateData.Dmar == NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + Dmar = mPrivateData.Dmar; + if (((UINT8 *) Dmar + Dmar->Header.Length) == NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + if (RemapType == DrhdType) { + DmaRemap = (DMAR_DRHD *) RemapEntry; + ASSERT (DmaRemap->Signature == DRHD_SIGNATURE); + Drhd = (EFI_ACPI_DMAR_DRHD_HEADER *) ((UINT8 *) Dmar + Dmar->Header.Length); + if (Drhd == NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + if (DmaRemap->RegisterBase == 0) { + return EFI_UNSUPPORTED; + } + + Drhd->Header.Type = EFI_ACPI_DMAR_TYPE_DRHD; + Drhd->Header.Length = sizeof (EFI_ACPI_DMAR_DRHD_HEADER); + Drhd->Flags = DmaRemap->Flags; + Drhd->SegmentNumber = DmaRemap->SegmentNumber; + Drhd->RegisterBaseAddress = DmaRemap->RegisterBase; + DevScope = NULL; + + for (DevIndex = 0; DevIndex < DmaRemap->DeviceScopeNumber; DevIndex++) { + if (((UINT8 *) Drhd + Drhd->Header.Length) == NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + DevScope = (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *) ((UINT8 *) Drhd + Drhd->Header.Length); + if (DevScope != NULL) { + DevScope->Type = DmaRemap->DeviceScope[DevIndex].DeviceType; + DevScope->Length = sizeof (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER); + DevScope->EnumerationId = DmaRemap->DeviceScope[DevIndex].EnumerationID; + DevScope->StartBusNumber = DmaRemap->DeviceScope[DevIndex].StartBusNumber; + if (((UINT8 *) DevScope + DevScope->Length) == NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + PciPath = (EFI_ACPI_DMAR_PCI_PATH *) ((UINT8 *) DevScope + DevScope->Length); + PciInputPath = (EFI_ACPI_DMAR_PCI_PATH *) DmaRemap->DeviceScope[DevIndex].PciNode; + while (*(UINT8 *) PciInputPath != (UINT8) -1) { + CopyMem(PciPath, PciInputPath, sizeof (EFI_ACPI_DMAR_PCI_PATH)); + DevScope->Length += sizeof (EFI_ACPI_DMAR_PCI_PATH); + PciInputPath++; + PciPath++; + } + Drhd->Header.Length = Drhd->Header.Length + (UINT16) DevScope->Length; + } else { + DEBUG ((DEBUG_ERROR, "DevScope Error. Invalid pointer.\n")); + } + } + + Dmar->Header.Length += Drhd->Header.Length; + + } else if (RemapType == RmrrType) { + RevMemRegion = (DMAR_RMRR *) RemapEntry; + ASSERT (RevMemRegion->Signature == RMRR_SIGNATURE); + Rmrr = (EFI_ACPI_DMAR_RMRR_HEADER *) ((UINT8 *) Dmar + Dmar->Header.Length); + if (Rmrr == NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + Rmrr->Header.Type = EFI_ACPI_DMAR_TYPE_RMRR; + Rmrr->Header.Length = sizeof (EFI_ACPI_DMAR_RMRR_HEADER); + Rmrr->SegmentNumber = RevMemRegion->SegmentNumber; + Rmrr->ReservedMemoryRegionBaseAddress = RevMemRegion->RsvdMemBase; + Rmrr->ReservedMemoryRegionLimitAddress = RevMemRegion->RsvdMemLimit; + + DevScope = NULL; + for (DevIndex = 0; DevIndex < RevMemRegion->DeviceScopeNumber; DevIndex++) { + if (((UINT8 *) Rmrr + Rmrr->Header.Length) == NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + DevScope = (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *) ((UINT8 *) Rmrr + Rmrr->Header.Length); + if (DevScope != NULL) { + DevScope->Type = RevMemRegion->DeviceScope[DevIndex].DeviceType; + DevScope->StartBusNumber = RevMemRegion->DeviceScope[DevIndex].StartBusNumber; + DevScope->Length = sizeof (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER); + if (((UINT8 *) DevScope + DevScope->Length) == NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + PciPath = (EFI_ACPI_DMAR_PCI_PATH *) ((UINT8 *) DevScope + DevScope->Length); + PciInputPath = (EFI_ACPI_DMAR_PCI_PATH *) RevMemRegion->DeviceScope[DevIndex].PciNode; + while (*(UINT8 *) PciInputPath != (UINT8) -1) { + CopyMem (PciPath, PciInputPath, sizeof (EFI_ACPI_DMAR_PCI_PATH)); + DevScope->Length += sizeof (EFI_ACPI_DMAR_PCI_PATH); + PciInputPath++; + PciPath++; + } + Rmrr->Header.Length = Rmrr->Header.Length + (UINT16) DevScope->Length; + } else { + DEBUG ((DEBUG_ERROR, "DevScope Error. Invalid pointer.\n")); + } + } + + Dmar->Header.Length += Rmrr->Header.Length; + + } else if (RemapType == AtsrType) { + AtsrRegion = (DMAR_ATSR *) RemapEntry; + ASSERT (AtsrRegion->Signature == ATSR_SIGNATURE); + Atsr = (EFI_ACPI_DMAR_SATC_HEADER *) ((UINT8 *) Dmar + Dmar->Header.Length); + if (Atsr == NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + Atsr->Header.Type = EFI_ACPI_DMAR_TYPE_ATSR; + Atsr->Flags = AtsrRegion->Flags; + Atsr->SegmentNumber = AtsrRegion->SegmentNumber; + Atsr->Header.Length = sizeof (EFI_ACPI_DMAR_SATC_HEADER); + + DevScope = NULL; + for (DevIndex = 0; DevIndex < AtsrRegion->DeviceScopeNumber; DevIndex++) { + if ((AtsrRegion->ATSRPresentBit & (01 << DevIndex)) == 00) { + continue; + } + if (((UINT8 *) Atsr + Atsr->Header.Length) == NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + DevScope = (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER *) ((UINT8 *) Atsr + Atsr->Header.Length); + if (DevScope != NULL) { + DevScope->Type = AtsrRegion->DeviceScope[DevIndex].DeviceType; + DevScope->StartBusNumber = AtsrRegion->DeviceScope[DevIndex].StartBusNumber; + DevScope->Length = sizeof (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER); + if (((UINT8 *) DevScope + DevScope->Length) == NULL) { + ASSERT (FALSE); + return EFI_INVALID_PARAMETER; + } + + PciPath = (EFI_ACPI_DMAR_PCI_PATH *) ((UINT8 *) DevScope + DevScope->Length); + PciInputPath = (EFI_ACPI_DMAR_PCI_PATH *) AtsrRegion->DeviceScope[DevIndex].PciNode; + while (*(UINT8 *) PciInputPath != (UINT8) -1) { + CopyMem(PciPath, PciInputPath, sizeof (EFI_ACPI_DMAR_PCI_PATH)); + DevScope->Length += sizeof (EFI_ACPI_DMAR_PCI_PATH); + PciInputPath++; + PciPath++; + } + + Atsr->Header.Length = Atsr->Header.Length + (UINT16) DevScope->Length; + + } else { + DEBUG ((DEBUG_ERROR, "DevScope Error. Invalid pointer.\n")); + } + } + + Dmar->Header.Length += Atsr->Header.Length; + + } else if (RemapType == RhsaType) { + RhsaRegion = (DMAR_RHSA *) RemapEntry; + ASSERT (RhsaRegion->Signature == RHSA_SIGNATURE); + + Rhsa = (EFI_ACPI_DMAR_RHSA_HEADER *) ((UINT8 *) Dmar + Dmar->Header.Length); + Rhsa->Header.Type = EFI_ACPI_DMAR_TYPE_RHSA; + Rhsa->ProximityDomain = RhsaRegion->Domian; + Rhsa->RegisterBaseAddress = RhsaRegion->RegisterBase; + Rhsa->Header.Length = sizeof (EFI_ACPI_DMAR_RHSA_HEADER); + Dmar->Header.Length += Rhsa->Header.Length; + } else { + return EFI_INVALID_PARAMETER; + } + + ASSERT (Dmar->Header.Length < TABLE_SIZE); + return EFI_SUCCESS; +} + +/** + + Returns info about the provided entry + + @param Entry - DMA remapping entry + @param Type - DMA remapping type + @param IncludeAll - Include all or all root port ASTR + @param Length - GC_TODO: add arg description + + @retval EFI_INVALID_PARAMETER - Null input pointer + @retval EFI_SUCCESS - Table info updated + +**/ +EFI_STATUS +GetTablesInfo ( + IN UINT8 *Entry, + IN OUT REMAP_TYPE *Type, + IN OUT BOOLEAN *IncludeAll, + IN OUT UINTN *Length + ) +{ + EFI_ACPI_DMAR_DRHD_HEADER *Comm; + + if (!Entry || !Type || !IncludeAll || !Length) { + ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); + return EFI_INVALID_PARAMETER; + } + + Comm = (EFI_ACPI_DMAR_DRHD_HEADER *) Entry; + *Length = Comm->Header.Length; + + if (Comm->Header.Type == EFI_ACPI_DMAR_TYPE_RMRR) { + *Type = RmrrType; + } else if (Comm->Header.Type == EFI_ACPI_DMAR_TYPE_DRHD) { + *Type = DrhdType; + } else if (Comm->Header.Type == EFI_ACPI_DMAR_TYPE_ATSR) { + *Type = AtsrType; + } else if (Comm->Header.Type == EFI_ACPI_DMAR_TYPE_RHSA) { + *Type = RhsaType; + } else { + *Type = 0xFF; + } + + if (Comm->Flags & EFI_ACPI_DMAR_DRHD_FLAGS_INCLUDE_PCI_ALL) { + *IncludeAll = TRUE; + } else { + *IncludeAll = FALSE; + } + + return EFI_SUCCESS; +} + +/** + + Reorder the table entries + + @param None + + @retval EFI_SUCCESS - The table entries are ordered + +**/ +EFI_STATUS +ReorderTables ( + VOID + ) +{ + REMAP_TYPE Type; + BOOLEAN IncludeAll; + UINTN Length; + UINTN CurrLength; + UINTN TableLength; + UINT8 *Ptr; + UINT8 *PtrOrder; + + Ptr = (UINT8 *) mPrivateData.Dmar; + PtrOrder = (UINT8 *) mPrivateData.DmarOrder; + + CopyMem (PtrOrder, Ptr, sizeof (EFI_ACPI_DMAR_HEADER)); + PtrOrder += sizeof (EFI_ACPI_DMAR_HEADER); + + TableLength = mPrivateData.Dmar->Header.Length; + + CurrLength = sizeof (EFI_ACPI_DMAR_HEADER); + Ptr = (UINT8 *) mPrivateData.Dmar + CurrLength; + while (CurrLength < TableLength) { + GetTablesInfo (Ptr, &Type, &IncludeAll, &Length); + if (Type == DrhdType && !IncludeAll) { + CopyMem (PtrOrder, Ptr, Length); + PtrOrder += Length; + } + + Ptr += Length; + CurrLength += Length; + } + + CurrLength = sizeof (EFI_ACPI_DMAR_HEADER); + Ptr = (UINT8 *) mPrivateData.Dmar + CurrLength; + while (CurrLength < TableLength) { + GetTablesInfo (Ptr, &Type, &IncludeAll, &Length); + if (Type == DrhdType && IncludeAll) { + CopyMem (PtrOrder, Ptr, Length); + PtrOrder += Length; + } + + Ptr += Length; + CurrLength += Length; + } + + CurrLength = sizeof (EFI_ACPI_DMAR_HEADER); + Ptr = (UINT8 *) mPrivateData.Dmar + CurrLength; + while (CurrLength < TableLength) { + GetTablesInfo (Ptr, &Type, &IncludeAll, &Length); + if (Type == RmrrType && !IncludeAll) { + CopyMem (PtrOrder, Ptr, Length); + PtrOrder += Length; + } + + Ptr += Length; + CurrLength += Length; + } + + CurrLength = sizeof (EFI_ACPI_DMAR_HEADER); + Ptr = (UINT8 *) mPrivateData.Dmar + CurrLength; + while (CurrLength < TableLength) { + GetTablesInfo (Ptr, &Type, &IncludeAll, &Length); + if (Type == AtsrType && !IncludeAll) { + CopyMem (PtrOrder, Ptr, Length); + PtrOrder += Length; + } + + Ptr += Length; + CurrLength += Length; + } + + CurrLength = sizeof (EFI_ACPI_DMAR_HEADER); + Ptr = (UINT8 *) mPrivateData.Dmar + CurrLength; + while (CurrLength < TableLength) { + GetTablesInfo (Ptr, &Type, &IncludeAll, &Length); + if (Type == RhsaType) { + CopyMem (PtrOrder, Ptr, Length); + PtrOrder += Length; + } + + Ptr += Length; + CurrLength += Length; + } + + return EFI_SUCCESS; +} + +/** + + Return a reordered version of the DMAR table provided on input + + @param[in] This - DMA remap protocol + @param[in][out] DmarTable - DMAR table + + @retval EFI_INVALID_PARAMETER - DmarTable NULL + @retval EFI_UNSUPPORTED - DMAR table length doesn't meet expected value + @retval EFI_SUCCESS - Updated DMAR table returned + +**/ +EFI_STATUS +EFIAPI +GetDmarTable ( + IN DMA_REMAP_PROTOCOL *This, + IN OUT VOID **DmarTable + ) +{ + if (DmarTable == NULL) { + return EFI_INVALID_PARAMETER; + } + + if (mPrivateData.Dmar->Header.Length <= sizeof (EFI_ACPI_DMAR_HEADER)) { + return EFI_UNSUPPORTED; + } + + ReorderTables (); + *DmarTable = mPrivateData.DmarOrder; + return EFI_SUCCESS; +} + +#define TBT_SECURITY_EVENT_STRING "DMA Protection Disabled" +#define TBT_SECURITY_EVENT_STRING_LEN (sizeof (TBT_SECURITY_EVENT_STRING) - 1) + +GLOBAL_REMOVE_IF_UNREFERENCED EFI_EVENT EndOfDxeEvent; + +/** + Security EndOfDxe CallBack Function + If the firmware/BIOS has an option to enable and disable DMA protections via a VT-d switch in BIOS options, then the shipping configuration must be with VT-d protection enabled. + On every boot where VT-d/DMA protection is disabled, or will be disabled, or configured to a lower security state, and a platform has a TPM enabled, then the platform SHALL + extend an EV_EFI_ACTION event into PCR[7] before enabling external DMA + The event string SHALL be "DMA Protection Disabled". The platform firmware MUST log this measurement in the event log using the string "DMA Protection Disabled" for the Event Data. + Measure and log launch of TBT Security, and extend the measurement result into a specific PCR. + Extend an EV_EFI_ACTION event into PCR[7] before enabling external DMA. The event string SHALL be "DMA Protection Disabled". The platform firmware MUST log this measurement + in the event log using the string "DMA Protection Disabled" for the Event Data. + + @param[in] Event - A pointer to the Event that triggered the callback. + @param[in] Context - A pointer to private data registered with the callback function. +**/ +VOID +EFIAPI +ExtendPCR7CallBack ( + IN EFI_EVENT Event, + IN VOID *Context + ) +{ + UINTN Status; + UINT64 HashDataLen; + + DEBUG ((DEBUG_INFO, "ExtendPCR7CallBack START\n")); + + // + // When VT-d/DMA protection is disabled and a platform has a TPM enabled, + // the platform SHALL extend an EV_EFI_ACTION event into PCR[7]. + // + HashDataLen = TBT_SECURITY_EVENT_STRING_LEN; + + Status = TpmMeasureAndLogData ( + 7, + EV_EFI_ACTION, + TBT_SECURITY_EVENT_STRING, + (UINT32) HashDataLen, + TBT_SECURITY_EVENT_STRING, + HashDataLen + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "TpmMeasureAndLogData Status: %r\n", Status)); + } else { + DEBUG ((DEBUG_INFO, "TpmMeasureAndLogData Successfully\n")); + } + + DEBUG ((DEBUG_INFO, "ExtendPCR7CallBack END\n")); +} + +/** + Register an End of DXE event for extended a TPM log to PCR[7] when vtd is diable + This feature is introduced by TBT Security requirment +**/ +VOID +RegisterExtendPCR7CallBack ( + VOID + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + + // + // Register an End of DXE event for extended a TPM log to PCR[7]. + // + DEBUG ((DEBUG_INFO, "Register an End of DXE event for extended a TPM log to PCR[7] when VTd/DMA protection is disabled.\n")); + Status = gBS->CreateEventEx ( + EVT_NOTIFY_SIGNAL, + TPL_NOTIFY, + ExtendPCR7CallBack, + NULL, + &gEfiEndOfDxeEventGroupGuid, + &EndOfDxeEvent + ); + if (EFI_ERROR (Status)) { + DEBUG ((DEBUG_ERROR, "Failed to Register an End of DXE event for extended a TPM log to PCR[7], Status: %r\n", Status)); + } +} + +/** + + VT-D Driver entry point + + @param ImageHandle The image handle. + @param SystemTable The system table. + + @retval Status - If not EFI_SUCCESS then an error occurred during initialization. + +**/ +EFI_STATUS +EFIAPI +VtdTableEntryPoint ( + IN EFI_HANDLE ImageHandle, + IN EFI_SYSTEM_TABLE *SystemTable + ) +{ + EFI_STATUS Status = EFI_SUCCESS; + EFI_ACPI_DMAR_HEADER *Dmar; + UINT64 TempOemTableId; + UINT8 VTdSupport; + UINT8 DmaCtrlOptIn; + UINT8 InterruptRemap; + UINT8 X2ApicOptOut; + UINT8 ATS; + UINTN Dmarlength; + UINT8 ControlIommu; + + // + // Initialize our protocol + // + ZeroMem (&mPrivateData, sizeof (VTD_SUPPORT_INSTANCE)); + + Status = GetOptionData (&gEfiSocketIioVariableGuid, OFFSET_OF (SOCKET_IIO_CONFIGURATION, VTdSupport), &VTdSupport, sizeof (VTdSupport)); + Status |= GetOptionData (&gEfiSocketIioVariableGuid, OFFSET_OF (SOCKET_IIO_CONFIGURATION, DmaCtrlOptIn), &DmaCtrlOptIn, sizeof (DmaCtrlOptIn)); + Status |= GetOptionData (&gEfiSocketIioVariableGuid, OFFSET_OF (SOCKET_IIO_CONFIGURATION, InterruptRemap), &InterruptRemap, sizeof (InterruptRemap)); + Status |= GetOptionData (&gEfiSocketIioVariableGuid, OFFSET_OF (SOCKET_IIO_CONFIGURATION, ATS), &ATS, sizeof (ATS)); + Status |= GetOptionData (&gEfiSocketIioVariableGuid, OFFSET_OF (SOCKET_IIO_CONFIGURATION, X2ApicOptOut), &X2ApicOptOut, sizeof (X2ApicOptOut)); + + if (!EFI_ERROR (Status)) { + mPrivateData.DmaRemapProt.VTdSupport = VTdSupport; + mPrivateData.DmaRemapProt.DmaCtrlOptIn = DmaCtrlOptIn; + mPrivateData.DmaRemapProt.InterruptRemap = VTdSupport && (InterruptRemap != IIO_OPTION_DISABLE); + mPrivateData.DmaRemapProt.ATS = ATS; + mPrivateData.DmaRemapProt.X2ApicOptOut = X2ApicOptOut; + } + + Status = GetOptionData (&gEfiSocketIioVariableGuid, OFFSET_OF (SOCKET_IIO_CONFIGURATION, ControlIommu), &ControlIommu, sizeof (ControlIommu)); + if (EFI_ERROR (Status)) { + ControlIommu = 0; + } + + mPrivateData.Signature = EFI_ACPI_6_4_DMA_REMAPPING_TABLE_SIGNATURE; + + Dmarlength = MAX_SOCKET * NUMBER_PORTS_PER_SOCKET * ( sizeof (EFI_ACPI_DMAR_HEADER) + sizeof (EFI_ACPI_DMAR_DRHD_HEADER) + + sizeof (EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER) + sizeof (EFI_ACPI_DMAR_PCI_PATH)); + + mPrivateData.Dmar = (EFI_ACPI_DMAR_HEADER *) AllocateZeroPool (Dmarlength); + + mPrivateData.DmarOrder = (EFI_ACPI_DMAR_HEADER *) AllocateZeroPool (Dmarlength); + + mPrivateData.DmaRemapProt.InsertDmaRemap = InsertDmaRemap; + mPrivateData.DmaRemapProt.GetDmarTable = GetDmarTable; + + if (mPrivateData.Dmar != NULL) { + Dmar = mPrivateData.Dmar; + Dmar->Header.Length = sizeof (EFI_ACPI_DMAR_HEADER); + Dmar->Header.Signature = EFI_ACPI_6_4_DMA_REMAPPING_TABLE_SIGNATURE; + Dmar->Header.Revision = EFI_ACPI_DMAR_REVISION; + Dmar->Header.OemRevision = ACPI_DMAR_OEM_REVISION; + Dmar->Header.CreatorId = ACPI_DMAR_OEM_CREATOR_ID; + Dmar->Header.CreatorRevision = ACPI_DMAR_OEM_CREATOR_REVISION; + Dmar->HostAddressWidth = MAX_BUS_ADDR_WIDTH; + + TempOemTableId = PcdGet64 (PcdAcpiDefaultOemTableId); + + CopyMem (Dmar->Header.OemId, PcdGetPtr (PcdAcpiDefaultOemId), sizeof (Dmar->Header.OemId)); + CopyMem (&Dmar->Header.OemTableId, &TempOemTableId, sizeof (Dmar->Header.OemTableId)); + + Status = gBS->InstallProtocolInterface ( + &mPrivateData.Handle, + &gDmaRemapProtocolGuid, + EFI_NATIVE_INTERFACE, + &mPrivateData.DmaRemapProt + ); + } else { + + ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER); + Status = EFI_OUT_OF_RESOURCES; + } + + if (FixedPcdGetBool (PcdConditionallyExtendPcr7)) { + if (!VTdSupport || !DmaCtrlOptIn || (ControlIommu == 0)) { + // + // Inform OS by TPM PCR7 when VTd/DMA protection is disabled. + // + RegisterExtendPCR7CallBack (); + } + } + + return Status; +} diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf b/Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf new file mode 100644 index 0000000000..a60deb9e9a --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf @@ -0,0 +1,66 @@ +## @file +# +# @copyright +# Copyright 2009 - 2021 Intel Corporation. <BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = AcpiVtd + FILE_GUID = 64A11188-5B86-4f59-A702-73365896E65E + MODULE_TYPE = DXE_DRIVER + VERSION_STRING = 1.0 + ENTRY_POINT = VtdTableEntryPoint + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 +# + +[Sources] + AcpiVtd.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + WhitleyOpenBoardPkg/PlatformPkg.dec + WhitleySiliconPkg/SiliconPkg.dec + WhitleySiliconPkg/CpRcPkg.dec + +[LibraryClasses] + UefiDriverEntryPoint + IoLib + BaseMemoryLib + DebugLib + UefiRuntimeServicesTableLib + UefiBootServicesTableLib + DevicePathLib + HobLib + SetupLib + TpmMeasurementLib + +[Protocols] + gDmaRemapProtocolGuid ## CONSUMES + +[Guids] + gEfiHobListGuid ## CONSUMES + gEfiSocketIioVariableGuid ## CONSUMES + gEfiEndOfDxeEventGroupGuid ## CONSUMES + +[Pcd] + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId + gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId + gPlatformTokenSpaceGuid.PcdConditionallyExtendPcr7 + +[FixedPcd] + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount + gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuCoreCount + +[Depex] + gEfiVariableArchProtocolGuid AND + gEfiIioUdsProtocolGuid AND + gEfiIioSystemProtocolGuid + diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/AcpiVtd.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/AcpiVtd.h new file mode 100644 index 0000000000..d3ad4d7918 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/AcpiVtd.h @@ -0,0 +1,53 @@ +/** @file + This file describes the contents of the VTD ACPI Support + + @copyright + Copyright 1996 - 2021 Intel Corporation. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef _ACPI_VTD_H +#define _ACPI_VTD_H + +// +// Statements that include other files +// +#include <PiDxe.h> +#include <Library/UefiLib.h> +#include <Library/DxeServicesLib.h> +#include <Library/PcdLib.h> +#include <Library/IoLib.h> +#include <Library/BaseMemoryLib.h> +#include <Library/DebugLib.h> +#include <Library/UefiRuntimeServicesTableLib.h> +#include <Library/MemoryAllocationLib.h> +#include <Library/UefiBootServicesTableLib.h> +#include <Library/UefiDriverEntryPoint.h> +#include <Library/DevicePathLib.h> +#include <Library/HobLib.h> +#include <IndustryStandard/Acpi.h> +#include <IndustryStandard/DmaRemappingReportingTable.h> +#include <Protocol/DmaRemap.h> +#include <Guid/HobList.h> +#include <Guid/PlatformInfo.h> +#include <Guid/SocketVariable.h> + +// +// equates used in DMAR Table. +// +#define ACPI_DMAR_OEM_REVISION 0x01 +#define ACPI_DMAR_OEM_CREATOR_ID 0x01 +#define ACPI_DMAR_OEM_CREATOR_REVISION 0x01 + +#define TABLE_SIZE 4 * 1024 + +typedef struct { + UINT32 Signature; + EFI_HANDLE Handle; + DMA_REMAP_PROTOCOL DmaRemapProt; + EFI_ACPI_DMAR_HEADER *Dmar; + EFI_ACPI_DMAR_HEADER *DmarOrder; +} VTD_SUPPORT_INSTANCE; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/DmaRemap.h b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/DmaRemap.h new file mode 100644 index 0000000000..4e6a7439e1 --- /dev/null +++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/DmaRemap.h @@ -0,0 +1,109 @@ +/** @file + Protocol used to support ACPI VT-d DMA remapping reporting + + @copyright + Copyright 2006 - 2021 Intel Corporation. <BR> + + SPDX-License-Identifier: BSD-2-Clause-Patent +**/ + +#ifndef __DMA_REMAP_H__ +#define __DMA_REMAP_H__ + +// +// Protocol for GUID. +// +typedef struct _DMA_REMAP_PROTOCOL DMA_REMAP_PROTOCOL; + +#define DRHD_SIGNATURE (('D'<<24) + ('R'<<16) + ('H'<<8) + 'D') +#define RMRR_SIGNATURE (('R'<<24) + ('M'<<16) + ('R'<<8) + 'R') +#define ATSR_SIGNATURE (('A'<<24) + ('T'<<16) + ('S'<<8) + 'R') +#define RHSA_SIGNATURE (('A'<<24) + ('S'<<16) + ('H'<<8) + 'R') +#define ANDD_SIGNATURE (('A'<<24) + ('N'<<16) + ('D'<<8) + 'D') + +typedef enum { + DrhdType, + RmrrType, + AtsrType, + RhsaType +} REMAP_TYPE; + +typedef enum { + PciEndpoint = 1, + PciBridge = 2 +} PCI_DEV_TYPE; + +typedef struct { + UINT8 Device; + UINT8 Function; +} PCI_NODE; + +typedef struct { + UINT8 DeviceType; + UINT8 EnumerationID; + UINT8 StartBusNumber; + PCI_NODE *PciNode; +} DEVICE_SCOPE; + +typedef struct { + UINT32 Signature; + UINT8 Flags; + UINT16 SegmentNumber; + UINT64 RegisterBase; + UINTN DeviceScopeNumber; + DEVICE_SCOPE *DeviceScope; +} DMAR_DRHD; + +typedef struct { + UINT32 Signature; + UINT16 SegmentNumber; + UINT64 RsvdMemBase; + UINT64 RsvdMemLimit; + UINTN DeviceScopeNumber; + DEVICE_SCOPE *DeviceScope; +} DMAR_RMRR; + +typedef struct { + UINT32 Signature; + UINT8 Flags; + UINT16 SegmentNumber; + UINTN DeviceScopeNumber; + UINT32 ATSRPresentBit; + DEVICE_SCOPE *DeviceScope; +} DMAR_ATSR; + +typedef struct { + UINT32 Signature; + UINT64 RegisterBase; + UINT32 Domian; + UINT16 RhsaCount; +} DMAR_RHSA; + +typedef +EFI_STATUS +(EFIAPI *INSERT_DMA_REMAP) ( + IN DMA_REMAP_PROTOCOL *This, + IN REMAP_TYPE RemapType, + IN VOID *RemapEntry + ); + +typedef +EFI_STATUS +(EFIAPI *GET_DMAR_TABLE) ( + IN DMA_REMAP_PROTOCOL *This, + IN VOID **DmarTable + ); + +typedef struct _DMA_REMAP_PROTOCOL { + BOOLEAN VTdSupport; + BOOLEAN DmaCtrlOptIn; + BOOLEAN InterruptRemap; + BOOLEAN X2ApicOptOut; + BOOLEAN ATS; + INSERT_DMA_REMAP InsertDmaRemap; + GET_DMAR_TABLE GetDmarTable; +} DMA_REMAP_PROTOCOL; + +extern EFI_GUID gDmaRemapProtocolGuid; + +#endif diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec index fb4383d484..363d4e4059 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec @@ -153,6 +153,7 @@ gEfiIpmiBootGuid = { 0x5c9b75ec, 0x8ec7, 0x45f2, { 0x8f, 0x8f, 0xc1, 0xd8, 0x8f, 0x3b, 0x93, 0x45 } } gEfiGenericIpmiDriverInstalledGuid = { 0x7cdad61a, 0x3df8, 0x4425, { 0x96, 0x8c, 0x66, 0x28, 0xc8, 0x35, 0xff, 0xce } } + gDmaRemapProtocolGuid = { 0x4e873773, 0x8391, 0x4e47, { 0xb7, 0xf4, 0xca, 0xfb, 0xdc, 0xc4, 0xb2, 0x04 } } [PcdsFixedAtBuild] @@ -211,6 +212,9 @@ gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionSize|0x01000000|UINT32|0xF00000B0 gCpPlatFlashTokenSpaceGuid.PcdFlashCfrRegionBase|0xFF900000|UINT32|0xF00000B1 + #If True, extend PCR7 when VT-d disabled. + gPlatformTokenSpaceGuid.PcdConditionallyExtendPcr7|FALSE|BOOLEAN|0xE0000045 + [PcdsFixedAtBuild, PcdsPatchableInModule] gPlatformTokenSpaceGuid.PcdShellFile|{ 0xB7, 0xD6, 0x7A, 0xC5, 0x15, 0x05, 0xA8, 0x40, 0x9D, 0x21, 0x55, 0x16, 0x52, 0x85, 0x4E, 0x37 }|VOID*|0x40000004 ## Specify memory size with page number for a pre-allocated reserved memory to be used diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc index a6e40e7904..df1d2d7ae6 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc @@ -741,6 +741,7 @@ $(RP_PKG)/Features/Pci/Dxe/PciPlatform/PciPlatform.inf + $(RP_PKG)/Features/AcpiVtd/AcpiVtd.inf $(PLATFORM_PKG)/Acpi/AcpiSmm/AcpiSmm.inf { <LibraryClasses> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf index 1ae7435aa0..79fcf1e369 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf @@ -672,6 +672,7 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000 INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf + INF WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf [FV.FvOsBoot] diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinitions.h b/Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinitions.h index 55496e60d4..b23d817205 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinitions.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinitions.h @@ -57,4 +57,8 @@ #define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19 #define IIO_BIFURCATE_AUTO 0xFF +#define IIO_OPTION_AUTO 2 +#define IIO_OPTION_ENABLE 1 +#define IIO_OPTION_DISABLE 0 + #endif /* _IIOSETUPDEFINITIONS_H_ */ -- 2.27.0.windows.1 |
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[edk2-platforms][PATCH V2 4/5] WhitleyOpenBoardPkg/Acpi: Use binary AcpiPlatform driver
Isaac Oram
This uses the binary AcpiPlatform driver from FvLateOpenBoard to
produce and update more complete ACPI tables. Cc: Chasel Chiu <chasel.chiu@...> Cc: Nate DeSimone <nathaniel.l.desimone@...> Signed-off-by: Isaac Oram <isaac.w.oram@...> --- Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 4 ---- Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf | 2 -- 2 files changed, 6 deletions(-) diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc index f0a83fffd1..a6e40e7904 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc @@ -741,10 +741,6 @@ $(RP_PKG)/Features/Pci/Dxe/PciPlatform/PciPlatform.inf - $(PLATFORM_PKG)/Acpi/AcpiTables/AcpiPlatform.inf { - <LibraryClasses> - BoardAcpiTableLib|$(RP_PKG)/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf - } $(PLATFORM_PKG)/Acpi/AcpiSmm/AcpiSmm.inf { <LibraryClasses> diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf index d128f61b9d..1ae7435aa0 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf @@ -672,8 +672,6 @@ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000 INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf - INF MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf - INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf [FV.FvOsBoot] -- 2.27.0.windows.1 |
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[edk2-platforms][PATCH V2 3/5] WhitleySiliconPkg/Interfaces: Remove PcdsDynamic use.
Isaac Oram
Remove Dynamic PCD options in favor of DynamicEx only.
Delete some dead code and misleading comments. Cc: Chasel Chiu <chasel.chiu@...> Cc: Nate DeSimone <nathaniel.l.desimone@...> Signed-off-by: Isaac Oram <isaac.w.oram@...> --- Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec | 4 ++-- Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec | 2 +- Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec | 19 ++++--------------- 3 files changed, 7 insertions(+), 18 deletions(-) diff --git a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec index 3a6d87dd7f..902abd30f8 100644 --- a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec +++ b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec @@ -516,7 +516,7 @@ WhitleySiliconPkg/WhitleySiliconPkg.dec } -[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapBase|0xFE800000|UINT32|0x00000020 gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize|0|UINT32|0x00000021 gEfiCpRcPkgTokenSpaceGuid.PcdNvDimmEn|FALSE|BOOLEAN|0x00000035 @@ -526,7 +526,7 @@ gEfiCpRcPkgTokenSpaceGuid.PcdOemMtsConfigValue|0xD|UINT16|0x0000003C gEfiCpRcPkgTokenSpaceGuid.PcdSerialPortEnable|TRUE|BOOLEAN|0x0000003D -[PcdsDynamic, PcdsDynamicEx] +[PcdsDynamicEx] gEfiCpRcPkgTokenSpaceGuid.PcdSyshostMemoryAddress|0x00000000|UINT64|0x00000048 gEfiCpRcPkgTokenSpaceGuid.PcdMemMapHostMemoryAddress|0x00000000|UINT64|0x00000049 gEfiCpRcPkgTokenSpaceGuid.PcdDprMemSize|0x00300000|UINT32|0x0000004A diff --git a/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec b/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec index f30558b5d8..7b027b58c6 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec +++ b/Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec @@ -49,7 +49,7 @@ gCpuPkgTokenSpaceGuid.PcdCpuIcelakeFamilyFlag|FALSE|BOOLEAN|0x10000038 gCpuPkgTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|FALSE|BOOLEAN|0x1000000F -[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] ## Indicates the platform type: desktop, mobile or server.<BR><BR> # 0 - desktop<BR> diff --git a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec index ea8fd0a49b..c4993cb897 100644 --- a/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec +++ b/Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec @@ -601,17 +601,7 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43, [PcdsFeatureFlag] gPlatformTokenSpaceGuid.PcdLockCsrSsidSvidRegister|TRUE|BOOLEAN|0x10000001 gPlatformTokenSpaceGuid.PcdMultiPchEnabled |FALSE|BOOLEAN|0x10000003 - gSiPkgTokenSpaceGuid.PcdSleEnable |FALSE|BOOLEAN|0xF0000007 -#gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable |FALSE|BOOLEAN|0xF000000F -#gSiPkgTokenSpaceGuid.PcdAmtEnable |FALSE|BOOLEAN|0xF0000010 -#gSiPkgTokenSpaceGuid.PcdPttEnable |FALSE|BOOLEAN|0xF0000011 -#gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemBaseAddr |0xFE600000|UINT32|0x00010055 -## -## gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType determines the SMBIOS OEM type (0x80 to 0xFF) defined -## in SMBIOS, values 0-0x7F will be treated as disable FWSTS SMBIOS reporting. -## FWSTS structure uses it as SMBIOS OEM type to provide FWSTS information. -## -#gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType|0xDB|UINT8|0x00010047 + gSiPkgTokenSpaceGuid.PcdSleEnable |FALSE|BOOLEAN|0xF0000007 gPlatformTokenSpaceGuid.PcdUseRxTxMultiCastRegisters|FALSE|BOOLEAN|0x10000002 @@ -624,8 +614,7 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43, gSiPkgTokenSpaceGuid.PcdHardwareLocalSemaphores|FALSE|BOOLEAN|0xF0000012 -### [PcdsFixedAtBuild, PcdsPatchableInModule] -[PcdsFixedAtBuild,PcdsPatchableInModule,PcdsDynamic, PcdsDynamicEx] +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] # # SouthCluster # @@ -670,7 +659,7 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43, # VTD PCDs End # -[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx] +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamicEx] # # SouthCluster # @@ -968,7 +957,7 @@ gPeiSmmControlPpiGuid = {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7, 0x43, # gSiPkgTokenSpaceGuid.PcdNumaAcpiDataStaticPointer|0|UINT64|0x5000000E -[PcdsDynamic, PcdsDynamicEx] +[PcdsDynamicEx] gPlatformTokenSpaceGuid.PcdFpgaSwSmiInputValue|0|UINT8|0x30000007 gPlatformTokenSpaceGuid.PcdPlatformType|0x00000000|UINT8|0x3000004A gPlatformTokenSpaceGuid.ReservedB|FALSE|BOOLEAN|0x6000001D -- 2.27.0.windows.1 |
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[edk2-platforms][PATCH V2 2/5] WhitleySiliconPkg/Interfaces: Update to Server-RC-0.2.2.003a
Isaac Oram
This updates IIO interface adding AltAttenTable and the corresponding
PCD and defaults. Adds HideWriteDataParityLogs. Updates PCD defaults for a variety of settings. Removes Dynamic PCD options in favor of DynamicEx only. Cc: Chasel Chiu <chasel.chiu@...> Cc: Nate DeSimone <nathaniel.l.desimone@...> Signed-off-by: Isaac Oram <isaac.w.oram@...> --- Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc | 271 +++++++++++++------- Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec | 2 +- Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h | 1 + Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h | 1 + 4 files changed, 181 insertions(+), 94 deletions(-) diff --git a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc index e356c917fe..0e00a72fcd 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc +++ b/Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc @@ -1088,6 +1088,7 @@ gStructPcdTokenSpaceGuid.PcdSetup.Gen34ReEqualization|0x1 gStructPcdTokenSpaceGuid.PcdSetup.Gen34TimeWindow|0x2 # Time Window (Gen3/4) gStructPcdTokenSpaceGuid.PcdSetup.Gen3LinkDegradation|0x1 # Gen3 Link Degradation gStructPcdTokenSpaceGuid.PcdSetup.Gen4LinkDegradation|0x1 # Gen4 Link Degradation +gStructPcdTokenSpaceGuid.PcdSetup.HideWriteDataParityLogs|0x1 # Hide Data Parity Error Logs gStructPcdTokenSpaceGuid.PcdSetup.IioDmaErrorEn|0x1 # IIO Dma Error gStructPcdTokenSpaceGuid.PcdSetup.IioDmiErrorEn|0x1 # IIO Dmi Error gStructPcdTokenSpaceGuid.PcdSetup.IioErrRegistersClearEn|0x1 # IIO Error Registers Clear @@ -1540,6 +1541,90 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[81]|0x0 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[82]|0x0 # ACPI PME Interrupt gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ACPIPMEn[83]|0x0 # ACPI PME Interrupt gStructPcdTokenSpaceGuid.PcdSocketIioConfig.ATS|0x1 # ATS +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[0]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[1]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[2]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[3]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[4]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[5]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[6]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[7]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[8]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[9]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[10]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[11]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[12]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[13]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[14]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[15]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[16]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[17]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[18]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[19]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[20]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[21]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[22]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[23]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[24]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[25]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[26]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[27]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[28]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[29]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[30]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[31]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[32]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[33]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[34]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[35]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[36]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[37]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[38]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[39]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[40]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[41]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[42]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[43]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[44]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[45]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[46]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[47]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[48]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[49]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[50]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[51]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[52]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[53]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[54]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[55]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[56]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[57]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[58]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[59]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[60]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[61]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[62]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[63]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[64]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[65]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[66]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[67]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[68]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[69]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[70]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[71]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[72]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[73]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[74]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[75]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[76]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[77]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[78]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[79]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[80]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[81]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[82]|0x0 # Alt ATTEN Table +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.AltAttenTable[83]|0x0 # Alt ATTEN Table gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[0]|0x1 # DMA gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[1]|0x1 # DMA gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Cb3DmaEn[2]|0x1 # DMA @@ -5089,8 +5174,8 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[80]|0x0 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[81]|0x0 # P2P Memory Read gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[82]|0x0 # P2P Memory Read gStructPcdTokenSpaceGuid.PcdSocketIioConfig.P2PRdDis[83]|0x0 # P2P Memory Read -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCIe_AtomicOpReq|0x1 # PCIe Atomic Operation Request Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCIe_LTR|0x2 # PCIe Latency Tolerance Reporting +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCIe_AtomicOpReq|0x2 # PCIe Atomic Op Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCIe_LTR|0x2 # PCIe LTR Support gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PCUF6Hide|0x0 # Hide PCU Func 6 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[1]|0x0 # Hide Port? gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[2]|0x0 # Hide Port? @@ -5176,7 +5261,7 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[81]|0x0 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[82]|0x0 # Hide Port? gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PEXPHIDE[83]|0x0 # Hide Port? gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Pci64BitResourceAllocation|0x1 # PCI 64-Bit Resource Allocation -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Pcie10bitTag|0x1 # PCIe 10-bit Tag Enable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.Pcie10bitTag|0x2 # PCIe 10-bit Tag Enable gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[0]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack1 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[1]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack2 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICEnabled[2]|0x0 # Intel� AIC Retimer/AIC SSD HW at Stack3 @@ -5299,90 +5384,90 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[78]|0x0 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAICPortEnable[79]|0x0 # Port 5D gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAcpiHotPlugEnable|0x0 # PCIe ACPI Hot Plug gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAllocatingFlow|0x1 # PCIe Allocating Write Flows -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[0]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[1]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[2]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[3]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[4]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[5]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[6]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[7]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[8]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[9]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[10]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[11]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[12]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[13]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[14]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[15]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[16]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[17]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[18]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[19]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[20]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[21]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[22]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[23]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[24]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[25]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[26]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[27]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[28]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[29]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[30]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[31]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[32]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[33]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[34]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[35]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[36]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[37]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[38]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[39]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[40]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[41]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[42]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[43]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[44]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[45]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[46]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[47]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[48]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[49]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[50]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[51]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[52]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[53]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[54]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[55]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[56]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[57]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[58]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[59]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[60]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[61]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[62]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[63]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[64]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[65]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[66]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[67]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[68]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[69]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[70]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[71]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[72]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[73]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[74]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[75]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[76]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[77]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[78]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[79]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[80]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[81]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[82]|0x2 # PCI-E ASPM Support -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[83]|0x2 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[0]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[1]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[2]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[3]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[4]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[5]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[6]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[7]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[8]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[9]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[10]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[11]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[12]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[13]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[14]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[15]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[16]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[17]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[18]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[19]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[20]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[21]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[22]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[23]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[24]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[25]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[26]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[27]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[28]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[29]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[30]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[31]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[32]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[33]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[34]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[35]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[36]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[37]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[38]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[39]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[40]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[41]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[42]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[43]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[44]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[45]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[46]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[47]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[48]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[49]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[50]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[51]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[52]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[53]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[54]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[55]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[56]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[57]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[58]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[59]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[60]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[61]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[62]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[63]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[64]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[65]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[66]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[67]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[68]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[69]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[70]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[71]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[72]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[73]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[74]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[75]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[76]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[77]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[78]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[79]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[80]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[81]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[82]|0x4 # PCI-E ASPM Support +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieAspm[83]|0x4 # PCI-E ASPM Support gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieBiosTrainEnable|0x1 # PCIe Train by BIOS gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[0]|0x1 # PCI-E Port Clocking gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieCommonClock[1]|0x1 # PCI-E Port Clocking @@ -5636,7 +5721,7 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[80 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[81]|0x1 # Data Link Feature Exchange gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[82]|0x1 # Data Link Feature Exchange gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieDataLinkFeatureExchangeEnable[83]|0x1 # Data Link Feature Exchange -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieExtendedTagField|0x1 # PCIe Extended Tag Enable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieExtendedTagField|0x2 # PCIe Extended Tag Support gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieGlobalAspm|0x1 # PCI-E ASPM Support (Global) gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugEnable|0x0 # PCIe Hot Plug gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieHotPlugOnPort[1]|0x2 # Hot Plug Capable @@ -6311,7 +6396,7 @@ gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[80]|0x0 gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[81]|0x0 # Link Speed gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[82]|0x0 # Link Speed gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePortLinkSpeed[83]|0x0 # Link Speed -gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePtm|0x0 # PCIe PTM Enable +gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PciePtm|0x2 # PCIe PTM Support gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieRelaxedOrdering|0x1 # Pcie Relaxed Ordering gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotItemCtrl|0x0 # PCIe Slot Item Control gStructPcdTokenSpaceGuid.PcdSocketIioConfig.PcieSlotOprom1|0x1 # PCIe Slot 1 OpROM @@ -7570,7 +7655,7 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SetMemTested|0x1 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.ShortStroke2GB|0x0 # 2GB Short Stroke Configuration gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SmartTestKey|0x0 # SmartTestKey gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SmbSpdAccess|0x0 # SPD-SMBUS Access -gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SpareSwErrTh|0x4 # Sparing SW Error Match Threshold +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SpareSwErrTh|0x4 # SW Per Bank Threshold gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SpdPrintEn|0x0 # SPD Print gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.SpdPrintLength|0x0 # SPD Print Length gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.Srat|0x1 # Publish SRAT @@ -7705,7 +7790,7 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.partialmirrorsize[3]|0x0 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pda|0x1 # PDA gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pprErrInjTest|0x0 # PPR Error Injection test gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.pprType|0x2 # PPR Type -gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.promoteMrcWarnings|0x1 # MRC Promote Warnings +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.promoteMrcWarnings|0x0 # MRC Promote Warnings gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.promoteWarnings|0x1 # Promote Warnings gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.readVrefCenter|0x1 # Read Vref Centering gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.refreshMode|0x2 # 2x Refresh Enable @@ -7761,11 +7846,11 @@ gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tRTP|0x0 gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tWR|0x0 # tWR gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.tWTR|0x0 # tWTR gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.thermalthrottlingsupport|0x2 # Throttling Mode -gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.timeWindow|0x0 # Correctable Error Time Window +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.timeWindow|0x18 # SW Correctable Error Time Window gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.turnaroundOpt|0x1 # Turnaround Time Optimization gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.turnaroundOptDdrt|0x1 # Turnaround Time Optimization PMem gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.txEqCalibration|0x1 # Tx Eq Training -gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.volMemMode|0x1 # Volatile Memory Mode +gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.volMemMode|0x0 # Volatile Memory Mode gStructPcdTokenSpaceGuid.PcdSocketMemoryConfig.wrVrefCenter|0x1 # Write Vref Centering gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[0]|0x1 # Bus Resources Allocation Ratio gStructPcdTokenSpaceGuid.PcdSocketMpLinkConfig.BusRatio[1]|0x1 # Bus Resources Allocation Ratio diff --git a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec index 91eace9aa0..3a6d87dd7f 100644 --- a/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec +++ b/Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec @@ -251,7 +251,7 @@ gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Major|0 gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Minor|2 gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.Revision|2 - gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x0033 + gEfiCpRcPkgTokenSpaceGuid.PcdRcVersion.BuildNumber|0x003a # # MRC DEFAULT SETTINGS diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h index 7df44e93c3..a820cc6c25 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h @@ -437,6 +437,7 @@ typedef struct { UINT8 VtdPciAcsCtlBit2; UINT8 VtdPciAcsCtlBit3; UINT8 VtdPciAcsCtlBit4; + UINT8 AltAttenTable[TOTAL_PORTS_VAR]; //On Setup } SOCKET_IIO_CONFIGURATION; #pragma pack() diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h b/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h index df11dda735..a8e3e69255 100644 --- a/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h +++ b/Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h @@ -379,6 +379,7 @@ typedef struct { UINT8 DisPMETOAck[MAX_TOTAL_PORTS]; UINT8 ACPIHP[MAX_TOTAL_PORTS]; UINT8 ACPIPM[MAX_TOTAL_PORTS]; + UINT8 AltAttenTable[MAX_TOTAL_PORTS]; UINT8 SRIS[MAX_TOTAL_PORTS]; UINT8 TXEQ[MAX_TOTAL_PORTS]; UINT8 EcrcGenEn[MAX_TOTAL_PORTS]; -- 2.27.0.windows.1 |
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[edk2-platforms][PATCH V2 1/5] WhitleyOpenBoardPkg/Smbios: Add SMBIOS PCD
Isaac Oram
This adds PCD that need to be produced by the board port to properly
populate the FvOpenBoardPkg SMBIOS support and generate reasonable SMBIOS tables. Cc: Chasel Chiu <chasel.chiu@...> Cc: Nate DeSimone <nathaniel.l.desimone@...> Signed-off-by: Isaac Oram <isaac.w.oram@...> --- Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 107 ++++++++++++++++++++ Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 5 +- 2 files changed, 110 insertions(+), 2 deletions(-) diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec index 8e0b674505..fb4383d484 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec @@ -47,6 +47,7 @@ #OEM SKU gOemSkuTokenSpaceGuid = { 0x9e37d253, 0xabf8, 0x4985, { 0x8e, 0x23, 0xba, 0xca, 0x10, 0x39, 0x56, 0x13 } } gPlatformKtiEparamUpdateDataGuid = { 0x7bc065cf, 0xafe8, 0x4396, { 0xae, 0x9f, 0xba, 0x27, 0xdf, 0xbe, 0xcf, 0x3d } } + gSmbiosTablesTokenSpaceGuid = { 0x5e80ad48, 0xf240, 0x4fe9, { 0x87, 0xef, 0x4b, 0x46, 0xf4, 0xde, 0x78, 0xa0 } } gPlatformGpioInitDataGuid = { 0x9282563e, 0xae17, 0x4e12, { 0xb1, 0xdc, 0x7, 0xf, 0x29, 0xf3, 0x71, 0x20 } } # # UBA_END @@ -250,6 +251,7 @@ ## This value is used to save memory address of MRC data structure. gPlatformTokenSpaceGuid.PcdBoardTypeBitmask|0x00000000|UINT32|0x30000041 + gPlatformTokenSpaceGuid.PcdHalfWidth|FALSE|BOOLEAN|0x30000042 # # IMR0 programming values @@ -289,6 +291,93 @@ # FALSE - Disable Intel(R) TXT feature on the platform gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable | TRUE|BOOLEAN|0x3000000f + # + # SMBIOS Type 0 - BIOS Information + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVendor|"TBD"|VOID*|0x5B000000 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosVersion|"TBD"|VOID*|0x5B000001 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBiosReleaseDate|"TBD"|VOID*|0x5B000002 + + # + # SMBIOS Type 1 - System Information + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemManufacturer|"TBD"|VOID*|0x5B010000 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemProductName|"TBD"|VOID*|0x5B010001 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemVersion|"TBD"|VOID*|0x5B010002 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSerialNumber|"TBD"|VOID*|0x5B010003 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemSkuNumber|"TBD"|VOID*|0x5B010004 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemFamily|"TBD"|VOID*|0x5B010005 + + # + # SMBIOS Type 2 - Base Board (or Module) Information + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardManufacturer|"TBD"|VOID*|0x5B020000 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardProductName|"TBD"|VOID*|0x5B020001 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardVersion|"TBD"|VOID*|0x5B020002 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardSerialNumber|"TBD"|VOID*|0x5B020003 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardAssetTag|"TBD"|VOID*|0x5B020004 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesBaseBoardLocationInChassis|"TBD"|VOID*|0x5B020005 + + # + # SMBIOS Type 3 - System Enclosure or Chassis Information + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisManufacturer|"TBD"|VOID*|0x5B030000 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisVersion|"TBD"|VOID*|0x5B030001 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSerialNumber|"TBD"|VOID*|0x5B030002 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisAssetTag|"TBD"|VOID*|0x5B030003 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesChassisSkuNumber|"TBD"|VOID*|0x5B030004 + + # + # SMBIOS Type 11 - OEM Strings + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesOemString1|"TBD"|VOID*|0x5B0B0001 + + # + # SMBIOS Type 12 - System Configuration Options + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSysConfigOption1|"TBD"|VOID*|0x5B0C0001 + + # + # SMBIOS Type 14 - Group Associations + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTableType|0xDD|UINT8|0x5B0D0001 + + # + # SMBIOS Type 17 - Memory Device + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesMemorySerialNumberFormat|0x00|UINT8|0x5B110000 + + # + # SMBIOS Type 27 - Cooling Device + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesCoolingDeviceDescription|"TBD"|VOID*|0x5B1B0000 + + # + # SMBIOS Type 28 - Temperature Probe + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesTemperatureProbeDescription|"TBD"|VOID*|0x5B1C0000 + + # + # SMBIOS Type 34 - Management Device + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceDescription|"TBD"|VOID*|0x5B220000 + + # + # SMBIOS Type 35 - Management Device Component + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesManagementDeviceComponentDescription|"TBD"|VOID*|0x5B230000 + + # + # SMBIOS Type 39 - System Power Supply + # + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyLocation|"TBD"|VOID*|0x5B270000 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyDeviceName|"TBD"|VOID*|0x5B270001 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyManufacturer|"TBD"|VOID*|0x5B270002 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplySerialNumber|"TBD"|VOID*|0x5B270003 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyAssetTagNumber|"TBD"|VOID*|0x5B270004 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyModelPartNumber|"TBD"|VOID*|0x5B270005 + gSmbiosTablesTokenSpaceGuid.PcdSmbiosTablesSystemPowerSupplyRevisionLevel|"TBD"|VOID*|0x5B270006 + [PcdsFeatureFlag] gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE|BOOLEAN|0x00000020 @@ -366,6 +455,24 @@ gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID|0x0|UINT16|0x00000008 gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmSize|0x100|UINT32|0x00000009 +# Form factor is MemoryFormFactorDimm by default +# MemoryFormFactorOther = 0x01 +# MemoryFormFactorUnknown = 0x02 +# MemoryFormFactorSimm = 0x03 +# MemoryFormFactorSip = 0x04 +# MemoryFormFactorChip = 0x05 +# MemoryFormFactorDip = 0x06 +# MemoryFormFactorZip = 0x07 +# MemoryFormFactorProprietaryCard = 0x08 +# MemoryFormFactorDimm = 0x09 +# MemoryFormFactorTsop = 0x0A +# MemoryFormFactorRowOfChips = 0x0B +# MemoryFormFactorRimm = 0x0C +# MemoryFormFactorSodimm = 0x0D +# MemoryFormFactorSrimm = 0x0E +# MemoryFormFactorFbDimm = 0x0F +# MemoryFormFactorDie = 0x10 + gOemSkuTokenSpaceGuid.PcdOemSkuMemDevFormFactor|0x09|UINT8|0x10000010 # # USB diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc index dc3dd0e026..f0a83fffd1 100644 --- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc +++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc @@ -649,8 +649,9 @@ # Beware of circular dependencies on PCD if you want to use another DebugLib instance. # PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf - NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNull.inf # Include FSP DynamicEx PCD - NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateSilicon.inf # Include FvLateSilicon DynamicEx PCD + NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNull.inf # Include FSP DynamicEx PCD + NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateSilicon.inf # Include FvLateSilicon DynamicEx PCD + NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateOpenBoard.inf # Include FvLateBoard DynamicEx PCD } $(RP_PKG)/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf $(RP_PKG)/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf -- 2.27.0.windows.1 |
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[edk2-platforms][PATCH V2 0/5] WhitleyOpenBoardPkg: Enable VT-D support
Isaac Oram
This patch series enables VT-D support in the WhitleyOpenBoardPkg.
For the initial patch, I missed that there was a different AcpiPlatform driver required. This patch series incorporates that requirement and the additional changes that requires. The AcpiPlatform driver leverages SMBIOS and the AcpiVtd driver to update ACPI tables ultimately providing the VT-D support. The original V1 patch for VT-D has been updated to match file naming convention (VTD to Vtd) and to match the proprietary binary signature format used. This complete support for VT-D is accomplished by: Including additional SMBIOS support in FvLateOpenBoard.fv Including additional ACPI table support in FvLateOpenBoard.fv Including proprietary AcpiPlatform driver in FvLateOpenBoard.fv Updating to FSP 2.2.0.3A where the additional FvLateOpenBoard content is present Adding FvLateOpenBoard.fv DynamicEx PCD support Adding open source AcpiVtd driver to patch ACPI tables called by AcpiPlatform. SMBIOS table content is customizable via DynamicEx PCD added. Cc: Chasel Chiu <chasel.chiu@...> Cc: Nate DeSimone <nathaniel.l.desimone@...> Cc: Harikrishna Doppalapudi <harikrishnad@...> Cc: Manish Jha <manishj@...> Cc: Manickavasakam Karpagavinayagam <manickavasakamk@...> Signed-off-by: Isaac Oram <isaac.w.oram@...> Isaac Oram (4): WhitleyOpenBoardPkg/Smbios: Add SMBIOS PCD WhitleySiliconPkg/Interfaces: Update to Server-RC-0.2.2.003a WhitleySiliconPkg/Interfaces: Remove PcdsDynamic use. WhitleyOpenBoardPkg/Acpi: Use binary AcpiPlatform driver Oram, Isaac W (1): WhitleyOpenBoardPkg: Enable VT-D support Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.c | 604 ++++++++++++++++++++ Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf | 66 +++ Platform/Intel/WhitleyOpenBoardPkg/Include/AcpiVtd.h | 53 ++ Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/DmaRemap.h | 109 ++++ Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 111 ++++ Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc | 10 +- Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.fdf | 3 +- Platform/Intel/WhitleyOpenBoardPkg/StructurePcd.dsc | 271 ++++++--- Silicon/Intel/WhitleySiliconPkg/CpRcPkg.dec | 6 +- Silicon/Intel/WhitleySiliconPkg/Cpu/CpuRcPkg.dec | 2 +- Silicon/Intel/WhitleySiliconPkg/Include/Guid/SocketIioVariable.h | 1 + Silicon/Intel/WhitleySiliconPkg/Include/IioConfig.h | 1 + Silicon/Intel/WhitleySiliconPkg/Include/IioSetupDefinitions.h | 4 + Silicon/Intel/WhitleySiliconPkg/SiliconPkg.dec | 19 +- 14 files changed, 1140 insertions(+), 120 deletions(-) create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.c create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/AcpiVtd.h create mode 100644 Platform/Intel/WhitleyOpenBoardPkg/Include/Protocol/DmaRemap.h -- 2.27.0.windows.1 |
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Re: [PATCH 5/5] Platform/RaspberryPi: Disconnect/shutdown all drivers before reboot
Ard Biesheuvel
On Tue, 5 Oct 2021 at 23:25, Jeremy Linton <jeremy.linton@...> wrote:
Works for me. MicroSecondDelay (Delay); |
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Re: [PATCH 5/5] Platform/RaspberryPi: Disconnect/shutdown all drivers before reboot
Jeremy Linton
Hi,
On 10/5/21 5:11 AM, Ard Biesheuvel wrote: On Sat, 2 Oct 2021 at 02:52, Jeremy Linton <jeremy.linton@...> wrote:Sure.STATIC if (EFI_ERROR (Status)) {Yup Which makes the above bits about failure returns sorta redundant as I should probably just make DisconnectAll() void. There isn't really anything to do with a failed return other than print a message and ignore it.+}Capture Status here and ASSERT_EFI_ERROR() ?? MicroSecondDelay (Delay); |
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Re: [PATCH 2/5] Platform/RaspberryPi: Expand locking to cover return data
Jeremy Linton
Hi,
On 10/5/21 5:12 AM, Ard Biesheuvel wrote: On Sat, 2 Oct 2021 at 02:52, Jeremy Linton <jeremy.linton@...> wrote:Sure. Is it whitespace, or general conflicts? I noticed that groups.io's web UI looked like I had MIME linebreaks sprinked through my patch despite specifying 8bit ASCII. I flirted with 7-bit ASCII with some of the previous patches, but its pretty clear that the arm foss server is mangling what it thinks are MIME emails and putting cr/lf's changes its behavior a bit.This fails to apply for me - can you rebase onto the last Let me try and force the 7bit again, which git rejects if it finds utf in the files (and a few of them had it in the past <sigh>). --- |
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Re: [PATCH v3 12/28] AmpereAltraPkg: Add Ac01PcieLib library instance
Leif Lindholm
On Mon, Oct 04, 2021 at 19:03:40 +0700, Nhi Pham wrote:
Hi Leif,It's still a little bit awkward, but if that's the only way to get debug out of PCYLib... So, I'm assuming this PHYLib is a library shared across multipleSeems above. This wrapper function is to conform with the function prototype+VOIDNo, use MicroSecondDelay directly. codebases? Would it be possible for PHYLib to link in ArmArchTimerLib directly and wrap this there instead? Something about this integration just feels kind of backwards to me. Because we now have (sort of) an undocumented dircular dependency: this driver declares a dependency of PciePhyLib, but that library needs to be manually initialized by this driver. / Leif |
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Re: Mergify is no longer auto closing personal Github PRs
Michael D Kinney
Hi Rebecca,
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Yes. This is the new behavior after changes were added in July 9, 2021. https://github.com/tianocore/edk2/commit/b491eace373ea3fa435a0136db3c38e0360e6f11#diff-a3528dea46dcf4932a9c3dfdd1a9e320daeed9256f3906d4174915470add4189 .mergify: Simplify Mergify rules using GitHub status checks * Enable Mergify queue feature to support auto rebase when 'push' label is set and gauarntee that all EDK II CI checks are run before merging in changes with linear history. * Use status checks configured in GitHub branch protections * Allow non EDK II Maintainers to create a PR Requires an EDK II Maintainer to accept the change and request merge by adding 'push' label. Only EDK II Maintainers have ability to set/clear labels. * Do not automatically close PRs for personal builds. Cc: Liming Gao <gaoliming@...> Cc: Sean Brogan <sean.brogan@...> Cc: Bret Barkelew <Bret.Barkelew@...> Signed-off-by: Michael D Kinney <michael.d.kinney@...> Acked-by: Bret Barkelew <bret.barkelew@...> Reviewed-by: Liming Gao <gaoliming@...> Developers that submit personal builds are responsible for closing them if they are no longer required. This allows the same PR to be used if the developer wants to fix issues on the same branch. We will likely have to do periodic review to close PRs that are left open for an extended period of time. Mike -----Original Message----- |
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Re: Python2.7 is not working with the EDK2 build system
Should we move to require a min Python version at some point?
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On Oct 5, 2021, at 9:48 AM, Cole <crobinso@...> wrote: |
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Re: 回复: [edk2-devel] Python2.7 is not working with the EDK2 build system
Cole
On 9/6/21 9:18 PM, gaoliming wrote:
Bob:Sorry for the delayed response, I was on paternity leave since August. I haven't seen the actual error in this thread. Is there a clear python error being thrown? Maybe the fix is simple but I can't But as mentioned elsewhere, python2 has been End of Life since Jan 1 2020, over 1.5 years ago. It's going to become increasingly difficult to keep code working on python2 and latest python3. - Cole |
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Re: [PATCH v1 0/2] ACPI 6.4 SBSA generic watchdog renaming
Sami Mujawar
Merged as 06a326caf125..942c9bd357d8
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Thanks. Regards, Sami Mujawar On 16/08/2021 03:52 PM, Chris Jones wrote:
Bugzilla: 3565 (https://bugzilla.tianocore.org/show_bug.cgi?id=3565) |
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Re: [PATCH v1] DynamicTablesPkg: Update FADT generator to ACPI 6.4
Sami Mujawar
Merged as 862e814de403..06a326caf125
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Thanks. Regards, Sami Mujawar On 17/08/2021 02:50 PM, Chris Jones wrote:
Bugzilla: 3568 (https://bugzilla.tianocore.org/show_bug.cgi?id=3568) |
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Mergify is no longer auto closing personal Github PRs
Rebecca Cran
I noticed that Mergify is no longer auto closing personal builds: for example https://github.com/tianocore/edk2/pull/2026 is still open.
Compare that to https://github.com/tianocore/edk2/pull/1708 where mergify commented "All checks passed. Auto close personal build." -- Rebecca Cran |
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Re: [PATCH V3 00/12] Migrate ArmVirtPkg modules to OvmfPkg
Hi Ard,
This way reduces the impact of MdePkg. We can try it.
Thanks
Abner
From: devel@edk2.groups.io <devel@edk2.groups.io> on behalf of Ard Biesheuvel <ardb@...>
Sent: Tuesday, October 5, 2021 5:30 PM To: edk2-devel-groups-io <devel@edk2.groups.io>; Chang, Abner (HPS SW/FW Technologist) <abner.chang@...> Cc: Ard Biesheuvel <ardb+tianocore@...>; Leif Lindholm <leif@...>; Sami Mujawar <sami.mujawar@...>; Jiewen Yao <jiewen.yao@...>; Jordan Justen <jordan.l.justen@...>; Gerd Hoffmann <kraxel@...>; Schaefer, Daniel <daniel.schaefer@...>; Sunil V L <sunilvl@...>; Liming Gao <gaoliming@...>; Zhiguang Liu <zhiguang.liu@...>; Michael D Kinney <michael.d.kinney@...> Subject: Re: [edk2-devel] [PATCH V3 00/12] Migrate ArmVirtPkg modules to OvmfPkg On Thu, 30 Sept 2021 at 03:43, Abner Chang <abner.chang@...> wrote:
> > In V3: Address comments on V2. > In V2: Remove HPE license on the files that just moved around or > the changes in the file are just code removal. > > edk2 BZ #: 3665 > edk2 platform corresponding changes will be submitted after > this pactch set is reviewed. > > This pacthes set is to migrate some modules from ArmVirtPkg > to under OvmfPkg for the upcoming RiscVVirtPkg that can leverage > those modules without the dependency with Arm*Pkg. > > The modules moved from ArmVirtPkg to OvmfPkg are, > - FdtClientDxe > - PciPcdProducerLib > - HighMemDxe > - QemuFwCfgLib > - FdtPciHostBridgeLib > - VirtioFdtDxe > > Below PCDs are moved to under MdePkg and leverage by RiscVVirtPkg. > This change also remove the dependency on ArmPkg of OvmfPkg. > - PcdPciIoTranslation > - PcdPciIoTranslation > - PcdPciMmio32(64)Translation > > Signed-off-by: Abner Chang <abner.chang@...> > Cc: Ard Biesheuvel <ardb+tianocore@...> > Cc: Leif Lindholm <leif@...> > Cc: Sami Mujawar <sami.mujawar@...> > Cc: Jiewen Yao <jiewen.yao@...> > Cc: Jordan Justen <jordan.l.justen@...> > Cc: Gerd Hoffmann <kraxel@...> > Cc: Daniel Schaefer <daniel.schaefer@...> > Cc: Sunil V L <sunilvl@...> > Cc: Liming Gao <gaoliming@...> > Cc: Zhiguang Liu <zhiguang.liu@...> > Cc: Michael D Kinney <michael.d.kinney@...> > > Abner Chang (12): > ArmVirtPkg/FdtClintDxe: Move FdtClientDxe to EmbeddedPkg > MdePkg: Add PcdPciIoTranslation PCD > ArmPkg: Use PcdPciIoTranslation PCD from MdePkg > ArmVirtPkg/FdtPciPcdProducerLib: Relocate PciPcdProducerLib to OvmfPkg > ArmVirtPkg/HighMemDxe: Relocate HighMemDxe to OvmfPkg > OvmfPkg/HighMemDxe: Add RISC-V in the supported arch. > ArmVirtPkg/QemuFwCfgLib: Relocate QemuFwCfgLib to OvmfPkg > OvmfPkg/QemuFwCfgLibMMIO: Add RISC-V arch support > MdePkg: Add PcdPciMmio32(64)Translation PCDs > ArmVirtPkg/FdtPciHostBridgeLib: Relocate FdtPciHostBridgeLib to > OvmfPkg/Fdt > OvmfPkg/FdtPciHostBridgeLib: Add RISC-V in the supported arch. > ArmVirtPkg/VirtioFdtDxe: Relocate VirtioFdtDxe to OvmfPkg/Fdt > Hello all, These patches look ok to me, but I wonder if the MdePkg maintainers are happy taking these PCD declaration changes. Translations for PCIe are typically defined per host bridge, and I would rather move away from using PCDs for this entirely than 'promote' them by carrying them in MdePkg. As this issue is somewhat orthogonal to what Abner is trying to fix, perhaps it is better to avoid MdePkg changes for now, and just duplicate these PCDs into OvmfPkg. This is reasonable, given that we know that QEMU only exposes a single host bridge. The one in ArmPkg can hopefully be removed and replaced with something that is more appropriate. > ArmPkg/ArmPkg.dec | 15 ++++++-------- > ArmVirtPkg/ArmVirtPkg.dec | 3 --- > EmbeddedPkg/EmbeddedPkg.dec | 1 + > MdePkg/MdePkg.dec | 12 +++++++++++ > ArmVirtPkg/ArmVirtCloudHv.dsc | 18 ++++++++--------- > ArmVirtPkg/ArmVirtKvmTool.dsc | 18 ++++++++--------- > ArmVirtPkg/ArmVirtQemu.dsc | 20 +++++++++---------- > ArmVirtPkg/ArmVirtQemuKernel.dsc | 20 +++++++++---------- > ArmVirtPkg/ArmVirtXen.dsc | 2 +- > EmbeddedPkg/EmbeddedPkg.dsc | 1 + > ArmVirtPkg/ArmVirtCloudHv.fdf | 6 +++--- > ArmVirtPkg/ArmVirtKvmTool.fdf | 6 +++--- > ArmVirtPkg/ArmVirtXen.fdf | 2 +- > ArmVirtPkg/ArmVirtQemuFvMain.fdf.inc | 6 +++--- > .../ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf | 2 +- > .../ArmVirtGicArchLib/ArmVirtGicArchLib.inf | 1 + > .../ArmVirtPL031FdtClientLib.inf | 1 + > .../ArmVirtPsciResetSystemLib.inf | 1 + > .../ArmVirtTimerFdtClientLib.inf | 1 + > .../KvmtoolRtcFdtClientLib.inf | 1 + > .../NorFlashKvmtoolLib/NorFlashKvmtoolLib.inf | 1 + > .../NorFlashQemuLib/NorFlashQemuLib.inf | 1 + > .../XenAcpiPlatformDxe/XenAcpiPlatformDxe.inf | 1 + > ArmVirtPkg/XenioFdtDxe/XenioFdtDxe.inf | 1 + > .../Drivers}/FdtClientDxe/FdtClientDxe.inf | 1 - > .../FdtPciHostBridgeLib.inf | 11 +++++----- > .../FdtPciPcdProducerLib.inf | 5 ++--- > .../Fdt}/HighMemDxe/HighMemDxe.inf | 7 ++++--- > .../Fdt}/VirtioFdtDxe/VirtioFdtDxe.inf | 2 +- > .../Library/QemuFwCfgLib/QemuFwCfgLibMmio.inf | 6 +++--- > .../Include/Protocol/FdtClient.h | 0 > .../Drivers}/FdtClientDxe/FdtClientDxe.c | 0 > .../FdtPciHostBridgeLib/FdtPciHostBridgeLib.c | 0 > .../FdtPciPcdProducerLib.c | 0 > .../Fdt}/HighMemDxe/HighMemDxe.c | 3 ++- > .../Fdt}/VirtioFdtDxe/VirtioFdtDxe.c | 0 > .../Library/QemuFwCfgLib/QemuFwCfgLibMmio.c | 7 ++++--- > Maintainers.txt | 6 ++++++ > 38 files changed, 106 insertions(+), 83 deletions(-) > rename {ArmVirtPkg => EmbeddedPkg/Drivers}/FdtClientDxe/FdtClientDxe.inf (92%) > rename {ArmVirtPkg/Library => OvmfPkg/Fdt}/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf (77%) > rename {ArmVirtPkg/Library => OvmfPkg/Fdt}/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf (87%) > rename {ArmVirtPkg => OvmfPkg/Fdt}/HighMemDxe/HighMemDxe.inf (83%) > rename {ArmVirtPkg => OvmfPkg/Fdt}/VirtioFdtDxe/VirtioFdtDxe.inf (92%) > rename ArmVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf => OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibMmio.inf (86%) > rename {ArmVirtPkg => EmbeddedPkg}/Include/Protocol/FdtClient.h (100%) > rename {ArmVirtPkg => EmbeddedPkg/Drivers}/FdtClientDxe/FdtClientDxe.c (100%) > rename {ArmVirtPkg/Library => OvmfPkg/Fdt}/FdtPciHostBridgeLib/FdtPciHostBridgeLib.c (100%) > rename {ArmVirtPkg/Library => OvmfPkg/Fdt}/FdtPciPcdProducerLib/FdtPciPcdProducerLib.c (100%) > rename {ArmVirtPkg => OvmfPkg/Fdt}/HighMemDxe/HighMemDxe.c (95%) > rename {ArmVirtPkg => OvmfPkg/Fdt}/VirtioFdtDxe/VirtioFdtDxe.c (100%) > rename ArmVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.c => OvmfPkg/Library/QemuFwCfgLib/QemuFwCfgLibMmio.c (93%) > > -- > 2.17.1 > > > > > > |
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Re: [PATCH v1 12/13] DynamicTablesPkg: Add CM_ARM_LPI_INFO object
Sami Mujawar
Hi Pierre,
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Thank you for this patch. Reviewed-by: Sami Mujawar <sami.mujawar@...> Regards, Sami Mujawar On 23/06/2021 12:40 PM, Pierre.Gondois@... wrote:
From: Pierre Gondois <Pierre.Gondois@...> |
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Re: [PATCH v1 13/13] DynamicTablesPkg: SSDT CPU topology and LPI state generator
Sami Mujawar
Hi Pierre,
I ahve a few minor suggestions marked inline as [SAMI]. With those changed. Reviewed-by: Sami Mujawar <sami.mujawar@...> Regards, Sami Mujawar On 23/06/2021 12:40 PM, Pierre.Gondois@... wrote: From: Pierre Gondois <Pierre.Gondois@...>[SAMI] I think the DBG2 header is not required here. Can you check this and if any other includes below can be removed, please? +#include <Library/AcpiLib.h>[SAMI] I think the LPI information should be marked as (OPTIONAL). +*/[SAMI] I think it would be good to use MAX_UINT32 instead of -1 here. Same for the if condition a few lines below. +[SAMI] I think this macro should be renamed to MAX_NODE_COUNT. +[SAMI] Please remove unused sections. + |
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