Hi Ling,

Many thanks for this.
I have accrued a huge review backlog, but I hope to be able to have a
look at this set before the end of this week.

Best Regards,

Leif

On August 20, 2021 3:23 PM, Gerd Hoffmann wrote:

On Thu, Aug 19, 2021 at 02:27:16PM +0000, Min Xu wrote:

On August 19, 2021 2:50 PM, Gerd Hoffmann wrote:

+/**
+ In Tdx guest, some information need to be passed from host VMM
+to

guest

+ firmware. For example, the memory resource, etc. These
+ information are prepared by host VMM and put in HobList which
+ is described in

TdxMetadata.

What kind of information is passed to the guest here?

Please see

https://software.intel.com/content/dam/develop/external/us/en/document

s/tdx-virtual-firmware-design-guide-rev-1.pdf
Section 4.2 TD Hand-Off Block (HOB)

So basically the physical memory map.
qemu has etc/e820 for that.

qemu has fw_cfg to pass information from the VMM to the guest

firmware.

What are the reasons to not use fw_cfg?

Not all the VMM support fw_cfg. Cloud-Hypervisor is the example.

I can't see any support for Cloud-Hypervisor in OVMF.

Right that currently OVMF is not supported by Cloud-Hypervisor in Td guest. But we're
planning to support Cloud-Hypervisor to launch OVMF in Td guest and have done
some POC.

Also FreeBSD's bhyve doesn't support fw_cfg either and has its own ways to
detect memory. Cloud-Hypervisor can surely do that too.

So, why does this matter?

Yes, Cloud-Hypervisor has some POC to launch OVMF in Non-Td guest. In that POC
Cloud-Hypervisor leverage a 4k page in MEMFD and pass ACPI data to guest
Firmware in that memory.
https://github.com/cloud-hypervisor/edk2 "ch" branch
https://github.com/cloud-hypervisor/edk2/commit/52cb72a748ef70833100ca664f6c2a704c28a93f

https://github.com/cloud-hypervisor/cloud-hypervisor
TD Hob list gives Cloud-Hypervisor a chance to pass information to guest

firmware.

For example, ACPI can be downloaded from QEMU via fw_cfg to firmware.
But Cloud-Hypervisor cannot pass ACPI via fw_cfg. In this situation,
TD Hob can resolve this problem.

Sure, but again, why does this matter? For qemu?

I don't quite understand the question here(For qumu?).
What I mean in my last answer is that TD Hob can resolve the problem when the host VMM
doesn't support fw_cfg communication mechanism.
For the host VMMs which doesn't support fw_cfg, when ACPI data need to be passed to guest
firmware, a 4k page (to hold ACPI data) is added in MEMFD. Then when SMBIOS is needed,
shall we add another page in MEMFD? If the ACPI data is too big to be held in a 4k page, then
the size of the reserved memory region in MEMFD is the restriction.

I don't like the idea to have TDX take a completely different code paths.
That increases the code complexity and makes testing harder for no good
reason.

TD Hob is not a completely different code path. This is a useful supplement to the fw_cfg which
is not supported by some host VMM.
From another perspective TD Hob can be treated as a set of launch parameter by host VMM.
It provides the flexibility for the host VMM to bring up the guest firmware with more parameters.
Another benefit is that TD Hob can be measured into some secure register (for example, in TD guest
it is RTMR registers, like the TPM PCR) so that attestation can be done based on the measurement.

Thanks Gerd for the comments. I am not sure if my explanation addressed your concern. Your comments
is always welcomed.

Thanks!
Min

Modify my role to be one of the EHL maintainers.

Signed-off-by: jinjhuli <jin.jhu.lim@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Sai Chaganty <rangasai.v.chaganty@...>
---
Maintainers.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Maintainers.txt b/Maintainers.txt
index d5865ba..b8a4140 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -56,7 +56,7 @@ M: Sai Chaganty <rangasai.v.chaganty@...>
Silicon/Intel/ElkhartlakeSiliconBinPkg
M: Nate DeSimone <nathaniel.l.desimone@...>
M: Sai Chaganty <rangasai.v.chaganty@...>
-R: Jin Jhu Lim <jin.jhu.lim@...>
+M: Jin Jhu Lim <jin.jhu.lim@...>

Silicon/Intel/KabylakeSiliconBinPkg
M: Chasel Chiu <chasel.chiu@...>
--
2.28.0.windows.1

On Tue, 24 Aug 2021 at 08:00, Marcin Wojtas <mw@...> wrote:

Hi Ard,

śr., 11 sie 2021 o 12:58 Marcin Wojtas <mw@...> napisał(a):

Hi Ard,

śr., 11 sie 2021 o 12:42 Ard Biesheuvel <ardb@...> napisał(a):

On Wed, 11 Aug 2021 at 00:04, Marcin Wojtas <mw@...> wrote:

BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT.
Fix that for all platforms with the Marvell SoC's.

Signed-off-by: Marcin Wojtas <mw@...>

Did you add back the _STA methods that I removed from the secondary
UARTs you introduced in the original series?

Yes, this patch adds _STA to the relevant COM2 nodes in
Armada80x0McBin and Cn913xDbA DSDT files.

Do you have any further comments to this patch?

Pushed as 75899d2a8f97..17e0c2f6f79b

Thanks,

---
Changelog:
v1->v2:
* Rebase on top of tree

Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 +++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 76 ++++++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 60 ++++++++++++++++
5 files changed, 280 insertions(+)

diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
index 345c1e4dd6..88e38efeeb 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
@@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x000) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU1)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x001) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU2)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x100) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x101) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}

Device (AHC0)
@@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "MRVL0002") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
{
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
@@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
@@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment
Name (_BBN, 0x00) // _BBN: BIOS Bus Number
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_PRT, Package () // _PRT: PCI Routing Table
{
Package () { 0xFFFF, 0x0, 0x0, 0x40 },
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
index 91401c74c8..77d3aebaf1 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
@@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x000) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU1)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x001) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU2)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x100) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x101) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}

Device (AHC0)
@@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0002") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x02) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
@@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)
@@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
@@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)
@@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment
Name (_BBN, 0x00) // _BBN: BIOS Bus Number
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_PRT, Package () // _PRT: PCI Routing Table
{
Package () { 0xFFFF, 0x0, 0x0, 0x40 },
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
index 7931dc3ef8..a7d1c76e07 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
@@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x000) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU1)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x001) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU2)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x100) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x101) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}

Device (AHC0)
@@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -92,6 +112,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0002") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -123,6 +147,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -151,6 +179,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -170,6 +202,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -189,6 +225,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x02) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -208,6 +248,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -235,6 +279,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, ARMADA80X0_MCBIN_DBG2_UART_REG_BASE) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -261,6 +309,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -278,6 +330,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0101") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -312,6 +368,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
@@ -351,6 +411,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)
@@ -429,6 +493,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
@@ -449,6 +517,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)
@@ -475,6 +547,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment
Name (_BBN, 0x00) // _BBN: BIOS Bus Number
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_PRT, Package () // _PRT: PCI Routing Table
{
Package () { 0xFFFF, 0x0, 0x0, 0x40 },
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
index 8377b13763..d6619e367b 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
@@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x02) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
index 8c098cd14c..7335e443c6 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
@@ -21,21 +21,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x000) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU1)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x001) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU2)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x100) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x101) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}

Device (AHC0)
@@ -43,6 +59,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -68,6 +88,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "MRVL0003") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -99,6 +123,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -127,6 +155,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -146,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -165,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -192,6 +232,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, CN913X_DBG2_UART_REG_BASE) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -218,6 +262,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -240,6 +288,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
@@ -318,6 +370,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
@@ -344,6 +400,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment
Name (_BBN, 0x00) // _BBN: BIOS Bus Number
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_PRT, Package () // _PRT: PCI Routing Table
{
Package () { 0xFFFF, 0x0, 0x0, 0x40 },
--
2.29.0

Hi all,
Since the CI for UefiPayloadPkg is important to our develop progress, would you please speed up the review process? Thanks a lot!

Thanks,
Dun Tan

On Mon, Aug 23, 2021 at 03:09:25PM +0800, Lin, Gary (HPS OE-Linux) wrote:

https://bugzilla.tianocore.org/show_bug.cgi?id=3573

To avoid the potential inconsistency between PcdAcpiS3Enable and
QemuFwCfgS3Enabled(), this commit modifies SmmControl2Dxe to detect
S3 support by PcdAcpiS3Enable as modules in MdeModulePkg do.

Reviewed-by: Gerd Hoffmann <kraxel@...>

On Mon, Aug 23, 2021 at 03:09:24PM +0800, Lin, Gary (HPS OE-Linux) wrote:

https://bugzilla.tianocore.org/show_bug.cgi?id=3573

To avoid the potential inconsistency between PcdAcpiS3Enable and
QemuFwCfgS3Enabled(), this commit modifies PlatformBootManagerLib to
detect S3 support by PcdAcpiS3Enable as modules in MdeModulePkg do.

Reviewed-by: Gerd Hoffmann <kraxel@...>

On Mon, Aug 23, 2021 at 03:09:23PM +0800, Lin, Gary (HPS OE-Linux) wrote:

https://bugzilla.tianocore.org/show_bug.cgi?id=3573

To avoid the potential inconsistency between PcdAcpiS3Enable and
QemuFwCfgS3Enabled(), this commit modifies LockBoxLib to detect
S3 support by PcdAcpiS3Enable as modules in MdeModulePkg do.

Reviewed-by: Gerd Hoffmann <kraxel@...>

+++ b/OvmfPkg/XenPlatformPei/Platform.c

+ //
+ // This S3 conditional test is mainly for HVM Direct Kernel Boot since
+ // QEMU fwcfg isn't really supported other than that.
+ //
+ if (QemuFwCfgS3Enabled ()) {
+ DEBUG ((DEBUG_INFO, "S3 support was detected on QEMU\n"));
+ Status = PcdSetBoolS (PcdAcpiS3Enable, TRUE);
+ ASSERT_EFI_ERROR (Status);
+ }

OvmfPkg/PlatformPei/Platform.c already does that, so this makes kvm and
xen more consistent.

Reviewed-by: Gerd Hoffmann <kraxel@...>

take care,
Gerd

On Mon, Aug 23, 2021 at 03:08:14PM +0800, Lin, Gary (HPS OE-Linux) wrote:

https://bugzilla.tianocore.org/show_bug.cgi?id=3574

Without QemuKernelLoaderFsDxe, QemuLoadKernelImage() couldn't download
the kernel, initrd, and kernel command line from QEMU's fw_cfg.

v3:
Add the bugzilla link

Reviewed-by: Gerd Hoffmann <kraxel@...>

Enables firmware first error handling on the given platform. Installs
and publishes the SDEI and HEST ACPI tables required for firmware first
error handling.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@...>
---
Platform/ARM/SgiPkg/SgiPlatform.dsc.inc =
| 10 ++
Platform/ARM/SgiPkg/SgiPlatform.fdf =
| 7 +
Platform/ARM/SgiPkg/Drivers/PlatformErrorHandlerDxe/PlatformErrorHandler=
Dxe.inf | 51 ++++++
Platform/ARM/SgiPkg/Drivers/PlatformErrorHandlerDxe/PlatformErrorHandler=
Dxe.c | 171 ++++++++++++++++++++
4 files changed, 239 insertions(+)

diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc b/Platform/ARM/SgiPk=
g/SgiPlatform.dsc.inc
index 102d7926bde1..20f003b96cdb 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
@@ -24,6 +24,9 @@
# To allow firmware first error handling, set this to TRUE.
DEFINE ENABLE_GHES_MM =3D FALSE
=20
+ # To allow firmware first error handling, set this to TRUE.
+ DEFINE ENABLE_FIRWARE_FIRST =3D FALSE
+
[BuildOptions]
*_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES
=20
@@ -326,6 +329,13 @@
#
Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf
=20
+ #
+ # platform error handler driver
+ #
+!if $(ENABLE_FIRMWARE_FIRST) =3D=3D TRUE
+ Platform/ARM/SgiPkg/Drivers/PlatformErrorHandlerDxe/PlatformErrorHandl=
erDxe.inf
+!endif
+
#
# FAT filesystem + GPT/MBR partitioning
#
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.fdf b/Platform/ARM/SgiPkg/Sg=
iPlatform.fdf
index d6e942e19b81..b1d088610c4c 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.fdf
+++ b/Platform/ARM/SgiPkg/SgiPlatform.fdf
@@ -190,6 +190,13 @@ READ_LOCK_STATUS =3D TRUE
#
INF Platform/ARM/SgiPkg/Drivers/PlatformDxe/PlatformDxe.inf
=20
+ #
+ # platform error handler driver
+ #
+!if $(ENABLE_FIRMWARE_FIRST) =3D=3D TRUE
+ INF Platform/ARM/SgiPkg/Drivers/PlatformErrorHandlerDxe/PlatformErrorH=
andlerDxe.inf
+!endif
+
#
# Bds
#
diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformErrorHandlerDxe/Platform=
ErrorHandlerDxe.inf b/Platform/ARM/SgiPkg/Drivers/PlatformErrorHandlerDxe=
/PlatformErrorHandlerDxe.inf
new file mode 100644
index 000000000000..fe9ed4175b0b
--- /dev/null
+++ b/Platform/ARM/SgiPkg/Drivers/PlatformErrorHandlerDxe/PlatformErrorHa=
ndlerDxe.inf
@@ -0,0 +1,51 @@
+## @file
+# Dxe driver to handle platform errors.
+#
+# This driver installs SDEI and HEST ACPI tables required for firmware =
first
+# error handling.
+#
+# Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x0001001A
+ BASE_NAME =3D PlatformErrorHandlerDxe
+ FILE_GUID =3D a3187ea4-feb4-415f-b11e-2312623ffa6=
f
+ MODULE_TYPE =3D DXE_DRIVER
+ VERSION_STRING =3D 1.0
+ ENTRY_POINT =3D PlatformErrorHandlerEntryPoint
+
+[Sources.common]
+ PlatformErrorHandlerDxe.c
+
+[Packages]
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/SgiPkg/SgiPlatform.dec
+
+[LibraryClasses]
+ AcpiLib
+ BaseLib
+ DebugLib
+ UefiDriverEntryPoint
+
+[Guids]
+ gArmSgiAcpiTablesGuid
+
+[Protocols]
+ gEfiAcpiTableProtocolGuid ## PROTOCOL ALWAYS_CONSUMED
+ gHestTableProtocolGuid ## PROTOCOL ALWAYS_CONSUMED
+
+[FixedPcd]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId
+
+[Depex]
+ AFTER gArmPlatformHestErrorSourcesGuid
diff --git a/Platform/ARM/SgiPkg/Drivers/PlatformErrorHandlerDxe/Platform=
ErrorHandlerDxe.c b/Platform/ARM/SgiPkg/Drivers/PlatformErrorHandlerDxe/P=
latformErrorHandlerDxe.c
new file mode 100644
index 000000000000..25b29152f1bb
--- /dev/null
+++ b/Platform/ARM/SgiPkg/Drivers/PlatformErrorHandlerDxe/PlatformErrorHa=
ndlerDxe.c
@@ -0,0 +1,171 @@
+/** @file
+ Driver to handle and support all platform errors.
+
+ Installs the SDEI and HEST ACPI tables for firmware first error handli=
ng.
+
+ Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI 6.3, Table 18-382, Hardware Error Source Table
+ - SDEI Platform Design Document, revision b, 10 Appendix C, ACPI tab=
le
+ definitions for SDEI
+**/
+
+#include <IndustryStandard/Acpi.h>
+
+#include <Library/AcpiLib.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+
+#include <Protocol/AcpiTable.h>
+#include <Protocol/HestTable.h>
+
+
+/**
+ Build and install the SDEI ACPI table.
+
+ For platforms that allow firmware-first platform error handling, SDEI =
is used
+ as the notification mechanism for those errors.
+
+ @retval EFI_SUCCESS SDEI table installed successfully.
+ @retval Other For any error during installation.
+**/
+STATIC
+EFI_STATUS
+InstallSdeiTable (VOID)
+{
+ EFI_ACPI_TABLE_PROTOCOL *mAcpiTableProtocol =3D NULL;
+ EFI_ACPI_DESCRIPTION_HEADER Header;
+ EFI_STATUS Status;
+ UINTN AcpiTableHandle;
+
+ Header =3D
+ (EFI_ACPI_DESCRIPTION_HEADER) {
+ EFI_ACPI_6_3_SOFTWARE_DELEGATED_EXCEPTIONS_INTERFACE_TABLE_SIGNATUR=
E,
+ sizeof (EFI_ACPI_DESCRIPTION_HEADER), // Length
+ 0x01, // Revision
+ 0x00, // Checksum
+ {'A', 'R', 'M', 'L', 'T', 'D'}, // OemId
+ 0x4152464e49464552, // OemTableId:"REFINFRA"
+ 0x20201027, // OemRevision
+ 0x204d5241, // CreatorId:"ARM "
+ 0x00000001, // CreatorRevision
+ };
+
+ Header.Checksum =3D CalculateCheckSum8 ((UINT8 *)&Header, Header.Lengt=
h);
+ Status =3D gBS->LocateProtocol (
+ &gEfiAcpiTableProtocolGuid,
+ NULL,
+ (VOID **)&mAcpiTableProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: Failed to locate ACPI table protocol, status: %r\n",
+ __FUNCTION__,
+ Status
+ ));
+ return Status;
+ }
+
+ Status =3D mAcpiTableProtocol->InstallAcpiTable (
+ mAcpiTableProtocol,
+ &Header,
+ Header.Length,
+ &AcpiTableHandle
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: Failed to install SDEI ACPI table, status: %r\n",
+ __FUNCTION__,
+ Status
+ ));
+ }
+
+ return Status;
+}
+
+/**
+ Install the HEST ACPI table.
+
+ HEST ACPI table is used to list the platform errors for which the erro=
r
+ handling has been supported. Use the HEST table generation protocol to
+ install the HEST table.
+
+ @retval EFI_SUCCESS HEST table installed successfully.
+ @retval Other For any error during installation.
+**/
+STATIC
+EFI_STATUS
+InstallHestTable (VOID)
+{
+ HEST_TABLE_PROTOCOL *HestProtocol;
+ EFI_STATUS Status;
+
+ Status =3D gBS->LocateProtocol (
+ &gHestTableProtocolGuid,
+ NULL,
+ (VOID **)&HestProtocol
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: Failed to locate HEST DXE Protocol, status: %r\n",
+ __FUNCTION__,
+ Status
+ ));
+ return Status;
+ }
+
+ Status =3D HestProtocol->InstallHestTable ();
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: Failed to install HEST table, status: %r\n",
+ __FUNCTION__,
+ Status
+ ));
+ }
+
+ return Status;
+}
+
+/**
+ Entry point for the DXE driver.
+
+ This function installs the HEST ACPI table, using the HEST table gener=
ation
+ protocol. Also creates and installs the SDEI ACPI table required for f=
irmware
+ first error handling.
+
+ @param[in] ImageHandle Handle to the EFI image.
+ @param[in] SystemTable A pointer to the EFI System Table.
+
+ @retval EFI_SUCCESS On successful installation of ACPI tables
+ @retval Other On Failure
+**/
+EFI_STATUS
+EFIAPI
+PlatformErrorHandlerEntryPoint (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_STATUS Status;
+
+ // Build and install SDEI table.
+ Status =3D InstallSdeiTable ();
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // Install the created HEST table.
+ Status =3D InstallHestTable ();
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
--=20
2.17.1

For ACPI tables that are generated dynamically, define the ACPI table
header values that have to be used to build the table header.

Co-authored-by: Thomas Abraham <thomas.abraham@...>
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@...>
---
Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 7 +++++++
1 file changed, 7 insertions(+)

diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc b/Platform/ARM/SgiPk=
g/SgiPlatform.dsc.inc
index 5307280ef9a3..102d7926bde1 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
@@ -221,6 +221,13 @@
gArmPlatformTokenSpaceGuid.PcdGhesGenericErrorDataMmBufferSize|0x20000
!endif
=20
+ # ACPI Table Header IDs
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"ARMLTD"
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4152464e4946=
4552 # REFINFRA
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x20200831
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x204d5241 # AR=
M
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|1
+
########################################################################=
########
#
# Components Section - list of all EDK II Modules needed by this Platfor=
m
--=20
2.17.1

Allow platforms to define the base address and size of the memory region
that is reserved for MM drivers to populate the GHES generic error
status block with information about the platform error.

Co-authored-by: Thomas Abraham <thomas.abraham@...>
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@...>
---
Platform/ARM/SgiPkg/SgiPlatform.dec | 1 +
Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 4 ++++
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf | 6 ++++++
Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c | 13 ++++++++++=
+--
4 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dec b/Platform/ARM/SgiPkg/Sg=
iPlatform.dec
index 8cd818a9bf64..e46fa5d9a1d5 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dec
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dec
@@ -31,6 +31,7 @@
[PcdsFeatureFlag.common]
gArmSgiTokenSpaceGuid.PcdVirtioBlkSupported|FALSE|BOOLEAN|0x00000001
gArmSgiTokenSpaceGuid.PcdVirtioNetSupported|FALSE|BOOLEAN|0x00000010
+ gArmSgiTokenSpaceGuid.PcdGhesMmSupported|FALSE|BOOLEAN|0x00000027
=20
[PcdsFixedAtBuild]
gArmSgiTokenSpaceGuid.PcdDramBlock2Base|0|UINT64|0x00000002
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc b/Platform/ARM/SgiPk=
g/SgiPlatform.dsc.inc
index bb32584de63d..5307280ef9a3 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
@@ -107,6 +107,10 @@
gArmSgiTokenSpaceGuid.PcdVirtioNetSupported|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdEnableVariableRuntimeCache|FALSE
=20
+!if $(ENABLE_GHES_MM) =3D=3D TRUE
+ gArmSgiTokenSpaceGuid.PcdGhesMmSupported|TRUE
+!endif
+
[PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdVFPEnabled|1
gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf b/Pl=
atform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
index 22e247ea4fae..8cc362ea194f 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLib.inf
@@ -79,10 +79,16 @@
gArmSgiTokenSpaceGuid.PcdWdogBase
gArmSgiTokenSpaceGuid.PcdWdogSize
=20
+ gArmPlatformTokenSpaceGuid.PcdGhesGenericErrorDataMmBufferBase
+ gArmPlatformTokenSpaceGuid.PcdGhesGenericErrorDataMmBufferSize
+
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
=20
+[FeaturePcd]
+ gArmSgiTokenSpaceGuid.PcdGhesMmSupported
+
[Guids]
gArmSgiPlatformIdDescriptorGuid
gEfiHobListGuid ## CONSUMES ## SystemTable
diff --git a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c b/P=
latform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
index 8139b75d8ee4..fd4a90bbc0ef 100644
--- a/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
+++ b/Platform/ARM/SgiPkg/Library/PlatformLib/PlatformLibMem.c
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2018-2020, ARM Limited. All rights reserved.
+* Copyright (c) 2018-2021, ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -17,7 +17,8 @@
=20
// Total number of descriptors, including the final "end-of-table" descr=
iptor.
#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS \
- (14 + (FixedPcdGet32 (PcdChipCount) * 2))
+ (14 + (FixedPcdGet32 (PcdChipCount) * 2)) + \
+ (FeaturePcdGet (PcdGhesMmSupported))
=20
/**
Returns the Virtual Memory Map of the platform.
@@ -239,6 +240,14 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdMmBufferSiz=
e);
VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTRIB=
UTE_UNCACHED_UNBUFFERED;
=20
+ if (FeaturePcdGet (PcdGhesMmSupported)) {
+ // GHESv2 Generic Error Memory Space
+ VirtualMemoryTable[++Index].PhysicalBase =3D PcdGet64 (PcdGhesGener=
icErrorDataMmBufferBase);
+ VirtualMemoryTable[Index].VirtualBase =3D PcdGet64 (PcdGhesGener=
icErrorDataMmBufferBase);
+ VirtualMemoryTable[Index].Length =3D PcdGet64 (PcdGhesGener=
icErrorDataMmBufferSize);
+ VirtualMemoryTable[Index].Attributes =3D ARM_MEMORY_REGION_ATTR=
IBUTE_DEVICE;
+ }
+
// End of Table
VirtualMemoryTable[++Index].PhysicalBase =3D 0;
VirtualMemoryTable[Index].VirtualBase =3D 0;
--=20
2.17.1

Enable the use of HEST table generation protocol, GHES error source
descriptor protocol and DMC-620 MM driver on ARM Neoverse Reference
Design platforms. This allows firmware-first error handling and
reporting of DMC-620 memory controller's 1-bit DRAM ECC errors.

Co-authored-by: Thomas Abraham <thomas.abraham@...>
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@...>
---
Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 17 +++++++++++
Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc | 30 ++++++++++++++++++++
Platform/ARM/SgiPkg/PlatformStandaloneMm.fdf | 6 ++++
Platform/ARM/SgiPkg/SgiPlatform.fdf | 6 ++++
4 files changed, 59 insertions(+)

diff --git a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc b/Platform/ARM/SgiPk=
g/SgiPlatform.dsc.inc
index 7e37732fb93c..bb32584de63d 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
@@ -21,6 +21,9 @@
DEFINE LPI_EN =3D FALSE
DEFINE CPPC_EN =3D FALSE
=20
+ # To allow firmware first error handling, set this to TRUE.
+ DEFINE ENABLE_GHES_MM =3D FALSE
+
[BuildOptions]
*_*_*_CC_FLAGS =3D -D DISABLE_NEW_DEPRECATED_INTERFACES
=20
@@ -208,6 +211,12 @@
gArmTokenSpaceGuid.PcdMmBufferBase|0xFF600000
gArmTokenSpaceGuid.PcdMmBufferSize|0x10000
=20
+!if $(ENABLE_GHES_MM) =3D=3D TRUE
+ ## GHESv2 Generic Error memory space
+ gArmPlatformTokenSpaceGuid.PcdGhesGenericErrorDataMmBufferBase|0xFF610=
000
+ gArmPlatformTokenSpaceGuid.PcdGhesGenericErrorDataMmBufferSize|0x20000
+!endif
+
########################################################################=
########
#
# Components Section - list of all EDK II Modules needed by this Platfor=
m
@@ -365,3 +374,11 @@
!else
ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
!endif
+
+ #
+ # GHESv2 HEST error sources support
+ #
+ MdeModulePkg/Universal/Apei/HestDxe/HestDxe.inf
+!if $(ENABLE_GHES_MM) =3D=3D TRUE
+ ArmPlatformPkg/Drivers/HestMmErrorSources/HestErrorSourceDxe.inf
+!endif
diff --git a/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc b/Platform/ARM/Sgi=
Pkg/SgiPlatformMm.dsc.inc
index 5287e1f8e568..dbba82c74f39 100644
--- a/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc
+++ b/Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc
@@ -11,6 +11,10 @@
# Library Class section - list of all Library Classes needed by this Pla=
tform.
#
########################################################################=
########
+[Defines]
+ # To enable DMC-620 MM driver, set this to TRUE.
+ DEFINE ENABLE_DMC620_MM =3D FALSE
+
[LibraryClasses]
#
# Basic
@@ -94,6 +98,25 @@
gEfiSecurityPkgTokenSpaceGuid.PcdUserPhysicalPresence|TRUE
!endif
=20
+!if $(ENABLE_GHES_MM) =3D=3D TRUE
+ ## GHESv2 Generic Error Memory Space
+ gArmPlatformTokenSpaceGuid.PcdGhesGenericErrorDataMmBufferBase|0xFF610=
000
+ gArmPlatformTokenSpaceGuid.PcdGhesGenericErrorDataMmBufferSize|0x20000
+!endif
+
+!if $(ENABLE_DMC620_MM) =3D=3D TRUE
+ ## DMC620
+ gDmc620MmTokenSpaceGuid.PcdDmc620NumCtrl|2
+ gDmc620MmTokenSpaceGuid.PcdDmc620RegisterBase|0x4E000000
+ gDmc620MmTokenSpaceGuid.PcdDmc620CtrlSize|0x100000
+ gDmc620MmTokenSpaceGuid.PcdDmc620CorrectableErrorThreshold|10
+ gDmc620MmTokenSpaceGuid.PcdDmc620ErrSourceCount|1
+ gDmc620MmTokenSpaceGuid.PcdDmc620DramErrorSdeiEventBase|804
+ gDmc620MmTokenSpaceGuid.PcdDmc620DramOneBitErrorDataBase|0xFF610000
+ gDmc620MmTokenSpaceGuid.PcdDmc620DramOneBitErrorDataSize|0x100
+ gDmc620MmTokenSpaceGuid.PcdDmc620DramOneBitErrorSourceId|0
+!endif
+
########################################################################=
###########################
#
# Components Section - list of the modules and components that will be p=
rocessed by compilation
@@ -134,6 +157,13 @@
}
!endif
=20
+!if $(ENABLE_GHES_MM) =3D=3D TRUE
+ ArmPlatformPkg/Drivers/HestMmErrorSources/HestErrorSourceStandaloneMm.=
inf
+!endif
+!if $(ENABLE_DMC620_MM) =3D=3D TRUE
+ Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.inf
+!endif
+
########################################################################=
###########################
#
# BuildOptions Section - Define the module specific tool chain flags tha=
t should be used as
diff --git a/Platform/ARM/SgiPkg/PlatformStandaloneMm.fdf b/Platform/ARM/=
SgiPkg/PlatformStandaloneMm.fdf
index c1c24b747fa5..e029b9164570 100644
--- a/Platform/ARM/SgiPkg/PlatformStandaloneMm.fdf
+++ b/Platform/ARM/SgiPkg/PlatformStandaloneMm.fdf
@@ -48,6 +48,12 @@ READ_STATUS =3D TRUE
READ_LOCK_CAP =3D TRUE
READ_LOCK_STATUS =3D TRUE
=20
+!if $(ENABLE_GHES_MM) =3D=3D TRUE
+ INF ArmPlatformPkg/Drivers/HestMmErrorSources/HestErrorSourceStandalon=
eMm.inf
+!endif
+!if $(ENABLE_DMC620_MM) =3D=3D TRUE
+ INF Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.inf
+!endif
INF StandaloneMmPkg/Core/StandaloneMmCore.inf
!if $(SECURE_STORAGE_ENABLE) =3D=3D TRUE
INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashStandaloneMm.inf
diff --git a/Platform/ARM/SgiPkg/SgiPlatform.fdf b/Platform/ARM/SgiPkg/Sg=
iPlatform.fdf
index 8227ae03330c..d6e942e19b81 100644
--- a/Platform/ARM/SgiPkg/SgiPlatform.fdf
+++ b/Platform/ARM/SgiPkg/SgiPlatform.fdf
@@ -179,6 +179,12 @@ READ_LOCK_STATUS =3D TRUE
# MM Communicate
INF ArmPkg/Drivers/MmCommunicationDxe/MmCommunication.inf
=20
+ # Hest Error Source Support
+ INF MdeModulePkg/Universal/Apei/HestDxe/HestDxe.inf
+!if $(ENABLE_GHES_MM) =3D=3D TRUE
+ INF ArmPlatformPkg/Drivers/HestMmErrorSources/HestErrorSourceDxe.inf
+!endif
+
#
# Platform driver
#
--=20
2.17.1

DMC-620 memory controller improves system reliability by generating
interrupts on detecting ECC errors on the data. Add a initial DMC-620 MM
driver that implements a MMI handler for handling single-bit ECC error
events originating from the DRAM.

The driver implements the HEST error source descriptor protocol in order
to publish the GHES error source descriptor for single-bit DRAM errors.
The GHES error source descriptor that is published is of type 'memory
error'. A GHES error source descriptor is published for each instances
if the DMC-620 controller in the system.

The driver registers a MMI handler for handling 1-bit DRAM ECC error
events. The MMI handler, when invoked, reads the DMC-620 error record
registers and populates the EFI_PLATFORM_MEMORY_ERROR_DATA type error
section information structure with the corresponding information read
from the error record registers.

Co-authored-by: Thomas Abraham <thomas.abraham@...>
Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@...>
---
Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.dec | 30 ++
Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.inf | 61 ++++
Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.h | 174 ++++++++++
Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.c | 362 ++++++++++=
++++++++++
Platform/ARM/Drivers/Dmc620Mm/Dmc620MmErrorSourceInfo.c | 194 ++++++++++=
+
5 files changed, 821 insertions(+)

diff --git a/Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.dec b/Platform/ARM/Dr=
ivers/Dmc620Mm/Dmc620Mm.dec
new file mode 100644
index 000000000000..8f3508574203
--- /dev/null
+++ b/Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.dec
@@ -0,0 +1,30 @@
+## @file
+# DMC-620 MM driver specific declrations.
+#
+# This file defines GUIDs and declares PCD values for DMC-620 MM driver=
.
+#
+# Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ DEC_SPECIFICATION =3D 0x0001001A
+ PACKAGE_NAME =3D Dmc620Mm
+ PACKAGE_GUID =3D 94110B10-8E72-42A0-8963-D2B57FCF0F3=
8
+ PACKAGE_VERSION =3D 0.1
+
+[Guids]
+ gDmc620MmTokenSpaceGuid =3D {0xc305f72a, 0xd10d, 0x45e8, { 0x81, 0x78,=
0x51, 0x8b, 0x78, 0x62, 0x77, 0x79 } }
+ gArmDmcEventHandlerGuid =3D { 0x5ef0afd5, 0xe01a, 0x4c30, { 0x86, 0x19=
, 0x45, 0x46, 0x26, 0x91, 0x80, 0x98 }}
+
+[PcdsFixedAtBuild.common]
+ gDmc620MmTokenSpaceGuid.PcdDmc620CorrectableErrorThreshold|10|UINT32|0=
x00000004
+ gDmc620MmTokenSpaceGuid.PcdDmc620CtrlSize|0x100000|UINT32|0x00000003
+ gDmc620MmTokenSpaceGuid.PcdDmc620DramErrorSdeiEventBase|0|UINT32|0x000=
00006
+ gDmc620MmTokenSpaceGuid.PcdDmc620DramOneBitErrorDataBase|0|UINT64|0x00=
000007
+ gDmc620MmTokenSpaceGuid.PcdDmc620DramOneBitErrorDataSize|0|UINT64|0x00=
000008
+ gDmc620MmTokenSpaceGuid.PcdDmc620DramOneBitErrorSourceId|0|UINT16|0x00=
000009
+ gDmc620MmTokenSpaceGuid.PcdDmc620ErrSourceCount|1|UINT32|0x00000005
+ gDmc620MmTokenSpaceGuid.PcdDmc620NumCtrl|2|UINT32|0x00000001
+ gDmc620MmTokenSpaceGuid.PcdDmc620RegisterBase|0x4E000000|UINT64|0x0000=
0002
diff --git a/Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.inf b/Platform/ARM/Dr=
ivers/Dmc620Mm/Dmc620Mm.inf
new file mode 100644
index 000000000000..8cad07749a23
--- /dev/null
+++ b/Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.inf
@@ -0,0 +1,61 @@
+## @file
+# StandaloneMM driver for the DMC620 Memory Controller.
+#
+# Driver to handle 1-bit Corrected DRAM errors for DMC(s).
+#
+# Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION =3D 0x0001001A
+ BASE_NAME =3D StandaloneMmDmc620Driver
+ FILE_GUID =3D CB53ACD9-A1A1-43B3-A638-AC74DA5D9DA=
2
+ MODULE_TYPE =3D MM_STANDALONE
+ VERSION_STRING =3D 1.0
+ PI_SPECIFICATION_VERSION =3D 0x00010032
+ ENTRY_POINT =3D Dmc620MmDriverInitialize
+
+[Sources]
+ Dmc620Mm.c
+ Dmc620MmErrorSourceInfo.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ EmbeddedPkg/EmbeddedPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.dec
+ StandaloneMmPkg/StandaloneMmPkg.dec
+
+[LibraryClasses]
+ ArmLib
+ ArmSvcLib
+ BaseMemoryLib
+ DebugLib
+ StandaloneMmDriverEntryPoint
+
+[Protocols]
+ gMmHestErrorSourceDescProtocolGuid ##PRODUCES
+
+[FixedPcd]
+ gArmPlatformTokenSpaceGuid.PcdGhesGenericErrorDataMmBufferBase
+ gArmPlatformTokenSpaceGuid.PcdGhesGenericErrorDataMmBufferSize
+
+ gDmc620MmTokenSpaceGuid.PcdDmc620CorrectableErrorThreshold
+ gDmc620MmTokenSpaceGuid.PcdDmc620CtrlSize
+ gDmc620MmTokenSpaceGuid.PcdDmc620DramErrorSdeiEventBase
+ gDmc620MmTokenSpaceGuid.PcdDmc620DramOneBitErrorDataBase
+ gDmc620MmTokenSpaceGuid.PcdDmc620DramOneBitErrorDataSize
+ gDmc620MmTokenSpaceGuid.PcdDmc620DramOneBitErrorSourceId
+ gDmc620MmTokenSpaceGuid.PcdDmc620ErrSourceCount
+ gDmc620MmTokenSpaceGuid.PcdDmc620NumCtrl
+ gDmc620MmTokenSpaceGuid.PcdDmc620RegisterBase
+
+[Guids]
+ gArmDmcEventHandlerGuid
+
+[Depex]
+ TRUE
diff --git a/Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.h b/Platform/ARM/Driv=
ers/Dmc620Mm/Dmc620Mm.h
new file mode 100644
index 000000000000..f5c96396b870
--- /dev/null
+++ b/Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.h
@@ -0,0 +1,174 @@
+/** @file
+ DMC-620 memory controller MM driver definitions.
+
+ Macros and structure definitions for DMC-620 error handling MM driver.
+
+ Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef DMC620_MM_DRIVER_H_
+#define DMC620_MM_DRIVER_H_
+
+#include <Base.h>
+#include <Guid/Cper.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/ArmLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Protocol/HestErrorSourceInfo.h>
+
+// DMC-620 memc register field values and masks.
+#define DMC620_MEMC_STATUS_MASK (BIT2|BIT1|BIT0)
+#define DMC620_MEMC_STATUS_READY (BIT1|BIT0)
+#define DMC620_MEMC_CMD_EXECUTE_DRAIN (BIT2|BIT0)
+
+// DMC-620 Error Record Status register fields values and masks.
+#define DMC620_ERR_STATUS_MV BIT26
+#define DMC620_ERR_STATUS_AV BIT31
+
+// DMC-620 Error Record MISC-0 register fields values and masks.
+#define DMC620_ERR_MISC0_COLUMN_MASK \
+ (BIT9|BIT8|BIT7|BIT6|BIT5|BIT4|BIT3|BIT2|BIT1|BIT0)
+#define DMC620_ERR_MISC0_ROW_MASK (0x0FFFFC00)
+#define DMC620_ERR_MISC0_ROW_SHIFT 10
+#define DMC620_ERR_MISC0_RANK_MASK (BIT30|BIT29|BIT28)
+#define DMC620_ERR_MISC0_RANK_SHIFT 28
+#define DMC620_ERR_MISC0_VAILD BIT31
+
+// DMC-620 Error Record register fields values and mask.
+#define DMC620_ERR_MISC1_VAILD BIT31
+#define DMC620_ERR_MISC1_BANK_MASK (BIT3|BIT2|BIT1|BIT0)
+
+// DMC-620 Error Record Global Status register bit field.
+#define DMC620_ERR_GSR_ECC_CORRECTED_FH BIT1
+
+//
+// DMC-620 Memory Mapped register definitions.
+//
+
+// Unused DMC-620 register fields.
+#define RESV_0 0x1BD
+#define RESV_1 0x2C
+#define RESV_2 0x8
+#define RESV_3 0x58
+
+#pragma pack(1)
+typedef struct {
+ UINT32 MemcStatus;
+ UINT32 MemcConfig;
+ UINT32 MemcCmd;
+ UINT32 Reserved[RESV_0];
+ UINT32 Err0Fr;
+ UINT32 Reserved1;
+ UINT32 Err0Ctlr0;
+ UINT32 Err0Ctlr1;
+ UINT32 Err0Status;
+ UINT8 Reserved2[RESV_1];
+ UINT32 Err1Fr;
+ UINT32 Reserved3;
+ UINT32 Err1Ctlr;
+ UINT32 Reserved4;
+ UINT32 Err1Status;
+ UINT32 Reserved5;
+ UINT32 Err1Addr0;
+ UINT32 Err1Addr1;
+ UINT32 Err1Misc0;
+ UINT32 Err1Misc1;
+ UINT32 Err1Misc2;
+ UINT32 Err1Misc3;
+ UINT32 Err1Misc4;
+ UINT32 Err1Misc5;
+ UINT8 Reserved6[RESV_2];
+ UINT32 Err2Fr;
+ UINT32 Reserved7;
+ UINT32 Err2Ctlr;
+ UINT32 Reserved8;
+ UINT32 Err2Status;
+ UINT32 Reserved9;
+ UINT32 Err2Addr0;
+ UINT32 Err2Addr1;
+ UINT32 Err2Misc0;
+ UINT32 Err2Misc1;
+ UINT32 Err2Misc2;
+ UINT32 Err2Misc3;
+ UINT32 Err2Misc4;
+ UINT32 Err2Misc5;
+ UINT8 Reserved10[RESV_2];
+ UINT32 Reserved11[RESV_3];
+ UINT32 Errgsr;
+} DMC620_REGS_TYPE;
+
+// DMC-620 Typical Error Record register definition.
+typedef struct {
+ UINT32 ErrFr;
+ UINT32 Reserved;
+ UINT32 ErrCtlr;
+ UINT32 Reserved1;
+ UINT32 ErrStatus;
+ UINT32 Reserved2;
+ UINT32 ErrAddr0;
+ UINT32 ErrAddr1;
+ UINT32 ErrMisc0;
+ UINT32 ErrMisc1;
+ UINT32 ErrMisc2;
+ UINT32 ErrMisc3;
+ UINT32 ErrMisc4;
+ UINT32 ErrMisc5;
+ UINT8 Reserved3[RESV_2];
+} DMC620_ERR_REGS_TYPE;
+#pragma pack()
+
+// List of supported error sources by DMC-620.
+typedef enum {
+ DramEccCfh =3D 0,
+ DramEccFh,
+ ChiFh,
+ SramEccCfh,
+ SramEccFh,
+ DmcErrRecovery
+} DMC_ERR_SOURCES;
+
+/**
+ MMI handler implementing the HEST error source desc protocol.
+
+ Returns the error source descriptor information for all DMC(s) error s=
ources
+ and also returns its count and length.
+
+ @param[in] This Pointer for this protocol.
+ @param[out] Buffer HEST error source descriptor Informat=
ion
+ buffer.
+ @param[out] ErrorSourcesLength Total length of Error Source Descript=
ors.
+ @param[out] ErrorSourceCount Total number of supported error sourc=
es.
+
+ @retval EFI_SUCCESS Buffer has valid Error Source descript=
or
+ information.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+**/
+EFI_STATUS
+EFIAPI
+DmcErrorSourceDescInfoGet (
+ IN MM_HEST_ERROR_SOURCE_DESC_PROTOCOL *This,
+ OUT VOID **Buffer,
+ OUT UINTN *ErrorSourcesLength,
+ OUT UINTN *ErrorSourcesCount
+ );
+
+/**
+ Allow reporting of supported DMC-620 error sources.
+
+ Install the HEST Error Source Descriptor protocol handler to allow pub=
lishing
+ of the supported DMC-620 memory controller error sources.
+
+ @param[in] MmSystemTable Pointer to System table.
+
+ @retval EFI_SUCCESS Protocol installation successful.
+ @retval EFI_INVALID_PARAMETER Invalid system table parameter.
+**/
+EFI_STATUS
+Dmc620InstallErrorSourceDescProtocol (
+ IN EFI_MM_SYSTEM_TABLE *MmSystemTable
+ );
+
+#endif // DMC620_MM_DRIVER_H_
diff --git a/Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.c b/Platform/ARM/Driv=
ers/Dmc620Mm/Dmc620Mm.c
new file mode 100644
index 000000000000..91daf713f275
--- /dev/null
+++ b/Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.c
@@ -0,0 +1,362 @@
+/** @file
+ DMC-620 Memory Controller error handling (Standalone MM) driver.
+
+ Supports 1-bit Bit DRAM error handling for multiple DMC instances. On =
a error
+ event, publishes the CPER error record of Memory Error type.
+
+ Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference
+ - DMC620 Dynamic Memory Controller, revision r1p0.
+ - UEFI Reference Specification 2.8, Section N.2.5 Memory Error Secti=
on
+**/
+
+#include <Dmc620Mm.h>
+
+/**
+ Helper function to handle the DMC-620 DRAM errors.
+
+ Reads the DRAM error record registers. Creates a CPER error record of =
type
+ 'Memory Error' and populates it with information collected from DRAM e=
rror
+ record registers.
+
+ @param[in] DmcCtrl A pointer to DMC control registers.
+ @param[in] DmcInstance DMC instance which raised the fault=
event.
+ @param[in] ErrRecType A type of the DMC error record.
+ @param[in] ErrorBlockBaseAddress Unique address for populating the e=
rror
+ block status for given DMC error so=
urce.
+**/
+STATIC
+VOID
+Dmc620HandleDramError (
+ IN DMC620_REGS_TYPE *DmcCtrl,
+ IN UINTN DmcInstance,
+ IN UINTN ErrRecType,
+ IN UINTN ErrorBlockBaseAddress
+ )
+{
+ EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_STRUCTURE *ErrBlockSectionDesc;
+ EFI_ACPI_6_3_GENERIC_ERROR_STATUS_STRUCTURE *ErrBlockStatusHeaderD=
ata;
+ EFI_PLATFORM_MEMORY_ERROR_DATA MemorySectionInfo =3D =
{0};
+ DMC620_ERR_REGS_TYPE *ErrRecord;
+ EFI_GUID SectionType;
+ UINT32 ResetReg;
+ VOID *ErrBlockSectionData;
+ UINTN *ErrorStatusRegister;
+ UINTN *ReadAckRegister;
+ UINTN *ErrStatusBlock;
+ UINTN ErrStatus;
+ UINTN ErrAddr0;
+ UINTN ErrAddr1;
+ UINTN ErrMisc0;
+ UINTN ErrMisc1;
+ UINT8 CorrectedError;
+
+ //
+ // Check the type of DRAM error (1-bit or 2-bit) and accordingly selec=
t
+ // error record to use.
+ //
+ if (ErrRecType =3D=3D DMC620_ERR_GSR_ECC_CORRECTED_FH) {
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: DRAM ECC Corrected Fault (1-Bit ECC error)\n",
+ __FUNCTION__
+ ));
+ ErrRecord =3D (DMC620_ERR_REGS_TYPE *)&DmcCtrl->Err1Fr;
+ CorrectedError =3D 1;
+ } else {
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: DRAM ECC Fault Handling (2-bit ECC error)\n",
+ __FUNCTION__
+ ));
+ ErrRecord =3D (DMC620_ERR_REGS_TYPE *)&DmcCtrl->Err2Fr;
+ CorrectedError =3D 0;
+ }
+
+ // Read most recent DRAM error record registers.
+ ErrStatus =3D MmioRead32 ((UINTN)&ErrRecord->ErrStatus);
+ ErrAddr0 =3D MmioRead32 ((UINTN)&ErrRecord->ErrAddr0);
+ ErrAddr1 =3D MmioRead32 ((UINTN)&ErrRecord->ErrAddr1);
+ ErrMisc0 =3D MmioRead32 ((UINTN)&ErrRecord->ErrMisc0);
+ ErrMisc1 =3D MmioRead32 ((UINTN)&ErrRecord->ErrMisc1);
+
+ // Clear the status register so that new error records are populated.
+ ResetReg =3D MmioRead32 ((UINTN)&ErrRecord->ErrStatus);
+ MmioWrite32 ((UINTN)&ErrRecord->ErrStatus, ResetReg);
+
+ //
+ // Get Physical address of DRAM error from Error Record Address regist=
er
+ // and populate Memory Error Section.
+ //
+ if (ErrStatus & DMC620_ERR_STATUS_AV) {
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: DRAM Error: Address_0 : 0x%x Address_1 : 0x%x\n",
+ __FUNCTION__,
+ ErrAddr0,
+ ErrAddr1
+ ));
+
+ //
+ // Populate Memory CPER section with DRAM error address (48 bits) an=
d
+ // address mask fields.
+ //
+ MemorySectionInfo.ValidFields |=3D
+ EFI_PLATFORM_MEMORY_PHY_ADDRESS_MASK_VALID |
+ EFI_PLATFORM_MEMORY_PHY_ADDRESS_VALID;
+ MemorySectionInfo.PhysicalAddressMask =3D 0xFFFFFFFFFFFF;
+ MemorySectionInfo.PhysicalAddress =3D (ErrAddr1 << 32) | ErrAddr0;
+ }
+
+ //
+ // Read the Error Record Misc registers and populate relevant fields i=
n
+ // Memory CPER error section.
+ //
+ if ((ErrStatus & DMC620_ERR_STATUS_MV)
+ && (ErrMisc0 & DMC620_ERR_MISC0_VAILD))
+ {
+ // Populate Memory error section wih DRAM column information.
+ MemorySectionInfo.ValidFields |=3D EFI_PLATFORM_MEMORY_COLUMN_VALID;
+ MemorySectionInfo.Column =3D ErrMisc0 & DMC620_ERR_MISC0_COLUMN_MASK=
;
+
+ //
+ // Populate Memory Error Section with DRAM row information.
+ // Row bits (bit 16 and 17) are to be filled as extended.
+ //
+ MemorySectionInfo.ValidFields |=3D
+ EFI_PLATFORM_MEMORY_ERROR_EXTENDED_ROW_BIT_16_17_VALID;
+ MemorySectionInfo.Row =3D
+ (ErrMisc0 & DMC620_ERR_MISC0_ROW_MASK) >> DMC620_ERR_MISC0_ROW_SHI=
FT;
+ MemorySectionInfo.Extended =3D
+ ((ErrMisc0 & DMC620_ERR_MISC0_ROW_MASK) >>
+ (DMC620_ERR_MISC0_ROW_SHIFT + 16));
+
+ // Populate Memory Error Section wih DRAM rank information.
+ MemorySectionInfo.ValidFields |=3D EFI_PLATFORM_MEMORY_ERROR_RANK_NU=
M_VALID;
+ MemorySectionInfo.RankNum =3D (ErrMisc0 & DMC620_ERR_MISC0_RANK_MASK=
) >>
+ DMC620_ERR_MISC0_RANK_SHIFT;
+ }
+
+ // Read Error Record MISC1 register and populate the Memory Error Sect=
ion.
+ if ((ErrStatus & DMC620_ERR_STATUS_MV)
+ && (ErrMisc1 & DMC620_ERR_MISC1_VAILD))
+ {
+ MemorySectionInfo.ValidFields |=3D EFI_PLATFORM_MEMORY_BANK_VALID;
+ MemorySectionInfo.Bank =3D (ErrMisc1 & DMC620_ERR_MISC1_BANK_MASK);
+ }
+
+ //
+ // Misc registers 2..5 are not used and convey only the error counter
+ // information. They are cleared as they do not contribute in Error
+ // Record creation.
+ //
+ if (ErrStatus & DMC620_ERR_STATUS_MV) {
+ ResetReg =3D 0x0;
+ MmioWrite32 ((UINTN)&ErrRecord->ErrMisc2, ResetReg);
+ MmioWrite32 ((UINTN)&ErrRecord->ErrMisc3, ResetReg);
+ MmioWrite32 ((UINTN)&ErrRecord->ErrMisc4, ResetReg);
+ MmioWrite32 ((UINTN)&ErrRecord->ErrMisc5, ResetReg);
+ }
+
+ //
+ // Reset error records Status register for recording new DRAM error sy=
ndrome
+ // information.
+ //
+ ResetReg =3D MmioRead32 ((UINTN)&ErrRecord->ErrStatus);
+ MmioWrite32 ((UINTN)&ErrRecord->ErrStatus, ResetReg);
+
+ //
+ // Allocate memory for Error Acknowledge register, Error Status regist=
er and
+ // Error status block data.
+ //
+ ReadAckRegister =3D (UINTN *)ErrorBlockBaseAddress;
+ ErrorStatusRegister =3D (UINTN *)ErrorBlockBaseAddress + 1;
+ ErrStatusBlock =3D (UINTN *)ErrorStatusRegister + 1;
+
+ // Initialize Error Status Register with Error Status Block address.
+ *ErrorStatusRegister =3D (UINTN)ErrStatusBlock;
+
+ //
+ // Locate Block Status Header base address and populate it with Error =
Status
+ // Block Header information.
+ //
+ ErrBlockStatusHeaderData =3D (EFI_ACPI_6_3_GENERIC_ERROR_STATUS_STRUCT=
URE *)
+ ErrStatusBlock;
+ *ErrBlockStatusHeaderData =3D
+ (EFI_ACPI_6_3_GENERIC_ERROR_STATUS_STRUCTURE) {
+ .BlockStatus =3D {
+ .UncorrectableErrorValid =3D ((CorrectedError =3D=3D 0) ? 0 =
: 1),
+ .CorrectableErrorValid =3D ((CorrectedError =3D=3D 1) ? 1 =
: 0),
+ .MultipleUncorrectableErrors =3D 0x0,
+ .MultipleCorrectableErrors =3D 0x0,
+ .ErrorDataEntryCount =3D 0x1
+ },
+ .RawDataOffset =3D
+ (sizeof (EFI_ACPI_6_3_GENERIC_ERROR_STATUS_STRUCTURE) +
+ sizeof (EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_STRUCTURE)),
+ .RawDataLength =3D 0,
+ .DataLength =3D
+ (sizeof (EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_STRUCTURE) +
+ sizeof(EFI_PLATFORM_MEMORY_ERROR_DATA)),
+ .ErrorSeverity =3D ((CorrectedError =3D=3D 1) ?
+ EFI_ACPI_6_3_ERROR_SEVERITY_CORRECTED :
+ EFI_ACPI_6_3_ERROR_SEVERITY_FATAL),
+ };
+
+ //
+ // Locate Section Descriptor base address and populate Error Status Se=
ction
+ // Descriptor data.
+ //
+ ErrBlockSectionDesc =3D (EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_STRUCTU=
RE *)
+ (ErrBlockStatusHeaderData + 1);
+ *ErrBlockSectionDesc =3D
+ (EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_STRUCTURE) {
+ .ErrorSeverity =3D ((CorrectedError =3D=3D 1) ?
+ EFI_ACPI_6_3_ERROR_SEVERITY_CORRECTED :
+ EFI_ACPI_6_3_ERROR_SEVERITY_FATAL),
+ .Revision =3D EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_REVISION,
+ .ValidationBits =3D 0,
+ .Flags =3D 0,
+ .ErrorDataLength =3D sizeof (EFI_PLATFORM_MEMORY_ERROR_DATA),
+ .FruId =3D {0},
+ .FruText =3D {0},
+ .Timestamp =3D {0},
+ };
+ SectionType =3D (EFI_GUID) EFI_ERROR_SECTION_PLATFORM_MEMORY_GUID;
+ CopyGuid ((EFI_GUID *)ErrBlockSectionDesc->SectionType, &SectionType);
+
+ // Locate Section base address and populate Memory Error Section(Cper)=
data.
+ ErrBlockSectionData =3D (VOID *)(ErrBlockSectionDesc + 1);
+ CopyMem (
+ ErrBlockSectionData,
+ (VOID *)&MemorySectionInfo,
+ sizeof (EFI_PLATFORM_MEMORY_ERROR_DATA)
+ );
+}
+
+/**
+ DMC-620 1-bit ECC event handler.
+
+ Supports multiple DMC error processing. Current implementation handles=
the
+ DRAM ECC errors.
+
+ @param[in] DispatchHandle The unique handle assigned to this ha=
ndler by
+ MmiHandlerRegister().
+ @param[in] Context Points to an optional handler context=
which
+ was specified when the handler was
+ registered.
+ @param[in, out] CommBuffer Buffer passed from Non-MM to MM envir=
onmvent.
+ @param[in, out] CommBufferSize The size of the CommBuffer.
+
+ @retval EFI_SUCCESS Event handler successful.
+ @retval Other Failure of event handler.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+Dmc620ErrorEventHandler (
+ IN EFI_HANDLE DispatchHandle,
+ IN CONST VOID *Context, OPTIONAL
+ IN OUT VOID *CommBuffer, OPTIONAL
+ IN OUT UINTN *CommBufferSize OPTIONAL
+ )
+{
+ DMC620_REGS_TYPE *DmcCtrl;
+ UINTN DmcIdx;
+ UINTN ErrGsr;
+
+ // DMC instance which raised the error event.
+ DmcIdx =3D *(UINTN *)CommBuffer;
+ // Error Record Base address for that DMC instance.
+ DmcCtrl =3D (DMC620_REGS_TYPE *)(FixedPcdGet64 (PcdDmc620RegisterBase)=
+
+ (FixedPcdGet64 (PcdDmc620CtrlSize) * DmcIdx));
+
+ DEBUG ((
+ DEBUG_INFO,
+ "%a: DMC error event raised for DMC: %d with DmcBaseAddr: 0x%x \n",
+ __FUNCTION__,
+ DmcIdx,
+ (UINTN)DmcCtrl
+ ));
+
+ ErrGsr =3D MmioRead32 ((UINTN)&DmcCtrl->Errgsr);
+
+ if (ErrGsr & DMC620_ERR_GSR_ECC_CORRECTED_FH) {
+ // Handle corrected 1-bit DRAM ECC error.
+ Dmc620HandleDramError (
+ DmcCtrl,
+ DmcIdx,
+ DMC620_ERR_GSR_ECC_CORRECTED_FH,
+ FixedPcdGet64 (
+ PcdDmc620DramOneBitErrorDataBase) +
+ (FixedPcdGet64 (PcdDmc620DramOneBitErrorDataSize) * DmcIdx)
+ );
+ } else {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: Unsupported DMC-620 error reported, ignoring\n",
+ __FUNCTION__
+ ));
+ }
+
+ // No data to send using the MM communication buffer so clear the comm=
buffer
+ // size.
+ *CommBufferSize =3D 0;
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Initialize function for the driver.
+
+ Registers MMI handlers to process fault events on DMC and installs req=
uired
+ protocols to publish the error source descriptors.
+
+ @param[in] ImageHandle Handle to image.
+ @param[in] SystemTable Pointer to System table.
+
+ @retval EFI_SUCCESS On successful installation of error event handle=
r for
+ DMC.
+ @retval Other Failure in installing error event handlers for D=
MC.
+**/
+EFI_STATUS
+EFIAPI
+Dmc620MmDriverInitialize (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_MM_SYSTEM_TABLE *SystemTable
+ )
+{
+ EFI_MM_SYSTEM_TABLE *mMmst;
+ EFI_STATUS Status;
+ EFI_HANDLE DispatchHandle;
+
+ ASSERT (SystemTable !=3D NULL);
+ mMmst =3D SystemTable;
+
+ // Register MMI handlers for DMC-620 error events.
+ Status =3D mMmst->MmiHandlerRegister (
+ Dmc620ErrorEventHandler,
+ &gArmDmcEventHandlerGuid,
+ &DispatchHandle
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: Registration failed for DMC error event handler, Status:%r\n"=
,
+ __FUNCTION__,
+ Status
+ ));
+
+ return Status;
+ }
+
+ // Installs the HEST error source descriptor protocol.
+ Status =3D Dmc620InstallErrorSourceDescProtocol (SystemTable);
+ if (EFI_ERROR(Status)) {
+ mMmst->MmiHandlerUnRegister (DispatchHandle);
+ }
+
+ return Status;
+}
diff --git a/Platform/ARM/Drivers/Dmc620Mm/Dmc620MmErrorSourceInfo.c b/Pl=
atform/ARM/Drivers/Dmc620Mm/Dmc620MmErrorSourceInfo.c
new file mode 100644
index 000000000000..59dcff019a07
--- /dev/null
+++ b/Platform/ARM/Drivers/Dmc620Mm/Dmc620MmErrorSourceInfo.c
@@ -0,0 +1,194 @@
+/** @file
+ Create and populate DMC-620 HEST error source descriptors.
+
+ Implements the HEST Error Source Descriptor protocol. Creates the GHES=
v2
+ type error source descriptors for supported hardware errors. Appends
+ the created descriptors to the Buffer parameter of the protocol.
+
+ Copyright (c) 2020 - 2021, ARM Limited. All rights reserved.
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Specification Reference:
+ - ACPI Reference Specification 6.3, Table 18-393 GHESv2 Structure.
+**/
+
+#include <Library/AcpiLib.h>
+#include <Dmc620Mm.h>
+
+/**
+ Populate the DMC-620 DRAM Error Source Descriptor.
+
+ Creates error source descriptor of GHESv2 type to be appended to the H=
est
+ table. The error source descriptor is populated with appropriate value=
s
+ based on the instance number of DMC-620. Allocates and initializes mem=
ory
+ for Error Status Block(Cper) section for each error source.
+
+ @param[in] ErrorDesc HEST error source descriptor Information.
+ @param[in] DmcIdx Instance number of the DMC-620.
+**/
+STATIC
+VOID
+EFIAPI
+Dmc620SetupDramErrorDescriptor (
+ IN EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE *Er=
rorDesc,
+ IN UINTN DmcIdx
+ )
+{
+ UINTN ErrorBlockData;
+
+ //
+ // Address of reserved memory for the error status block that will be =
used
+ // to hold the information about the DRAM error. Initialize this memor=
y
+ // with 0.
+ //
+ ErrorBlockData =3D FixedPcdGet64 (PcdDmc620DramOneBitErrorDataBase) +
+ (FixedPcdGet64 (PcdDmc620DramOneBitErrorDataSize) *
+ DmcIdx);
+ SetMem (
+ (VOID *)ErrorBlockData,
+ FixedPcdGet64 (PcdDmc620DramOneBitErrorDataSize),
+ 0
+ );
+
+ // Build the DRAM error source descriptor.
+ *ErrorDesc =3D
+ (EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE) {
+ .Type =3D EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_VERSION_2,
+ .SourceId =3D FixedPcdGet16 (PcdDmc620DramOneBitErrorSourceId) + D=
mcIdx,
+ .RelatedSourceId =3D 0xFFFF,
+ .Flags =3D 0,
+ .Enabled =3D 1,
+ .NumberOfRecordsToPreAllocate =3D 1,
+ .MaxSectionsPerRecord =3D 1,
+ .MaxRawDataLength =3D sizeof (EFI_PLATFORM_MEMORY_ERROR_DATA),
+ .ErrorStatusAddress =3D ARM_GAS64 (ErrorBlockData + 8),
+ .NotificationStructure =3D
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_STRUCTURE_INIT (
+ EFI_ACPI_6_3_HARDWARE_ERROR_NOTIFICATION_SOFTWARE_DELEGATED_EX=
CEPTION,
+ 0,
+ FixedPcdGet32 (PcdDmc620DramErrorSdeiEventBase) + DmcIdx
+ ),
+ .ErrorStatusBlockLength =3D
+ sizeof (EFI_ACPI_6_3_GENERIC_ERROR_STATUS_STRUCTURE) +
+ sizeof (EFI_ACPI_6_3_GENERIC_ERROR_DATA_ENTRY_STRUCTURE) +
+ sizeof (EFI_PLATFORM_MEMORY_ERROR_DATA),
+ .ReadAckRegister =3D ARM_GAS64 (ErrorBlockData),
+ .ReadAckPreserve =3D 0,
+ .ReadAckWrite =3D 0
+ };
+}
+
+/**
+ MMI handler implementing the HEST error source descriptor protocol.
+
+ Returns the error source descriptor information for all supported hard=
ware
+ error sources. As mentioned in the HEST Error Source Decriptor protoco=
l this
+ handler returns with error source count and length when Buffer paramet=
er is
+ NULL.
+
+ @param[in] This Pointer for this protocol.
+ @param[out] Buffer HEST error source descriptor Informat=
ion
+ buffer.
+ @param[out] ErrorSourcesLength Total length of Error Source Descript=
ors
+ @param[out] ErrorSourceCount Total number of supported error spurc=
es.
+
+ @retval EFI_SUCCESS Buffer has valid Error Source descript=
or
+ information.
+ @retval EFI_INVALID_PARAMETER Buffer is NULL.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+Dmc620ErrorSourceDescInfoGet (
+ IN MM_HEST_ERROR_SOURCE_DESC_PROTOCOL *This,
+ OUT VOID **Buffer,
+ OUT UINTN *ErrorSourcesLength,
+ OUT UINTN *ErrorSourcesCount
+ )
+{
+ EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE *ErrorD=
escriptor;
+ UINTN DmcIdx;
+
+ //
+ // Update the error source length and error source count parameters.
+ //
+ *ErrorSourcesLength =3D
+ FixedPcdGet64 (PcdDmc620NumCtrl) *
+ FixedPcdGet64 (PcdDmc620ErrSourceCount) *
+ sizeof (EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTU=
RE);
+ *ErrorSourcesCount =3D FixedPcdGet64 (PcdDmc620NumCtrl) *
+ FixedPcdGet64 (PcdDmc620ErrSourceCount);
+
+ //
+ // If 'Buffer' is NULL return, as this invocation of the protocol hand=
ler is
+ // to determine the total size of all the error source descriptor inst=
ances.
+ //
+ if (Buffer =3D=3D NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Buffer to be updated with error source descriptor(s) information.
+ ErrorDescriptor =3D
+ (EFI_ACPI_6_3_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE *)*B=
uffer;
+
+ //
+ // Create and populate the available error source descriptor for all D=
MC(s).
+ //
+ for (DmcIdx =3D 0; DmcIdx < FixedPcdGet64 (PcdDmc620NumCtrl); DmcIdx++=
) {
+ // Add the one-bit DRAM error source descriptor.
+ Dmc620SetupDramErrorDescriptor (ErrorDescriptor, DmcIdx);
+ ErrorDescriptor++;
+ }
+
+ return EFI_SUCCESS;
+}
+
+//
+// DMC-620 MM_HEST_ERROR_SOURCE_DESC_PROTOCOL protocol instance.
+//
+STATIC MM_HEST_ERROR_SOURCE_DESC_PROTOCOL mDmc620ErrorSourceDesc =3D {
+ Dmc620ErrorSourceDescInfoGet
+};
+
+/**
+ Allow reporting of supported DMC-620 error sources.
+
+ Install the HEST Error Source Descriptor protocol handler to allow pub=
lishing
+ of the supported Dmc(s) hardware error sources.
+
+ @param[in] MmSystemTable Pointer to System table.
+
+ @retval EFI_SUCCESS Protocol installation successful.
+ @retval EFI_INVALID_PARAMETER Invalid system table parameter.
+**/
+EFI_STATUS
+Dmc620InstallErrorSourceDescProtocol (
+ IN EFI_MM_SYSTEM_TABLE *MmSystemTable
+ )
+{
+ EFI_HANDLE mDmcHandle =3D NULL;
+ EFI_STATUS Status;
+
+ // Check if the MmSystemTable is initialized.
+ if (MmSystemTable =3D=3D NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ // Install HEST error source descriptor protocol for DMC(s).
+ Status =3D MmSystemTable->MmInstallProtocolInterface (
+ &mDmcHandle,
+ &gMmHestErrorSourceDescProtocolGuid,
+ EFI_NATIVE_INTERFACE,
+ &mDmc620ErrorSourceDesc
+ );
+ if (EFI_ERROR(Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "%a: Failed installing HEST error source protocol, status: %r\n",
+ __FUNCTION__,
+ Status
+ ));
+ }
+
+ return Status;
+}
--=20
2.17.1

Changes since v2:
- Rebased to the latest upstream code.

This patch series introduces platform support for RAS using Firmware Firs=
t
error handling. Firmware first error handling on ARM Neoverse reference d=
esign
platforms is achieved using HEST[1] and SDEI[2] ACPI tables.

For doing so the Platform Error handler DXE driver is introduced. This dr=
iver
is integral part of the firmware first error handling framework in EDK2. =
SDEI
being the notification mechanism used to communicate the platform errors =
to
OSPM, it builds and installs the SDEI ACPI table. Also installs the HEST =
table
which is already created as part of firmware first framework in EDK2.

This series does provide a reference implementation to leverage the firmw=
are
first framework by implementing a platform MM driver for Dynamic Memory
Controller DMC[3] that has RAS feature enabled. This driver mainly handle=
s
following:
- Implements the Hest Error Source Descriptor protocol introduced as part=
of
firmware first framework in EDK2. Publishes the 1-bit ECC DRAM error so=
urces
as GHESv2[4] type error source descriptors.
- For any 1-bit CE that occurs on DRAM it reads DMC error record register=
s and
populates a error status block (CPER)[5] of Memory Type error[6].

References:
[1] : ACPI 6.3, Table 18-382, Hardware Error Source Table
[2] : SDEI Platform Design Document, revision b, 10 Appendix C, ACPI tabl=
e
definitions for SDEI
[3] : DMC620 Dynamic Memory Controller, revision r1p0
[4] : ACPI Reference Specification 6.3, Table 18-393 GHESv2 Structure
[5] : UEFI Reference Specification 2.8, Appendix N - Common Platform Erro=
r
Record
[6] : UEFI Reference Specification 2.8, Section N.2.5 Memory Error Sectio=
n

This patch series is dependent on the edk2 patch series
https://edk2.groups.io/g/devel/message/79741

Link to github branch with the patches in this series -
https://github.com/omkkul01/edk2-platforms/tree/ras_firware_first_edk2-pl=
atforms_v3

Omkar Anand Kulkarni (5):
Platform/ARM: Add DMC-620 ECC error handling driver
Platform/Sgi: dmc-620 firmware-first error handling
Platform/Sgi: define memory region for GHES error status block
Platform/Sgi: Define values for ACPI table header
Platform/Sgi: Add platform error handling driver

Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.dec | 30 ++
Platform/ARM/SgiPkg/SgiPlatform.dec | 1 +
Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 38 ++
Platform/ARM/SgiPkg/SgiPlatformMm.dsc.inc | 30 ++
Platform/ARM/SgiPkg/PlatformStandaloneMm.fdf | 6 +
Platform/ARM/SgiPkg/SgiPlatform.fdf | 13 +
Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.inf | 61 +++
.../PlatformErrorHandlerDxe.inf | 51 +++
.../Library/PlatformLib/PlatformLib.inf | 6 +
Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.h | 174 +++++++++
Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.c | 362 ++++++++++++++++++
.../Dmc620Mm/Dmc620MmErrorSourceInfo.c | 194 ++++++++++
.../PlatformErrorHandlerDxe.c | 171 +++++++++
.../Library/PlatformLib/PlatformLibMem.c | 13 +-
14 files changed, 1148 insertions(+), 2 deletions(-)
create mode 100644 Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.dec
create mode 100644 Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.inf
create mode 100644 Platform/ARM/SgiPkg/Drivers/PlatformErrorHandlerDxe/P=
latformErrorHandlerDxe.inf
create mode 100644 Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.h
create mode 100644 Platform/ARM/Drivers/Dmc620Mm/Dmc620Mm.c
create mode 100644 Platform/ARM/Drivers/Dmc620Mm/Dmc620MmErrorSourceInfo=
.c
create mode 100644 Platform/ARM/SgiPkg/Drivers/PlatformErrorHandlerDxe/P=
latformErrorHandlerDxe.c

--=20
2.17.1

Hi Ard,

śr., 11 sie 2021 o 12:58 Marcin Wojtas <mw@...> napisał(a):

Hi Ard,

śr., 11 sie 2021 o 12:42 Ard Biesheuvel <ardb@...> napisał(a):

On Wed, 11 Aug 2021 at 00:04, Marcin Wojtas <mw@...> wrote:

BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT.
Fix that for all platforms with the Marvell SoC's.

Signed-off-by: Marcin Wojtas <mw@...>

Did you add back the _STA methods that I removed from the secondary
UARTs you introduced in the original series?

Yes, this patch adds _STA to the relevant COM2 nodes in
Armada80x0McBin and Cn913xDbA DSDT files.

Do you have any further comments to this patch?

Best regards,
Marcin

---
Changelog:
v1->v2:
* Rebase on top of tree

Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 +++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++++++++++++++++
Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 76 ++++++++++++++++++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++
Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 60 ++++++++++++++++
5 files changed, 280 insertions(+)

diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
index 345c1e4dd6..88e38efeeb 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl
@@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x000) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU1)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x001) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU2)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x100) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x101) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}

Device (AHC0)
@@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "MRVL0002") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
{
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
@@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
@@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA7K", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment
Name (_BBN, 0x00) // _BBN: BIOS Bus Number
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_PRT, Package () // _PRT: PCI Routing Table
{
Package () { 0xFFFF, 0x0, 0x0, 0x40 },
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
index 91401c74c8..77d3aebaf1 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl
@@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x000) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU1)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x001) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU2)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x100) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x101) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}

Device (AHC0)
@@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0002") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x02) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
@@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)
@@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
@@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)
@@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment
Name (_BBN, 0x00) // _BBN: BIOS Bus Number
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_PRT, Package () // _PRT: PCI Routing Table
{
Package () { 0xFFFF, 0x0, 0x0, 0x40 },
diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
index 7931dc3ef8..a7d1c76e07 100644
--- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
+++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl
@@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x000) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU1)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x001) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU2)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x100) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x101) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}

Device (AHC0)
@@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -92,6 +112,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0002") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -123,6 +147,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -151,6 +179,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -170,6 +202,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -189,6 +225,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x02) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -208,6 +248,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -235,6 +279,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, ARMADA80X0_MCBIN_DBG2_UART_REG_BASE) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -261,6 +309,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -278,6 +330,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "MRVL0101") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -312,6 +368,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
@@ -351,6 +411,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)
@@ -429,6 +493,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
@@ -449,6 +517,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)
@@ -475,6 +547,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMADA8K", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment
Name (_BBN, 0x00) // _BBN: BIOS Bus Number
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_PRT, Package () // _PRT: PCI Routing Table
{
Package () { 0xFFFF, 0x0, 0x0, 0x40 },
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
index 8377b13763..d6619e367b 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl
@@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x02) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU ", "CN9131", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)
diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
index 8c098cd14c..7335e443c6 100644
--- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
+++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl
@@ -21,21 +21,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x000) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU1)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x001) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU2)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x100) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}
Device (CPU3)
{
Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID
Name (_UID, 0x101) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
}

Device (AHC0)
@@ -43,6 +59,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "LNRO001E") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CLS, Package (0x03) // _CLS: Class Code
{
0x01,
@@ -68,6 +88,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "MRVL0003") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -99,6 +123,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "MRVL0004") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -127,6 +155,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -146,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "PNP0D10") // _HID: Hardware ID
Name (_UID, 0x01) // _UID: Unique ID
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }

Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -165,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -192,6 +232,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "MRVL0001") // _HID: Hardware ID
Name (_CID, "HISI0031") // _CID: Compatible ID
Name (_UID, 0x01) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_ADR, CN913X_DBG2_UART_REG_BASE) // _ADR: Address
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
@@ -218,6 +262,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
{
Name (_HID, "MRVL0100") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite,
@@ -240,6 +288,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_HID, "MRVL0110") // _HID: Hardware ID
Name (_CCA, 0x01) // Cache-coherent controller
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)
@@ -318,6 +370,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
{
Name (_HID, "PRP0001") // _HID: Hardware ID
Name (_UID, 0x00) // _UID: Unique ID
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_CRS, ResourceTemplate ()
{
Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)
@@ -344,6 +400,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9130", 3)
Name (_SEG, 0x00) // _SEG: PCI Segment
Name (_BBN, 0x00) // _BBN: BIOS Bus Number
Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute
+ Method (_STA) // _STA: Device status
+ {
+ Return (0xF)
+ }
Name (_PRT, Package () // _PRT: PCI Routing Table
{
Package () { 0xFFFF, 0x0, 0x0, 0x40 },
--
2.29.0

Hi All,

Sorry for the [edk2-platforms] prefix attached to the subject line. This is edk2 patch series. Will fix the prefix in next version.

- Omkar.

Changes since v2:
- Addressed the comments given by Sami.
- Added Readme file with all cover letter information.
- Rebased to the latest upstream code.

Hardware Error Source Table (HEST)[1] and Software Delegated Exception
Interface (SDEI)[2] ACPI tables are used to acomplish firmware first error
handling.This patch series introduces a framework to build and install the
HEST ACPI table dynamically.

The following figure illustrates the possible usage of the dyanamic generation
of HEST ACPI table.

NS | S
+--------------------------------------+--------------------------------------+
| | |
|+-------------------------------------+---------------------+
|+-------------------------------------+---------------------+ |
|| +---------------------+--------------------+| |
|| | | || |
|| +-----------+ |+------------------+ | +-----------------+|| +-------------+|
|| |HestTable | || HestErrorSource | | | HestErrorSource ||| | DMC-620
||
|| | DXE | || DXE | | | StandaloneMM ||| |Standalone MM||
|| +-----------+ |+------------------+ | +-----------------+|| +-------------+|
|| |GHESv2 | || |
|| +---------------------+--------------------+| |
|| +--------------------+ | | |
|| |PlatformErrorHandler| | | |
|| | DXE | | | |
|| +--------------------+ | | |
||FF FWK | | |
|+-------------------------------------+---------------------+
|+-------------------------------------+---------------------+ |
| | |
+--------------------------------------+--------------------------------------+
|
Figure: Firmware First Error Handling approach.

All the hardware error sources are added to HEST table as GHESv2[3] error
source descriptors. The framework comprises of following DXE and MM
drivers:

- HestTableDxe:
Builds HEST table header and allows appending error source descriptors to
the
HEST table. Also provides protocol interface to install the built HEST table.

- HestErrorSourceDxe & HestErrorSourceStandaloneMM:
These two drivers together retrieve all possible error source descriptors of
type GHESv2 from the MM drivers implementing HEST Error Source
Descriptor
protocol. Once all the descriptors are collected HestErrorSourceDxe
appends
it to HEST table using HestTableDxe driver.

Link to github branch with the patches in this series -
https://github.com/omkkul01/edk2/tree/ras_firware_first_edk2-
platforms_v3

Omkar Anand Kulkarni (5):
MdeModulePkg: Allow dynamic generation of HEST ACPI table
ArmPlatformPkg: add definition for
MM_HEST_ERROR_SOURCE_DESC_PROTOCOL
ArmPlatformPkg: retreive error source descriptors from MM
EmbeddedPkg: Add helpers for HEST table generation
ArmPlatformPkg: Add Readme file

ArmPlatformPkg/ArmPlatformPkg.dec | 10 +
MdeModulePkg/MdeModulePkg.dec | 3 +
.../HestMmErrorSources/HestErrorSourceDxe.inf | 45 +++
.../HestErrorSourceStandaloneMm.inf | 51 +++
.../Universal/Apei/HestDxe/HestDxe.inf | 49 +++
.../HestMmErrorSourceCommon.h | 37 ++
.../Include/Protocol/HestErrorSourceInfo.h | 64 ++++
EmbeddedPkg/Include/Library/AcpiLib.h | 20 ++
MdeModulePkg/Include/Protocol/HestTable.h | 71 ++++
MdePkg/Include/Protocol/MmCommunication.h | 2 +
.../HestMmErrorSources/HestErrorSourceDxe.c | 309 +++++++++++++++++
.../HestErrorSourceStandaloneMm.c | 312 +++++++++++++++++
MdeModulePkg/Universal/Apei/HestDxe/HestDxe.c | 318
++++++++++++++++++
.../Drivers/HestMmErrorSources/Readme.md | 66 ++++
14 files changed, 1357 insertions(+)
create mode 100644
ArmPlatformPkg/Drivers/HestMmErrorSources/HestErrorSourceDxe.inf
create mode 100644
ArmPlatformPkg/Drivers/HestMmErrorSources/HestErrorSourceStandalone
Mm.inf
create mode 100644 MdeModulePkg/Universal/Apei/HestDxe/HestDxe.inf
create mode 100644
ArmPlatformPkg/Drivers/HestMmErrorSources/HestMmErrorSourceCommo
n.h
create mode 100644
ArmPlatformPkg/Include/Protocol/HestErrorSourceInfo.h
create mode 100644 MdeModulePkg/Include/Protocol/HestTable.h
create mode 100644
ArmPlatformPkg/Drivers/HestMmErrorSources/HestErrorSourceDxe.c
create mode 100644
ArmPlatformPkg/Drivers/HestMmErrorSources/HestErrorSourceStandalone
Mm.c
create mode 100644 MdeModulePkg/Universal/Apei/HestDxe/HestDxe.c
create mode 100644
ArmPlatformPkg/Drivers/HestMmErrorSources/Readme.md

--
2.17.1



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IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

Added a readme file that explains the software framework for dynamic
generation of HEST table.

Signed-off-by: Omkar Anand Kulkarni <omkar.kulkarni@...>
---
ArmPlatformPkg/Drivers/HestMmErrorSources/Readme.md | 66 +++++++++++++++=
+++++
1 file changed, 66 insertions(+)

diff --git a/ArmPlatformPkg/Drivers/HestMmErrorSources/Readme.md b/ArmPla=
tformPkg/Drivers/HestMmErrorSources/Readme.md
new file mode 100644
index 000000000000..1b6f0713cb9a
--- /dev/null
+++ b/ArmPlatformPkg/Drivers/HestMmErrorSources/Readme.md
@@ -0,0 +1,66 @@
+Hardware Error Source Table (HEST)[1] and Software Delegated Exception I=
nterface
+(SDEI)[2] ACPI tables are used to acomplish firmware first error handlin=
g.This
+patch series introduces a framework to build and install the HEST ACPI t=
able
+dynamically.
+
+The following figure illustrates the possible usage of the dyanamic
+generation of HEST ACPI table.
+
+ NS | S
++--------------------------------------+--------------------------------=
------+
+| | =
|
+|+-------------------------------------+---------------------+ =
|
+|| +---------------------+--------------------+| =
|
+|| | | || =
|
+|| +-----------+ |+------------------+ | +-----------------+|| +--------=
-----+|
+|| |HestTable | || HestErrorSource | | | HestErrorSource ||| | DMC-620=
||
+|| | DXE | || DXE | | | StandaloneMM ||| |Standalo=
ne MM||
+|| +-----------+ |+------------------+ | +-----------------+|| +--------=
-----+|
+|| |GHESv2 | || =
|
+|| +---------------------+--------------------+| =
|
+|| +--------------------+ | | =
|
+|| |PlatformErrorHandler| | | =
|
+|| | DXE | | | =
|
+|| +--------------------+ | | =
|
+||FF FWK | | =
|
+|+-------------------------------------+---------------------+ =
|
+| | =
|
++--------------------------------------+--------------------------------=
------+
+ |
+ Figure: Dynamic Hest Table Generation.
+
+All the hardware error sources are added to HEST table as GHESv2[3] erro=
r source
+descriptors. The framework comprises of following DXE and MM drivers:
+
+- HestTableDxe:
+ Builds HEST table header and allows appending error source descriptors=
to the
+ HEST table. Also provides protocol interface to install the built HEST=
table.
+
+- HestErrorSourceDxe & HestErrorSourceStandaloneMM:
+ These two drivers together retrieve all possible error source descript=
ors of
+ type GHESv2 from the MM drivers implementing HEST Error Source Descrip=
tor
+ protocol. Once all the descriptors are collected HestErrorSourceDxe ap=
pends
+ it to HEST table using HestTableDxe driver.
+
+- PlatformErrorHandlerDxe:
+ Builds and installs SDEI ACPI table. This driver does not initialize(l=
oad)
+ until HestErrorSourceDxe driver has finished appending all possible GH=
ESv2
+ error source descriptors to the HEST table. Once that is complete usin=
g the
+ HestTableDxe driver it installs the HEST table.
+
+This patch series provides reference implementation for DMC-620 Dynamic =
Memory
+Controller[4] that has RAS feature enabled. This is platform code
+implemented as Standalone MM driver in edk2-platforms.
+
+References:
+[1] : ACPI 6.3, Table 18-382, Hardware Error Source Table
+[2] : SDEI Platform Design Document, revision b, 10 Appendix C, ACPI tab=
le
+ definitions for SDEI
+[3] : ACPI Reference Specification 6.3, Table 18-393 GHESv2 Structure
+[4] : DMC620 Dynamic Memory Controller, revision r1p0
+[5] : UEFI Reference Specification 2.8, Appendix N - Common Platform Err=
or
+ Record
+[6] : UEFI Reference Specification 2.8, Section N.2.5 Memory Error Secti=
on
+
+Link to github branch with the patches in this series -
+https://github.com/omkkul01/edk2/tree/ras_firmware_first_edk2
--=20
2.17.1