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Re: [edk2-non-osi] [PATCH] Maintainers.txt: Modify maintainer role for EHL Nate DeSimone #79805 Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...> toggle quoted messageShow quoted text -----Original Message----- From: Lim, Jin Jhu <jin.jhu.lim@...> Sent: Tuesday, August 24, 2021 4:47 AM To: devel@edk2.groups.io Cc: Lim, Jin Jhu <jin.jhu.lim@...>; Desimone, Nathaniel L <nathaniel.l.desimone@...>; Chaganty, Rangasai V <rangasai.v.chaganty@...> Subject: [edk2-devel] [edk2-non-osi] [PATCH] Maintainers.txt: Modify maintainer role for EHL Modify my role to be one of the EHL maintainers. Signed-off-by: jinjhuli <jin.jhu.lim@...> Cc: Nate DeSimone <nathaniel.l.desimone@...> Cc: Sai Chaganty <rangasai.v.chaganty@...> --- Maintainers.txt \| 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Maintainers.txt b/Maintainers.txt index d5865ba..b8a4140 100644 --- a/Maintainers.txt +++ b/Maintainers.txt @@ -56,7 +56,7 @@ M: Sai Chaganty <rangasai.v.chaganty@...> Silicon/Intel/ElkhartlakeSiliconBinPkg M: Nate DeSimone <nathaniel.l.desimone@...> M: Sai Chaganty <rangasai.v.chaganty@...> -R: Jin Jhu Lim <jin.jhu.lim@...> +M: Jin Jhu Lim <jin.jhu.lim@...> Silicon/Intel/KabylakeSiliconBinPkg M: Chasel Chiu <chasel.chiu@...> -- 2.28.0.windows.1
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Re: [PATCH] UefiPayloadPkg: Include Network modules in UefiPayloadPkg. Guo Dong #79804 It would be better if the FD size could change based on features as below, but it looks the FDF doesn't support expression ☹ !if $(NETWORK_DRIVER_ENABLE) == TRUE $(NUM_BLOCKS) += 0x170 !endif DEFINE FD_SIZE = $(NUM_BLOCKS) * $(FD_BLOCK_SIZE) Reviewed-by: Guo Dong <guo.dong@...> Thanks, Guo toggle quoted messageShow quoted text -----Original Message----- From: Sravanthi, K KavyaX <k.kavyax.sravanthi@...> Sent: Monday, August 23, 2021 10:40 PM To: devel@edk2.groups.io Cc: Sravanthi, K KavyaX <k.kavyax.sravanthi@...>; Dong, Guo <guo.dong@...>; Ni, Ray <ray.ni@...>; Ma, Maurice <maurice.ma@...>; You, Benjamin <benjamin.you@...> Subject: [PATCH] UefiPayloadPkg: Include Network modules in UefiPayloadPkg. From: Sravanthi <k.kavyax.sravanthi@...> Include Network modules in UefiPayloadPkg.dsc and UefiPayloadPkg.fdf Cc: Guo Dong <guo.dong@...> Cc: Ray Ni <ray.ni@...> Cc: Maurice Ma <maurice.ma@...> Cc: Benjamin You <benjamin.you@...> Signed-off-by: Sravanthi <k.kavyax.sravanthi@...> --- UefiPayloadPkg/UefiPayloadPkg.dsc \| 9 +++++++++ UefiPayloadPkg/UefiPayloadPkg.fdf \| 11 +++++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/UefiPayloadPkg/UefiPayloadPkg.dsc b/UefiPayloadPkg/UefiPayloadPkg.dsc index ff02ac6103..8691cb217a 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.dsc +++ b/UefiPayloadPkg/UefiPayloadPkg.dsc @@ -92,6 +92,7 @@ DEFINE DISABLE_RESET_SYSTEM = FALSE DEFINE SECURE_BOOT_ENABLE = TRUE DEFINE ENABLE_TCG_SUPPORT = TRUE + DEFINE NETWORK_DRIVER_ENABLE = TRUE # Dfine the maximum size of the capsule image without a reset flag that the platform can support. DEFINE MAX_SIZE_NON_POPULATE_CAPSULE = 0xa00000 @@ -167,6 +168,7 @@ OpensslLib\|CryptoPkg/Library/OpensslLib/OpensslLib.inf IntrinsicLib\|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf RngLib\|MdePkg/Library/BaseRngLib/BaseRngLib.inf + TlsLib\|CryptoPkg/Library/TlsLib/TlsLib.inf !if $(UNIVERSAL_PAYLOAD) == TRUE HobLib\|UefiPayloadPkg/Library/DxeHobLib/DxeHobLib.inf @@ -452,6 +454,13 @@ !endif !endif +# +# UEFI network modules +# +!if $(NETWORK_DRIVER_ENABLE) == TRUE + !include NetworkPkg/Network.dsc.inc +!endif + [Components.X64] # # DXE Core diff --git a/UefiPayloadPkg/UefiPayloadPkg.fdf b/UefiPayloadPkg/UefiPayloadPkg.fdf index afb57612f7..1b6c93c961 100644 --- a/UefiPayloadPkg/UefiPayloadPkg.fdf +++ b/UefiPayloadPkg/UefiPayloadPkg.fdf @@ -17,8 +17,8 @@ DEFINE FD_SIZE = 0x00850000 DEFINE NUM_BLOCKS = 0x850 !else -DEFINE FD_SIZE = 0x00470000 -DEFINE NUM_BLOCKS = 0x470 +DEFINE FD_SIZE = 0x00640000 +DEFINE NUM_BLOCKS = 0x640 !endif ################################################################################ @@ -214,6 +214,13 @@ INF SecurityPkg/Tcg/TcgDxe/TcgDxe.inf INF SecurityPkg/Tcg/Tcg2Acpi/Tcg2Acpi.inf !endif +# +# UEFI network modules +# +!if $(NETWORK_DRIVER_ENABLE) == TRUE + !include NetworkPkg/Network.fdf.inc +!endif + # # Shell # -- 2.30.2.windows.1
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Re: [PATCH 18/23] OvmfPkg: Enable Tdx in SecMain.c Yao, Jiewen #79803 Comment below: toggle quoted messageShow quoted text -----Original Message----- From: kraxel@... <kraxel@...> Sent: Wednesday, August 25, 2021 10:52 PM To: Yao, Jiewen <jiewen.yao@...> Cc: devel@edk2.groups.io; Ard Biesheuvel <ardb@...>; Xu, Min M <min.m.xu@...>; Ard Biesheuvel <ardb+tianocore@...>; Justen, Jordan L <jordan.l.justen@...>; Brijesh Singh <brijesh.singh@...>; Erdem Aktas <erdemaktas@...>; James Bottomley <jejb@...>; Tom Lendacky <thomas.lendacky@...> Subject: Re: [edk2-devel] [PATCH 18/23] OvmfPkg: Enable Tdx in SecMain.c Hi, In TDVF design, we choose the use TDX defined initial pointer to pass the initial memory information - TD_HOB, instead of CMOS region. Please help me understand what is the real concern here. Well, qemu settled to the fw_cfg design or a number of reasons. It is pretty flexible for example. The firmware can ask for the information it needs at any time and can store it as it pleases. I'd suggest to not take it for granted that an additional alternative way to do basically the same thing will be accepted to upstream qemu. Submit your patches to qemu-devel to discuss that. [Jiewen] I think Intel Linux team is doing that separately. Please ask them to send the patches. Changes like this obviously need coordination and agreement between qemu and edk2 projects, and ideally both guest and host code is reviewed in parallel. [Jiewen] Sure. I add Yamahata, Isaku <isaku.yamahata@...> here. He can help answer the KVM/QEMU related question. Some reference for QEMU: https://lists.nongnu.org/archive/html/qemu-devel/2021-07/msg01682.html in patchwork, https://patchwork.kernel.org/project/qemu-devel/cover/cover.1625704980.git.isaku.yamahata@intel.com/ And I guess you probably need look at the KVM as well. Most fw_cfg entries are constant anyway, so we can easily avoid a second call by caching the results of the first call if that helps TDVF. [Jiewen] It is possible. We can have multiple ways: 1) Per usage cache. However, that means every driver need use its own way to cache the data, either PCD or HOB in PEI phase. Also driver A need to know clearly that driver B will use the same data, then it will cache otherwise it will not cache. I treat it as a huge burden for the developer. 2) Always cache per driver. That means every driver need follow the same pattern: search cache, if miss the get it and cache it. But it still cannot guarantee the data order in different path architecturally. 3) Always cache in one common driver. One driver can get all data one time and cache them. That can resolve the data order problem. I am not sure if that is desired. But I cannot see too much difference between passing data at entry point. Not investigated yet. seabios fw_cfg handling is close to (3) for small items (not kernel or initrd or other large data sets) so I think I would look into that first. [Jiewen] I don't think it is urgent at this moment. Using HOB in the initial pointer can be an alternative pattern to mitigate such risk. We just need measure them once then any component can use that. Also, it can help the people to evaluate the RTMR hash and TD event log data for the configuration in attestation flow, because the configuration is independent with the code execution flow. Well, it covers only the memory map, correct? All other configuration is still loaded from fw_cfg. I can't see the improvement here. [Jiewen] At this point of time, memory map is the most important parameter in the TD Hob, because we do need the memory information at the TD entrypoint. That is mandatory for any TD boot. Well, I can see that the memory map is kind of special here because you need that quite early in the firmware initialization workflow. [Jiewen] That is correct. The fw_cfg is still allowed in the TDVF design guide, just because we feel it is a burden to convert everything suddenly. What is the longer-term plan here? Does it make sense to special-case the memory map? If we want handle other fw_cfg items that way too later on, shouldn't we better check how we can improve the fw_cfg interface so it works better with confidential computing? [Jiewen] So far, my hope is to limit the fw_cfg as much as possible. My worry is that we have to measure fw_cfg everywhere. If we miss one place, it will be a completeness vulnerability for trusted computing. I also think if we can add measurement code inside of fw_cfg get function. Then we need improve the FwCfg API - Current style: QemuFwCfgSelectItem() + QemuFwCfgReadxxx() is not friendly for measurement. For example, we can combine them and do QemuFwCfgSelectRead (). The QemuFwCfgWritexxx() interface may also bring inconsistency issue. If we use this API, we have 2 copy data. One is in TDVF (trusted), and the other is in VMM/QEMU (untrusted). What if the VMM modifies its untrusted copy? What I can see is many potential attack surfaces. :-( How do you pass the HOB to the guest? Copy data to guest ram? Map a ro page into guest address space? What happens on VM reset? [Jiewen] Yes, VMM will prepare the memory information based upon TDVF metadata. The VMM need copy TD HOB data to a predefined memory region according to TDVF metadata. Is all that documented somewhere? The TVDF design overview focuses on the guest/firmware side of things, so it isn't very helpful here. [Jiewen] The TDX architecture define this architecture way, the RCX/R9 refer is the pointer. We have a couple of TDX document at https://software.intel.com/content/www/us/en/develop/articles/intel-trust-domain-extensions.html https://software.intel.com/content/dam/develop/external/us/en/documents/tdx-module-1eas-v0.85.039.pdf Section 8.1 defines the VCPU init state. The RCX/R8 hold the launch parameter. https://software.intel.com/content/dam/develop/external/us/en/documents/tdx-virtual-firmware-design-guide-rev-1.pdf Section 4.1.2 describes the TD HOB usage for RCX/R8. Section 7 adds more detail on memory map reporting. Please let me know if you need any other information. Did I mention posting the qemu patches would be a good idea? I don't fully understand the VM reset question. I try to answer. But if that is not what you are asking, please clarify. What happens if you reboot the guest? On non-TDX guests the VM will be reset, the cpu will jump to the reset vector (executing from rom / flash), firmware will re-initialize everything and re-load any config information it needs from fw_cfg This action that VMM initiates TD HOB happens when the VMM launches a TD guest. After that the region will becomes TD private memory and own by TD. VMM can no longer access it (no read/no write). If VM reset, then this memory is gone. If VMM need launch a new TD, the VMM need initiate the data again. Sounds like reset is not supported, you need to stop and re-start the guest instead. Is that correct? [Jiewen] That is correct. In our definition, reset == stop + restart. take care, Gerd
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[edk2-libc Patch 0/1] Base Python interpreter 3.6.8 version code from python open source project Jayaprakash, N #79802 * BLURB HERE * Jayaprakash Nevara (1): AppPkg/Applications/Python/Python3.6.8: Base code from python git repo v3.6.8 .../Python-3.6.8/.azure-pipelines/ci.yml \| 136 + .../.azure-pipelines/docker-steps.yml \| 76 + .../.azure-pipelines/docs-steps.yml \| 46 + .../.azure-pipelines/macos-steps.yml \| 25 + .../.azure-pipelines/posix-deps.sh \| 26 + .../.azure-pipelines/posix-steps.yml \| 63 + .../Python-3.6.8/.azure-pipelines/pr.yml \| 86 + .../.azure-pipelines/prebuild-checks.yml \| 36 + .../.azure-pipelines/windows-steps.yml \| 32 + .../Python/Python-3.6.8/.bzrignore \| 42 + .../Python/Python-3.6.8/.gitattributes \| 58 + .../.github/PULL_REQUEST_TEMPLATE.md \| 9 + .../Python/Python-3.6.8/.github/appveyor.yml \| 38 + .../Python/Python-3.6.8/.github/codecov.yml \| 36 + .../Python/Python-3.6.8/.gitignore \| 103 + .../Python/Python-3.6.8/.hgignore \| 105 + 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.../Lib/test/test_email/test_email.py \| 5402 ++ .../Lib/test/test_email/test_generator.py \| 296 + .../test/test_email/test_headerregistry.py \| 1653 + .../Lib/test/test_email/test_inversion.py \| 70 + .../Lib/test/test_email/test_message.py \| 803 + .../Lib/test/test_email/test_parser.py \| 110 + .../Lib/test/test_email/test_pickleable.py \| 76 + .../Lib/test/test_email/test_policy.py \| 346 + .../Lib/test/test_email/test_utils.py \| 165 + .../Lib/test/test_email/torture_test.py \| 133 + .../Python-3.6.8/Lib/test/test_ensurepip.py \| 310 + .../Python/Python-3.6.8/Lib/test/test_enum.py \| 2635 + .../Python-3.6.8/Lib/test/test_enumerate.py \| 269 + .../Python/Python-3.6.8/Lib/test/test_eof.py \| 28 + .../Python-3.6.8/Lib/test/test_epoll.py \| 264 + .../Python-3.6.8/Lib/test/test_errno.py \| 35 + .../Lib/test/test_exception_hierarchy.py \| 204 + .../Lib/test/test_exception_variations.py \| 176 + .../Python-3.6.8/Lib/test/test_exceptions.py \| 1288 + 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.../Modules/_multiprocessing/semaphore.c \| 679 + .../Python/Python-3.6.8/Modules/_opcode.c \| 78 + .../Python/Python-3.6.8/Modules/_operator.c \| 1232 + .../Python/Python-3.6.8/Modules/_pickle.c \| 7421 ++ .../Python-3.6.8/Modules/_posixsubprocess.c \| 812 + .../Python-3.6.8/Modules/_randommodule.c \| 548 + .../Python/Python-3.6.8/Modules/_scproxy.c \| 263 + .../Python-3.6.8/Modules/_sha3/README.txt \| 11 + .../Python-3.6.8/Modules/_sha3/cleanup.py \| 50 + .../Modules/_sha3/clinic/sha3module.c.h \| 85 + .../Modules/_sha3/kcp/KeccakHash.c \| 82 + .../Modules/_sha3/kcp/KeccakHash.h \| 114 + .../Modules/_sha3/kcp/KeccakP-1600-64.macros \| 2208 + .../_sha3/kcp/KeccakP-1600-SnP-opt32.h \| 37 + .../_sha3/kcp/KeccakP-1600-SnP-opt64.h \| 49 + .../Modules/_sha3/kcp/KeccakP-1600-SnP.h \| 7 + .../_sha3/kcp/KeccakP-1600-inplace32BI.c \| 1162 + .../_sha3/kcp/KeccakP-1600-opt64-config.h \| 3 + .../Modules/_sha3/kcp/KeccakP-1600-opt64.c \| 474 + .../_sha3/kcp/KeccakP-1600-unrolling.macros \| 185 + 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.../Python/Python-3.6.8/Modules/_sqlite/row.h \| 39 + .../Python-3.6.8/Modules/_sqlite/statement.c \| 544 + .../Python-3.6.8/Modules/_sqlite/statement.h \| 60 + .../Python-3.6.8/Modules/_sqlite/util.c \| 153 + .../Python-3.6.8/Modules/_sqlite/util.h \| 42 + .../Python/Python-3.6.8/Modules/_sre.c \| 2971 + .../Python/Python-3.6.8/Modules/_ssl.c \| 5717 ++ .../Python/Python-3.6.8/Modules/_ssl_data.h \| 1948 + .../Python/Python-3.6.8/Modules/_stat.c \| 599 + .../Python/Python-3.6.8/Modules/_struct.c \| 2364 + .../Python/Python-3.6.8/Modules/_testbuffer.c \| 2894 + .../Python-3.6.8/Modules/_testcapimodule.c \| 5002 ++ .../Modules/_testimportmultiple.c \| 57 + .../Python-3.6.8/Modules/_testmultiphase.c \| 670 + .../Python-3.6.8/Modules/_threadmodule.c \| 1414 + .../Python/Python-3.6.8/Modules/_tkinter.c \| 3659 + .../Python-3.6.8/Modules/_tracemalloc.c \| 1827 + .../Python/Python-3.6.8/Modules/_weakref.c \| 174 + .../Python/Python-3.6.8/Modules/_winapi.c \| 1604 + .../Python/Python-3.6.8/Modules/addrinfo.h \| 168 + .../Python/Python-3.6.8/Modules/ar_beos \| 73 + .../Python/Python-3.6.8/Modules/arraymodule.c \| 3039 + .../Python-3.6.8/Modules/atexitmodule.c \| 346 + .../Python/Python-3.6.8/Modules/audioop.c \| 1921 + .../Python/Python-3.6.8/Modules/binascii.c \| 1586 + .../Python-3.6.8/Modules/cjkcodecs/README \| 79 + .../Modules/cjkcodecs/_codecs_cn.c \| 464 + .../Modules/cjkcodecs/_codecs_hk.c \| 191 + .../Modules/cjkcodecs/_codecs_iso2022.c \| 1143 + .../Modules/cjkcodecs/_codecs_jp.c \| 760 + .../Modules/cjkcodecs/_codecs_kr.c \| 468 + .../Modules/cjkcodecs/_codecs_tw.c \| 143 + .../Modules/cjkcodecs/alg_jisx0201.h \| 65 + .../Modules/cjkcodecs/cjkcodecs.h \| 417 + .../cjkcodecs/clinic/multibytecodec.c.h \| 333 + .../Modules/cjkcodecs/emu_jisx0213_2000.h \| 54 + .../Modules/cjkcodecs/mappings_cn.h \| 4103 + .../Modules/cjkcodecs/mappings_hk.h \| 2378 + .../cjkcodecs/mappings_jisx0213_pair.h \| 59 + .../Modules/cjkcodecs/mappings_jp.h \| 4765 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.../Python-3.6.8/Modules/clinic/_winapi.c.h \| 892 + .../Modules/clinic/arraymodule.c.h \| 508 + .../Python-3.6.8/Modules/clinic/audioop.c.h \| 931 + .../Python-3.6.8/Modules/clinic/binascii.c.h \| 553 + .../Modules/clinic/cmathmodule.c.h \| 885 + .../Modules/clinic/fcntlmodule.c.h \| 189 + .../Python-3.6.8/Modules/clinic/grpmodule.c.h \| 89 + .../Python-3.6.8/Modules/clinic/md5module.c.h \| 97 + .../Modules/clinic/posixmodule.c.h \| 6153 ++ .../Python-3.6.8/Modules/clinic/pwdmodule.c.h \| 72 + .../Python-3.6.8/Modules/clinic/pyexpat.c.h \| 292 + .../Modules/clinic/sha1module.c.h \| 97 + .../Modules/clinic/sha256module.c.h \| 127 + .../Modules/clinic/sha512module.c.h \| 127 + .../Modules/clinic/signalmodule.c.h \| 442 + .../Modules/clinic/spwdmodule.c.h \| 69 + .../Modules/clinic/unicodedata.c.h \| 382 + .../Modules/clinic/zlibmodule.c.h \| 474 + .../Python/Python-3.6.8/Modules/cmathmodule.c \| 1413 + .../Python/Python-3.6.8/Modules/config.c.in \| 67 + .../Python/Python-3.6.8/Modules/errnomodule.c \| 935 + .../Python/Python-3.6.8/Modules/expat/COPYING \| 21 + .../Python/Python-3.6.8/Modules/expat/ascii.h \| 120 + .../Python-3.6.8/Modules/expat/asciitab.h \| 64 + .../Python/Python-3.6.8/Modules/expat/expat.h \| 1085 + .../Python-3.6.8/Modules/expat/expat_config.h \| 19 + .../Modules/expat/expat_external.h \| 166 + .../Python-3.6.8/Modules/expat/iasciitab.h \| 65 + .../Python-3.6.8/Modules/expat/internal.h \| 124 + .../Python-3.6.8/Modules/expat/latin1tab.h \| 64 + .../Python-3.6.8/Modules/expat/loadlibrary.c \| 143 + .../Python-3.6.8/Modules/expat/nametab.h \| 182 + .../Python-3.6.8/Modules/expat/pyexpatns.h \| 125 + .../Python-3.6.8/Modules/expat/siphash.h \| 391 + .../Python-3.6.8/Modules/expat/utf8tab.h \| 64 + .../Python-3.6.8/Modules/expat/winconfig.h \| 63 + .../Python-3.6.8/Modules/expat/xmlparse.c \| 7217 ++ .../Python-3.6.8/Modules/expat/xmlrole.c \| 1386 + .../Python-3.6.8/Modules/expat/xmlrole.h \| 142 + .../Python-3.6.8/Modules/expat/xmltok.c \| 1809 + .../Python-3.6.8/Modules/expat/xmltok.h \| 345 + .../Python-3.6.8/Modules/expat/xmltok_impl.c \| 1763 + .../Python-3.6.8/Modules/expat/xmltok_impl.h \| 73 + .../Python-3.6.8/Modules/expat/xmltok_ns.c \| 142 + .../Python-3.6.8/Modules/faulthandler.c \| 1413 + .../Python/Python-3.6.8/Modules/fcntlmodule.c \| 655 + .../Python-3.6.8/Modules/fpectlmodule.c \| 277 + .../Python-3.6.8/Modules/fpetestmodule.c \| 200 + .../Python-3.6.8/Modules/gc_weakref.txt \| 219 + .../Python/Python-3.6.8/Modules/gcmodule.c \| 1800 + .../Python/Python-3.6.8/Modules/getaddrinfo.c \| 638 + .../Python-3.6.8/Modules/getbuildinfo.c \| 67 + .../Python/Python-3.6.8/Modules/getnameinfo.c \| 214 + .../Python/Python-3.6.8/Modules/getpath.c \| 879 + .../Python/Python-3.6.8/Modules/grpmodule.c \| 256 + .../Python/Python-3.6.8/Modules/hashlib.h \| 64 + .../Python/Python-3.6.8/Modules/hashtable.c \| 524 + .../Python/Python-3.6.8/Modules/hashtable.h \| 211 + .../Python-3.6.8/Modules/itertoolsmodule.c \| 4676 + .../Python/Python-3.6.8/Modules/ld_so_aix.in \| 195 + .../Python/Python-3.6.8/Modules/ld_so_beos \| 78 + .../Python/Python-3.6.8/Modules/main.c \| 868 + .../Python/Python-3.6.8/Modules/makesetup \| 296 + .../Python/Python-3.6.8/Modules/makexp_aix \| 81 + .../Python/Python-3.6.8/Modules/mathmodule.c \| 2155 + .../Python/Python-3.6.8/Modules/md5module.c \| 585 + .../Python/Python-3.6.8/Modules/mmapmodule.c \| 1490 + .../Python/Python-3.6.8/Modules/nismodule.c \| 469 + .../Python/Python-3.6.8/Modules/ossaudiodev.c \| 1317 + .../Python/Python-3.6.8/Modules/overlapped.c \| 1346 + .../Python-3.6.8/Modules/parsermodule.c \| 1228 + .../Python/Python-3.6.8/Modules/posixmodule.c \| 13227 +++ .../Python/Python-3.6.8/Modules/posixmodule.h \| 25 + .../Python/Python-3.6.8/Modules/pwdmodule.c \| 247 + .../Python/Python-3.6.8/Modules/pyexpat.c \| 1998 + .../Python/Python-3.6.8/Modules/readline.c \| 1431 + .../Python/Python-3.6.8/Modules/resource.c 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Re: [PATCH 2/2] OvmfPkg/PlatformPei: prefer etc/e820 for memory detection Yao, Jiewen #79801 Thanks for the detail info. We do have process for handle compatibility. My recommendation is: 1) Please send out RFC email about removing CMOS support in QEMU. To see if someone still need support old version before qemu version 1.7 (released Nov 2013). 2) Let's wait for 1 WW. 3) If no people need this, we can file a bugzilla to remove CMOS. Then we can follow up to submit patch to remove. Please help me understand another thing: Is that any plan in QEMU to remove CMOS interface ? That could be a good indicator to remove the problem - we have two ways to get one data. I am worried the logic below to add "LowerMemorySize > 0". ===================== GetSystemMemorySizeBelow4gb() { EFI_STATUS Status; UINT64 LowerMemorySize; UINT8 Cmos0x34; UINT8 Cmos0x35; Status = ScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL); if (Status == EFI_SUCCESS \|\| LowerMemorySize > 0) { return LowerMemorySize; } ... } EFI_STATUS ScanOrAdd64BitE820Ram ( IN BOOLEAN AddHighHob, OUT UINT64 LowMemory OPTIONAL, OUT UINT64 MaxAddress OPTIONAL ) { EFI_STATUS Status; FIRMWARE_CONFIG_ITEM FwCfgItem; UINTN FwCfgSize; EFI_E820_ENTRY64 E820Entry; UINTN Processed; Status = QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize); if (EFI_ERROR (Status)) { return Status; } if (FwCfgSize % sizeof E820Entry != 0) { return EFI_PROTOCOL_ERROR; } if (LowMemory != NULL) { LowMemory = 0; } ... } ===================== In GetSystemMemorySizeBelow4gb (), we return LowerMemorySize, if Status is SUCCESS, or (Status == ERROR && LowerMemorySize > 0) However, the LowerMemorySize is unitialized data in stack. It may be a garbage. In ScanOrAdd64BitE820Ram(), the LowerMemorySize is initialized after the ERROR is returned. That means, if the Status is ERROR, we have still a big chance to return LowerMemorySize > 0 case, if the LowerMemorySize is garbage. Would you please also share the info, what kind of test you have run for that code? Have you tried the E820 fail case? Thank you Yao Jiewen toggle quoted messageShow quoted text -----Original Message----- From: kraxel@... <kraxel@...> Sent: Wednesday, August 25, 2021 9:14 PM To: Yao, Jiewen <jiewen.yao@...> Cc: devel@edk2.groups.io Subject: Re: [edk2-devel] [PATCH 2/2] OvmfPkg/PlatformPei: prefer etc/e820 for memory detection On Wed, Aug 25, 2021 at 09:24:43AM +0000, Yao, Jiewen wrote: Hi Would you please follow EDKII process? 1) File an EDKII Bugzilla. Ok, will do. 2) CC all reviewers in OVMF package. Is there some way to automate this? I see there is BaseTools/Scripts/GetMaintainer.py, but the script wants a commit hash not a patch file as argument, so I can't hook it into 'git send-email'. Please also describe what the reason of change, what is the benefit we can get from the change? I just feel it is confusing. Previously, the data is consistent from CMOS. Now, we have two ways to get one data from different sources. It is not* consistent from CMOS. CMOS is only used for memory below 4G whereas the etc/e820 fw_cfg file is used for memory above 4G. So this patch actually makes things more consistent. Please help me understand: A) What if the data are different from different source? B) Why we choose to trust E820 at first, the CMOS? Not verse versa. e820 is the newer and more capable interface, specifically cmos can handle at most 1TB of memory (which is the reason why e820 is already used to detect high memory). C) If we trust E820 (in B), then why we need go back to CMOS, if LowMemorySize is 0? Backward compatibility with old qemu versions. etc/e820 is available in qemu version 1.7 (released Nov 2013) and newer. Does OVMF have any policy for backward compatibility? If breaking compatibility with qemu versions that old is acceptable I happily delete any CMOS access from qemu PlatformPei and throw an assert() instead. take care, Gerd
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Re: [PATCH 18/23] OvmfPkg: Enable Tdx in SecMain.c Gerd Hoffmann #79800 Hi, In TDVF design, we choose the use TDX defined initial pointer to pass the initial memory information - TD_HOB, instead of CMOS region. Please help me understand what is the real concern here. Well, qemu settled to the fw_cfg design or a number of reasons. It is pretty flexible for example. The firmware can ask for the information it needs at any time and can store it as it pleases. I'd suggest to not take it for granted that an additional alternative way to do basically the same thing will be accepted to upstream qemu. Submit your patches to qemu-devel to discuss that. [Jiewen] I think Intel Linux team is doing that separately. Please ask them to send the patches. Changes like this obviously need coordination and agreement between qemu and edk2 projects, and ideally both guest and host code is reviewed in parallel. Most fw_cfg entries are constant anyway, so we can easily avoid a second call by caching the results of the first call if that helps TDVF. [Jiewen] It is possible. We can have multiple ways: 1) Per usage cache. However, that means every driver need use its own way to cache the data, either PCD or HOB in PEI phase. Also driver A need to know clearly that driver B will use the same data, then it will cache otherwise it will not cache. I treat it as a huge burden for the developer. 2) Always cache per driver. That means every driver need follow the same pattern: search cache, if miss the get it and cache it. But it still cannot guarantee the data order in different path architecturally. 3) Always cache in one common driver. One driver can get all data one time and cache them. That can resolve the data order problem. I am not sure if that is desired. But I cannot see too much difference between passing data at entry point. Not investigated yet. seabios fw_cfg handling is close to (3) for small items (not kernel or initrd or other large data sets) so I think I would look into that first. Using HOB in the initial pointer can be an alternative pattern to mitigate such risk. We just need measure them once then any component can use that. Also, it can help the people to evaluate the RTMR hash and TD event log data for the configuration in attestation flow, because the configuration is independent with the code execution flow. Well, it covers only the memory map, correct? All other configuration is still loaded from fw_cfg. I can't see the improvement here. [Jiewen] At this point of time, memory map is the most important parameter in the TD Hob, because we do need the memory information at the TD entrypoint. That is mandatory for any TD boot. Well, I can see that the memory map is kind of special here because you need that quite early in the firmware initialization workflow. The fw_cfg is still allowed in the TDVF design guide, just because we feel it is a burden to convert everything suddenly. What is the longer-term plan here? Does it make sense to special-case the memory map? If we want handle other fw_cfg items that way too later on, shouldn't we better check how we can improve the fw_cfg interface so it works better with confidential computing? How do you pass the HOB to the guest? Copy data to guest ram? Map a ro page into guest address space? What happens on VM reset? [Jiewen] Yes, VMM will prepare the memory information based upon TDVF metadata. The VMM need copy TD HOB data to a predefined memory region according to TDVF metadata. Is all that documented somewhere? The TVDF design overview focuses on the guest/firmware side of things, so it isn't very helpful here. Did I mention posting the qemu patches would be a good idea? I don't fully understand the VM reset question. I try to answer. But if that is not what you are asking, please clarify. What happens if you reboot the guest? On non-TDX guests the VM will be reset, the cpu will jump to the reset vector (executing from rom / flash), firmware will re-initialize everything and re-load any config information it needs from fw_cfg This action that VMM initiates TD HOB happens when the VMM launches a TD guest. After that the region will becomes TD private memory and own by TD. VMM can no longer access it (no read/no write). If VM reset, then this memory is gone. If VMM need launch a new TD, the VMM need initiate the data again. Sounds like reset is not supported, you need to stop and re-start the guest instead. Is that correct? take care, Gerd
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Re: [PATCH 2/2] OvmfPkg/PlatformPei: prefer etc/e820 for memory detection Gerd Hoffmann #79799 On Wed, Aug 25, 2021 at 09:24:43AM +0000, Yao, Jiewen wrote: Hi Would you please follow EDKII process? 1) File an EDKII Bugzilla. Ok, will do. 2) CC all reviewers in OVMF package. Is there some way to automate this? I see there is BaseTools/Scripts/GetMaintainer.py, but the script wants a commit hash not a patch file as argument, so I can't hook it into 'git send-email'. Please also describe what the reason of change, what is the benefit we can get from the change? I just feel it is confusing. Previously, the data is consistent from CMOS. Now, we have two ways to get one data from different sources. It is not consistent from CMOS. CMOS is only used for memory below 4G whereas the etc/e820 fw_cfg file is used for memory above 4G. So this patch actually makes things more consistent. Please help me understand: A) What if the data are different from different source? B) Why we choose to trust E820 at first, the CMOS? Not verse versa. e820 is the newer and more capable interface, specifically cmos can handle at most 1TB of memory (which is the reason why e820 is already used to detect high memory). C) If we trust E820 (in B), then why we need go back to CMOS, if LowMemorySize is 0? Backward compatibility with old qemu versions. etc/e820 is available in qemu version 1.7 (released Nov 2013) and newer. Does OVMF have any policy for backward compatibility? If breaking compatibility with qemu versions that old is acceptable I happily delete any CMOS access from qemu PlatformPei and throw an assert() instead. take care, Gerd
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Re: [PATCH] ArmPkg/GicV3Dxe: Don't signal EOI on arbitrary interrupts Leif Lindholm #79798 On Tue, Aug 24, 2021 at 17:31:32 +0200, Ard Biesheuvel wrote: Currently, at ExitBootServices() time, the GICv3 driver signals End-Of-Interrupt (EOI) on all interrupt lines that are supported by the interrupt controller. This appears to have been carried over from the GICv2 version, but has been turned into something that violates the GIC spec, and may trigger SError exceptions on some implementations. Marc puts it as follows: The GIC interrupt state machine is pretty strict. An interrupt can only be deactivated (with or without prior priority drop) if it has been acknowledged first. In GIC speak, this means that only the following sequences are valid: With EOImode==0: x = ICC_IAR{0,1}_EL1; ICC_EOIR{0,1}_EL1 = x; With EOImode==1: x = ICC_IAR{0,1}_EL1; ICC_EOIR{0,1}_EL1 = x; ICC_DIR_EL1 = x; Any write to ICC_EOIR{0,1}_EL1 that isn't the direct consequence of the same value being read from ICC_IAR{0,1}_EL1, and with the correct nesting, breaks the state machine and leads to unpredictable results that affects all interrupts in the system (most likely, the priority system is dead). See Figure 4-3 ("Interrupt handling state machine") in Arm IHI 0069F for a description of the acceptable transitions. Additionally, on implementations that have ICC_CTLR_EL1.SEIS==1, a SError may be generated to signal the error. See the various <quote> IMPLEMENTATION_DEFINED "SError ...."; </quote> that are all over the pseudocode contained in the same architecture spec. Needless to say, this is pretty final for any SW that would do silly things on such implementations (which do exist). Given that in our implementation, every signalled interrupt is acked, handled and EOId in sequence, there is no reason to EOI all interrupts at ExitBootServices() time in the first place, so let's just drop this code. This fixes an issue reported by Marc where an SError is triggered by this code, bringing down the system. Reported-by: Marc Zyngier <maz@...> Signed-off-by: Ard Biesheuvel <ardb@...> Yikes. Pretty sure that wasn't the right thing to do on gicv2 either. Reviewed-by: Leif Lindholm <leif@...> --- This is a clear bugfix, but given how late we are in the cycle, I will leave it up to Liming to decide whether we can still take this for the upcoming stable tag. I can see hypothetical situations where this could break existing (broken) firmware ... so I would prefer to leave it until after the stable tag unless there is substantial benefit to including it here. / Leif ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c \| 4 ---- 1 file changed, 4 deletions(-) diff --git a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c index 85ee4c87b6d1..fa515d1a01ba 100644 --- a/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c +++ b/ArmPkg/Drivers/ArmGic/GicV3/ArmGicV3Dxe.c @@ -344,10 +344,6 @@ GicV3ExitBootServicesEvent ( GicV3DisableInterruptSource (&gHardwareInterruptV3Protocol, Index); } - for (Index = 0; Index < mGicNumInterrupts; Index++) { - GicV3EndOfInterrupt (&gHardwareInterruptV3Protocol, Index); - } - // Disable Gic Interface ArmGicV3DisableInterruptInterface (); -- 2.30.2
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Re: Question regarding subscription and mailing list Marvin Häuser #79797 Hey, https://edk2.groups.io/g/devel -> "Join This Group" Best regards, Marvin toggle quoted messageShow quoted text On 25/08/2021 04:52, jinjhuli wrote: Hi, Good Day! May I know how can I subscribe and receive mailing list for this group? Thanks. Regards, Jin Jhu
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edk2-test-stable202108 is Released G Edhaya Chandran #79796 Hello All, edk2-test-stable202108 is now released. Please refer to the link for more details : https://github.com/tianocore/edk2-test/releases/tag/edk2-test-stable202108 Thanking you all for your contributions. Please feel free to contact me or Barton for any clarifications. With Warm Regards, Edhay From: G Edhaya Chandran Sent: 11 August 2021 01:02 To: devel@edk2.groups.io Cc: Samer El-Haj-Mahmoud <Samer.El-Haj-Mahmoud@...>; Barton Gao <gaojie@...> Subject: edk2-test Release Notice Hello All, This mail is to notify that the edk2-test repository shall be released by end of August 2021 with the tag edk2-test-stable202108. The base-line commit shall be: 814b2af535d977b3967d65de77e42ab18a4f4db4 Please feel free to contact me or Barton for any clarifications. With Warm Regards, Edhay IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
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Re: [PATCH 2/2] OvmfPkg/PlatformPei: prefer etc/e820 for memory detection Yao, Jiewen #79795 Hi Would you please follow EDKII process? 1) File an EDKII Bugzilla. 2) CC all reviewers in OVMF package. Please also describe what the reason of change, what is the benefit we can get from the change? I just feel it is confusing. Previously, the data is consistent from CMOS. Now, we have two ways to get one data from different sources. Please help me understand: A) What if the data are different from different source? B) Why we choose to trust E820 at first, the CMOS? Not verse versa. C) If we trust E820 (in B), then why we need go back to CMOS, if LowMemorySize is 0? Thank you Yao Jiewen toggle quoted messageShow quoted text -----Original Message----- From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Gerd Hoffmann Sent: Thursday, August 19, 2021 4:11 PM To: devel@edk2.groups.io Cc: Gerd Hoffmann <kraxel@...> Subject: [edk2-devel] [PATCH 2/2] OvmfPkg/PlatformPei: prefer etc/e820 for memory detection Prefer the e820 map provided via qemu firmware config interface for memory detection. Use rtc cmos only as fallback, which should be rarely needed these days as qemu supports etc/e820 since 2013. Signed-off-by: Gerd Hoffmann <kraxel@...> --- OvmfPkg/PlatformPei/MemDetect.c \| 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/OvmfPkg/PlatformPei/MemDetect.c b/OvmfPkg/PlatformPei/MemDetect.c index d7fb3e742be3..71bd28bd1d2b 100644 --- a/OvmfPkg/PlatformPei/MemDetect.c +++ b/OvmfPkg/PlatformPei/MemDetect.c @@ -293,9 +293,16 @@ GetSystemMemorySizeBelow4gb ( VOID ) { + EFI_STATUS Status; + UINT64 LowerMemorySize; UINT8 Cmos0x34; UINT8 Cmos0x35; + Status = ScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL); + if (Status == EFI_SUCCESS \|\| LowerMemorySize > 0) { + return LowerMemorySize; + } + // // CMOS 0x34/0x35 specifies the system memory above 16 MB. // * CMOS(0x35) is the high byte @@ -722,7 +729,6 @@ QemuInitializeRam ( // Determine total memory size available // LowerMemorySize = GetSystemMemorySizeBelow4gb (); - UpperMemorySize = GetSystemMemorySizeAbove4gb (); if (mBootMode == BOOT_ON_S3_RESUME) { // @@ -769,8 +775,11 @@ QemuInitializeRam ( // memory size read from the CMOS. // Status = ScanOrAdd64BitE820Ram (TRUE, NULL, NULL); - if (EFI_ERROR (Status) && UpperMemorySize != 0) { - AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); + if (EFI_ERROR (Status)) { + UpperMemorySize = GetSystemMemorySizeAbove4gb (); + if (UpperMemorySize != 0) { + AddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize); + } } } -- 2.31.1
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Re: [PATCH 18/23] OvmfPkg: Enable Tdx in SecMain.c Yao, Jiewen #79794 Comment below: toggle quoted messageShow quoted text -----Original Message----- From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Gerd Hoffmann Sent: Wednesday, August 25, 2021 3:52 PM To: Yao, Jiewen <jiewen.yao@...> Cc: Ard Biesheuvel <ardb@...>; Xu, Min M <min.m.xu@...>; devel@edk2.groups.io; Ard Biesheuvel <ardb+tianocore@...>; Justen, Jordan L <jordan.l.justen@...>; Brijesh Singh <brijesh.singh@...>; Erdem Aktas <erdemaktas@...>; James Bottomley <jejb@...>; Tom Lendacky <thomas.lendacky@...> Subject: Re: [edk2-devel] [PATCH 18/23] OvmfPkg: Enable Tdx in SecMain.c Hi, fw_cfg is just a KVM/QEMU specific way to pass some parameter, but not all parameter. For example, OVMF today still get the memory size from CMOS. https://github.com/tianocore/edk2/blob/master/OvmfPkg/PlatformPei/MemDe tect.c#L278 Patches to fix that are on the list. [Jiewen] Surprisingly. It was sent one week ago. I obviously miss that email. Please file a Bugzilla and include me in CC list next time. In TDVF design, we choose the use TDX defined initial pointer to pass the initial memory information - TD_HOB, instead of CMOS region. Please help me understand what is the real concern here. Well, qemu settled to the fw_cfg design or a number of reasons. It is pretty flexible for example. The firmware can ask for the information it needs at any time and can store it as it pleases. I'd suggest to not take it for granted that an additional alternative way to do basically the same thing will be accepted to upstream qemu. Submit your patches to qemu-devel to discuss that. [Jiewen] I think Intel Linux team is doing that separately. That means, if you get the same data twice from the fw_cfg, the TDVF must measure them twice. And TDVF may need handle the case that the data in first call is different with the data in second call. Most fw_cfg entries are constant anyway, so we can easily avoid a second call by caching the results of the first call if that helps TDVF. [Jiewen] It is possible. We can have multiple ways: 1) Per usage cache. However, that means every driver need use its own way to cache the data, either PCD or HOB in PEI phase. Also driver A need to know clearly that driver B will use the same data, then it will cache otherwise it will not cache. I treat it as a huge burden for the developer. 2) Always cache per driver. That means every driver need follow the same pattern: search cache, if miss the get it and cache it. But it still cannot guarantee the data order in different path architecturally. 3) Always cache in one common driver. One driver can get all data one time and cache them. That can resolve the data order problem. I am not sure if that is desired. But I cannot see too much difference between passing data at entry point. Using HOB in the initial pointer can be an alternative pattern to mitigate such risk. We just need measure them once then any component can use that. Also, it can help the people to evaluate the RTMR hash and TD event log data for the configuration in attestation flow, because the configuration is independent with the code execution flow. Well, it covers only the memory map, correct? All other configuration is still loaded from fw_cfg. I can't see the improvement here. [Jiewen] At this point of time, memory map is the most important parameter in the TD Hob, because we do need the memory information at the TD entrypoint. That is mandatory for any TD boot. The fw_cfg is still allowed in the TDVF design guide, just because we feel it is a burden to convert everything suddenly. I hope to limit the configuration from VMM. Most fw_cfg will NOT be used for TDVF, for example, "etc/smi", "etc/tpm", "etc/edk2/https/cacerts", "etc/msr_feature_control", "etc/system-states", especially in the container use case. The flexibility is a double-sward. You can treat the TD Hob as the boot parameter for the kernel, here is the kernel == TDVF. Having a static way to get configuration data in memory at one time is the simplest solution, from my perspective. How do you pass the HOB to the guest? Copy data to guest ram? Map a ro page into guest address space? What happens on VM reset? [Jiewen] Yes, VMM will prepare the memory information based upon TDVF metadata. The VMM need copy TD HOB data to a predefined memory region according to TDVF metadata. I don't fully understand the VM reset question. I try to answer. But if that is not what you are asking, please clarify. This action that VMM initiates TD HOB happens when the VMM launches a TD guest. After that the region will becomes TD private memory and own by TD. VMM can no longer access it (no read/no write). If VM reset, then this memory is gone. If VMM need launch a new TD, the VMM need initiate the data again. Please be aware that confidential computing (TDX) changes the threat model completely, any input from VMM is considered as malicious. Current solution might be OK for normal OVMF. But it does not mean the same solution is still the best one for confidential computing use case. Well, SEV seems to be happy with fw_cfg. Any input from AMD on the topic? take care, Gerd
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Re: [PATCH 18/23] OvmfPkg: Enable Tdx in SecMain.c Gerd Hoffmann #79793 Hi, fw_cfg is just a KVM/QEMU specific way to pass some parameter, but not all parameter. For example, OVMF today still get the memory size from CMOS. https://github.com/tianocore/edk2/blob/master/OvmfPkg/PlatformPei/MemDetect.c#L278 Patches to fix that are on the list. In TDVF design, we choose the use TDX defined initial pointer to pass the initial memory information - TD_HOB, instead of CMOS region. Please help me understand what is the real concern here. Well, qemu settled to the fw_cfg design or a number of reasons. It is pretty flexible for example. The firmware can ask for the information it needs at any time and can store it as it pleases. I'd suggest to not take it for granted that an additional alternative way to do basically the same thing will be accepted to upstream qemu. Submit your patches to qemu-devel to discuss that. That means, if you get the same data twice from the fw_cfg, the TDVF must measure them twice. And TDVF may need handle the case that the data in first call is different with the data in second call. Most fw_cfg entries are constant anyway, so we can easily avoid a second call by caching the results of the first call if that helps TDVF. Using HOB in the initial pointer can be an alternative pattern to mitigate such risk. We just need measure them once then any component can use that. Also, it can help the people to evaluate the RTMR hash and TD event log data for the configuration in attestation flow, because the configuration is independent with the code execution flow. Well, it covers only the memory map, correct? All other configuration is still loaded from fw_cfg. I can't see the improvement here. How do you pass the HOB to the guest? Copy data to guest ram? Map a ro page into guest address space? What happens on VM reset? Please be aware that confidential computing (TDX) changes the threat model completely, any input from VMM is considered as malicious. Current solution might be OK for normal OVMF. But it does not mean the same solution is still the best one for confidential computing use case. Well, SEV seems to be happy with fw_cfg. Any input from AMD on the topic? take care, Gerd
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Re: [PATCH v3 0/3] reuse the SevEsWork area Yao, Jiewen #79792 Thank you Brijesh. Reviewed-by: Jiewen Yao <Jiewen.yao@...> Since we are in code freeze, I will merge after we finalize the stable tag 202108. Thank you Yao Jiewen toggle quoted messageShow quoted text -----Original Message----- From: Brijesh Singh <brijesh.singh@...> Sent: Tuesday, August 17, 2021 9:47 PM To: devel@edk2.groups.io Cc: James Bottomley <jejb@...>; Xu, Min M <min.m.xu@...>; Yao, Jiewen <jiewen.yao@...>; Tom Lendacky <thomas.lendacky@...>; Justen, Jordan L <jordan.l.justen@...>; Ard Biesheuvel <ardb+tianocore@...>; Erdem Aktas <erdemaktas@...>; Michael Roth <Michael.Roth@...>; Brijesh Singh <brijesh.singh@...> Subject: [PATCH v3 0/3] reuse the SevEsWork area Based on the discussion on the mailing list, we agreed that instead of wasting extra page in the MEMFD, we can reuse the SevEsWorkArea buffer for the TDX. To avoid any confusion, lets introduce a OvmfWorkArea that will contains 32 bytes of header followed by the actual workarea. While at it, move the code to clear the GHCB page from PageTable build to AmdSev.asm. I have used the existing TDX BZ for it because the request came during the TDX patch review. if anyone have concern please let me know and I will happily create a new BZ. Full tree is at: https://github.com/AMDESE/ovmf/tree/sev-new-work-area Brijesh Singh (3): OvmfPkg: introduce a common work area OvmfPkg/ResetVector: update SEV support to use new work area format OvmfPkg/ResetVector: move the GHCB page setup in AmdSev.asm Cc: James Bottomley <jejb@...> Cc: Min Xu <min.m.xu@...> Cc: Jiewen Yao <jiewen.yao@...> Cc: Tom Lendacky <thomas.lendacky@...> Cc: Jordan Justen <jordan.l.justen@...> Cc: Ard Biesheuvel <ardb+tianocore@...> Cc: Erdem Aktas <erdemaktas@...> Changes since v2: - address Tom's feedback Changes since v1: - address Jiewen's feedback. Brijesh Singh (3): OvmfPkg: introduce a common work area OvmfPkg/ResetVector: update SEV support to use new work area format OvmfPkg/ResetVector: move the GHCB page setup in AmdSev.asm OvmfPkg/OvmfPkg.dec \| 12 +++ OvmfPkg/OvmfPkgX64.fdf \| 9 +- OvmfPkg/PlatformPei/PlatformPei.inf \| 4 +- OvmfPkg/ResetVector/ResetVector.inf \| 1 + OvmfPkg/Sec/SecMain.inf \| 2 + OvmfPkg/Include/Library/MemEncryptSevLib.h \| 21 +--- OvmfPkg/Include/WorkArea.h \| 67 +++++++++++++ OvmfPkg/PlatformPei/MemDetect.c \| 8 +- OvmfPkg/Sec/SecMain.c \| 36 ++++++- OvmfPkg/OvmfPkgDefines.fdf.inc \| 6 ++ OvmfPkg/ResetVector/Ia32/AmdSev.asm \| 109 +++++++++++++++++---- OvmfPkg/ResetVector/Ia32/PageTables64.asm \| 57 +++-------- OvmfPkg/ResetVector/ResetVector.nasmb \| 1 + 13 files changed, 238 insertions(+), 95 deletions(-) create mode 100644 OvmfPkg/Include/WorkArea.h -- 2.17.1
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Re: [PATCH 18/23] OvmfPkg: Enable Tdx in SecMain.c Gerd Hoffmann #79791 Hi, I can't see any support for Cloud-Hypervisor in OVMF. Right that currently OVMF is not supported by Cloud-Hypervisor in Td guest. But we're planning to support Cloud-Hypervisor to launch OVMF in Td guest and have done some POC. Also FreeBSD's bhyve doesn't support fw_cfg either and has its own ways to detect memory. Cloud-Hypervisor can surely do that too. So, why does this matter? Yes, Cloud-Hypervisor has some POC to launch OVMF in Non-Td guest. In that POC Cloud-Hypervisor leverage a 4k page in MEMFD and pass ACPI data to guest Firmware in that memory. https://github.com/cloud-hypervisor/edk2 "ch" branch https://github.com/cloud-hypervisor/edk2/commit/52cb72a748ef70833100ca664f6c2a704c28a93f Post the Cloud-Hypervisor patches to the list for review if you want them included in OVMF. out-of-tree patches lingering in some random branch @ github do not matter. https://github.com/cloud-hypervisor/cloud-hypervisor TD Hob list gives Cloud-Hypervisor a chance to pass information to guest firmware. For example, ACPI can be downloaded from QEMU via fw_cfg to firmware. But Cloud-Hypervisor cannot pass ACPI via fw_cfg. In this situation, TD Hob can resolve this problem. Sure, but again, why does this matter? For qemu? I don't quite understand the question here(For qumu?). Well, each VMM has different interfaces for guest <-> host communication. qemu/kvm uses fw_cfg. Xen and Bhyve have something different, and Cloud-Hypervisor seems to have something different again. What I mean in my last answer is that TD Hob can resolve the problem when the host VMM doesn't support fw_cfg communication mechanism. Sure. If Cloud-Hypervisor wants use that (for both TDX and non-TDX probably), fine. Submit the patches and we can discuss details. But why do you want switch qemu/kvm from fw_cfg to TD Hob? I don't like the idea to have TDX take a completely different code paths. That increases the code complexity and makes testing harder for no good reason. TD Hob is not a completely different code path. This is a useful supplement to the fw_cfg which is not supported by some host VMM. The code uses that unconditionally though and not only in case fw_cfg is not available. From another perspective TD Hob can be treated as a set of launch parameter by host VMM. It provides the flexibility for the host VMM to bring up the guest firmware with more parameters. I'm wondering what you are running on the host? I assumed we are discussing qemu/kvm as VMM, is that actually the case? Or do you use Cloud Hypervisor? qemu doesn't provide a TD Hob. So, when running qemu you probably have some out-of-tree patches adding that. Have you submitted them upstream? What is the status? I suspect you need to come up with some very good arguments to get that accepted. The need to bring parameters to the guest firmware is the reason why fw_cfg exists in the first place ... Another benefit is that TD Hob can be measured into some secure register (for example, in TD guest it is RTMR registers, like the TPM PCR) so that attestation can be done based on the measurement. fw_cfg is measured too (according to one of the tdx pdfs, don't remember which one). take care, Gerd
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Re: [PATCH 18/23] OvmfPkg: Enable Tdx in SecMain.c Yao, Jiewen #79790 HI Ard and Gerd I am not sure if I fully understand the argument here. In TDX architecture, the VMM provides a pointer to the TD guest as initial parameter. We define the detail information there to be TD Hob. This solution is generic to all hypervisor. fw_cfg is just a KVM/QEMU specific way to pass some parameter, but not all parameter. For example, OVMF today still get the memory size from CMOS. https://github.com/tianocore/edk2/blob/master/OvmfPkg/PlatformPei/MemDetect.c#L278 In TDVF design, we choose the use TDX defined initial pointer to pass the initial memory information - TD_HOB, instead of CMOS region. Please help me understand what is the real concern here. I understand the QEMU specific fw_cfg (https://github.com/qemu/qemu/blob/master/docs/specs/fw_cfg.txt). If you want to use fw_cfg to pass some QEMU specific parameter, it is still possible. For security reason, any input from the IO device must be measured by the TD guest. That means, if you get the same data twice from the fw_cfg, the TDVF must measure them twice. And TDVF may need handle the case that the data in first call is different with the data in second call. I can see potential attack surface there from architecture perspective. Using HOB in the initial pointer can be an alternative pattern to mitigate such risk. We just need measure them once then any component can use that. Also, it can help the people to evaluate the RTMR hash and TD event log data for the configuration in attestation flow, because the configuration is independent with the code execution flow. Please be aware that confidential computing (TDX) changes the threat model completely, any input from VMM is considered as malicious. Current solution might be OK for normal OVMF. But it does not mean the same solution is still the best one for confidential computing use case. Thank you Yao Jiewen toggle quoted messageShow quoted text -----Original Message----- From: Ard Biesheuvel <ardb@...> Sent: Tuesday, August 24, 2021 8:56 PM To: Xu, Min M <min.m.xu@...> Cc: Gerd Hoffmann <kraxel@...>; devel@edk2.groups.io; Ard Biesheuvel <ardb+tianocore@...>; Justen, Jordan L <jordan.l.justen@...>; Brijesh Singh <brijesh.singh@...>; Erdem Aktas <erdemaktas@...>; James Bottomley <jejb@...>; Yao, Jiewen <jiewen.yao@...>; Tom Lendacky <thomas.lendacky@...> Subject: Re: [edk2-devel] [PATCH 18/23] OvmfPkg: Enable Tdx in SecMain.c On Tue, 24 Aug 2021 at 14:07, Xu, Min M <min.m.xu@...> wrote: On August 20, 2021 3:23 PM, Gerd Hoffmann wrote: On Thu, Aug 19, 2021 at 02:27:16PM +0000, Min Xu wrote: On August 19, 2021 2:50 PM, Gerd Hoffmann wrote: +/** + In Tdx guest, some information need to be passed from host VMM +to guest + firmware. For example, the memory resource, etc. These + information are prepared by host VMM and put in HobList which + is described in TdxMetadata. What kind of information is passed to the guest here? Please see https://software.intel.com/content/dam/develop/external/us/en/document s/tdx-virtual-firmware-design-guide-rev-1.pdf Section 4.2 TD Hand-Off Block (HOB) So basically the physical memory map. qemu has etc/e820 for that. qemu has fw_cfg to pass information from the VMM to the guest firmware. What are the reasons to not use fw_cfg? Not all the VMM support fw_cfg. Cloud-Hypervisor is the example. I can't see any support for Cloud-Hypervisor in OVMF. Right that currently OVMF is not supported by Cloud-Hypervisor in Td guest. But we're planning to support Cloud-Hypervisor to launch OVMF in Td guest and have done some POC. If cloud hypervisor support is coming to OVMF, please contribute those patches first, so they can be discussed in public. Adding special facilities here to accommodate out of tree functionality that may look completely differently after review is not the right way to approach this. -- Ard. Also FreeBSD's bhyve doesn't support fw_cfg either and has its own ways to detect memory. Cloud-Hypervisor can surely do that too. So, why does this matter? Yes, Cloud-Hypervisor has some POC to launch OVMF in Non-Td guest. In that POC Cloud-Hypervisor leverage a 4k page in MEMFD and pass ACPI data to guest Firmware in that memory. https://github.com/cloud-hypervisor/edk2 "ch" branch https://github.com/cloud- hypervisor/edk2/commit/52cb72a748ef70833100ca664f6c2a704c28a93f https://github.com/cloud-hypervisor/cloud-hypervisor TD Hob list gives Cloud-Hypervisor a chance to pass information to guest firmware. For example, ACPI can be downloaded from QEMU via fw_cfg to firmware. But Cloud-Hypervisor cannot pass ACPI via fw_cfg. In this situation, TD Hob can resolve this problem. Sure, but again, why does this matter? For qemu? I don't quite understand the question here(For qumu?). What I mean in my last answer is that TD Hob can resolve the problem when the host VMM doesn't support fw_cfg communication mechanism. For the host VMMs which doesn't support fw_cfg, when ACPI data need to be passed to guest firmware, a 4k page (to hold ACPI data) is added in MEMFD. Then when SMBIOS is needed, shall we add another page in MEMFD? If the ACPI data is too big to be held in a 4k page, then the size of the reserved memory region in MEMFD is the restriction. I don't like the idea to have TDX take a completely different code paths. That increases the code complexity and makes testing harder for no good reason. TD Hob is not a completely different code path. This is a useful supplement to the fw_cfg which is not supported by some host VMM. From another perspective TD Hob can be treated as a set of launch parameter by host VMM. It provides the flexibility for the host VMM to bring up the guest firmware with more parameters. Another benefit is that TD Hob can be measured into some secure register (for example, in TD guest it is RTMR registers, like the TPM PCR) so that attestation can be done based on the measurement. Thanks Gerd for the comments. I am not sure if my explanation addressed your concern. Your comments is always welcomed. Thanks! Min
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Re: [PATCH 1/2] OvmfPkg/PlatformPei: ScanOrAdd64BitE820Ram improvements Philippe Mathieu-Daudé <philmd@...> #79789 On 8/19/21 10:11 AM, Gerd Hoffmann wrote: Add a bool parameter to ScanOrAdd64BitE820Ram to explicitly specify whenever ScanOrAdd64BitE820Ram should add HOBs for high memory (above 4G) or scan only. Also add a lowmem parameter so ScanOrAdd64BitE820Ram can report the memory size below 4G. This allows a more flexible usage of ScanOrAdd64BitE820Ram, a followup patch will use it for all memory detection. No functional change. Signed-off-by: Gerd Hoffmann <kraxel@...> --- OvmfPkg/PlatformPei/MemDetect.c \| 28 +++++++++++++++++++++------- 1 file changed, 21 insertions(+), 7 deletions(-) Reviewed-by: Philippe Mathieu-Daude <philmd@...>
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[PATCH] UefiCpuPkg/PiSmmCpuDxeSmm: Update mPatchCetSupported set condition Wenxing Hou #79788 REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3D3584 Function AsmCpuid should frist check the Value for Basic CPUID Information.The fix is to update the mPatchCetSupported judgment statement. =0D Signed-off-by: Wenxing Hou <wenxing.hou@...> Cc: Eric Dong <eric.dong@...> Cc: Ray Ni <ray.ni@...> Cc: Rahul Kumar <rahul1.kumar@...> Cc: Sheng W <w.sheng@...> Cc: Yao Jiewen <jiewen.yao@...> --- UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c \| 11 +++++++---- UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c \| 14 ++++++++------ 2 files changed, 15 insertions(+), 10 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmC= puDxeSmm/PiSmmCpuDxeSmm.c index db68e1316e..e394da7095 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c @@ -729,10 +729,10 @@ PiCpuSmmEntry ( =0D DEBUG ((DEBUG_INFO, "PcdControlFlowEnforcementPropertyMask =3D %d\n", Pc= dGet32 (PcdControlFlowEnforcementPropertyMask)));=0D if (PcdGet32 (PcdControlFlowEnforcementPropertyMask) !=3D 0) {=0D - AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);=0D - if (RegEax > CPUID_EXTENDED_FUNCTION) {=0D + AsmCpuid(CPUID_SIGNATURE, &RegEax, NULL, NULL, NULL);=0D + if (RegEax >=3D CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS) {=0D AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURE= D_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL, NULL, &RegEcx, &RegEdx);=0D - DEBUG ((DEBUG_INFO, "CPUID[7/0] ECX - 0x%08x\n", RegEcx));=0D + DEBUG ((DEBUG_INFO, " CPUID[7/0] ECX - 0x%08x\n", RegEcx));=0D DEBUG ((DEBUG_INFO, " CET_SS - 0x%08x\n", RegEcx & CPUID_CET_SS));= =0D DEBUG ((DEBUG_INFO, " CET_IBT - 0x%08x\n", RegEdx & CPUID_CET_IBT))= ;=0D if ((RegEcx & CPUID_CET_SS) =3D=3D 0) {=0D @@ -747,7 +747,10 @@ PiCpuSmmEntry ( AsmCpuidEx(CPUID_EXTENDED_STATE, 12, &RegEax, NULL, &RegEcx, NULL)= ;=0D DEBUG ((DEBUG_INFO, "CPUID[D/12] EAX - 0x%08x, ECX - 0x%08x\n", Re= gEax, RegEcx));=0D }=0D - }=0D + } else {=0D + mCetSupported =3D FALSE;=0D + PatchInstructionX86(mPatchCetSupported, mCetSupported, 1);=0D + }=0D } else {=0D mCetSupported =3D FALSE;=0D PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);=0D diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c b/UefiCpuPkg/PiSmmCpuDx= eSmm/SmmProfile.c index d7ed9ab7a7..f4d39c6967 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/SmmProfile.c @@ -985,13 +985,15 @@ CheckFeatureSupported ( MSR_IA32_MISC_ENABLE_REGISTER MiscEnableMsr;=0D =0D if ((PcdGet32 (PcdControlFlowEnforcementPropertyMask) !=3D 0) && mCetSup= ported) {=0D - AsmCpuid (CPUID_EXTENDED_FUNCTION, &RegEax, NULL, NULL, NULL);=0D - if (RegEax <=3D CPUID_EXTENDED_FUNCTION) {=0D - mCetSupported =3D FALSE;=0D - PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);=0D + AsmCpuid(CPUID_SIGNATURE, &RegEax, NULL, NULL, NULL);=0D + if (RegEax >=3D CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS) {=0D + AsmCpuidEx(CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_= EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL, NULL, &RegEcx, NULL);=0D + if ((RegEcx & CPUID_CET_SS) =3D=3D 0) {=0D + mCetSupported =3D FALSE;=0D + PatchInstructionX86(mPatchCetSupported, mCetSupported, 1);=0D + }=0D }=0D - AsmCpuidEx (CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS, CPUID_STRUCTURED_= EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO, NULL, NULL, &RegEcx, NULL);=0D - if ((RegEcx & CPUID_CET_SS) =3D=3D 0) {=0D + else {=0D mCetSupported =3D FALSE;=0D PatchInstructionX86 (mPatchCetSupported, mCetSupported, 1);=0D }=0D --=20 2.26.2.windows.1
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Re: about raise patch in EDK2 Andrew Fish #79787 You are not subscribed so all your posts have to be manually approved. toggle quoted messageShow quoted text On Aug 24, 2021, at 8:25 PM, Hou, Wenxing <wenxing.hou@...> wrote: Hi I raise a patch to EDK2. But, I get the message: “The following message to <devel@edk2.groups.io> was undeliverable. The reason for the problem: 5.3.0 - Other mail system problem 500-'This message has been flagged as spam.'” So I want to get the method for this problem. Thank you!
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about raise patch in EDK2 Hou, Wenxing <wenxing.hou@...> #79786 Hi I raise a patch to EDK2. But, I get the message: “The following message to <devel@edk2.groups.io> was undeliverable. The reason for the problem: 5.3.0 - Other mail system problem 500-'This message has been flagged as spam.'” So I want to get the method for this problem. Thank you!
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