Date   

[PATCH] Maintainers.txt: Update maintainer/reviewer roles in MdeModulePkg

Wu, Hao A
 

Remove Hao A Wu as the MdeModulePkg maintainer.
Add Liming Gao as the MdeModulePkg maintainer.
Remove Hao A Wu as the MdeModulePkg: Firmware Update modules reviewer.
Remove Hao A Wu as the MdeModulePkg: Serial modules reviewer.

Cc: Jian J Wang <jian.j.wang@...>
Cc: Liming Gao <gaoliming@...>
Cc: Guomin Jiang <guomin.jiang@...>
Cc: Ray Ni <ray.ni@...>
Cc: Zhichao Gao <zhichao.gao@...>
Signed-off-by: Hao A Wu <hao.a.wu@...>
---
Maintainers.txt | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/Maintainers.txt b/Maintainers.txt
index cd2f555750..5f53ea93ad 100644
--- a/Maintainers.txt
+++ b/Maintainers.txt
@@ -225,7 +225,7 @@ MdeModulePkg
F: MdeModulePkg/=0D
W: https://github.com/tianocore/tianocore.github.io/wiki/MdeModulePkg=0D
M: Jian J Wang <jian.j.wang@...> [jwang36]=0D
-M: Hao A Wu <hao.a.wu@...> [hwu25]=0D
+M: Liming Gao <gaoliming@...> [lgao4]=0D
=0D
MdeModulePkg: ACPI modules=0D
F: MdeModulePkg/Include/*Acpi*.h=0D
@@ -332,7 +332,6 @@ F: MdeModulePkg/Include/Protocol/FirmwareManagementProg=
ress.h
F: MdeModulePkg/Library/DisplayUpdateProgressLib*/=0D
F: MdeModulePkg/Library/FmpAuthenticationLibNull/=0D
F: MdeModulePkg/Universal/Esrt*/=0D
-R: Hao A Wu <hao.a.wu@...> [hwu25]=0D
R: Liming Gao <gaoliming@...> [lgao4]=0D
R: Guomin Jiang <guomin.jiang@...> [guominjia]=0D
=0D
@@ -378,7 +377,6 @@ R: Ray Ni <ray.ni@...> [niruiyu]
MdeModulePkg: Serial modules=0D
F: MdeModulePkg/*Serial*/=0D
F: MdeModulePkg/Include/*SerialPort*.h=0D
-R: Hao A Wu <hao.a.wu@...> [hwu25]=0D
R: Ray Ni <ray.ni@...> [niruiyu]=0D
R: Zhichao Gao <zhichao.gao@...> [ZhichaoGao]=0D
=0D
--=20
2.27.0.windows.1


EDK II Stable Tag release edk2-stable202108 completed

gaoliming
 

Hi, all

 

The tag edk2-stable202108 has been created. https://github.com/tianocore/edk2/releases/tag/edk2-stable202108

  git clone -b edk2-stable202108 https://github.com/tianocore/edk2.git

 

The tag edk2-stable202108 has been added into the main EDK II Wiki page.

  https://github.com/tianocore/tianocore.github.io/wiki/EDK-II

 

The quiet period has now ended. Thank you for your cooperation and patience. Normal commits can now be resumed.

 

Next edk2 stable tag (edk2-stable202111) planning has been added into wiki page.

https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Release-Planning.

 

If you have ideas for features in the next stable tag, please enter a Bugzilla for evaluation. Please let me know if there are existing open Bugzilla entries that should be targeted at this next stable tag.

 

Thanks

Liming


Re: [RFC PATCH v5 00/28] Add AMD Secure Nested Paging (SEV-SNP) support

Gerd Hoffmann
 

Hi,

[ /me reading through a bunch of old threads .... ]

Many of the integrity guarantees of SEV-SNP are enforced through a new
structure called the Reverse Map Table (RMP). Adding a new page to SEV-SNP
VM requires a 2-step process. First, the hypervisor assigns a page to the
guest using the new RMPUPDATE instruction. This transitions the page to
guest-invalid. Second, the guest validates the page using the new PVALIDATE
instruction.
Intel TDX names this "accepting pages", but it is basically the same
concept, correct?

If so I see opportunities to share code here. The problem of tracking
which pages are validated/accepted and which are not should be the same
for both TDX and SEV-SNP. The overall workflow (which phase
validates/accepts which pages etc.) should be identical too.

At this time we only support the pre-validation. OVMF detects all the available
system RAM in the PEI phase. When SEV-SNP is enabled, the memory is validated
before it is made available to the EDK2 core.
How do you detect memory? Intel wants pass a hob with a memory map (and
possibly more config info) to the early boot code, and I'm wondering why
TDX needs that while SEV-SNP apparently doesn't (at least I havn't
noticed anything similar while going over the patches quickly).

thanks,
Gerd


Re: [edk2-platforms: PATCH V10 2/2] Platform/Intel: Correct CPU APIC IDs

Ni, Ray
 

Reviewed-by: Ray Ni <ray.ni@...>

-----Original Message-----
From: Lin, JackX <jackx.lin@...>
Sent: Friday, August 27, 2021 2:04 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@...>; Dong, Eric <eric.dong@...>; Yao, Jiewen <jiewen.yao@...>; Ni, Ray <ray.ni@...>; Chaganty, Rangasai V <rangasai.v.chaganty@...>; Kuo, Donald <donald.kuo@...>; Kumar, Chandana C <chandana.c.kumar@...>
Subject: [edk2-platforms: PATCH V10 2/2] Platform/Intel: Correct CPU APIC IDs

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3365

Correct coding style

Signed-off-by: JackX Lin <JackX.Lin@...>
Cc: Chasel Chiu <chasel.chiu@...>
Cc: Dong Eric <eric.dong@...>
Cc: Jiewen Yao <jiewen.yao@...>
Cc: Ray Ni <ray.ni@...>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@...>
Cc: Donald Kuo <Donald.Kuo@...>
Cc: Chandana C Kumar <chandana.c.kumar@...>
Cc: JackX Lin <JackX.Lin@...>
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 238 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------------------------------------------------------------------------------------------------
1 file changed, 117 insertions(+), 121 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index ab3296d68a..c03d899163 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -49,7 +49,7 @@ VOID *mLocalTable[] = {
&Wsmt,
};

-EFI_ACPI_TABLE_PROTOCOL *mAcpiTable;
+EFI_ACPI_TABLE_PROTOCOL *mAcpiTable;

UINT32 mNumOfBitShift = 6;
BOOLEAN mForceX2ApicId;
@@ -215,7 +215,7 @@ SortCpuLocalApicInTable (
} //end for CurrentProcessor

//keep for debug purpose
- DEBUG(( EFI_D_ERROR, "::ACPI:: APIC ID Order Table Init. CoreThreadMask = %x, mNumOfBitShift = %x\n", CoreThreadMask, mNumOfBitShift));
+ DEBUG ((DEBUG_INFO, "::ACPI:: APIC ID Order Table Init. CoreThreadMask = %x, mNumOfBitShift = %x\n", CoreThreadMask, mNumOfBitShift));
DebugDisplayReOrderTable (TempCpuApicIdOrderTable);

//
@@ -238,7 +238,7 @@ SortCpuLocalApicInTable (
}

if (mNumberOfCpus <= Index) {
- DEBUG ((EFI_D_ERROR, "Asserting the SortCpuLocalApicInTable Index Bufferflow\n"));
+ DEBUG ((DEBUG_ERROR, "Asserting the SortCpuLocalApicInTable Index
+ Bufferflow\n"));
return EFI_INVALID_PARAMETER;
}
}
@@ -293,7 +293,7 @@ SortCpuLocalApicInTable (
}

//keep for debug purpose
- DEBUG ((EFI_D_ERROR, "APIC ID Order Table ReOrdered\n"));
+ DEBUG ((DEBUG_INFO, "APIC ID Order Table ReOrdered\n"));
DebugDisplayReOrderTable (mCpuApicIdOrderTable);

mCpuOrderSorted = TRUE;
@@ -493,11 +493,11 @@ InitializeMadtHeader (
}

Status = InitializeHeader (
- &MadtHeader->Header,
- EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
- 0
- );
+ &MadtHeader->Header,
+ EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+ 0
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -675,11 +675,11 @@ BuildAcpiTable (
// Allocate the memory needed for the table.
//
Status = AllocateTable (
- TableSpecificHdrLength,
- Structures,
- StructureCount,
- &InternalTable
- );
+ TableSpecificHdrLength,
+ Structures,
+ StructureCount,
+ &InternalTable
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -771,7 +771,7 @@ InstallMadtFromScratch (
// Call for Local APIC ID Reorder
Status = SortCpuLocalApicInTable ();
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "SortCpuLocalApicInTable failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "SortCpuLocalApicInTable failed: %r\n",
+ Status));
goto Done;
}

@@ -801,11 +801,11 @@ InstallMadtFromScratch (
//
Status = InitializeMadtHeader (&MadtTableHeader);
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "InitializeMadtHeader failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "InitializeMadtHeader failed: %r\n", Status));
goto Done;
}

- DEBUG ((EFI_D_INFO, "Number of CPUs detected = %d \n", mNumberOfCpus));
+ DEBUG ((DEBUG_INFO, "Number of CPUs detected = %d \n",
+ mNumberOfCpus));

//
// Build Processor Local APIC Structures and Processor Local X2APIC Structures @@ -831,10 +831,10 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &ProcLocalApicStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &ProcLocalApicStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
} else if (mCpuApicIdOrderTable[Index].ApicId != 0xFFFFFFFF) {
ProcLocalX2ApicStruct.Flags = (UINT8) mCpuApicIdOrderTable[Index].Flags;
ProcLocalX2ApicStruct.X2ApicId = mCpuApicIdOrderTable[Index].ApicId;
@@ -842,13 +842,13 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &ProcLocalX2ApicStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &ProcLocalX2ApicStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
}
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (local APIC/x2APIC) failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (local APIC/x2APIC)
+ failed: %r\n", Status));
goto Done;
}
}
@@ -860,44 +860,44 @@ InstallMadtFromScratch (
IoApicStruct.Length = sizeof (EFI_ACPI_4_0_IO_APIC_STRUCTURE);
IoApicStruct.Reserved = 0;

- PcIoApicEnable = PcdGet32(PcdPcIoApicEnable);
+ PcIoApicEnable = PcdGet32 (PcdPcIoApicEnable);

- if (FixedPcdGet32(PcdMaxCpuSocketCount) <= 4) {
+ if (FixedPcdGet32 (PcdMaxCpuSocketCount) <= 4) {
IoApicStruct.IoApicId = PcdGet8(PcdIoApicId);
IoApicStruct.IoApicAddress = PcdGet32(PcdIoApicAddress);
IoApicStruct.GlobalSystemInterruptBase = 0;
ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &IoApicStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &IoApicStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n",
+ Status));
goto Done;
}
}

for (PcIoApicIndex = 0; PcIoApicIndex < PcdGet8(PcdPcIoApicCount); PcIoApicIndex++) {
- PcIoApicMask = (1 << PcIoApicIndex);
- if ((PcIoApicEnable & PcIoApicMask) == 0) {
- continue;
- }
+ PcIoApicMask = (1 << PcIoApicIndex);
+ if ((PcIoApicEnable & PcIoApicMask) == 0) {
+ continue;
+ }

- IoApicStruct.IoApicId = (UINT8)(PcdGet8(PcdPcIoApicIdBase) + PcIoApicIndex);
- IoApicStruct.IoApicAddress = CurrentIoApicAddress;
- CurrentIoApicAddress = (CurrentIoApicAddress & 0xFFFF8000) + 0x8000;
- IoApicStruct.GlobalSystemInterruptBase = (UINT32)(24 + (PcIoApicIndex * 8));
- ASSERT (MadtStructsIndex < MaxMadtStructCount);
- Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &IoApicStruct,
- &MadtStructs[MadtStructsIndex++]
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", Status));
- goto Done;
- }
+ IoApicStruct.IoApicId = (UINT8)(PcdGet8(PcdPcIoApicIdBase) + PcIoApicIndex);
+ IoApicStruct.IoApicAddress = CurrentIoApicAddress;
+ CurrentIoApicAddress = (CurrentIoApicAddress & 0xFFFF8000) + 0x8000;
+ IoApicStruct.GlobalSystemInterruptBase = (UINT32)(24 + (PcIoApicIndex * 8));
+ ASSERT (MadtStructsIndex < MaxMadtStructCount);
+ Status = CopyStructure (
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &IoApicStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", Status));
+ goto Done;
+ }
}

//
@@ -916,12 +916,12 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &IntSrcOverrideStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &IntSrcOverrideStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (IRQ2 source override) failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (IRQ2 source override)
+ failed: %r\n", Status));
goto Done;
}

@@ -935,12 +935,12 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &IntSrcOverrideStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &IntSrcOverrideStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (IRQ9 source override) failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (IRQ9 source override)
+ failed: %r\n", Status));
goto Done;
}

@@ -955,12 +955,12 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &LocalApciNmiStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &LocalApciNmiStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (APIC NMI) failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (APIC NMI) failed: %r\n",
+ Status));
goto Done;
}

@@ -979,10 +979,10 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &LocalX2ApicNmiStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &LocalX2ApicNmiStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "CopyMadtStructure (x2APIC NMI) failed: %r\n", Status));
goto Done;
@@ -993,14 +993,14 @@ InstallMadtFromScratch (
// Build Madt Structure from the Madt Header and collection of pointers in MadtStructs[]
//
Status = BuildAcpiTable (
- (EFI_ACPI_DESCRIPTION_HEADER *) &MadtTableHeader,
- sizeof (EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER),
- MadtStructs,
- MadtStructsIndex,
- (UINT8 **)&NewMadtTable
- );
+ (EFI_ACPI_DESCRIPTION_HEADER *) &MadtTableHeader,
+ sizeof (EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER),
+ MadtStructs,
+ MadtStructsIndex,
+ (UINT8 **) &NewMadtTable
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "BuildAcpiTable failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "BuildAcpiTable failed: %r\n", Status));
goto Done;
}

@@ -1008,11 +1008,11 @@ InstallMadtFromScratch (
// Publish Madt Structure to ACPI
//
Status = mAcpiTable->InstallAcpiTable (
- mAcpiTable,
- NewMadtTable,
- NewMadtTable->Header.Length,
- &TableHandle
- );
+ mAcpiTable,
+ NewMadtTable,
+ NewMadtTable->Header.Length,
+ &TableHandle
+ );

Done:
//
@@ -1054,8 +1054,8 @@ InstallMcfgFromScratch (
PciSegmentInfo = GetPciSegmentInfo (&SegmentCount);

McfgTable = AllocateZeroPool (
- sizeof(EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER) +
- sizeof(EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE) * SegmentCount
+ sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER) +
+ sizeof
+ (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLO
+ CATION_STRUCTURE) * SegmentCount
);
if (McfgTable == NULL) {
DEBUG ((DEBUG_ERROR, "Could not allocate MCFG structure\n")); @@ -1063,11 +1063,11 @@ InstallMcfgFromScratch (
}

Status = InitializeHeader (
- &McfgTable->Header,
- EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
- 0
- );
+ &McfgTable->Header,
+ EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
+ 0
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -1091,11 +1091,11 @@ InstallMcfgFromScratch (
// Publish Madt Structure to ACPI
//
Status = mAcpiTable->InstallAcpiTable (
- mAcpiTable,
- McfgTable,
- McfgTable->Header.Length,
- &TableHandle
- );
+ mAcpiTable,
+ McfgTable,
+ McfgTable->Header.Length,
+ &TableHandle
+ );

return Status;
}
@@ -1179,7 +1179,7 @@ PlatformUpdateTables (
switch (Table->Signature) {

case EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE:
- ASSERT(FALSE);
+ ASSERT (FALSE);
break;

case EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:
@@ -1223,9 +1223,9 @@ PlatformUpdateTables (
FadtHeader->XGpe1Blk.AccessSize = 0;
}

- DEBUG(( EFI_D_ERROR, "ACPI FADT table @ address 0x%x\n", Table ));
- DEBUG(( EFI_D_ERROR, " IaPcBootArch 0x%x\n", FadtHeader->IaPcBootArch ));
- DEBUG(( EFI_D_ERROR, " Flags 0x%x\n", FadtHeader->Flags ));
+ DEBUG ((DEBUG_INFO, "ACPI FADT table @ address 0x%x\n", Table));
+ DEBUG ((DEBUG_INFO, " IaPcBootArch 0x%x\n", FadtHeader->IaPcBootArch));
+ DEBUG ((DEBUG_INFO, " Flags 0x%x\n", FadtHeader->Flags));
break;

case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:
@@ -1245,12 +1245,12 @@ PlatformUpdateTables (
HpetBlockId.Bits.VendorId = HpetCapabilities.Bits.VendorId;
HpetTable->EventTimerBlockId = HpetBlockId.Uint32;
HpetTable->MainCounterMinimumClockTickInPeriodicMode = (UINT16)HpetCapabilities.Bits.CounterClockPeriod;
- DEBUG(( EFI_D_ERROR, "ACPI HPET table @ address 0x%x\n", Table ));
- DEBUG(( EFI_D_ERROR, " HPET base 0x%x\n", PcdGet32 (PcdHpetBaseAddress) ));
+ DEBUG ((DEBUG_INFO, "ACPI HPET table @ address 0x%x\n", Table));
+ DEBUG ((DEBUG_INFO, " HPET base 0x%x\n", PcdGet32
+ (PcdHpetBaseAddress)));
break;

case EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE:
- ASSERT(FALSE);
+ ASSERT (FALSE);
break;

default:
@@ -1302,8 +1302,8 @@ IsHardwareChange (
// pFADT->XDsdt
//
HWChangeSize = HandleCount + 1;
- HWChange = AllocateZeroPool( sizeof(UINT32) * HWChangeSize );
- ASSERT( HWChange != NULL );
+ HWChange = AllocateZeroPool (sizeof(UINT32) * HWChangeSize);
+ ASSERT(HWChange != NULL);

if (HWChange == NULL) return;

@@ -1344,14 +1344,14 @@ IsHardwareChange (
// Calculate CRC value with HWChange data.
//
Status = gBS->CalculateCrc32(HWChange, HWChangeSize, &CRC);
- DEBUG((DEBUG_INFO, "CRC = %x and Status = %r\n", CRC, Status));
+ DEBUG ((DEBUG_INFO, "CRC = %x and Status = %r\n", CRC, Status));

//
// Set HardwareSignature value based on CRC value.
//
FacsPtr = (EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)(UINTN)pFADT->FirmwareCtrl;
FacsPtr->HardwareSignature = CRC;
- FreePool( HWChange );
+ FreePool (HWChange);
}

VOID
@@ -1374,17 +1374,16 @@ UpdateLocalTable (

if (Version != EFI_ACPI_TABLE_VERSION_NONE) {
Status = mAcpiTable->InstallAcpiTable (
- mAcpiTable,
- CurrentTable,
- CurrentTable->Length,
- &TableHandle
- );
+ mAcpiTable,
+ CurrentTable,
+ CurrentTable->Length,
+ &TableHandle
+ );
ASSERT_EFI_ERROR (Status);
}
}
}

-
VOID
EFIAPI
AcpiEndOfDxeEvent (
@@ -1392,16 +1391,14 @@ AcpiEndOfDxeEvent (
VOID *ParentImageHandle
)
{
-
if (Event != NULL) {
- gBS->CloseEvent(Event);
+ gBS->CloseEvent (Event);
}

-
//
// Calculate Hardware Signature value based on current platform configurations
//
- IsHardwareChange();
+ IsHardwareChange ();
}

/**
@@ -1425,7 +1422,6 @@ InstallAcpiPlatform (
EFI_STATUS Status;
EFI_EVENT EndOfDxeEvent;

-
Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&mMpService);
ASSERT_EFI_ERROR (Status);

@@ -1449,10 +1445,10 @@ InstallAcpiPlatform (
// Determine the number of processors
//
mMpService->GetNumberOfProcessors (
- mMpService,
- &mNumberOfCpus,
- &mNumberOfEnabledCPUs
- );
+ mMpService,
+ &mNumberOfCpus,
+ &mNumberOfEnabledCPUs
+ );

DEBUG ((DEBUG_INFO, "mNumberOfCpus - %d\n", mNumberOfCpus));
DEBUG ((DEBUG_INFO, "mNumberOfEnabledCPUs - %d\n", mNumberOfEnabledCPUs)); @@ -1461,7 +1457,7 @@ InstallAcpiPlatform (
DEBUG ((DEBUG_INFO, "mForceX2ApicId - 0x%x\n", mForceX2ApicId));

// support up to 64 threads/socket
- AsmCpuidEx(CPUID_EXTENDED_TOPOLOGY, 1, &mNumOfBitShift, NULL, NULL, NULL);
+ AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 1, &mNumOfBitShift, NULL, NULL,
+ NULL);
mNumOfBitShift &= 0x1F;
DEBUG ((DEBUG_INFO, "mNumOfBitShift - 0x%x\n", mNumOfBitShift));

--
2.32.0.windows.2


Re: [edk2-platforms: PATCH V10 1/2] Platform/Intel: Correct CPU APIC IDs

Ni, Ray
 

Reviewed-by: Ray Ni <ray.ni@...>

-----Original Message-----
From: Lin, JackX <jackx.lin@...>
Sent: Friday, August 27, 2021 2:04 PM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@...>; Dong, Eric <eric.dong@...>; Yao, Jiewen <jiewen.yao@...>; Ni, Ray <ray.ni@...>; Chaganty, Rangasai V <rangasai.v.chaganty@...>; Kuo, Donald <donald.kuo@...>; Kumar, Chandana C <chandana.c.kumar@...>
Subject: [edk2-platforms: PATCH V10 1/2] Platform/Intel: Correct CPU APIC IDs

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3365

BIOS cannot find correct AcpiProcId in mApicIdMap because of there is no suitable map, that causes ACPI_BIOS_ERROR.
Remove mApicIdMap for determing AcpiProcId, uses normal countings instead.

Signed-off-by: JackX Lin <JackX.Lin@...>
Cc: Chasel Chiu <chasel.chiu@...>
Cc: Dong Eric <eric.dong@...>
Cc: Jiewen Yao <jiewen.yao@...>
Cc: Ray Ni <ray.ni@...>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@...>
Cc: Donald Kuo <Donald.Kuo@...>
Cc: Chandana C Kumar <chandana.c.kumar@...>
Cc: JackX Lin <JackX.Lin@...>
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 417 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h | 4 +++-
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 4 +++-
3 files changed, 164 insertions(+), 261 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index 2b51c34ef2..ab3296d68a 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -1,14 +1,13 @@
/** @file
ACPI Platform Driver

-Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent

**/

#include "AcpiPlatform.h"
-
-#define MAX_CPU_NUM (FixedPcdGet32(PcdMaxCpuThreadCount) * FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuSocketCount))
+#define MAX_SOCKET (FixedPcdGet32 (PcdMaxCpuSocketCount))

#pragma pack(1)

@@ -16,8 +15,8 @@ typedef struct {
UINT32 AcpiProcessorId;
UINT32 ApicId;
UINT32 Flags;
- UINT32 SwProcApicId;
UINT32 SocketNum;
+ UINT32 Thread;
} EFI_CPU_ID_ORDER_MAP;

//
@@ -58,170 +57,58 @@ BOOLEAN mX2ApicEnabled;

EFI_MP_SERVICES_PROTOCOL *mMpService;
BOOLEAN mCpuOrderSorted;
-EFI_CPU_ID_ORDER_MAP mCpuApicIdOrderTable[MAX_CPU_NUM];
-UINTN mNumberOfCPUs = 0;
+EFI_CPU_ID_ORDER_MAP *mCpuApicIdOrderTable = NULL;
+UINTN mNumberOfCpus = 0;
UINTN mNumberOfEnabledCPUs = 0;

-// following are possible APICID Map for SKX -static const UINT32 ApicIdMapA[] = { //for SKUs have number of core > 16
- //it is 14 + 14 + 14 + 14 format
- 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000006, 0x00000007,
- 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, 0x00000010, 0x00000011,
- 0x00000012, 0x00000013, 0x00000014, 0x00000015, 0x00000016, 0x00000017, 0x00000018, 0x00000019,
- 0x0000001A, 0x0000001B, 0x0000001C, 0x0000001D, 0x00000020, 0x00000021, 0x00000022, 0x00000023,
- 0x00000024, 0x00000025, 0x00000026, 0x00000027, 0x00000028, 0x00000029, 0x0000002A, 0x0000002B,
- 0x0000002C, 0x0000002D, 0x00000030, 0x00000031, 0x00000032, 0x00000033, 0x00000034, 0x00000035,
- 0x00000036, 0x00000037, 0x00000038, 0x00000039, 0x0000003A, 0x0000003B, 0x0000003C, 0x0000003D -};
-
-static const UINT32 ApicIdMapB[] = { //for SKUs have number of cores <= 16 use 32 ID space
- //it is 16+16 format
- 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000006, 0x00000007,
- 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, 0x0000000E, 0x0000000F,
- 0x00000010, 0x00000011, 0x00000012, 0x00000013, 0x00000014, 0x00000015, 0x00000016, 0x00000017,
- 0x00000018, 0x00000019, 0x0000001A, 0x0000001B, 0x0000001C, 0x0000001D, 0x0000001E, 0x0000001F,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF -};
-
-
-static const UINT32 ApicIdMapC[] = { //for SKUs have number of cores <= 16 use 64 ID space
- //it is 16+0+16+0 format
- 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000006, 0x00000007,
- 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, 0x0000000E, 0x0000000F,
- 0x00000020, 0x00000021, 0x00000022, 0x00000023, 0x00000024, 0x00000025, 0x00000026, 0x00000027,
- 0x00000028, 0x00000029, 0x0000002A, 0x0000002B, 0x0000002C, 0x0000002D, 0x0000002E, 0x0000002F,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF -};
-
-static const UINT32 ApicIdMapD[] = { //for SKUs have number of cores <= 8 use 16 ID space
- //it is 16 format
- 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000006, 0x00000007,
- 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, 0x0000000E, 0x0000000F,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF -};
-
-const UINT32 *mApicIdMap = NULL;

/**
- This function detect the APICID map and update ApicID Map pointer
+ The function is called by PerformQuickSort to compare int values.

- @param None
+ @param[in] Left The pointer to first buffer.
+ @param[in] Right The pointer to second buffer.

- @retval VOID
+ @return -1 Buffer1 is less than Buffer2.
+ @return 1 Buffer1 is greater than Buffer2.

**/
-VOID DetectApicIdMap(VOID)
+INTN
+EFIAPI
+ApicIdCompareFunction (
+ IN CONST VOID *Left,
+ IN CONST VOID *Right
+ )
{
- UINTN CoreCount;
+ UINT32 LeftApicId;
+ UINT32 RightApicId;

- CoreCount = 0;
-
- if(mApicIdMap != NULL) {
- return; //aleady initialized
- }
-
- mApicIdMap = ApicIdMapA; // default to > 16C SKUs
-
- CoreCount = mNumberOfEnabledCPUs / 2;
- DEBUG ((DEBUG_INFO, "CoreCount - %d\n", CoreCount));
-
- //DEBUG((EFI_D_ERROR, ":: Default to use Map A @ %08X FusedCoreCount: %02d, sktlevel: %d\n",mApicIdMap, FusedCoreCount, mNumOfBitShift));
- // Dont assert for single core, single thread system.
- //ASSERT (CoreCount != 0);
-
- if(CoreCount <= 16) {
-
- if(mNumOfBitShift == 4) {
- mApicIdMap = ApicIdMapD;
- //DEBUG((EFI_D_ERROR, ":: Use Map B @ %08X\n",mApicIdMap));
- }
-
- if(mNumOfBitShift == 5) {
- mApicIdMap = ApicIdMapB;
- //DEBUG((EFI_D_ERROR, ":: Use Map B @ %08X\n",mApicIdMap));
- }
-
- if(mNumOfBitShift == 6) {
- mApicIdMap = ApicIdMapC;
- //DEBUG((EFI_D_ERROR, ":: Use Map C @ %08X\n",mApicIdMap));
- }
+ LeftApicId = ((EFI_CPU_ID_ORDER_MAP *) Left)->ApicId; RightApicId =
+ ((EFI_CPU_ID_ORDER_MAP *) Right)->ApicId;

- }
-
- return;
+ return (LeftApicId > RightApicId)? 1 : (-1);
}

/**
- This function return the CoreThreadId of ApicId from ACPI ApicId Map array
-
- @param ApicId
-
- @retval Index of ACPI ApicId Map array
+ Print Cpu Apic ID Table

+ @param[in] CpuApicIdOrderTable Data will be dumped.
**/
-UINT32
-GetIndexFromApicId (
- UINT32 ApicId
- )
-{
- UINT32 CoreThreadId;
- UINT32 i;
-
- ASSERT (mApicIdMap != NULL);
-
- CoreThreadId = ApicId & ((1 << mNumOfBitShift) - 1);
-
- for(i = 0; i < (FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuThreadCount)); i++) {
- if(mApicIdMap[i] == CoreThreadId) {
- break;
- }
- }
-
- ASSERT (i <= (FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuThreadCount)));
-
- return i;
-}
-
-UINT32
-ApicId2SwProcApicId (
- UINT32 ApicId
- )
-{
- UINT32 Index;
-
- for (Index = 0; Index < MAX_CPU_NUM; Index++) {
- if ((mCpuApicIdOrderTable[Index].Flags == 1) && (mCpuApicIdOrderTable[Index].ApicId == ApicId)) {
- return Index;
- }
- }
-
- return (UINT32) -1;
-
-}
-
VOID
-DebugDisplayReOrderTable(
- VOID
+DebugDisplayReOrderTable (
+ IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
)
{
UINT32 Index;

- DEBUG ((EFI_D_ERROR, "Index AcpiProcId ApicId Flags SwApicId Skt\n"));
- for (Index=0; Index<MAX_CPU_NUM; Index++) {
- DEBUG ((EFI_D_ERROR, " %02d 0x%02X 0x%02X %d 0x%02X %d\n",
- Index, mCpuApicIdOrderTable[Index].AcpiProcessorId,
- mCpuApicIdOrderTable[Index].ApicId,
- mCpuApicIdOrderTable[Index].Flags,
- mCpuApicIdOrderTable[Index].SwProcApicId,
- mCpuApicIdOrderTable[Index].SocketNum));
+ DEBUG ((DEBUG_INFO, "Index AcpiProcId ApicId Thread Flags Skt\n"));
+ for (Index = 0; Index < mNumberOfCpus; Index++) {
+ DEBUG ((DEBUG_INFO, " %02d 0x%02X 0x%02X %d %d %d\n",
+ Index,
+ CpuApicIdOrderTable[Index].AcpiProcessorId,
+ CpuApicIdOrderTable[Index].ApicId,
+ CpuApicIdOrderTable[Index].Thread,
+ CpuApicIdOrderTable[Index].Flags,
+ CpuApicIdOrderTable[Index].SocketNum));
}
}

@@ -281,131 +168,135 @@ SortCpuLocalApicInTable (
UINT32 Index;
UINT32 CurrProcessor;
UINT32 BspApicId;
- UINT32 TempVal = 0;
+ EFI_CPU_ID_ORDER_MAP *TempVal;
EFI_CPU_ID_ORDER_MAP *CpuIdMapPtr;
UINT32 CoreThreadMask;
+ EFI_CPU_ID_ORDER_MAP *TempCpuApicIdOrderTable;
+ UINT32 Socket;

Index = 0;
Status = EFI_SUCCESS;

- CoreThreadMask = (UINT32) ((1 << mNumOfBitShift) - 1);
-
- if(!mCpuOrderSorted) {
-
- Index = 0;
+ if (mCpuOrderSorted) {
+ return Status;
+ }

- for (CurrProcessor = 0; CurrProcessor < mNumberOfCPUs; CurrProcessor++) {
- Status = mMpService->GetProcessorInfo (
- mMpService,
- CurrProcessor,
- &ProcessorInfoBuffer
- );
+ TempCpuApicIdOrderTable = AllocateZeroPool (mNumberOfCpus * sizeof
+ (EFI_CPU_ID_ORDER_MAP)); TempVal = AllocateZeroPool (sizeof
+ (EFI_CPU_ID_ORDER_MAP)); CoreThreadMask = (UINT32) ((1 <<
+ mNumOfBitShift) - 1);

- if ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0) {
- if(ProcessorInfoBuffer.ProcessorId & 1) { //is 2nd thread
- CpuIdMapPtr = (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[(Index - 1) + MAX_CPU_NUM / 2];
- } else { //is primary thread
- CpuIdMapPtr = (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[Index];
- Index++;
+ for (CurrProcessor = 0, Index = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++, Index++) {
+ Status = mMpService->GetProcessorInfo (
+ mMpService,
+ CurrProcessor,
+ &ProcessorInfoBuffer
+ );
+
+ CpuIdMapPtr = (EFI_CPU_ID_ORDER_MAP *) &TempCpuApicIdOrderTable[Index];
+ if ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0) {
+ CpuIdMapPtr->ApicId = (UINT32)ProcessorInfoBuffer.ProcessorId;
+ CpuIdMapPtr->Thread = ProcessorInfoBuffer.Location.Thread;
+ CpuIdMapPtr->Flags = ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0);
+ CpuIdMapPtr->SocketNum = ProcessorInfoBuffer.Location.Package;
+
+ //update processorbitMask
+ if (CpuIdMapPtr->Flags == 1) {
+ if (mForceX2ApicId) {
+ CpuIdMapPtr->SocketNum &= 0x7;
+ CpuIdMapPtr->AcpiProcessorId &= 0xFF; //keep lower 8bit due
+ to use Proc obj in dsdt
}
- CpuIdMapPtr->ApicId = (UINT32)ProcessorInfoBuffer.ProcessorId;
- CpuIdMapPtr->Flags = ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0);
- CpuIdMapPtr->SocketNum = (UINT32)ProcessorInfoBuffer.Location.Package;
- CpuIdMapPtr->AcpiProcessorId = (CpuIdMapPtr->SocketNum * FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuThreadCount)) + GetIndexFromApicId(CpuIdMapPtr->ApicId); //CpuIdMapPtr->ApicId;
- CpuIdMapPtr->SwProcApicId = ((UINT32)(ProcessorInfoBuffer.Location.Package << mNumOfBitShift) + (((UINT32)ProcessorInfoBuffer.ProcessorId) & CoreThreadMask));
- if(mX2ApicEnabled) { //if X2Apic, re-order the socket # so it starts from base 0 and contiguous
- //may not necessory!!!!!
- }
-
- //update processorbitMask
- if (CpuIdMapPtr->Flags == 1) {
+ }
+ } else { //not enabled
+ CpuIdMapPtr->ApicId = (UINT32)-1;
+ CpuIdMapPtr->Thread = (UINT32)-1;
+ CpuIdMapPtr->Flags = 0;
+ CpuIdMapPtr->SocketNum = (UINT32)-1;
+ } //end if PROC ENABLE
+ } //end for CurrentProcessor
+
+ //keep for debug purpose
+ DEBUG(( EFI_D_ERROR, "::ACPI:: APIC ID Order Table Init. CoreThreadMask = %x, mNumOfBitShift = %x\n", CoreThreadMask, mNumOfBitShift));
+ DebugDisplayReOrderTable (TempCpuApicIdOrderTable);
+
+ //
+ // Get Bsp Apic Id
+ //
+ BspApicId = GetApicId ();
+ DEBUG ((DEBUG_INFO, "BspApicId - 0x%x\n", BspApicId));
+
+ //
+ //check to see if 1st entry is BSP, if not swap it // if
+ (TempCpuApicIdOrderTable[0].ApicId != BspApicId) {
+ for (Index = 0; Index < mNumberOfCpus; Index++) {
+ if ((TempCpuApicIdOrderTable[Index].Flags == 1) && (TempCpuApicIdOrderTable[Index].ApicId == BspApicId)) {
+ CopyMem (&TempVal, &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP));
+ CopyMem (&TempCpuApicIdOrderTable[Index], &TempCpuApicIdOrderTable[0], sizeof (EFI_CPU_ID_ORDER_MAP));
+ CopyMem (&TempCpuApicIdOrderTable[0], &TempVal, sizeof (EFI_CPU_ID_ORDER_MAP));
+ break;
+ }
+ }

- if(mForceX2ApicId) {
- CpuIdMapPtr->SocketNum &= 0x7;
- CpuIdMapPtr->AcpiProcessorId &= 0xFF; //keep lower 8bit due to use Proc obj in dsdt
- CpuIdMapPtr->SwProcApicId &= 0xFF;
- }
- }
- } else { //not enabled
- CpuIdMapPtr = (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[Index];
- CpuIdMapPtr->ApicId = (UINT32)-1;
- CpuIdMapPtr->Flags = 0;
- CpuIdMapPtr->AcpiProcessorId = (UINT32)-1;
- CpuIdMapPtr->SwProcApicId = (UINT32)-1;
- CpuIdMapPtr->SocketNum = (UINT32)-1;
- } //end if PROC ENABLE
- } //end for CurrentProcessor
-
- //keep for debug purpose
- DEBUG(( EFI_D_ERROR, "::ACPI:: APIC ID Order Table Init. CoreThreadMask = %x, mNumOfBitShift = %x\n", CoreThreadMask, mNumOfBitShift));
- DebugDisplayReOrderTable();
-
- //make sure 1st entry is BSP
- if(mX2ApicEnabled) {
- BspApicId = (UINT32)AsmReadMsr64(0x802);
- } else {
- BspApicId = (*(volatile UINT32 *)(UINTN)0xFEE00020) >> 24;
+ if (mNumberOfCpus <= Index) {
+ DEBUG ((EFI_D_ERROR, "Asserting the SortCpuLocalApicInTable Index Bufferflow\n"));
+ return EFI_INVALID_PARAMETER;
}
- DEBUG ((EFI_D_INFO, "BspApicId - 0x%x\n", BspApicId));
+ }

- if(mCpuApicIdOrderTable[0].ApicId != BspApicId) {
- //check to see if 1st entry is BSP, if not swap it
- Index = ApicId2SwProcApicId(BspApicId);
+ //
+ // 1. Sort TempCpuApicIdOrderTable,
+ // sort it by using ApicId from minimum to maximum (Socket0 to SocketN), and the BSP must in the fist location of the table.
+ // So, start sorting the table from the second element and total elements are mNumberOfCpus-1.
+ //
+ PerformQuickSort ((TempCpuApicIdOrderTable + 1), (mNumberOfCpus - 1),
+ sizeof (EFI_CPU_ID_ORDER_MAP), (SORT_COMPARE) ApicIdCompareFunction);

- if(MAX_CPU_NUM <= Index) {
- DEBUG ((EFI_D_ERROR, "Asserting the SortCpuLocalApicInTable Index Bufferflow\n"));
- return EFI_INVALID_PARAMETER;
- }
+ //
+ // 2. Sort and map the primary threads to the front of the
+ CpuApicIdOrderTable // for (CurrProcessor = 0, Index = 0; Index <
+ mNumberOfCpus; Index++) {
+ if ((TempCpuApicIdOrderTable[Index].Thread) == 0) { // primary thread
+ CopyMem (&mCpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP));
+ CurrProcessor++;
+ }
+ }

- TempVal = mCpuApicIdOrderTable[Index].ApicId;
- mCpuApicIdOrderTable[Index].ApicId = mCpuApicIdOrderTable[0].ApicId;
- mCpuApicIdOrderTable[0].ApicId = TempVal;
- mCpuApicIdOrderTable[Index].Flags = mCpuApicIdOrderTable[0].Flags;
- mCpuApicIdOrderTable[0].Flags = 1;
- TempVal = mCpuApicIdOrderTable[Index].SwProcApicId;
- mCpuApicIdOrderTable[Index].SwProcApicId = mCpuApicIdOrderTable[0].SwProcApicId;
- mCpuApicIdOrderTable[0].SwProcApicId = TempVal;
- //swap AcpiProcId
- TempVal = mCpuApicIdOrderTable[Index].AcpiProcessorId;
- mCpuApicIdOrderTable[Index].AcpiProcessorId = mCpuApicIdOrderTable[0].AcpiProcessorId;
- mCpuApicIdOrderTable[0].AcpiProcessorId = TempVal;
+ //
+ // 3. Sort and map the second threads to the middle of the
+ CpuApicIdOrderTable // for (Index = 0; Index < mNumberOfCpus;
+ Index++) {
+ if ((TempCpuApicIdOrderTable[Index].Thread) == 1) { //second thread
+ CopyMem (&mCpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP));
+ CurrProcessor++;
+ }
+ }

+ //
+ // 4. Sort and map the not enabled threads to the bottom of the
+ CpuApicIdOrderTable // for (Index = 0; Index < mNumberOfCpus;
+ Index++) {
+ if (TempCpuApicIdOrderTable[Index].Flags == 0) { // not enabled
+ CopyMem (&mCpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP));
+ CurrProcessor++;
}
+ }

- //Make sure no holes between enabled threads
- for(CurrProcessor = 0; CurrProcessor < MAX_CPU_NUM; CurrProcessor++) {
-
- if(mCpuApicIdOrderTable[CurrProcessor].Flags == 0) {
- //make sure disabled entry has ProcId set to FFs
- mCpuApicIdOrderTable[CurrProcessor].ApicId = (UINT32)-1;
- mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId = (UINT32)-1;
- mCpuApicIdOrderTable[CurrProcessor].SwProcApicId = (UINT32)-1;
-
- for(Index = CurrProcessor+1; Index < MAX_CPU_NUM; Index++) {
- if(mCpuApicIdOrderTable[Index].Flags == 1) {
- //move enabled entry up
- mCpuApicIdOrderTable[CurrProcessor].Flags = 1;
- mCpuApicIdOrderTable[CurrProcessor].ApicId = mCpuApicIdOrderTable[Index].ApicId;
- mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId = mCpuApicIdOrderTable[Index].AcpiProcessorId;
- mCpuApicIdOrderTable[CurrProcessor].SwProcApicId = mCpuApicIdOrderTable[Index].SwProcApicId;
- mCpuApicIdOrderTable[CurrProcessor].SocketNum = mCpuApicIdOrderTable[Index].SocketNum;
- //disable moved entry
- mCpuApicIdOrderTable[Index].Flags = 0;
- mCpuApicIdOrderTable[Index].ApicId = (UINT32)-1;
- mCpuApicIdOrderTable[Index].AcpiProcessorId = (UINT32)-1;
- mCpuApicIdOrderTable[Index].SwProcApicId = (UINT32)-1;
- break;
- }
- }
+ //
+ // 5. Re-assigen AcpiProcessorId for AcpiProcessorUId uses purpose.
+ //
+ for (Socket = 0; Socket < MAX_SOCKET; Socket++) {
+ for (CurrProcessor = 0, Index = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) {
+ if (mCpuApicIdOrderTable[CurrProcessor].Flags && (mCpuApicIdOrderTable[CurrProcessor].SocketNum == Socket)) {
+ mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId = (ProcessorInfoBuffer.Location.Package << mNumOfBitShift) + Index;
+ Index++;
}
}
+ }

- //keep for debug purpose
- DEBUG ((EFI_D_ERROR, "APIC ID Order Table ReOrdered\n"));
- DebugDisplayReOrderTable();
+ //keep for debug purpose
+ DEBUG ((EFI_D_ERROR, "APIC ID Order Table ReOrdered\n"));
+ DebugDisplayReOrderTable (mCpuApicIdOrderTable);

- mCpuOrderSorted = TRUE;
- }
+ mCpuOrderSorted = TRUE;

return Status;
}
@@ -871,7 +762,11 @@ InstallMadtFromScratch (
NewMadtTable = NULL;
MaxMadtStructCount = 0;

- DetectApicIdMap();
+ mCpuApicIdOrderTable = AllocateZeroPool (mNumberOfCpus * sizeof
+ (EFI_CPU_ID_ORDER_MAP)); if (mCpuApicIdOrderTable == NULL) {
+ DEBUG ((DEBUG_ERROR, "Could not allocate mCpuApicIdOrderTable structure pointer array\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }

// Call for Local APIC ID Reorder
Status = SortCpuLocalApicInTable ();
@@ -881,8 +776,8 @@ InstallMadtFromScratch (
}

MaxMadtStructCount = (UINT32) (
- MAX_CPU_NUM + // processor local APIC structures
- MAX_CPU_NUM + // processor local x2APIC structures
+ mNumberOfCpus + // processor local APIC structures
+ mNumberOfCpus + // processor local x2APIC structures
1 + PcdGet8(PcdPcIoApicCount) + // I/O APIC structures
2 + // interrupt source override structures
1 + // local APIC NMI structures
@@ -910,7 +805,7 @@ InstallMadtFromScratch (
goto Done;
}

- DEBUG ((EFI_D_INFO, "Number of CPUs detected = %d \n", mNumberOfCPUs));
+ DEBUG ((EFI_D_INFO, "Number of CPUs detected = %d \n",
+ mNumberOfCpus));

//
// Build Processor Local APIC Structures and Processor Local X2APIC Structures @@ -923,7 +818,7 @@ InstallMadtFromScratch (
ProcLocalX2ApicStruct.Reserved[0] = 0;
ProcLocalX2ApicStruct.Reserved[1] = 0;

- for (Index = 0; Index < MAX_CPU_NUM; Index++) {
+ for (Index = 0; Index < mNumberOfCpus; Index++) {
//
// If x2APIC mode is not enabled, and if it is possible to express the
// APIC ID as a UINT8, use a processor local APIC structure. Otherwise, @@ -1136,6 +1031,10 @@ Done:
FreePool (NewMadtTable);
}

+ if (mCpuApicIdOrderTable != NULL) {
+ FreePool (mCpuApicIdOrderTable);
+ }
+
return Status;
}

@@ -1551,11 +1450,11 @@ InstallAcpiPlatform (
//
mMpService->GetNumberOfProcessors (
mMpService,
- &mNumberOfCPUs,
+ &mNumberOfCpus,
&mNumberOfEnabledCPUs
);
- ASSERT (mNumberOfCPUs <= MAX_CPU_NUM && mNumberOfEnabledCPUs >= 1);
- DEBUG ((DEBUG_INFO, "mNumberOfCPUs - %d\n", mNumberOfCPUs));
+
+ DEBUG ((DEBUG_INFO, "mNumberOfCpus - %d\n", mNumberOfCpus));
DEBUG ((DEBUG_INFO, "mNumberOfEnabledCPUs - %d\n", mNumberOfEnabledCPUs));

DEBUG ((DEBUG_INFO, "mX2ApicEnabled - 0x%x\n", mX2ApicEnabled)); diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
index bd11f9e988..61f7470f80 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
@@ -1,7 +1,7 @@
/** @file
This is an implementation of the ACPI platform driver.

-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent

**/
@@ -35,6 +35,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #include <Library/MemoryAllocationLib.h> #include <Library/AslUpdateLib.h> #include <Library/PciSegmentInfoLib.h>
+#include <Library/SortLib.h>
+#include <Library/LocalApicLib.h>

#include <Protocol/AcpiTable.h>
#include <Protocol/MpService.h>
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
index 5d9c8cab50..95f6656af0 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
@@ -1,7 +1,7 @@
### @file
# Component information file for AcpiPlatform module # -# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2021, Intel Corporation. All rights
+reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -43,6 +43,8 @@
PciSegmentInfoLib
AslUpdateLib
BoardAcpiTableLib
+ SortLib
+ LocalApicLib

[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
--
2.32.0.windows.2


[edk2-platforms: PATCH V10 2/2] Platform/Intel: Correct CPU APIC IDs

JackX Lin
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3365

Correct coding style

Signed-off-by: JackX Lin <JackX.Lin@...>
Cc: Chasel Chiu <chasel.chiu@...>
Cc: Dong Eric <eric.dong@...>
Cc: Jiewen Yao <jiewen.yao@...>
Cc: Ray Ni <ray.ni@...>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@...>
Cc: Donald Kuo <Donald.Kuo@...>
Cc: Chandana C Kumar <chandana.c.kumar@...>
Cc: JackX Lin <JackX.Lin@...>
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 238 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------------------------------------------------------------------------------------------------
1 file changed, 117 insertions(+), 121 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index ab3296d68a..c03d899163 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -49,7 +49,7 @@ VOID *mLocalTable[] = {
&Wsmt,
};

-EFI_ACPI_TABLE_PROTOCOL *mAcpiTable;
+EFI_ACPI_TABLE_PROTOCOL *mAcpiTable;

UINT32 mNumOfBitShift = 6;
BOOLEAN mForceX2ApicId;
@@ -215,7 +215,7 @@ SortCpuLocalApicInTable (
} //end for CurrentProcessor

//keep for debug purpose
- DEBUG(( EFI_D_ERROR, "::ACPI:: APIC ID Order Table Init. CoreThreadMask = %x, mNumOfBitShift = %x\n", CoreThreadMask, mNumOfBitShift));
+ DEBUG ((DEBUG_INFO, "::ACPI:: APIC ID Order Table Init. CoreThreadMask = %x, mNumOfBitShift = %x\n", CoreThreadMask, mNumOfBitShift));
DebugDisplayReOrderTable (TempCpuApicIdOrderTable);

//
@@ -238,7 +238,7 @@ SortCpuLocalApicInTable (
}

if (mNumberOfCpus <= Index) {
- DEBUG ((EFI_D_ERROR, "Asserting the SortCpuLocalApicInTable Index Bufferflow\n"));
+ DEBUG ((DEBUG_ERROR, "Asserting the SortCpuLocalApicInTable Index Bufferflow\n"));
return EFI_INVALID_PARAMETER;
}
}
@@ -293,7 +293,7 @@ SortCpuLocalApicInTable (
}

//keep for debug purpose
- DEBUG ((EFI_D_ERROR, "APIC ID Order Table ReOrdered\n"));
+ DEBUG ((DEBUG_INFO, "APIC ID Order Table ReOrdered\n"));
DebugDisplayReOrderTable (mCpuApicIdOrderTable);

mCpuOrderSorted = TRUE;
@@ -493,11 +493,11 @@ InitializeMadtHeader (
}

Status = InitializeHeader (
- &MadtHeader->Header,
- EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
- 0
- );
+ &MadtHeader->Header,
+ EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+ 0
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -675,11 +675,11 @@ BuildAcpiTable (
// Allocate the memory needed for the table.
//
Status = AllocateTable (
- TableSpecificHdrLength,
- Structures,
- StructureCount,
- &InternalTable
- );
+ TableSpecificHdrLength,
+ Structures,
+ StructureCount,
+ &InternalTable
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -771,7 +771,7 @@ InstallMadtFromScratch (
// Call for Local APIC ID Reorder
Status = SortCpuLocalApicInTable ();
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "SortCpuLocalApicInTable failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "SortCpuLocalApicInTable failed: %r\n", Status));
goto Done;
}

@@ -801,11 +801,11 @@ InstallMadtFromScratch (
//
Status = InitializeMadtHeader (&MadtTableHeader);
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "InitializeMadtHeader failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "InitializeMadtHeader failed: %r\n", Status));
goto Done;
}

- DEBUG ((EFI_D_INFO, "Number of CPUs detected = %d \n", mNumberOfCpus));
+ DEBUG ((DEBUG_INFO, "Number of CPUs detected = %d \n", mNumberOfCpus));

//
// Build Processor Local APIC Structures and Processor Local X2APIC Structures
@@ -831,10 +831,10 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &ProcLocalApicStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &ProcLocalApicStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
} else if (mCpuApicIdOrderTable[Index].ApicId != 0xFFFFFFFF) {
ProcLocalX2ApicStruct.Flags = (UINT8) mCpuApicIdOrderTable[Index].Flags;
ProcLocalX2ApicStruct.X2ApicId = mCpuApicIdOrderTable[Index].ApicId;
@@ -842,13 +842,13 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &ProcLocalX2ApicStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &ProcLocalX2ApicStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
}
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (local APIC/x2APIC) failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (local APIC/x2APIC) failed: %r\n", Status));
goto Done;
}
}
@@ -860,44 +860,44 @@ InstallMadtFromScratch (
IoApicStruct.Length = sizeof (EFI_ACPI_4_0_IO_APIC_STRUCTURE);
IoApicStruct.Reserved = 0;

- PcIoApicEnable = PcdGet32(PcdPcIoApicEnable);
+ PcIoApicEnable = PcdGet32 (PcdPcIoApicEnable);

- if (FixedPcdGet32(PcdMaxCpuSocketCount) <= 4) {
+ if (FixedPcdGet32 (PcdMaxCpuSocketCount) <= 4) {
IoApicStruct.IoApicId = PcdGet8(PcdIoApicId);
IoApicStruct.IoApicAddress = PcdGet32(PcdIoApicAddress);
IoApicStruct.GlobalSystemInterruptBase = 0;
ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &IoApicStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &IoApicStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", Status));
goto Done;
}
}

for (PcIoApicIndex = 0; PcIoApicIndex < PcdGet8(PcdPcIoApicCount); PcIoApicIndex++) {
- PcIoApicMask = (1 << PcIoApicIndex);
- if ((PcIoApicEnable & PcIoApicMask) == 0) {
- continue;
- }
+ PcIoApicMask = (1 << PcIoApicIndex);
+ if ((PcIoApicEnable & PcIoApicMask) == 0) {
+ continue;
+ }

- IoApicStruct.IoApicId = (UINT8)(PcdGet8(PcdPcIoApicIdBase) + PcIoApicIndex);
- IoApicStruct.IoApicAddress = CurrentIoApicAddress;
- CurrentIoApicAddress = (CurrentIoApicAddress & 0xFFFF8000) + 0x8000;
- IoApicStruct.GlobalSystemInterruptBase = (UINT32)(24 + (PcIoApicIndex * 8));
- ASSERT (MadtStructsIndex < MaxMadtStructCount);
- Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &IoApicStruct,
- &MadtStructs[MadtStructsIndex++]
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", Status));
- goto Done;
- }
+ IoApicStruct.IoApicId = (UINT8)(PcdGet8(PcdPcIoApicIdBase) + PcIoApicIndex);
+ IoApicStruct.IoApicAddress = CurrentIoApicAddress;
+ CurrentIoApicAddress = (CurrentIoApicAddress & 0xFFFF8000) + 0x8000;
+ IoApicStruct.GlobalSystemInterruptBase = (UINT32)(24 + (PcIoApicIndex * 8));
+ ASSERT (MadtStructsIndex < MaxMadtStructCount);
+ Status = CopyStructure (
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &IoApicStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", Status));
+ goto Done;
+ }
}

//
@@ -916,12 +916,12 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &IntSrcOverrideStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &IntSrcOverrideStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (IRQ2 source override) failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (IRQ2 source override) failed: %r\n", Status));
goto Done;
}

@@ -935,12 +935,12 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &IntSrcOverrideStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &IntSrcOverrideStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (IRQ9 source override) failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (IRQ9 source override) failed: %r\n", Status));
goto Done;
}

@@ -955,12 +955,12 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &LocalApciNmiStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &LocalApciNmiStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (APIC NMI) failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (APIC NMI) failed: %r\n", Status));
goto Done;
}

@@ -979,10 +979,10 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &LocalX2ApicNmiStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &LocalX2ApicNmiStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "CopyMadtStructure (x2APIC NMI) failed: %r\n", Status));
goto Done;
@@ -993,14 +993,14 @@ InstallMadtFromScratch (
// Build Madt Structure from the Madt Header and collection of pointers in MadtStructs[]
//
Status = BuildAcpiTable (
- (EFI_ACPI_DESCRIPTION_HEADER *) &MadtTableHeader,
- sizeof (EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER),
- MadtStructs,
- MadtStructsIndex,
- (UINT8 **)&NewMadtTable
- );
+ (EFI_ACPI_DESCRIPTION_HEADER *) &MadtTableHeader,
+ sizeof (EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER),
+ MadtStructs,
+ MadtStructsIndex,
+ (UINT8 **) &NewMadtTable
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "BuildAcpiTable failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "BuildAcpiTable failed: %r\n", Status));
goto Done;
}

@@ -1008,11 +1008,11 @@ InstallMadtFromScratch (
// Publish Madt Structure to ACPI
//
Status = mAcpiTable->InstallAcpiTable (
- mAcpiTable,
- NewMadtTable,
- NewMadtTable->Header.Length,
- &TableHandle
- );
+ mAcpiTable,
+ NewMadtTable,
+ NewMadtTable->Header.Length,
+ &TableHandle
+ );

Done:
//
@@ -1054,8 +1054,8 @@ InstallMcfgFromScratch (
PciSegmentInfo = GetPciSegmentInfo (&SegmentCount);

McfgTable = AllocateZeroPool (
- sizeof(EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER) +
- sizeof(EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE) * SegmentCount
+ sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER) +
+ sizeof (EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE) * SegmentCount
);
if (McfgTable == NULL) {
DEBUG ((DEBUG_ERROR, "Could not allocate MCFG structure\n"));
@@ -1063,11 +1063,11 @@ InstallMcfgFromScratch (
}

Status = InitializeHeader (
- &McfgTable->Header,
- EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
- 0
- );
+ &McfgTable->Header,
+ EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
+ 0
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -1091,11 +1091,11 @@ InstallMcfgFromScratch (
// Publish Madt Structure to ACPI
//
Status = mAcpiTable->InstallAcpiTable (
- mAcpiTable,
- McfgTable,
- McfgTable->Header.Length,
- &TableHandle
- );
+ mAcpiTable,
+ McfgTable,
+ McfgTable->Header.Length,
+ &TableHandle
+ );

return Status;
}
@@ -1179,7 +1179,7 @@ PlatformUpdateTables (
switch (Table->Signature) {

case EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE:
- ASSERT(FALSE);
+ ASSERT (FALSE);
break;

case EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:
@@ -1223,9 +1223,9 @@ PlatformUpdateTables (
FadtHeader->XGpe1Blk.AccessSize = 0;
}

- DEBUG(( EFI_D_ERROR, "ACPI FADT table @ address 0x%x\n", Table ));
- DEBUG(( EFI_D_ERROR, " IaPcBootArch 0x%x\n", FadtHeader->IaPcBootArch ));
- DEBUG(( EFI_D_ERROR, " Flags 0x%x\n", FadtHeader->Flags ));
+ DEBUG ((DEBUG_INFO, "ACPI FADT table @ address 0x%x\n", Table));
+ DEBUG ((DEBUG_INFO, " IaPcBootArch 0x%x\n", FadtHeader->IaPcBootArch));
+ DEBUG ((DEBUG_INFO, " Flags 0x%x\n", FadtHeader->Flags));
break;

case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:
@@ -1245,12 +1245,12 @@ PlatformUpdateTables (
HpetBlockId.Bits.VendorId = HpetCapabilities.Bits.VendorId;
HpetTable->EventTimerBlockId = HpetBlockId.Uint32;
HpetTable->MainCounterMinimumClockTickInPeriodicMode = (UINT16)HpetCapabilities.Bits.CounterClockPeriod;
- DEBUG(( EFI_D_ERROR, "ACPI HPET table @ address 0x%x\n", Table ));
- DEBUG(( EFI_D_ERROR, " HPET base 0x%x\n", PcdGet32 (PcdHpetBaseAddress) ));
+ DEBUG ((DEBUG_INFO, "ACPI HPET table @ address 0x%x\n", Table));
+ DEBUG ((DEBUG_INFO, " HPET base 0x%x\n", PcdGet32 (PcdHpetBaseAddress)));
break;

case EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE:
- ASSERT(FALSE);
+ ASSERT (FALSE);
break;

default:
@@ -1302,8 +1302,8 @@ IsHardwareChange (
// pFADT->XDsdt
//
HWChangeSize = HandleCount + 1;
- HWChange = AllocateZeroPool( sizeof(UINT32) * HWChangeSize );
- ASSERT( HWChange != NULL );
+ HWChange = AllocateZeroPool (sizeof(UINT32) * HWChangeSize);
+ ASSERT(HWChange != NULL);

if (HWChange == NULL) return;

@@ -1344,14 +1344,14 @@ IsHardwareChange (
// Calculate CRC value with HWChange data.
//
Status = gBS->CalculateCrc32(HWChange, HWChangeSize, &CRC);
- DEBUG((DEBUG_INFO, "CRC = %x and Status = %r\n", CRC, Status));
+ DEBUG ((DEBUG_INFO, "CRC = %x and Status = %r\n", CRC, Status));

//
// Set HardwareSignature value based on CRC value.
//
FacsPtr = (EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)(UINTN)pFADT->FirmwareCtrl;
FacsPtr->HardwareSignature = CRC;
- FreePool( HWChange );
+ FreePool (HWChange);
}

VOID
@@ -1374,17 +1374,16 @@ UpdateLocalTable (

if (Version != EFI_ACPI_TABLE_VERSION_NONE) {
Status = mAcpiTable->InstallAcpiTable (
- mAcpiTable,
- CurrentTable,
- CurrentTable->Length,
- &TableHandle
- );
+ mAcpiTable,
+ CurrentTable,
+ CurrentTable->Length,
+ &TableHandle
+ );
ASSERT_EFI_ERROR (Status);
}
}
}

-
VOID
EFIAPI
AcpiEndOfDxeEvent (
@@ -1392,16 +1391,14 @@ AcpiEndOfDxeEvent (
VOID *ParentImageHandle
)
{
-
if (Event != NULL) {
- gBS->CloseEvent(Event);
+ gBS->CloseEvent (Event);
}

-
//
// Calculate Hardware Signature value based on current platform configurations
//
- IsHardwareChange();
+ IsHardwareChange ();
}

/**
@@ -1425,7 +1422,6 @@ InstallAcpiPlatform (
EFI_STATUS Status;
EFI_EVENT EndOfDxeEvent;

-
Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&mMpService);
ASSERT_EFI_ERROR (Status);

@@ -1449,10 +1445,10 @@ InstallAcpiPlatform (
// Determine the number of processors
//
mMpService->GetNumberOfProcessors (
- mMpService,
- &mNumberOfCpus,
- &mNumberOfEnabledCPUs
- );
+ mMpService,
+ &mNumberOfCpus,
+ &mNumberOfEnabledCPUs
+ );

DEBUG ((DEBUG_INFO, "mNumberOfCpus - %d\n", mNumberOfCpus));
DEBUG ((DEBUG_INFO, "mNumberOfEnabledCPUs - %d\n", mNumberOfEnabledCPUs));
@@ -1461,7 +1457,7 @@ InstallAcpiPlatform (
DEBUG ((DEBUG_INFO, "mForceX2ApicId - 0x%x\n", mForceX2ApicId));

// support up to 64 threads/socket
- AsmCpuidEx(CPUID_EXTENDED_TOPOLOGY, 1, &mNumOfBitShift, NULL, NULL, NULL);
+ AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 1, &mNumOfBitShift, NULL, NULL, NULL);
mNumOfBitShift &= 0x1F;
DEBUG ((DEBUG_INFO, "mNumOfBitShift - 0x%x\n", mNumOfBitShift));

--
2.32.0.windows.2


[edk2-platforms: PATCH V10 1/2] Platform/Intel: Correct CPU APIC IDs

JackX Lin
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3365

BIOS cannot find correct AcpiProcId in mApicIdMap because of
there is no suitable map, that causes ACPI_BIOS_ERROR.
Remove mApicIdMap for determing AcpiProcId, uses normal
countings instead.

Signed-off-by: JackX Lin <JackX.Lin@...>
Cc: Chasel Chiu <chasel.chiu@...>
Cc: Dong Eric <eric.dong@...>
Cc: Jiewen Yao <jiewen.yao@...>
Cc: Ray Ni <ray.ni@...>
Cc: Rangasai V Chaganty <rangasai.v.chaganty@...>
Cc: Donald Kuo <Donald.Kuo@...>
Cc: Chandana C Kumar <chandana.c.kumar@...>
Cc: JackX Lin <JackX.Lin@...>
---
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c | 417 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h | 4 +++-
Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf | 4 +++-
3 files changed, 164 insertions(+), 261 deletions(-)

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
index 2b51c34ef2..ab3296d68a 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.c
@@ -1,14 +1,13 @@
/** @file
ACPI Platform Driver

-Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent

**/

#include "AcpiPlatform.h"
-
-#define MAX_CPU_NUM (FixedPcdGet32(PcdMaxCpuThreadCount) * FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuSocketCount))
+#define MAX_SOCKET (FixedPcdGet32 (PcdMaxCpuSocketCount))

#pragma pack(1)

@@ -16,8 +15,8 @@ typedef struct {
UINT32 AcpiProcessorId;
UINT32 ApicId;
UINT32 Flags;
- UINT32 SwProcApicId;
UINT32 SocketNum;
+ UINT32 Thread;
} EFI_CPU_ID_ORDER_MAP;

//
@@ -58,170 +57,58 @@ BOOLEAN mX2ApicEnabled;

EFI_MP_SERVICES_PROTOCOL *mMpService;
BOOLEAN mCpuOrderSorted;
-EFI_CPU_ID_ORDER_MAP mCpuApicIdOrderTable[MAX_CPU_NUM];
-UINTN mNumberOfCPUs = 0;
+EFI_CPU_ID_ORDER_MAP *mCpuApicIdOrderTable = NULL;
+UINTN mNumberOfCpus = 0;
UINTN mNumberOfEnabledCPUs = 0;

-// following are possible APICID Map for SKX
-static const UINT32 ApicIdMapA[] = { //for SKUs have number of core > 16
- //it is 14 + 14 + 14 + 14 format
- 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000006, 0x00000007,
- 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, 0x00000010, 0x00000011,
- 0x00000012, 0x00000013, 0x00000014, 0x00000015, 0x00000016, 0x00000017, 0x00000018, 0x00000019,
- 0x0000001A, 0x0000001B, 0x0000001C, 0x0000001D, 0x00000020, 0x00000021, 0x00000022, 0x00000023,
- 0x00000024, 0x00000025, 0x00000026, 0x00000027, 0x00000028, 0x00000029, 0x0000002A, 0x0000002B,
- 0x0000002C, 0x0000002D, 0x00000030, 0x00000031, 0x00000032, 0x00000033, 0x00000034, 0x00000035,
- 0x00000036, 0x00000037, 0x00000038, 0x00000039, 0x0000003A, 0x0000003B, 0x0000003C, 0x0000003D
-};
-
-static const UINT32 ApicIdMapB[] = { //for SKUs have number of cores <= 16 use 32 ID space
- //it is 16+16 format
- 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000006, 0x00000007,
- 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, 0x0000000E, 0x0000000F,
- 0x00000010, 0x00000011, 0x00000012, 0x00000013, 0x00000014, 0x00000015, 0x00000016, 0x00000017,
- 0x00000018, 0x00000019, 0x0000001A, 0x0000001B, 0x0000001C, 0x0000001D, 0x0000001E, 0x0000001F,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
-};
-
-
-static const UINT32 ApicIdMapC[] = { //for SKUs have number of cores <= 16 use 64 ID space
- //it is 16+0+16+0 format
- 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000006, 0x00000007,
- 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, 0x0000000E, 0x0000000F,
- 0x00000020, 0x00000021, 0x00000022, 0x00000023, 0x00000024, 0x00000025, 0x00000026, 0x00000027,
- 0x00000028, 0x00000029, 0x0000002A, 0x0000002B, 0x0000002C, 0x0000002D, 0x0000002E, 0x0000002F,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
-};
-
-static const UINT32 ApicIdMapD[] = { //for SKUs have number of cores <= 8 use 16 ID space
- //it is 16 format
- 0x00000000, 0x00000001, 0x00000002, 0x00000003, 0x00000004, 0x00000005, 0x00000006, 0x00000007,
- 0x00000008, 0x00000009, 0x0000000A, 0x0000000B, 0x0000000C, 0x0000000D, 0x0000000E, 0x0000000F,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
- 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
-};
-
-const UINT32 *mApicIdMap = NULL;

/**
- This function detect the APICID map and update ApicID Map pointer
+ The function is called by PerformQuickSort to compare int values.

- @param None
+ @param[in] Left The pointer to first buffer.
+ @param[in] Right The pointer to second buffer.

- @retval VOID
+ @return -1 Buffer1 is less than Buffer2.
+ @return 1 Buffer1 is greater than Buffer2.

**/
-VOID DetectApicIdMap(VOID)
+INTN
+EFIAPI
+ApicIdCompareFunction (
+ IN CONST VOID *Left,
+ IN CONST VOID *Right
+ )
{
- UINTN CoreCount;
+ UINT32 LeftApicId;
+ UINT32 RightApicId;

- CoreCount = 0;
-
- if(mApicIdMap != NULL) {
- return; //aleady initialized
- }
-
- mApicIdMap = ApicIdMapA; // default to > 16C SKUs
-
- CoreCount = mNumberOfEnabledCPUs / 2;
- DEBUG ((DEBUG_INFO, "CoreCount - %d\n", CoreCount));
-
- //DEBUG((EFI_D_ERROR, ":: Default to use Map A @ %08X FusedCoreCount: %02d, sktlevel: %d\n",mApicIdMap, FusedCoreCount, mNumOfBitShift));
- // Dont assert for single core, single thread system.
- //ASSERT (CoreCount != 0);
-
- if(CoreCount <= 16) {
-
- if(mNumOfBitShift == 4) {
- mApicIdMap = ApicIdMapD;
- //DEBUG((EFI_D_ERROR, ":: Use Map B @ %08X\n",mApicIdMap));
- }
-
- if(mNumOfBitShift == 5) {
- mApicIdMap = ApicIdMapB;
- //DEBUG((EFI_D_ERROR, ":: Use Map B @ %08X\n",mApicIdMap));
- }
-
- if(mNumOfBitShift == 6) {
- mApicIdMap = ApicIdMapC;
- //DEBUG((EFI_D_ERROR, ":: Use Map C @ %08X\n",mApicIdMap));
- }
+ LeftApicId = ((EFI_CPU_ID_ORDER_MAP *) Left)->ApicId;
+ RightApicId = ((EFI_CPU_ID_ORDER_MAP *) Right)->ApicId;

- }
-
- return;
+ return (LeftApicId > RightApicId)? 1 : (-1);
}

/**
- This function return the CoreThreadId of ApicId from ACPI ApicId Map array
-
- @param ApicId
-
- @retval Index of ACPI ApicId Map array
+ Print Cpu Apic ID Table

+ @param[in] CpuApicIdOrderTable Data will be dumped.
**/
-UINT32
-GetIndexFromApicId (
- UINT32 ApicId
- )
-{
- UINT32 CoreThreadId;
- UINT32 i;
-
- ASSERT (mApicIdMap != NULL);
-
- CoreThreadId = ApicId & ((1 << mNumOfBitShift) - 1);
-
- for(i = 0; i < (FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuThreadCount)); i++) {
- if(mApicIdMap[i] == CoreThreadId) {
- break;
- }
- }
-
- ASSERT (i <= (FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuThreadCount)));
-
- return i;
-}
-
-UINT32
-ApicId2SwProcApicId (
- UINT32 ApicId
- )
-{
- UINT32 Index;
-
- for (Index = 0; Index < MAX_CPU_NUM; Index++) {
- if ((mCpuApicIdOrderTable[Index].Flags == 1) && (mCpuApicIdOrderTable[Index].ApicId == ApicId)) {
- return Index;
- }
- }
-
- return (UINT32) -1;
-
-}
-
VOID
-DebugDisplayReOrderTable(
- VOID
+DebugDisplayReOrderTable (
+ IN EFI_CPU_ID_ORDER_MAP *CpuApicIdOrderTable
)
{
UINT32 Index;

- DEBUG ((EFI_D_ERROR, "Index AcpiProcId ApicId Flags SwApicId Skt\n"));
- for (Index=0; Index<MAX_CPU_NUM; Index++) {
- DEBUG ((EFI_D_ERROR, " %02d 0x%02X 0x%02X %d 0x%02X %d\n",
- Index, mCpuApicIdOrderTable[Index].AcpiProcessorId,
- mCpuApicIdOrderTable[Index].ApicId,
- mCpuApicIdOrderTable[Index].Flags,
- mCpuApicIdOrderTable[Index].SwProcApicId,
- mCpuApicIdOrderTable[Index].SocketNum));
+ DEBUG ((DEBUG_INFO, "Index AcpiProcId ApicId Thread Flags Skt\n"));
+ for (Index = 0; Index < mNumberOfCpus; Index++) {
+ DEBUG ((DEBUG_INFO, " %02d 0x%02X 0x%02X %d %d %d\n",
+ Index,
+ CpuApicIdOrderTable[Index].AcpiProcessorId,
+ CpuApicIdOrderTable[Index].ApicId,
+ CpuApicIdOrderTable[Index].Thread,
+ CpuApicIdOrderTable[Index].Flags,
+ CpuApicIdOrderTable[Index].SocketNum));
}
}

@@ -281,131 +168,135 @@ SortCpuLocalApicInTable (
UINT32 Index;
UINT32 CurrProcessor;
UINT32 BspApicId;
- UINT32 TempVal = 0;
+ EFI_CPU_ID_ORDER_MAP *TempVal;
EFI_CPU_ID_ORDER_MAP *CpuIdMapPtr;
UINT32 CoreThreadMask;
+ EFI_CPU_ID_ORDER_MAP *TempCpuApicIdOrderTable;
+ UINT32 Socket;

Index = 0;
Status = EFI_SUCCESS;

- CoreThreadMask = (UINT32) ((1 << mNumOfBitShift) - 1);
-
- if(!mCpuOrderSorted) {
-
- Index = 0;
+ if (mCpuOrderSorted) {
+ return Status;
+ }

- for (CurrProcessor = 0; CurrProcessor < mNumberOfCPUs; CurrProcessor++) {
- Status = mMpService->GetProcessorInfo (
- mMpService,
- CurrProcessor,
- &ProcessorInfoBuffer
- );
+ TempCpuApicIdOrderTable = AllocateZeroPool (mNumberOfCpus * sizeof (EFI_CPU_ID_ORDER_MAP));
+ TempVal = AllocateZeroPool (sizeof (EFI_CPU_ID_ORDER_MAP));
+ CoreThreadMask = (UINT32) ((1 << mNumOfBitShift) - 1);

- if ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0) {
- if(ProcessorInfoBuffer.ProcessorId & 1) { //is 2nd thread
- CpuIdMapPtr = (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[(Index - 1) + MAX_CPU_NUM / 2];
- } else { //is primary thread
- CpuIdMapPtr = (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[Index];
- Index++;
+ for (CurrProcessor = 0, Index = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++, Index++) {
+ Status = mMpService->GetProcessorInfo (
+ mMpService,
+ CurrProcessor,
+ &ProcessorInfoBuffer
+ );
+
+ CpuIdMapPtr = (EFI_CPU_ID_ORDER_MAP *) &TempCpuApicIdOrderTable[Index];
+ if ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0) {
+ CpuIdMapPtr->ApicId = (UINT32)ProcessorInfoBuffer.ProcessorId;
+ CpuIdMapPtr->Thread = ProcessorInfoBuffer.Location.Thread;
+ CpuIdMapPtr->Flags = ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0);
+ CpuIdMapPtr->SocketNum = ProcessorInfoBuffer.Location.Package;
+
+ //update processorbitMask
+ if (CpuIdMapPtr->Flags == 1) {
+ if (mForceX2ApicId) {
+ CpuIdMapPtr->SocketNum &= 0x7;
+ CpuIdMapPtr->AcpiProcessorId &= 0xFF; //keep lower 8bit due to use Proc obj in dsdt
}
- CpuIdMapPtr->ApicId = (UINT32)ProcessorInfoBuffer.ProcessorId;
- CpuIdMapPtr->Flags = ((ProcessorInfoBuffer.StatusFlag & PROCESSOR_ENABLED_BIT) != 0);
- CpuIdMapPtr->SocketNum = (UINT32)ProcessorInfoBuffer.Location.Package;
- CpuIdMapPtr->AcpiProcessorId = (CpuIdMapPtr->SocketNum * FixedPcdGet32(PcdMaxCpuCoreCount) * FixedPcdGet32(PcdMaxCpuThreadCount)) + GetIndexFromApicId(CpuIdMapPtr->ApicId); //CpuIdMapPtr->ApicId;
- CpuIdMapPtr->SwProcApicId = ((UINT32)(ProcessorInfoBuffer.Location.Package << mNumOfBitShift) + (((UINT32)ProcessorInfoBuffer.ProcessorId) & CoreThreadMask));
- if(mX2ApicEnabled) { //if X2Apic, re-order the socket # so it starts from base 0 and contiguous
- //may not necessory!!!!!
- }
-
- //update processorbitMask
- if (CpuIdMapPtr->Flags == 1) {
+ }
+ } else { //not enabled
+ CpuIdMapPtr->ApicId = (UINT32)-1;
+ CpuIdMapPtr->Thread = (UINT32)-1;
+ CpuIdMapPtr->Flags = 0;
+ CpuIdMapPtr->SocketNum = (UINT32)-1;
+ } //end if PROC ENABLE
+ } //end for CurrentProcessor
+
+ //keep for debug purpose
+ DEBUG(( EFI_D_ERROR, "::ACPI:: APIC ID Order Table Init. CoreThreadMask = %x, mNumOfBitShift = %x\n", CoreThreadMask, mNumOfBitShift));
+ DebugDisplayReOrderTable (TempCpuApicIdOrderTable);
+
+ //
+ // Get Bsp Apic Id
+ //
+ BspApicId = GetApicId ();
+ DEBUG ((DEBUG_INFO, "BspApicId - 0x%x\n", BspApicId));
+
+ //
+ //check to see if 1st entry is BSP, if not swap it
+ //
+ if (TempCpuApicIdOrderTable[0].ApicId != BspApicId) {
+ for (Index = 0; Index < mNumberOfCpus; Index++) {
+ if ((TempCpuApicIdOrderTable[Index].Flags == 1) && (TempCpuApicIdOrderTable[Index].ApicId == BspApicId)) {
+ CopyMem (&TempVal, &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP));
+ CopyMem (&TempCpuApicIdOrderTable[Index], &TempCpuApicIdOrderTable[0], sizeof (EFI_CPU_ID_ORDER_MAP));
+ CopyMem (&TempCpuApicIdOrderTable[0], &TempVal, sizeof (EFI_CPU_ID_ORDER_MAP));
+ break;
+ }
+ }

- if(mForceX2ApicId) {
- CpuIdMapPtr->SocketNum &= 0x7;
- CpuIdMapPtr->AcpiProcessorId &= 0xFF; //keep lower 8bit due to use Proc obj in dsdt
- CpuIdMapPtr->SwProcApicId &= 0xFF;
- }
- }
- } else { //not enabled
- CpuIdMapPtr = (EFI_CPU_ID_ORDER_MAP *)&mCpuApicIdOrderTable[Index];
- CpuIdMapPtr->ApicId = (UINT32)-1;
- CpuIdMapPtr->Flags = 0;
- CpuIdMapPtr->AcpiProcessorId = (UINT32)-1;
- CpuIdMapPtr->SwProcApicId = (UINT32)-1;
- CpuIdMapPtr->SocketNum = (UINT32)-1;
- } //end if PROC ENABLE
- } //end for CurrentProcessor
-
- //keep for debug purpose
- DEBUG(( EFI_D_ERROR, "::ACPI:: APIC ID Order Table Init. CoreThreadMask = %x, mNumOfBitShift = %x\n", CoreThreadMask, mNumOfBitShift));
- DebugDisplayReOrderTable();
-
- //make sure 1st entry is BSP
- if(mX2ApicEnabled) {
- BspApicId = (UINT32)AsmReadMsr64(0x802);
- } else {
- BspApicId = (*(volatile UINT32 *)(UINTN)0xFEE00020) >> 24;
+ if (mNumberOfCpus <= Index) {
+ DEBUG ((EFI_D_ERROR, "Asserting the SortCpuLocalApicInTable Index Bufferflow\n"));
+ return EFI_INVALID_PARAMETER;
}
- DEBUG ((EFI_D_INFO, "BspApicId - 0x%x\n", BspApicId));
+ }

- if(mCpuApicIdOrderTable[0].ApicId != BspApicId) {
- //check to see if 1st entry is BSP, if not swap it
- Index = ApicId2SwProcApicId(BspApicId);
+ //
+ // 1. Sort TempCpuApicIdOrderTable,
+ // sort it by using ApicId from minimum to maximum (Socket0 to SocketN), and the BSP must in the fist location of the table.
+ // So, start sorting the table from the second element and total elements are mNumberOfCpus-1.
+ //
+ PerformQuickSort ((TempCpuApicIdOrderTable + 1), (mNumberOfCpus - 1), sizeof (EFI_CPU_ID_ORDER_MAP), (SORT_COMPARE) ApicIdCompareFunction);

- if(MAX_CPU_NUM <= Index) {
- DEBUG ((EFI_D_ERROR, "Asserting the SortCpuLocalApicInTable Index Bufferflow\n"));
- return EFI_INVALID_PARAMETER;
- }
+ //
+ // 2. Sort and map the primary threads to the front of the CpuApicIdOrderTable
+ //
+ for (CurrProcessor = 0, Index = 0; Index < mNumberOfCpus; Index++) {
+ if ((TempCpuApicIdOrderTable[Index].Thread) == 0) { // primary thread
+ CopyMem (&mCpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP));
+ CurrProcessor++;
+ }
+ }

- TempVal = mCpuApicIdOrderTable[Index].ApicId;
- mCpuApicIdOrderTable[Index].ApicId = mCpuApicIdOrderTable[0].ApicId;
- mCpuApicIdOrderTable[0].ApicId = TempVal;
- mCpuApicIdOrderTable[Index].Flags = mCpuApicIdOrderTable[0].Flags;
- mCpuApicIdOrderTable[0].Flags = 1;
- TempVal = mCpuApicIdOrderTable[Index].SwProcApicId;
- mCpuApicIdOrderTable[Index].SwProcApicId = mCpuApicIdOrderTable[0].SwProcApicId;
- mCpuApicIdOrderTable[0].SwProcApicId = TempVal;
- //swap AcpiProcId
- TempVal = mCpuApicIdOrderTable[Index].AcpiProcessorId;
- mCpuApicIdOrderTable[Index].AcpiProcessorId = mCpuApicIdOrderTable[0].AcpiProcessorId;
- mCpuApicIdOrderTable[0].AcpiProcessorId = TempVal;
+ //
+ // 3. Sort and map the second threads to the middle of the CpuApicIdOrderTable
+ //
+ for (Index = 0; Index < mNumberOfCpus; Index++) {
+ if ((TempCpuApicIdOrderTable[Index].Thread) == 1) { //second thread
+ CopyMem (&mCpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP));
+ CurrProcessor++;
+ }
+ }

+ //
+ // 4. Sort and map the not enabled threads to the bottom of the CpuApicIdOrderTable
+ //
+ for (Index = 0; Index < mNumberOfCpus; Index++) {
+ if (TempCpuApicIdOrderTable[Index].Flags == 0) { // not enabled
+ CopyMem (&mCpuApicIdOrderTable[CurrProcessor], &TempCpuApicIdOrderTable[Index], sizeof (EFI_CPU_ID_ORDER_MAP));
+ CurrProcessor++;
}
+ }

- //Make sure no holes between enabled threads
- for(CurrProcessor = 0; CurrProcessor < MAX_CPU_NUM; CurrProcessor++) {
-
- if(mCpuApicIdOrderTable[CurrProcessor].Flags == 0) {
- //make sure disabled entry has ProcId set to FFs
- mCpuApicIdOrderTable[CurrProcessor].ApicId = (UINT32)-1;
- mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId = (UINT32)-1;
- mCpuApicIdOrderTable[CurrProcessor].SwProcApicId = (UINT32)-1;
-
- for(Index = CurrProcessor+1; Index < MAX_CPU_NUM; Index++) {
- if(mCpuApicIdOrderTable[Index].Flags == 1) {
- //move enabled entry up
- mCpuApicIdOrderTable[CurrProcessor].Flags = 1;
- mCpuApicIdOrderTable[CurrProcessor].ApicId = mCpuApicIdOrderTable[Index].ApicId;
- mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId = mCpuApicIdOrderTable[Index].AcpiProcessorId;
- mCpuApicIdOrderTable[CurrProcessor].SwProcApicId = mCpuApicIdOrderTable[Index].SwProcApicId;
- mCpuApicIdOrderTable[CurrProcessor].SocketNum = mCpuApicIdOrderTable[Index].SocketNum;
- //disable moved entry
- mCpuApicIdOrderTable[Index].Flags = 0;
- mCpuApicIdOrderTable[Index].ApicId = (UINT32)-1;
- mCpuApicIdOrderTable[Index].AcpiProcessorId = (UINT32)-1;
- mCpuApicIdOrderTable[Index].SwProcApicId = (UINT32)-1;
- break;
- }
- }
+ //
+ // 5. Re-assigen AcpiProcessorId for AcpiProcessorUId uses purpose.
+ //
+ for (Socket = 0; Socket < MAX_SOCKET; Socket++) {
+ for (CurrProcessor = 0, Index = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) {
+ if (mCpuApicIdOrderTable[CurrProcessor].Flags && (mCpuApicIdOrderTable[CurrProcessor].SocketNum == Socket)) {
+ mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId = (ProcessorInfoBuffer.Location.Package << mNumOfBitShift) + Index;
+ Index++;
}
}
+ }

- //keep for debug purpose
- DEBUG ((EFI_D_ERROR, "APIC ID Order Table ReOrdered\n"));
- DebugDisplayReOrderTable();
+ //keep for debug purpose
+ DEBUG ((EFI_D_ERROR, "APIC ID Order Table ReOrdered\n"));
+ DebugDisplayReOrderTable (mCpuApicIdOrderTable);

- mCpuOrderSorted = TRUE;
- }
+ mCpuOrderSorted = TRUE;

return Status;
}
@@ -871,7 +762,11 @@ InstallMadtFromScratch (
NewMadtTable = NULL;
MaxMadtStructCount = 0;

- DetectApicIdMap();
+ mCpuApicIdOrderTable = AllocateZeroPool (mNumberOfCpus * sizeof (EFI_CPU_ID_ORDER_MAP));
+ if (mCpuApicIdOrderTable == NULL) {
+ DEBUG ((DEBUG_ERROR, "Could not allocate mCpuApicIdOrderTable structure pointer array\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }

// Call for Local APIC ID Reorder
Status = SortCpuLocalApicInTable ();
@@ -881,8 +776,8 @@ InstallMadtFromScratch (
}

MaxMadtStructCount = (UINT32) (
- MAX_CPU_NUM + // processor local APIC structures
- MAX_CPU_NUM + // processor local x2APIC structures
+ mNumberOfCpus + // processor local APIC structures
+ mNumberOfCpus + // processor local x2APIC structures
1 + PcdGet8(PcdPcIoApicCount) + // I/O APIC structures
2 + // interrupt source override structures
1 + // local APIC NMI structures
@@ -910,7 +805,7 @@ InstallMadtFromScratch (
goto Done;
}

- DEBUG ((EFI_D_INFO, "Number of CPUs detected = %d \n", mNumberOfCPUs));
+ DEBUG ((EFI_D_INFO, "Number of CPUs detected = %d \n", mNumberOfCpus));

//
// Build Processor Local APIC Structures and Processor Local X2APIC Structures
@@ -923,7 +818,7 @@ InstallMadtFromScratch (
ProcLocalX2ApicStruct.Reserved[0] = 0;
ProcLocalX2ApicStruct.Reserved[1] = 0;

- for (Index = 0; Index < MAX_CPU_NUM; Index++) {
+ for (Index = 0; Index < mNumberOfCpus; Index++) {
//
// If x2APIC mode is not enabled, and if it is possible to express the
// APIC ID as a UINT8, use a processor local APIC structure. Otherwise,
@@ -1136,6 +1031,10 @@ Done:
FreePool (NewMadtTable);
}

+ if (mCpuApicIdOrderTable != NULL) {
+ FreePool (mCpuApicIdOrderTable);
+ }
+
return Status;
}

@@ -1551,11 +1450,11 @@ InstallAcpiPlatform (
//
mMpService->GetNumberOfProcessors (
mMpService,
- &mNumberOfCPUs,
+ &mNumberOfCpus,
&mNumberOfEnabledCPUs
);
- ASSERT (mNumberOfCPUs <= MAX_CPU_NUM && mNumberOfEnabledCPUs >= 1);
- DEBUG ((DEBUG_INFO, "mNumberOfCPUs - %d\n", mNumberOfCPUs));
+
+ DEBUG ((DEBUG_INFO, "mNumberOfCpus - %d\n", mNumberOfCpus));
DEBUG ((DEBUG_INFO, "mNumberOfEnabledCPUs - %d\n", mNumberOfEnabledCPUs));

DEBUG ((DEBUG_INFO, "mX2ApicEnabled - 0x%x\n", mX2ApicEnabled));
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
index bd11f9e988..61f7470f80 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
@@ -1,7 +1,7 @@
/** @file
This is an implementation of the ACPI platform driver.

-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent

**/
@@ -35,6 +35,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h>
#include <Library/AslUpdateLib.h>
#include <Library/PciSegmentInfoLib.h>
+#include <Library/SortLib.h>
+#include <Library/LocalApicLib.h>

#include <Protocol/AcpiTable.h>
#include <Protocol/MpService.h>
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
index 5d9c8cab50..95f6656af0 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
@@ -1,7 +1,7 @@
### @file
# Component information file for AcpiPlatform module
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -43,6 +43,8 @@
PciSegmentInfoLib
AslUpdateLib
BoardAcpiTableLib
+ SortLib
+ LocalApicLib

[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
--
2.32.0.windows.2


Re: [PATCH v2] UefiCpuPkg/PiSmmCpuDxeSmm: Update mPatchCetSupported set condition

Ni, Ray
 

@@ -747,6 +747,9 @@ PiCpuSmmEntry (
AsmCpuidEx(CPUID_EXTENDED_STATE, 12, &RegEax, NULL, &RegEcx, NULL);
DEBUG ((DEBUG_INFO, "CPUID[D/12] EAX - 0x%08x, ECX - 0x%08x\n", RegEax, RegEcx));
}
+ } else {
+ mCetSupported = FALSE;
+ PatchInstructionX86(mPatchCetSupported, mCetSupported, 1);
}
} else {
mCetSupported = FALSE;

Reviewed-by: Ray Ni <ray.ni@...>

Thanks for catching another issue that mCetSupported should be FALSE.


Re: [PATCH EDK2 v1 1/1] MdeModulePkg/HiiDatabaseDxe:remove dead code block

Dandan Bi
 

Reviewed-by: Dandan Bi <dandan.bi@...>


Thanks,
Dandan

-----Original Message-----
From: Wenyi Xie <xiewenyi2@...>
Sent: Thursday, August 26, 2021 9:16 AM
To: devel@edk2.groups.io; Wang, Jian J <jian.j.wang@...>; Wu, Hao A
<hao.a.wu@...>; Bi, Dandan <dandan.bi@...>; Dong, Eric
<eric.dong@...>
Cc: songdongkuang@...; xiewenyi2@...
Subject: [PATCH EDK2 v1 1/1] MdeModulePkg/HiiDatabaseDxe:remove dead
code block

As the if statement outside has confirmed that
BlockData->Name == NULL, so the if statement inside
is always false.

Cc: Jian J Wang <jian.j.wang@...>
Cc: Hao A Wu <hao.a.wu@...>
Cc: Dandan Bi <dandan.bi@...>
Cc: Eric Dong <eric.dong@...>
Signed-off-by: Wenyi Xie <xiewenyi2@...>
---
MdeModulePkg/Universal/HiiDatabaseDxe/ConfigRouting.c | 3 ---
1 file changed, 3 deletions(-)

diff --git a/MdeModulePkg/Universal/HiiDatabaseDxe/ConfigRouting.c
b/MdeModulePkg/Universal/HiiDatabaseDxe/ConfigRouting.c
index d492b769d51c..17a914208c6d 100644
--- a/MdeModulePkg/Universal/HiiDatabaseDxe/ConfigRouting.c
+++ b/MdeModulePkg/Universal/HiiDatabaseDxe/ConfigRouting.c
@@ -2871,9 +2871,6 @@ ParseIfrData (
//
if ((BlockData->Name == NULL) && ((BlockData->Offset + BlockData-
Width) > VarStorageData->Size)) {
Status = EFI_INVALID_PARAMETER;
- if (BlockData->Name != NULL) {
- FreePool (BlockData->Name);
- }
FreePool (BlockData);
goto Done;
}
--
2.20.1.windows.1


Re: [edk2-platforms: PATCH V9] Platform/Intel: Correct CPU APIC IDs

Ni, Ray
 

+ //
+ // 5. Re-assigen AcpiProcessorId for AcpiProcessorUId uses purpose.
+ //
+ for (Socket = 0; Socket < MAX_SOCKET; Socket++) {
1. Or if you add a "Index = 0" to reset Index for each Socket, that also work.

+ for (CurrProcessor = 0, Index = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) {
+ if (mCpuApicIdOrderTable[CurrProcessor].Flags && (mCpuApicIdOrderTable[CurrProcessor].SocketNum == Socket)) {
+ mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId = (ProcessorInfoBuffer.Location.Package << mNumOfBitShift) +
Index;
+ Index++;
}
}
+ }
1. I think you need to change above code to as below?
UINTN IndexInSocket[MAX_SOCKET];

ZeroMem (IndexInSocket, sizeof (IndexInSocket));

for (Socket = 0; Socket < MAX_SOCKET; Socket++) {
2. My code is wrong. The for-loop above is not needed. I think you can simply make sure resetting "Index" to 0 for each socket in your original logic.

for (CurrProcessor = 0, Index = 0; CurrProcessor < mNumberOfCpus; CurrProcessor++) {
if (mCpuApicIdOrderTable[CurrProcessor].Flags && (mCpuApicIdOrderTable[CurrProcessor].SocketNum == Socket)) {
mCpuApicIdOrderTable[CurrProcessor].AcpiProcessorId = (ProcessorInfoBuffer.Location.Package << mNumOfBitShift) +
IndexInSocket[Socket];
IndexInSocket[Socket]++;
}
}

2. Can you separate the code refinement change (looks like most of the changes below) in a separate patch?
(No more comments)
Sending multiple patches together basically consists of several steps:
a. make changes and commit first patch that fix the bug
b. make changes and commit second patch that refines the existing code.
(The 2nd change should not impact any behavior.)
c. "git format-patch -3" to generate three patch files.
d. use text editor to edit the number #0 patch file (cover letter) to describe briefly of the two patches
e. "git send-email *.patch"




- //keep for debug purpose
- DEBUG ((EFI_D_ERROR, "APIC ID Order Table ReOrdered\n"));
- DebugDisplayReOrderTable();
+ //keep for debug purpose
+ DEBUG ((DEBUG_INFO, "APIC ID Order Table ReOrdered\n"));
+ DebugDisplayReOrderTable (mCpuApicIdOrderTable);

- mCpuOrderSorted = TRUE;
- }
+ mCpuOrderSorted = TRUE;

return Status;
}
@@ -602,11 +493,11 @@ InitializeMadtHeader (
}

Status = InitializeHeader (
- &MadtHeader->Header,
- EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
- 0
- );
+ &MadtHeader->Header,
+ EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+ 0
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -784,11 +675,11 @@ BuildAcpiTable (
// Allocate the memory needed for the table.
//
Status = AllocateTable (
- TableSpecificHdrLength,
- Structures,
- StructureCount,
- &InternalTable
- );
+ TableSpecificHdrLength,
+ Structures,
+ StructureCount,
+ &InternalTable
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -871,18 +762,22 @@ InstallMadtFromScratch (
NewMadtTable = NULL;
MaxMadtStructCount = 0;

- DetectApicIdMap();
+ mCpuApicIdOrderTable = AllocateZeroPool (mNumberOfCpus * sizeof (EFI_CPU_ID_ORDER_MAP));
+ if (mCpuApicIdOrderTable == NULL) {
+ DEBUG ((DEBUG_ERROR, "Could not allocate mCpuApicIdOrderTable structure pointer array\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }

// Call for Local APIC ID Reorder
Status = SortCpuLocalApicInTable ();
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "SortCpuLocalApicInTable failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "SortCpuLocalApicInTable failed: %r\n", Status));
goto Done;
}

MaxMadtStructCount = (UINT32) (
- MAX_CPU_NUM + // processor local APIC structures
- MAX_CPU_NUM + // processor local x2APIC structures
+ mNumberOfCpus + // processor local APIC structures
+ mNumberOfCpus + // processor local x2APIC structures
1 + PcdGet8(PcdPcIoApicCount) + // I/O APIC structures
2 + // interrupt source override structures
1 + // local APIC NMI structures
@@ -906,11 +801,11 @@ InstallMadtFromScratch (
//
Status = InitializeMadtHeader (&MadtTableHeader);
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "InitializeMadtHeader failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "InitializeMadtHeader failed: %r\n", Status));
goto Done;
}

- DEBUG ((EFI_D_INFO, "Number of CPUs detected = %d \n", mNumberOfCPUs));
+ DEBUG ((DEBUG_INFO, "Number of CPUs detected = %d \n", mNumberOfCpus));

//
// Build Processor Local APIC Structures and Processor Local X2APIC Structures
@@ -923,7 +818,7 @@ InstallMadtFromScratch (
ProcLocalX2ApicStruct.Reserved[0] = 0;
ProcLocalX2ApicStruct.Reserved[1] = 0;

- for (Index = 0; Index < MAX_CPU_NUM; Index++) {
+ for (Index = 0; Index < mNumberOfCpus; Index++) {
//
// If x2APIC mode is not enabled, and if it is possible to express the
// APIC ID as a UINT8, use a processor local APIC structure. Otherwise,
@@ -936,10 +831,10 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &ProcLocalApicStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &ProcLocalApicStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
} else if (mCpuApicIdOrderTable[Index].ApicId != 0xFFFFFFFF) {
ProcLocalX2ApicStruct.Flags = (UINT8) mCpuApicIdOrderTable[Index].Flags;
ProcLocalX2ApicStruct.X2ApicId = mCpuApicIdOrderTable[Index].ApicId;
@@ -947,13 +842,13 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &ProcLocalX2ApicStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &ProcLocalX2ApicStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
}
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (local APIC/x2APIC) failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (local APIC/x2APIC) failed: %r\n", Status));
goto Done;
}
}
@@ -965,44 +860,44 @@ InstallMadtFromScratch (
IoApicStruct.Length = sizeof (EFI_ACPI_4_0_IO_APIC_STRUCTURE);
IoApicStruct.Reserved = 0;

- PcIoApicEnable = PcdGet32(PcdPcIoApicEnable);
+ PcIoApicEnable = PcdGet32 (PcdPcIoApicEnable);

- if (FixedPcdGet32(PcdMaxCpuSocketCount) <= 4) {
+ if (FixedPcdGet32 (PcdMaxCpuSocketCount) <= 4) {
IoApicStruct.IoApicId = PcdGet8(PcdIoApicId);
IoApicStruct.IoApicAddress = PcdGet32(PcdIoApicAddress);
IoApicStruct.GlobalSystemInterruptBase = 0;
ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &IoApicStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &IoApicStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", Status));
goto Done;
}
}

for (PcIoApicIndex = 0; PcIoApicIndex < PcdGet8(PcdPcIoApicCount); PcIoApicIndex++) {
- PcIoApicMask = (1 << PcIoApicIndex);
- if ((PcIoApicEnable & PcIoApicMask) == 0) {
- continue;
- }
+ PcIoApicMask = (1 << PcIoApicIndex);
+ if ((PcIoApicEnable & PcIoApicMask) == 0) {
+ continue;
+ }

- IoApicStruct.IoApicId = (UINT8)(PcdGet8(PcdPcIoApicIdBase) + PcIoApicIndex);
- IoApicStruct.IoApicAddress = CurrentIoApicAddress;
- CurrentIoApicAddress = (CurrentIoApicAddress & 0xFFFF8000) + 0x8000;
- IoApicStruct.GlobalSystemInterruptBase = (UINT32)(24 + (PcIoApicIndex * 8));
- ASSERT (MadtStructsIndex < MaxMadtStructCount);
- Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &IoApicStruct,
- &MadtStructs[MadtStructsIndex++]
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", Status));
- goto Done;
- }
+ IoApicStruct.IoApicId = (UINT8)(PcdGet8(PcdPcIoApicIdBase) + PcIoApicIndex);
+ IoApicStruct.IoApicAddress = CurrentIoApicAddress;
+ CurrentIoApicAddress = (CurrentIoApicAddress & 0xFFFF8000) + 0x8000;
+ IoApicStruct.GlobalSystemInterruptBase = (UINT32)(24 + (PcIoApicIndex * 8));
+ ASSERT (MadtStructsIndex < MaxMadtStructCount);
+ Status = CopyStructure (
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &IoApicStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (I/O APIC) failed: %r\n", Status));
+ goto Done;
+ }
}

//
@@ -1021,12 +916,12 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &IntSrcOverrideStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &IntSrcOverrideStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (IRQ2 source override) failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (IRQ2 source override) failed: %r\n", Status));
goto Done;
}

@@ -1040,12 +935,12 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &IntSrcOverrideStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &IntSrcOverrideStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (IRQ9 source override) failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (IRQ9 source override) failed: %r\n", Status));
goto Done;
}

@@ -1060,12 +955,12 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &LocalApciNmiStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &LocalApciNmiStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "CopyMadtStructure (APIC NMI) failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "CopyMadtStructure (APIC NMI) failed: %r\n", Status));
goto Done;
}

@@ -1084,10 +979,10 @@ InstallMadtFromScratch (

ASSERT (MadtStructsIndex < MaxMadtStructCount);
Status = CopyStructure (
- &MadtTableHeader.Header,
- (STRUCTURE_HEADER *) &LocalX2ApicNmiStruct,
- &MadtStructs[MadtStructsIndex++]
- );
+ &MadtTableHeader.Header,
+ (STRUCTURE_HEADER *) &LocalX2ApicNmiStruct,
+ &MadtStructs[MadtStructsIndex++]
+ );
if (EFI_ERROR (Status)) {
DEBUG ((DEBUG_ERROR, "CopyMadtStructure (x2APIC NMI) failed: %r\n", Status));
goto Done;
@@ -1098,14 +993,14 @@ InstallMadtFromScratch (
// Build Madt Structure from the Madt Header and collection of pointers in MadtStructs[]
//
Status = BuildAcpiTable (
- (EFI_ACPI_DESCRIPTION_HEADER *) &MadtTableHeader,
- sizeof (EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER),
- MadtStructs,
- MadtStructsIndex,
- (UINT8 **)&NewMadtTable
- );
+ (EFI_ACPI_DESCRIPTION_HEADER *) &MadtTableHeader,
+ sizeof (EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER),
+ MadtStructs,
+ MadtStructsIndex,
+ (UINT8 **) &NewMadtTable
+ );
if (EFI_ERROR (Status)) {
- DEBUG ((EFI_D_ERROR, "BuildAcpiTable failed: %r\n", Status));
+ DEBUG ((DEBUG_ERROR, "BuildAcpiTable failed: %r\n", Status));
goto Done;
}

@@ -1113,11 +1008,11 @@ InstallMadtFromScratch (
// Publish Madt Structure to ACPI
//
Status = mAcpiTable->InstallAcpiTable (
- mAcpiTable,
- NewMadtTable,
- NewMadtTable->Header.Length,
- &TableHandle
- );
+ mAcpiTable,
+ NewMadtTable,
+ NewMadtTable->Header.Length,
+ &TableHandle
+ );

Done:
//
@@ -1136,6 +1031,10 @@ Done:
FreePool (NewMadtTable);
}

+ if (mCpuApicIdOrderTable != NULL) {
+ FreePool (mCpuApicIdOrderTable);
+ }
+
return Status;
}

@@ -1155,8 +1054,8 @@ InstallMcfgFromScratch (
PciSegmentInfo = GetPciSegmentInfo (&SegmentCount);

McfgTable = AllocateZeroPool (
- sizeof(EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER) +
-
sizeof(EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE) *
SegmentCount
+ sizeof (EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_HEADER) +
+ sizeof
(EFI_ACPI_MEMORY_MAPPED_ENHANCED_CONFIGURATION_SPACE_BASE_ADDRESS_ALLOCATION_STRUCTURE) *
SegmentCount
);
if (McfgTable == NULL) {
DEBUG ((DEBUG_ERROR, "Could not allocate MCFG structure\n"));
@@ -1164,11 +1063,11 @@ InstallMcfgFromScratch (
}

Status = InitializeHeader (
- &McfgTable->Header,
-
EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
- 0
- );
+ &McfgTable->Header,
+
EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
+ 0
+ );
if (EFI_ERROR (Status)) {
return Status;
}
@@ -1192,11 +1091,11 @@ InstallMcfgFromScratch (
// Publish Madt Structure to ACPI
//
Status = mAcpiTable->InstallAcpiTable (
- mAcpiTable,
- McfgTable,
- McfgTable->Header.Length,
- &TableHandle
- );
+ mAcpiTable,
+ McfgTable,
+ McfgTable->Header.Length,
+ &TableHandle
+ );

return Status;
}
@@ -1280,7 +1179,7 @@ PlatformUpdateTables (
switch (Table->Signature) {

case EFI_ACPI_4_0_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE:
- ASSERT(FALSE);
+ ASSERT (FALSE);
break;

case EFI_ACPI_5_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE:
@@ -1324,9 +1223,9 @@ PlatformUpdateTables (
FadtHeader->XGpe1Blk.AccessSize = 0;
}

- DEBUG(( EFI_D_ERROR, "ACPI FADT table @ address 0x%x\n", Table ));
- DEBUG(( EFI_D_ERROR, " IaPcBootArch 0x%x\n", FadtHeader->IaPcBootArch ));
- DEBUG(( EFI_D_ERROR, " Flags 0x%x\n", FadtHeader->Flags ));
+ DEBUG ((DEBUG_INFO, "ACPI FADT table @ address 0x%x\n", Table));
+ DEBUG ((DEBUG_INFO, " IaPcBootArch 0x%x\n", FadtHeader->IaPcBootArch));
+ DEBUG ((DEBUG_INFO, " Flags 0x%x\n", FadtHeader->Flags));
break;

case EFI_ACPI_3_0_HIGH_PRECISION_EVENT_TIMER_TABLE_SIGNATURE:
@@ -1346,12 +1245,12 @@ PlatformUpdateTables (
HpetBlockId.Bits.VendorId = HpetCapabilities.Bits.VendorId;
HpetTable->EventTimerBlockId = HpetBlockId.Uint32;
HpetTable->MainCounterMinimumClockTickInPeriodicMode = (UINT16)HpetCapabilities.Bits.CounterClockPeriod;
- DEBUG(( EFI_D_ERROR, "ACPI HPET table @ address 0x%x\n", Table ));
- DEBUG(( EFI_D_ERROR, " HPET base 0x%x\n", PcdGet32 (PcdHpetBaseAddress) ));
+ DEBUG ((DEBUG_INFO, "ACPI HPET table @ address 0x%x\n", Table));
+ DEBUG ((DEBUG_INFO, " HPET base 0x%x\n", PcdGet32 (PcdHpetBaseAddress)));
break;

case
EFI_ACPI_3_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE:
- ASSERT(FALSE);
+ ASSERT (FALSE);
break;

default:
@@ -1403,8 +1302,8 @@ IsHardwareChange (
// pFADT->XDsdt
//
HWChangeSize = HandleCount + 1;
- HWChange = AllocateZeroPool( sizeof(UINT32) * HWChangeSize );
- ASSERT( HWChange != NULL );
+ HWChange = AllocateZeroPool (sizeof(UINT32) * HWChangeSize);
+ ASSERT(HWChange != NULL);

if (HWChange == NULL) return;

@@ -1445,14 +1344,14 @@ IsHardwareChange (
// Calculate CRC value with HWChange data.
//
Status = gBS->CalculateCrc32(HWChange, HWChangeSize, &CRC);
- DEBUG((DEBUG_INFO, "CRC = %x and Status = %r\n", CRC, Status));
+ DEBUG ((DEBUG_INFO, "CRC = %x and Status = %r\n", CRC, Status));

//
// Set HardwareSignature value based on CRC value.
//
FacsPtr = (EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)(UINTN)pFADT->FirmwareCtrl;
FacsPtr->HardwareSignature = CRC;
- FreePool( HWChange );
+ FreePool (HWChange);
}

VOID
@@ -1475,17 +1374,16 @@ UpdateLocalTable (

if (Version != EFI_ACPI_TABLE_VERSION_NONE) {
Status = mAcpiTable->InstallAcpiTable (
- mAcpiTable,
- CurrentTable,
- CurrentTable->Length,
- &TableHandle
- );
+ mAcpiTable,
+ CurrentTable,
+ CurrentTable->Length,
+ &TableHandle
+ );
ASSERT_EFI_ERROR (Status);
}
}
}

-
VOID
EFIAPI
AcpiEndOfDxeEvent (
@@ -1493,16 +1391,14 @@ AcpiEndOfDxeEvent (
VOID *ParentImageHandle
)
{
-
if (Event != NULL) {
- gBS->CloseEvent(Event);
+ gBS->CloseEvent (Event);
}

-
//
// Calculate Hardware Signature value based on current platform configurations
//
- IsHardwareChange();
+ IsHardwareChange ();
}

/**
@@ -1526,7 +1422,6 @@ InstallAcpiPlatform (
EFI_STATUS Status;
EFI_EVENT EndOfDxeEvent;

-
Status = gBS->LocateProtocol (&gEfiMpServiceProtocolGuid, NULL, (VOID **)&mMpService);
ASSERT_EFI_ERROR (Status);

@@ -1550,19 +1445,19 @@ InstallAcpiPlatform (
// Determine the number of processors
//
mMpService->GetNumberOfProcessors (
- mMpService,
- &mNumberOfCPUs,
- &mNumberOfEnabledCPUs
- );
- ASSERT (mNumberOfCPUs <= MAX_CPU_NUM && mNumberOfEnabledCPUs >= 1);
- DEBUG ((DEBUG_INFO, "mNumberOfCPUs - %d\n", mNumberOfCPUs));
+ mMpService,
+ &mNumberOfCpus,
+ &mNumberOfEnabledCPUs
+ );
+
+ DEBUG ((DEBUG_INFO, "mNumberOfCpus - %d\n", mNumberOfCpus));
DEBUG ((DEBUG_INFO, "mNumberOfEnabledCPUs - %d\n", mNumberOfEnabledCPUs));

DEBUG ((DEBUG_INFO, "mX2ApicEnabled - 0x%x\n", mX2ApicEnabled));
DEBUG ((DEBUG_INFO, "mForceX2ApicId - 0x%x\n", mForceX2ApicId));

// support up to 64 threads/socket
- AsmCpuidEx(CPUID_EXTENDED_TOPOLOGY, 1, &mNumOfBitShift, NULL, NULL, NULL);
+ AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 1, &mNumOfBitShift, NULL, NULL, NULL);
mNumOfBitShift &= 0x1F;
DEBUG ((DEBUG_INFO, "mNumOfBitShift - 0x%x\n", mNumOfBitShift));

diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
index bd11f9e988..61f7470f80 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.h
@@ -1,7 +1,7 @@
/** @file
This is an implementation of the ACPI platform driver.

-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent

**/
@@ -35,6 +35,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/MemoryAllocationLib.h>
#include <Library/AslUpdateLib.h>
#include <Library/PciSegmentInfoLib.h>
+#include <Library/SortLib.h>
+#include <Library/LocalApicLib.h>

#include <Protocol/AcpiTable.h>
#include <Protocol/MpService.h>
diff --git a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
index 5d9c8cab50..95f6656af0 100644
--- a/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
+++ b/Platform/Intel/MinPlatformPkg/Acpi/AcpiTables/AcpiPlatform.inf
@@ -1,7 +1,7 @@
### @file
# Component information file for AcpiPlatform module
#
-# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -43,6 +43,8 @@
PciSegmentInfoLib
AslUpdateLib
BoardAcpiTableLib
+ SortLib
+ LocalApicLib

[Pcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId
--
2.32.0.windows.2


Re: [edk2-platforms][PATCH v2 2/2] BoardModulePkg/BoardBdsHookLib: Simplify hotkey registration

Nate DeSimone
 

Yes agreed, making this more consistent would be a good improvement and one that I would support. There is always the perennial issue of finding the time to make those improvements and balancing that with everything else that needs to get done 😊.

 

From: Benjamin Doron <benjamin.doron00@...>
Sent: Thursday, August 26, 2021 4:50 PM
To: Desimone, Nathaniel L <nathaniel.l.desimone@...>
Cc: devel@edk2.groups.io; Dong, Eric <eric.dong@...>; Liming Gao <gaoliming@...>
Subject: Re: [edk2-platforms][PATCH v2 2/2] BoardModulePkg/BoardBdsHookLib: Simplify hotkey registration

 

Hi Nate,

That makes sense. I had been concerned that UiApp might be used in some places, but I didn't expect significant disparity between the boards (and I didn't check all of them, my mistake).

 

Maybe trying to align them on some differences, someday, might be a good idea? But not for now, in any case.

 

On Thu., Aug. 26, 2021, 7:41 p.m. Desimone, Nathaniel L, <nathaniel.l.desimone@...> wrote:

Hi Benjamin,

In principle this is a good idea, unfortunately some platforms have been coded to do stuff like this:
https://github.com/tianocore/edk2-platforms/blob/784f7739f5afd268042d4d9e8ef570131620c82c/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc#L323

And this:
https://github.com/tianocore/edk2-platforms/blob/784f7739f5afd268042d4d9e8ef570131620c82c/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc#L210

So the only way we can maintain a consistent user experience is to explicitly call out the GUID for the boot device selection menu. For now, I'll just push the first patch in this series.

Thanks,
Nate

-----Original Message-----
From: Benjamin Doron <benjamin.doron00@...>
Sent: Friday, August 13, 2021 5:43 PM
To: devel@edk2.groups.io
Cc: Dong, Eric <eric.dong@...>; Liming Gao <gaoliming@...>; Desimone, Nathaniel L <nathaniel.l.desimone@...>
Subject: [edk2-platforms][PATCH v2 2/2] BoardModulePkg/BoardBdsHookLib: Simplify hotkey registration

Retrieve BootOption of BootManagerMenu for registering F7 hotkey, rather than creating an additional boot option.

Tested, both F7 hotkey still opens the list of boot options.

Cc: Eric Dong <eric.dong@...>
Cc: Liming Gao <gaoliming@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Signed-off-by: Benjamin Doron <benjamin.doron00@...>
---
Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c | 19 ++++---------------
 1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
index e734e3ad15c3..7ac6c150f2e7 100644
--- a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
+++ b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
@@ -14,7 +14,6 @@ BOOLEAN    mPxeBoot       = FALSE;
 BOOLEAN    mHotKeypressed = FALSE;
 EFI_EVENT  HotKeyEvent    = NULL;

-UINTN      mBootMenuOptionNumber;
 UINTN      mSetupOptionNumber;


@@ -189,9 +188,6 @@ CreateFvBootOption (
 EFI_GUID mUiFile = {
   0x462CAA21, 0x7614, 0x4503, { 0x83, 0x6E, 0x8A, 0xB6, 0xF4, 0x66, 0x23, 0x31 }
 };
-EFI_GUID mBootMenuFile = {
-  0xEEC25BDC, 0x67F2, 0x4D95, { 0xB1, 0xD5, 0xF8, 0x1B, 0x20, 0x39, 0xD1, 0x1D }
-};


 /**
@@ -354,15 +350,6 @@ RegisterDefaultBootOption (
     ShellDataSize = 0;
     RegisterFvBootOption (&gUefiShellFileGuid,      INTERNAL_UEFI_SHELL_NAME, (UINTN) -1, LOAD_OPTION_ACTIVE, (UINT8 *)ShellData, ShellDataSize);

-  //
-  // Boot Menu
-  //
-  mBootMenuOptionNumber = RegisterFvBootOption (&mBootMenuFile, L"Boot Device List",   (UINTN) -1, LOAD_OPTION_CATEGORY_APP | LOAD_OPTION_ACTIVE | LOAD_OPTION_HIDDEN, NULL, 0);
-
-  if (mBootMenuOptionNumber == LoadOptionNumberUnassigned) {
-    DEBUG ((DEBUG_INFO, "BootMenuOptionNumber (%d) should not be same to LoadOptionNumberUnassigned(%d).\n", mBootMenuOptionNumber, LoadOptionNumberUnassigned));
-  }
-
   //
   // Boot Manager Menu
   //
@@ -468,8 +455,10 @@ RegisterStaticHotkey (
   F7.KeyState.KeyShiftState = EFI_SHIFT_STATE_VALID;
   F7.KeyState.KeyToggleState = 0;
   mBootMenuBoot  = !EnterSetup;
-  RegisterBootOptionHotkey ((UINT16) mBootMenuOptionNumber, &F7.Key, mBootMenuBoot);
-
+  Status = EfiBootManagerGetBootManagerMenu (&BootOption);
+  ASSERT_EFI_ERROR (Status);
+  RegisterBootOptionHotkey ((UINT16) BootOption.OptionNumber, &F7.Key, mBootMenuBoot);
+  EfiBootManagerFreeLoadOption (&BootOption);
 }


--
2.31.1


Re: [edk2-platforms][PATCH v2 1/2] BoardModulePkg/BoardBdsHookLib: Register UiApp as boot option

Nate DeSimone
 

-----Original Message-----
From: Benjamin Doron <benjamin.doron00@...>
Sent: Friday, August 13, 2021 5:43 PM
To: devel@edk2.groups.io
Cc: Dong, Eric <eric.dong@...>; Liming Gao <gaoliming@...>; Desimone, Nathaniel L <nathaniel.l.desimone@...>
Subject: [edk2-platforms][PATCH v2 1/2] BoardModulePkg/BoardBdsHookLib: Register UiApp as boot option

BootManagerMenuApp is the default PcdBootManagerMenuFile. It allows choosing a boot device, but system configuration is performed in UiApp.
Therefore, un-comment and fix UiApp boot option registration.

The F2 hotkey can be used to enter UiApp.

Cc: Eric Dong <eric.dong@...>
Cc: Liming Gao <gaoliming@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Signed-off-by: Benjamin Doron <benjamin.doron00@...>
---
Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c | 2 +- Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c | 29 +++++++-------------
2 files changed, 11 insertions(+), 20 deletions(-)

diff --git a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c
index a37139a0074e..0bcee7c9a4ba 100644
--- a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c
+++ b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHook
+++ Lib.c
@@ -1385,7 +1385,7 @@ BdsAfterConsoleReadyBeforeBootOptionCallback (
break; } - Print (L"Press F7 for BootMenu!\n");+ Print (L"Press F2 for Setup, or F7 for BootMenu!\n"); }diff --git a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
index 87138bdd79ff..e734e3ad15c3 100644
--- a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
+++ b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOpt
+++ ion.c
@@ -15,6 +15,7 @@ BOOLEAN mHotKeypressed = FALSE;
EFI_EVENT HotKeyEvent = NULL; UINTN mBootMenuOptionNumber;+UINTN mSetupOptionNumber; /**@@ -361,20 +362,11 @@ RegisterDefaultBootOption (
if (mBootMenuOptionNumber == LoadOptionNumberUnassigned) { DEBUG ((DEBUG_INFO, "BootMenuOptionNumber (%d) should not be same to LoadOptionNumberUnassigned(%d).\n", mBootMenuOptionNumber, LoadOptionNumberUnassigned)); }-#if 0+ // // Boot Manager Menu //- EfiInitializeFwVolDevicepathNode (&FileNode, &mUiFile);-- gBS->HandleProtocol (- gImageHandle,- &gEfiLoadedImageProtocolGuid,- (VOID **) &LoadedImage- );- DevicePath = AppendDevicePathNode (DevicePathFromHandle (LoadedImage->DeviceHandle), (EFI_DEVICE_PATH_PROTOCOL *) &FileNode);-#endif-+ mSetupOptionNumber = RegisterFvBootOption (&mUiFile, L"Enter Setup", (UINTN) -1, LOAD_OPTION_CATEGORY_APP | LOAD_OPTION_ACTIVE | LOAD_OPTION_HIDDEN, NULL, 0); } /**@@ -463,14 +455,13 @@ RegisterStaticHotkey (
// // [F2]/[F7] //- F2.Key.ScanCode = SCAN_F2;- F2.Key.UnicodeChar = CHAR_NULL;- F2.KeyState.KeyShiftState = EFI_SHIFT_STATE_VALID;- F2.KeyState.KeyToggleState = 0;- Status = EfiBootManagerGetBootManagerMenu (&BootOption);- ASSERT_EFI_ERROR (Status);- RegisterBootOptionHotkey ((UINT16) BootOption.OptionNumber, &F2.Key, TRUE);- EfiBootManagerFreeLoadOption (&BootOption);+ if (mSetupOptionNumber) {+ F2.Key.ScanCode = SCAN_F2;+ F2.Key.UnicodeChar = CHAR_NULL;+ F2.KeyState.KeyShiftState = EFI_SHIFT_STATE_VALID;+ F2.KeyState.KeyToggleState = 0;+ RegisterBootOptionHotkey ((UINT16) mSetupOptionNumber, &F2.Key, TRUE);+ } F7.Key.ScanCode = SCAN_F7; F7.Key.UnicodeChar = CHAR_NULL;--
2.31.1


Re: [edk2-platforms][PATCH v2 2/2] BoardModulePkg/BoardBdsHookLib: Simplify hotkey registration

Benjamin Doron
 

Hi Nate,
That makes sense. I had been concerned that UiApp might be used in some places, but I didn't expect significant disparity between the boards (and I didn't check all of them, my mistake).

Maybe trying to align them on some differences, someday, might be a good idea? But not for now, in any case.


On Thu., Aug. 26, 2021, 7:41 p.m. Desimone, Nathaniel L, <nathaniel.l.desimone@...> wrote:
Hi Benjamin,

In principle this is a good idea, unfortunately some platforms have been coded to do stuff like this:
https://github.com/tianocore/edk2-platforms/blob/784f7739f5afd268042d4d9e8ef570131620c82c/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc#L323

And this:
https://github.com/tianocore/edk2-platforms/blob/784f7739f5afd268042d4d9e8ef570131620c82c/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc#L210

So the only way we can maintain a consistent user experience is to explicitly call out the GUID for the boot device selection menu. For now, I'll just push the first patch in this series.

Thanks,
Nate

-----Original Message-----
From: Benjamin Doron <benjamin.doron00@...>
Sent: Friday, August 13, 2021 5:43 PM
To: devel@edk2.groups.io
Cc: Dong, Eric <eric.dong@...>; Liming Gao <gaoliming@...>; Desimone, Nathaniel L <nathaniel.l.desimone@...>
Subject: [edk2-platforms][PATCH v2 2/2] BoardModulePkg/BoardBdsHookLib: Simplify hotkey registration

Retrieve BootOption of BootManagerMenu for registering F7 hotkey, rather than creating an additional boot option.

Tested, both F7 hotkey still opens the list of boot options.

Cc: Eric Dong <eric.dong@...>
Cc: Liming Gao <gaoliming@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Signed-off-by: Benjamin Doron <benjamin.doron00@...>
---
Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c | 19 ++++---------------
 1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
index e734e3ad15c3..7ac6c150f2e7 100644
--- a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
+++ b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
@@ -14,7 +14,6 @@ BOOLEAN    mPxeBoot       = FALSE;
 BOOLEAN    mHotKeypressed = FALSE;
 EFI_EVENT  HotKeyEvent    = NULL;

-UINTN      mBootMenuOptionNumber;
 UINTN      mSetupOptionNumber;


@@ -189,9 +188,6 @@ CreateFvBootOption (
 EFI_GUID mUiFile = {
   0x462CAA21, 0x7614, 0x4503, { 0x83, 0x6E, 0x8A, 0xB6, 0xF4, 0x66, 0x23, 0x31 }
 };
-EFI_GUID mBootMenuFile = {
-  0xEEC25BDC, 0x67F2, 0x4D95, { 0xB1, 0xD5, 0xF8, 0x1B, 0x20, 0x39, 0xD1, 0x1D }
-};


 /**
@@ -354,15 +350,6 @@ RegisterDefaultBootOption (
     ShellDataSize = 0;
     RegisterFvBootOption (&gUefiShellFileGuid,      INTERNAL_UEFI_SHELL_NAME, (UINTN) -1, LOAD_OPTION_ACTIVE, (UINT8 *)ShellData, ShellDataSize);

-  //
-  // Boot Menu
-  //
-  mBootMenuOptionNumber = RegisterFvBootOption (&mBootMenuFile, L"Boot Device List",   (UINTN) -1, LOAD_OPTION_CATEGORY_APP | LOAD_OPTION_ACTIVE | LOAD_OPTION_HIDDEN, NULL, 0);
-
-  if (mBootMenuOptionNumber == LoadOptionNumberUnassigned) {
-    DEBUG ((DEBUG_INFO, "BootMenuOptionNumber (%d) should not be same to LoadOptionNumberUnassigned(%d).\n", mBootMenuOptionNumber, LoadOptionNumberUnassigned));
-  }
-
   //
   // Boot Manager Menu
   //
@@ -468,8 +455,10 @@ RegisterStaticHotkey (
   F7.KeyState.KeyShiftState = EFI_SHIFT_STATE_VALID;
   F7.KeyState.KeyToggleState = 0;
   mBootMenuBoot  = !EnterSetup;
-  RegisterBootOptionHotkey ((UINT16) mBootMenuOptionNumber, &F7.Key, mBootMenuBoot);
-
+  Status = EfiBootManagerGetBootManagerMenu (&BootOption);
+  ASSERT_EFI_ERROR (Status);
+  RegisterBootOptionHotkey ((UINT16) BootOption.OptionNumber, &F7.Key, mBootMenuBoot);
+  EfiBootManagerFreeLoadOption (&BootOption);
 }


--
2.31.1


Re: [edk2-platforms][PATCH v2 2/2] BoardModulePkg/BoardBdsHookLib: Simplify hotkey registration

Nate DeSimone
 

Hi Benjamin,

In principle this is a good idea, unfortunately some platforms have been coded to do stuff like this:
https://github.com/tianocore/edk2-platforms/blob/784f7739f5afd268042d4d9e8ef570131620c82c/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dsc#L323

And this:
https://github.com/tianocore/edk2-platforms/blob/784f7739f5afd268042d4d9e8ef570131620c82c/Platform/Intel/SimicsOpenBoardPkg/BoardX58Ich10/OpenBoardPkgPcd.dsc#L210

So the only way we can maintain a consistent user experience is to explicitly call out the GUID for the boot device selection menu. For now, I'll just push the first patch in this series.

Thanks,
Nate

-----Original Message-----
From: Benjamin Doron <benjamin.doron00@...>
Sent: Friday, August 13, 2021 5:43 PM
To: devel@edk2.groups.io
Cc: Dong, Eric <eric.dong@...>; Liming Gao <gaoliming@...>; Desimone, Nathaniel L <nathaniel.l.desimone@...>
Subject: [edk2-platforms][PATCH v2 2/2] BoardModulePkg/BoardBdsHookLib: Simplify hotkey registration

Retrieve BootOption of BootManagerMenu for registering F7 hotkey, rather than creating an additional boot option.

Tested, both F7 hotkey still opens the list of boot options.

Cc: Eric Dong <eric.dong@...>
Cc: Liming Gao <gaoliming@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Signed-off-by: Benjamin Doron <benjamin.doron00@...>
---
Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c | 19 ++++---------------
1 file changed, 4 insertions(+), 15 deletions(-)

diff --git a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
index e734e3ad15c3..7ac6c150f2e7 100644
--- a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
+++ b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
@@ -14,7 +14,6 @@ BOOLEAN mPxeBoot = FALSE;
BOOLEAN mHotKeypressed = FALSE;
EFI_EVENT HotKeyEvent = NULL;

-UINTN mBootMenuOptionNumber;
UINTN mSetupOptionNumber;


@@ -189,9 +188,6 @@ CreateFvBootOption (
EFI_GUID mUiFile = {
0x462CAA21, 0x7614, 0x4503, { 0x83, 0x6E, 0x8A, 0xB6, 0xF4, 0x66, 0x23, 0x31 }
};
-EFI_GUID mBootMenuFile = {
- 0xEEC25BDC, 0x67F2, 0x4D95, { 0xB1, 0xD5, 0xF8, 0x1B, 0x20, 0x39, 0xD1, 0x1D }
-};


/**
@@ -354,15 +350,6 @@ RegisterDefaultBootOption (
ShellDataSize = 0;
RegisterFvBootOption (&gUefiShellFileGuid, INTERNAL_UEFI_SHELL_NAME, (UINTN) -1, LOAD_OPTION_ACTIVE, (UINT8 *)ShellData, ShellDataSize);

- //
- // Boot Menu
- //
- mBootMenuOptionNumber = RegisterFvBootOption (&mBootMenuFile, L"Boot Device List", (UINTN) -1, LOAD_OPTION_CATEGORY_APP | LOAD_OPTION_ACTIVE | LOAD_OPTION_HIDDEN, NULL, 0);
-
- if (mBootMenuOptionNumber == LoadOptionNumberUnassigned) {
- DEBUG ((DEBUG_INFO, "BootMenuOptionNumber (%d) should not be same to LoadOptionNumberUnassigned(%d).\n", mBootMenuOptionNumber, LoadOptionNumberUnassigned));
- }
-
//
// Boot Manager Menu
//
@@ -468,8 +455,10 @@ RegisterStaticHotkey (
F7.KeyState.KeyShiftState = EFI_SHIFT_STATE_VALID;
F7.KeyState.KeyToggleState = 0;
mBootMenuBoot = !EnterSetup;
- RegisterBootOptionHotkey ((UINT16) mBootMenuOptionNumber, &F7.Key, mBootMenuBoot);
-
+ Status = EfiBootManagerGetBootManagerMenu (&BootOption);
+ ASSERT_EFI_ERROR (Status);
+ RegisterBootOptionHotkey ((UINT16) BootOption.OptionNumber, &F7.Key, mBootMenuBoot);
+ EfiBootManagerFreeLoadOption (&BootOption);
}


--
2.31.1


Re: [edk2-platforms][PATCH v2 1/2] BoardModulePkg/BoardBdsHookLib: Register UiApp as boot option

Nate DeSimone
 

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...>

-----Original Message-----
From: Benjamin Doron <benjamin.doron00@...>
Sent: Friday, August 13, 2021 5:43 PM
To: devel@edk2.groups.io
Cc: Dong, Eric <eric.dong@...>; Liming Gao <gaoliming@...>; Desimone, Nathaniel L <nathaniel.l.desimone@...>
Subject: [edk2-platforms][PATCH v2 1/2] BoardModulePkg/BoardBdsHookLib: Register UiApp as boot option

BootManagerMenuApp is the default PcdBootManagerMenuFile. It allows choosing a boot device, but system configuration is performed in UiApp.
Therefore, un-comment and fix UiApp boot option registration.

The F2 hotkey can be used to enter UiApp.

Cc: Eric Dong <eric.dong@...>
Cc: Liming Gao <gaoliming@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Signed-off-by: Benjamin Doron <benjamin.doron00@...>
---
Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c | 2 +-
Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c | 29 +++++++-------------
2 files changed, 11 insertions(+), 20 deletions(-)

diff --git a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c
index a37139a0074e..0bcee7c9a4ba 100644
--- a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c
+++ b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c
@@ -1385,7 +1385,7 @@ BdsAfterConsoleReadyBeforeBootOptionCallback (
break;
}

- Print (L"Press F7 for BootMenu!\n");
+ Print (L"Press F2 for Setup, or F7 for BootMenu!\n");


}
diff --git a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
index 87138bdd79ff..e734e3ad15c3 100644
--- a/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
+++ b/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
@@ -15,6 +15,7 @@ BOOLEAN mHotKeypressed = FALSE;
EFI_EVENT HotKeyEvent = NULL;

UINTN mBootMenuOptionNumber;
+UINTN mSetupOptionNumber;


/**
@@ -361,20 +362,11 @@ RegisterDefaultBootOption (
if (mBootMenuOptionNumber == LoadOptionNumberUnassigned) {
DEBUG ((DEBUG_INFO, "BootMenuOptionNumber (%d) should not be same to LoadOptionNumberUnassigned(%d).\n", mBootMenuOptionNumber, LoadOptionNumberUnassigned));
}
-#if 0
+
//
// Boot Manager Menu
//
- EfiInitializeFwVolDevicepathNode (&FileNode, &mUiFile);
-
- gBS->HandleProtocol (
- gImageHandle,
- &gEfiLoadedImageProtocolGuid,
- (VOID **) &LoadedImage
- );
- DevicePath = AppendDevicePathNode (DevicePathFromHandle (LoadedImage->DeviceHandle), (EFI_DEVICE_PATH_PROTOCOL *) &FileNode);
-#endif
-
+ mSetupOptionNumber = RegisterFvBootOption (&mUiFile, L"Enter Setup", (UINTN) -1, LOAD_OPTION_CATEGORY_APP | LOAD_OPTION_ACTIVE | LOAD_OPTION_HIDDEN, NULL, 0);
}

/**
@@ -463,14 +455,13 @@ RegisterStaticHotkey (
//
// [F2]/[F7]
//
- F2.Key.ScanCode = SCAN_F2;
- F2.Key.UnicodeChar = CHAR_NULL;
- F2.KeyState.KeyShiftState = EFI_SHIFT_STATE_VALID;
- F2.KeyState.KeyToggleState = 0;
- Status = EfiBootManagerGetBootManagerMenu (&BootOption);
- ASSERT_EFI_ERROR (Status);
- RegisterBootOptionHotkey ((UINT16) BootOption.OptionNumber, &F2.Key, TRUE);
- EfiBootManagerFreeLoadOption (&BootOption);
+ if (mSetupOptionNumber) {
+ F2.Key.ScanCode = SCAN_F2;
+ F2.Key.UnicodeChar = CHAR_NULL;
+ F2.KeyState.KeyShiftState = EFI_SHIFT_STATE_VALID;
+ F2.KeyState.KeyToggleState = 0;
+ RegisterBootOptionHotkey ((UINT16) mSetupOptionNumber, &F2.Key, TRUE);
+ }

F7.Key.ScanCode = SCAN_F7;
F7.Key.UnicodeChar = CHAR_NULL;
--
2.31.1


Re: [edk2-platforms][PATCH V1 1/1] WhitleyOpenBoardPkg/Uba: Add WilsonCitySMT board support

Nate DeSimone
 

-----Original Message-----
From: Oram, Isaac W <isaac.w.oram@...>
Sent: Monday, August 16, 2021 12:52 PM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@...>; Chiu, Chasel <chasel.chiu@...>; KARPAGAVINAYAGAM, MANICKAVASAKAM <manickavasakamk@...>; Jha, Manish <manishj@...>
Subject: [edk2-devel][edk2-platforms][PATCH V1 1/1] WhitleyOpenBoardPkg/Uba: Add WilsonCitySMT board support

Add support for another commonly used Whitley reference platform
motherboard

Cc: Nate DeSimone <nathaniel.l.desimone@...>
Cc: Chasel Chiu <chasel.chiu@...>
Cc: Manickavasakam Karpagavinayagam <manickavasakamk@...>
Cc: Manish Jha <manishj@...>
Signed-off-by: Isaac Oram <isaac.w.oram@...>
---
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf | 7 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/IioBifurInit.c | 141 ---------
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/KtiEparam.c | 39 ---
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c | 99 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h | 118 +++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf | 48 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c | 115 +++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h | 57 ++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf | 48 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c | 127 ++++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h | 27 ++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf | 44 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/AcpiTablePcds.c | 51 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/GpioTable.c | 327 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/IioBifurInit.c | 249 +++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/KtiEparam.c | 79 +++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PcdData.c | 273 ++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PchEarlyUpdate.c | 103 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInit.h | 79 +++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInitLib.c | 123 ++++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInitLib.inf | 166 ++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/SlotTable.c | 171 ++++++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/SoftStrapFixup.c | 120 +++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/UsbOC.c | 126 ++++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc | 8 +
25 files changed, 2565 insertions(+), 180 deletions(-)

diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
index cb40d6da78..fcf147885f 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
@@ -20,3 +20,10 @@ INF $(RP_PKG)/Uba/UbaMain/TypeWilsonCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdate
INF $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
INF $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
INF $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
+
+#
+# Platform TypeWilsonCitySMT
+#
+INF $(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
+INF $(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
+INF $(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/IioBifurInit.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/IioBifurInit.c
index c9e1be13ec..dc8fe7cc63 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/IioBifurInit.c
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/IioBifurInit.c
@@ -148,135 +148,6 @@ static IIO_SLOT_CONFIG_DATA_ENTRY_EX IioSlotTable[] = {
PORT_5D_INDEX, 17 , DISABLE , 0 , 25 , ENABLE , VPP_PORT_1 , 0x4E , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x20 , 2 , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x74 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_1 , 0x42 , 0x1 }
};

-
-//
-// Tables below are generated by script. Please do not change it directly.
-//
-// config file: Wilson_City_PCIe_Slot_Config_1p71.xlsx
-// config sheet: WilsonCity_CPX
-// sheet notes: WilsonCity for CPX4 Rev0.5, 11/07/2019
-//
-static IIO_BIFURCATION_DATA_ENTRY_EX IioBifurcationTable_CPX[] =
-{
- { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
- { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
- { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
- { Iio_Socket0, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, 0 , 0x76, 0xE2 , 4 },
- { Iio_Socket0, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
-
- { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
- { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
- { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
- { Iio_Socket1, Iio_Iou3, IIO_BIFURCATE_x4x4x4x4, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
- { Iio_Socket1, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
-
- { Iio_Socket2, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, 0 , 0x7C, 0xE2 , 4 },
- { Iio_Socket2, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
- { Iio_Socket2, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
- { Iio_Socket2, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
- { Iio_Socket2, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
-
- { Iio_Socket3, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
- { Iio_Socket3, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, 0 , 0x70, 0xE2 , 4 },
- { Iio_Socket3, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
- { Iio_Socket3, Iio_Iou3, IIO_BIFURCATE_x4x4x4x4, 0 , 0x74, 0xE2 , 4 },
- { Iio_Socket3, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX }
-};
-
-static IIO_SLOT_CONFIG_DATA_ENTRY_EX IioSlotTable_CPX[] = {
- // Port Index | Slot |Inter |Power |Power |Hotplug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD |Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer |Retimer |Mux |Mux |ExtnCard|ExtnCard |ExtnCard |ExtnCard|Ex.C. Retimer|Ex.C. Ret- |ExtnCard|Ex.C. Hotplug|Ex.C. Hotplug|Max |
- // | |lock |Limit Scale |Limit Value |Cap | | |Cap |Port |Address | |Clock | |Port | |Address |Channel |Width |Address |Channel |Support |SMBus Port |SMBus Addr |Retimer |SMBus Address|-imer Width |Hotplug |Vpp Port |Vpp Address |Retimer|
- { SOCKET_0_INDEX + PORT_1A_INDEX, 7 , DISABLE, 0 , 75 , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_0_INDEX + PORT_1B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_0_INDEX + PORT_1C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_0_INDEX + PORT_1D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_0_INDEX + PORT_2A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_0_INDEX + PORT_2B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_0_INDEX + PORT_2C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_0_INDEX + PORT_2D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_0_INDEX + PORT_3A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_0_INDEX + PORT_3B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_0_INDEX + PORT_3C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_0_INDEX + PORT_3D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_0_INDEX + PORT_4A_INDEX, 2 , DISABLE, 0 , 200 , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x76 , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x40 , 0x1 },
- { SOCKET_0_INDEX + PORT_4B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x76 , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x40 , 0x1 },
- { SOCKET_0_INDEX + PORT_4C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x76 , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x42 , 0x1 },
- { SOCKET_0_INDEX + PORT_4D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x76 , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x42 , 0x1 },
- { SOCKET_0_INDEX + PORT_5A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_0_INDEX + PORT_5B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_0_INDEX + PORT_5C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_0_INDEX + PORT_5D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- // Port Index | Slot |Inter |Power |Power |Hotplug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD |Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer |Retimer |Mux |Mux |ExtnCard|ExtnCard |ExtnCard |ExtnCard|Ex.C. Retimer|Ex.C. Ret- |ExtnCard|Ex.C. Hotplug|Ex.C. Hotplug|Max |
- // | |lock |Limit Scale |Limit Value |Cap | | |Cap |Port |Address | |Clock | |Port | |Address |Channel |Width |Address |Channel |Support |SMBus Port |SMBus Addr |Retimer |SMBus Address|-imer Width |Hotplug |Vpp Port |Vpp Address |Retimer|
- { SOCKET_1_INDEX + PORT_1A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_1_INDEX + PORT_1B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_1_INDEX + PORT_1C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_1_INDEX + PORT_1D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_1_INDEX + PORT_2A_INDEX, 6 , DISABLE, 0 , 75 , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_1_INDEX + PORT_2B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_1_INDEX + PORT_2C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_1_INDEX + PORT_2D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_1_INDEX + PORT_3A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_1_INDEX + PORT_3B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_1_INDEX + PORT_3C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_1_INDEX + PORT_3D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_1_INDEX + PORT_4A_INDEX, 10 , DISABLE, 0 , 25 , ENABLE , VPP_PORT_0 , 0x4C , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x26 , 2 , 16 , 0xe2 , SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x1 },
- { SOCKET_1_INDEX + PORT_4B_INDEX, 11 , DISABLE, 0 , 25 , ENABLE , VPP_PORT_1 , 0x4C , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x26 , 2 , 16 , 0xe2 , SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x1 },
- { SOCKET_1_INDEX + PORT_4C_INDEX, 12 , DISABLE, 0 , 25 , ENABLE , VPP_PORT_0 , 0x4E , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x26 , 2 , 16 , 0xe2 , SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x1 },
- { SOCKET_1_INDEX + PORT_4D_INDEX, 13 , DISABLE, 0 , 25 , ENABLE , VPP_PORT_1 , 0x4E , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x26 , 2 , 16 , 0xe2 , SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x1 },
- { SOCKET_1_INDEX + PORT_5A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_1_INDEX + PORT_5B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_1_INDEX + PORT_5C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_1_INDEX + PORT_5D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- // Port Index | Slot |Inter |Power |Power |Hotplug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD |Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer |Retimer |Mux |Mux |ExtnCard|ExtnCard |ExtnCard |ExtnCard|Ex.C. Retimer|Ex.C. Ret- |ExtnCard|Ex.C. Hotplug|Ex.C. Hotplug|Max |
- // | |lock |Limit Scale |Limit Value |Cap | | |Cap |Port |Address | |Clock | |Port | |Address |Channel |Width |Address |Channel |Support |SMBus Port |SMBus Addr |Retimer |SMBus Address|-imer Width |Hotplug |Vpp Port |Vpp Address |Retimer|
- { SOCKET_2_INDEX + PORT_1A_INDEX, 9 , DISABLE, 0 , 25 , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x7C , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x44 , 0x1 },
- { SOCKET_2_INDEX + PORT_1B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x7C , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x44 , 0x1 },
- { SOCKET_2_INDEX + PORT_1C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x7C , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x46 , 0x1 },
- { SOCKET_2_INDEX + PORT_1D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x7C , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x46 , 0x1 },
- { SOCKET_2_INDEX + PORT_2A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_2_INDEX + PORT_2B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_2_INDEX + PORT_2C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_2_INDEX + PORT_2D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_2_INDEX + PORT_3A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_2_INDEX + PORT_3B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_2_INDEX + PORT_3C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_2_INDEX + PORT_3D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_2_INDEX + PORT_4A_INDEX, 8 , DISABLE, 0 , 25 , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_2_INDEX + PORT_4B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_2_INDEX + PORT_4C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_2_INDEX + PORT_4D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_2_INDEX + PORT_5A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_2_INDEX + PORT_5B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_2_INDEX + PORT_5C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_2_INDEX + PORT_5D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- // Port Index | Slot |Inter |Power |Power |Hotplug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD |Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer |Retimer |Mux |Mux |ExtnCard|ExtnCard |ExtnCard |ExtnCard|Ex.C. Retimer|Ex.C. Ret- |ExtnCard|Ex.C. Hotplug|Ex.C. Hotplug|Max |
- // | |lock |Limit Scale |Limit Value |Cap | | |Cap |Port |Address | |Clock | |Port | |Address |Channel |Width |Address |Channel |Support |SMBus Port |SMBus Addr |Retimer |SMBus Address|-imer Width |Hotplug |Vpp Port |Vpp Address |Retimer|
- { SOCKET_3_INDEX + PORT_1A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_3_INDEX + PORT_1B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_3_INDEX + PORT_1C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_3_INDEX + PORT_1D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_3_INDEX + PORT_2A_INDEX, 4 , DISABLE, 0 , 25 , ENABLE , VPP_PORT_0 , 0x4A , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x70 , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x40 , 0x1 },
- { SOCKET_3_INDEX + PORT_2B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, ENABLE , VPP_PORT_0 , 0x4A , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x70 , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x40 , 0x1 },
- { SOCKET_3_INDEX + PORT_2C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, ENABLE , VPP_PORT_0 , 0x4A , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x70 , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x42 , 0x1 },
- { SOCKET_3_INDEX + PORT_2D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, ENABLE , VPP_PORT_0 , 0x4A , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x70 , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x42 , 0x1 },
- { SOCKET_3_INDEX + PORT_3A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_3_INDEX + PORT_3B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_3_INDEX + PORT_3C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_3_INDEX + PORT_3D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_3_INDEX + PORT_4A_INDEX, 14 , DISABLE, 0 , 25 , ENABLE , VPP_PORT_0 , 0x4C , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x20 , 2 , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x74 , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x40 , 0x1 },
- { SOCKET_3_INDEX + PORT_4B_INDEX, 15 , DISABLE, 0 , 25 , ENABLE , VPP_PORT_1 , 0x4C , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x20 , 2 , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x74 , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x40 , 0x1 },
- { SOCKET_3_INDEX + PORT_4C_INDEX, 16 , DISABLE, 0 , 25 , ENABLE , VPP_PORT_0 , 0x4E , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x20 , 2 , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x74 , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_0 , 0x42 , 0x1 },
- { SOCKET_3_INDEX + PORT_4D_INDEX, 17 , DISABLE, 0 , 25 , ENABLE , VPP_PORT_1 , 0x4E , DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, ENABLE , 0x20 , 2 , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x74 , ENABLE , SMB_ADDR_MAX, NOT_EXIST , ENABLE , VPP_PORT_1 , 0x42 , 0x1 },
- { SOCKET_3_INDEX + PORT_5A_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_3_INDEX + PORT_5B_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_3_INDEX + PORT_5C_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 },
- { SOCKET_3_INDEX + PORT_5D_INDEX, NO_SLT_IMP, DISABLE, PWR_SCL_MAX, PWR_VAL_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, DISABLE, VPP_PORT_MAX, VPP_ADDR_MAX, NOT_HIDE, ENABLE , DISABLE, DISABLE, DISABLE, SMB_ADDR_MAX, SMB_DATA_MAX, NOT_EXIST, SMB_ADDR_MAX, SMB_DATA_MAX, DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, DISABLE, SMB_ADDR_MAX, NOT_EXIST , DISABLE, VPP_PORT_MAX, SMB_ADDR_MAX, 0x0 }
- // Port Index | Slot |Inter |Power |Power |Hotplug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD |Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer |Retimer |Mux |Mux |ExtnCard|ExtnCard |ExtnCard |ExtnCard|Ex.C. Retimer|Ex.C. Ret- |ExtnCard|Ex.C. Hotplug|Ex.C. Hotplug|Max |
- // | |lock |Limit Scale |Limit Value |Cap | | |Cap |Port |Address | |Clock | |Port | |Address |Channel |Width |Address |Channel |Support |SMBus Port |SMBus Addr |Retimer |SMBus Address|-imer Width |Hotplug |Vpp Port |Vpp Address |Retimer|
-};
-
-
EFI_STATUS
UpdateWilsonCityRPIioConfig (
IN IIO_GLOBALS *IioGlobalData
@@ -297,18 +168,6 @@ PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX TypeWilsonCityRPIioConfigTable =
sizeof(IioSlotTable)
};

-PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX TypeWilsonCityRPIioConfigTable_CPX =
-{
- PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE,
- PLATFORM_IIO_CONFIG_UPDATE_VERSION_2,
-
- IioBifurcationTable_CPX,
- sizeof(IioBifurcationTable_CPX),
- UpdateWilsonCityRPIioConfig,
- IioSlotTable_CPX,
- sizeof(IioSlotTable_CPX)
-};
-
/**
Entry point function for the PEIM

diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/KtiEparam.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/KtiEparam.c
index dd67a65a54..63a0111750 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/KtiEparam.c
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCityRP/Pei/KtiEparam.c
@@ -41,45 +41,6 @@ PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeWilsonCityRPIcxKtiEparamUpdate = {
};


-ALL_LANES_EPARAM_LINK_INFO KtiWilsonCityRPCpxAllLanesEparamTable[] = {
- //
- // SocketID, Freq, Link, TXEQL, CTLEPEAK
- //
- //
- // Socket 0
- //
- {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2E39343F, ADAPTIVE_CTLE},
- {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK5), 0x2F39353F, ADAPTIVE_CTLE},
- //
- // Socket 1
- //
- {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2D37353F, ADAPTIVE_CTLE},
- {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK5), 0x2F3A343F, ADAPTIVE_CTLE},
-
- //
- // Socket 2
- //
- {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2E39343F, ADAPTIVE_CTLE},
- {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK5), 0x2F39353F, ADAPTIVE_CTLE},
-
- //
- // Socket 3
- //
- {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2D37353F, ADAPTIVE_CTLE},
- {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK5), 0x2F3A343F, ADAPTIVE_CTLE}
-};
-
-PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeWilsonCityRPCpxKtiEparamUpdate =
-{
- PLATFORM_KTIEP_UPDATE_SIGNATURE,
- PLATFORM_KTIEP_UPDATE_VERSION,
- KtiWilsonCityRPCpxAllLanesEparamTable,
- sizeof (KtiWilsonCityRPCpxAllLanesEparamTable),
- NULL,
- 0
-};
-
-
EFI_STATUS
TypeWilsonCityRPInstallKtiEparamData (
IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c
new file mode 100644
index 0000000000..fea80ce49e
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c
@@ -0,0 +1,99 @@
+/** @file
+ IIO Config Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "IioCfgUpdateDxe.h"
+
+EFI_STATUS
+UpdateWilsonCitySMTIioConfig (
+ IN IIO_GLOBALS *IioGlobalData
+ )
+{
+ return EFI_SUCCESS;
+}
+
+PLATFORM_IIO_CONFIG_UPDATE_TABLE TypeWilsonCitySMTIioConfigTable =
+{
+ PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE,
+ PLATFORM_IIO_CONFIG_UPDATE_VERSION,
+
+ IioBifurcationTable,
+ sizeof(IioBifurcationTable),
+ UpdateWilsonCitySMTIioConfig,
+ IioSlotTable,
+ sizeof(IioSlotTable)
+
+};
+
+/**
+ The Driver Entry Point.
+
+ The function is the driver Entry point.
+
+ @param ImageHandle A handle for the image that is initializing this driver
+ @param SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS: Driver initialized successfully
+ @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded
+ @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+IioCfgUpdateEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status;
+ UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;
+
+ DEBUG((DEBUG_INFO, "UBA:IioCfgUpdate-TypeWilsonCitySMT\n"));
+ Status = gBS->LocateProtocol (
+ &gUbaConfigDatabaseProtocolGuid,
+ NULL,
+ &UbaConfigProtocol
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid,
+ &TypeWilsonCitySMTIioConfigTable,
+ sizeof(TypeWilsonCitySMTIioConfigTable)
+ );
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid_1,
+ &TypeWilsonCitySMTIioConfigTable,
+ sizeof(TypeWilsonCitySMTIioConfigTable)
+ );
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid_2,
+ &TypeWilsonCitySMTIioConfigTable,
+ sizeof(TypeWilsonCitySMTIioConfigTable)
+ );
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid_3,
+ &TypeWilsonCitySMTIioConfigTable,
+ sizeof(TypeWilsonCitySMTIioConfigTable)
+ );
+
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h
new file mode 100644
index 0000000000..662fa2c650
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h
@@ -0,0 +1,118 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IIOCFG_UPDATE_DXE_H_
+#define _IIOCFG_UPDATE_DXE_H_
+
+#include <Base.h>
+#include <Uefi.h>
+#include <Protocol/UbaCfgDb.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciLib.h>
+#include <Library/UbaIioConfigLib.h>
+#include <IioPlatformData.h>
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 =0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Mcp0,
+ Iio_Mcp1,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ VPP_PORT_0 = 0,
+ VPP_PORT_1,
+ VPP_PORT_2,
+ VPP_PORT_3
+} VPP_PORT;
+
+#define ENABLE 1
+#define DISABLE 0
+#define NO_SLT_IMP 0xFF
+#define SLT_IMP 1
+#define HIDE 1
+#define NOT_HIDE 0
+#define VPP_PORT_0 0
+#define VPP_PORT_1 1
+#define VPP_PORT_MAX 0xFF
+#define VPP_ADDR_MAX 0xFF
+#define PWR_VAL_MAX 0xFF
+#define PWR_SCL_MAX 0xFF
+
+static IIO_BIFURCATION_DATA_ENTRY IioBifurcationTable[] =
+{
+ // Neon City IIO bifurcation table (Based on Neon City Block Diagram rev 0.6)
+ { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxx8x4x4 },
+ { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 },
+ { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
+};
+
+static IIO_SLOT_CONFIG_DATA_ENTRY IioSlotTable[] = {
+ // Port | Slot | Inter | Power Limit | Power Limit | Hot | Vpp | Vpp | PcieSSD | PcieSSD | PcieSSD | Hidden
+ // Index | | lock | Scale | Value | Plug | Port | Addr | Cap | VppPort | VppAddr |
+ { PORT_1A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x4C , HIDE },//Oculink
+ { PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x4C , HIDE },//Oculink
+ { PORT_1C_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ { PORT_2A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ // Slot 2 supports HP: PCA9555 (CPU0) Addres 0x40, SCH (Rev 0.604) P 118 (MRL in J65)
+ { PORT_3A_INDEX, 2 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 , NOT_HIDE },
+ { PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 , HIDE },
+ { PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 , HIDE },
+ { PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_0_INDEX , 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P 121 (MRL in J287)
+ { SOCKET_1_INDEX +
+ PORT_1A_INDEX, 4 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 , NOT_HIDE },
+ { SOCKET_1_INDEX +
+ PORT_1B_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_1C_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_1D_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2A_INDEX, 8 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_1 , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x44 , NOT_HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x44 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x46 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x46 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_3A_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ { SOCKET_1_INDEX +
+ PORT_3C_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ // Note: On Neon City, Slot 3 is assigned to PCH's PCIE port
+};
+
+#endif //_IIOCFG_UPDATE_DXE_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
new file mode 100644
index 0000000000..b34810f76c
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
@@ -0,0 +1,48 @@
+## @file
+#
+# @copyright
+# Copyright 2019 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IioCfgUpdateDxeWilsonCitySMT
+ FILE_GUID = 7934B6C8-4090-C8BD-48F5-3C8F1F0E84DA
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = IioCfgUpdateEntry
+
+[Sources]
+ IioCfgUpdateDxe.c
+ IioCfgUpdateDxe.h
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ UefiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[Guids]
+
+[FixedPcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
+[Protocols]
+ gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+ gEfiPlatformTypeWilsonCitySMTProtocolGuid
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c
new file mode 100644
index 0000000000..bdedb48316
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c
@@ -0,0 +1,115 @@
+/** @file
+ Slot Data Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "SlotDataUpdateDxe.h"
+
+UINT8
+GetTypeWilsonCitySMTIOU0Setting (
+ UINT8 IOU0Data
+)
+{
+ //
+ // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled.
+ //
+ IOU0Data = IIO_BIFURCATE_xxx8xxx8;
+ return IOU0Data;
+}
+
+UINT8
+GetTypeWilsonCitySMTIOU2Setting (
+ UINT8 SkuPersonalityType,
+ UINT8 IOU2Data
+)
+{
+ return IOU2Data;
+}
+
+static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeWilsonCitySMTBroadwayTable[] = {
+ {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 },
+ {Iio_Socket1, Iio_Iou1, Bw5_Addr_2},
+ {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 },
+};
+
+
+PLATFORM_SLOT_UPDATE_TABLE TypeWilsonCitySMTSlotTable =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeWilsonCitySMTBroadwayTable,
+ GetTypeWilsonCitySMTIOU0Setting,
+ 0
+};
+
+PLATFORM_SLOT_UPDATE_TABLE2 TypeWilsonCitySMTSlotTable2 =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeWilsonCitySMTBroadwayTable,
+ GetTypeWilsonCitySMTIOU0Setting,
+ 0,
+ GetTypeWilsonCitySMTIOU2Setting
+};
+
+/**
+ The Driver Entry Point.
+
+ The function is the driver Entry point.
+
+ @param ImageHandle A handle for the image that is initializing this driver
+ @param SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS: Driver initialized successfully
+ @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded
+ @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+SlotDataUpdateEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status;
+ UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;
+
+ DEBUG((DEBUG_INFO, "UBA:SlotDataUpdate-TypeWilsonCitySMT\n"));
+ Status = gBS->LocateProtocol (
+ &gUbaConfigDatabaseProtocolGuid,
+ NULL,
+ &UbaConfigProtocol
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformSlotDataDxeGuid,
+ &TypeWilsonCitySMTSlotTable,
+ sizeof(TypeWilsonCitySMTSlotTable)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformSlotDataDxeGuid,
+ &TypeWilsonCitySMTSlotTable2,
+ sizeof(TypeWilsonCitySMTSlotTable2)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h
new file mode 100644
index 0000000000..9be882b09e
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h
@@ -0,0 +1,57 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SLOT_DATA_UPDATE_DXE_H_
+#define _SLOT_DATA_UPDATE_DXE_H_
+
+
+#include <Base.h>
+#include <Uefi.h>
+
+#include <Protocol/UbaCfgDb.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciLib.h>
+
+#include <Library/UbaSlotUpdateLib.h>
+#include <IioPlatformData.h>
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 =0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Mcp0,
+ Iio_Mcp1,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ Bw5_Addr_0 = 0,
+ Bw5_Addr_1,
+ Bw5_Addr_2,
+ Bw5_Addr_3,
+ Bw5_Addr_Max
+} BW5_ADDRESS;
+
+#endif //_SLOT_DATA_UPDATE_DXE_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
new file mode 100644
index 0000000000..31c9eea5e3
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
@@ -0,0 +1,48 @@
+## @file
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SlotDataUpdateDxeWilsonCitySMT
+ FILE_GUID = BBDB00BE-4C5C-7AD3-D34A-7A979492840D
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SlotDataUpdateEntry
+
+[Sources]
+ SlotDataUpdateDxe.c
+ SlotDataUpdateDxe.h
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ UefiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[Guids]
+
+[FixedPcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
+[Protocols]
+ gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+ gEfiPlatformTypeWilsonCitySMTProtocolGuid
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c
new file mode 100644
index 0000000000..769003d2be
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c
@@ -0,0 +1,127 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "UsbOcUpdateDxe.h"
+
+#include <Library/UbaUsbOcUpdateLib.h>
+#include <PchLimits.h>
+#include <ConfigBlock/UsbConfig.h>
+#include <ConfigBlock/Usb2PhyConfig.h>
+
+USB_OVERCURRENT_PIN TypeWilsonCitySMTUsb20OverCurrentMappings[PCH_MAX_USB2_PORTS] = {
+ UsbOverCurrentPinSkip, //Port00: BMC
+ UsbOverCurrentPinSkip, //Port01: BMC
+ UsbOverCurrentPin0, //Port02: Rear Panel
+ UsbOverCurrentPin1, //Port03: Rear Panel
+ UsbOverCurrentPin1, //Port04: Rear Panel
+ UsbOverCurrentPinSkip, //Port05: NC
+ UsbOverCurrentPinSkip, //Port06: NC
+ UsbOverCurrentPin4, //Port07: Type A internal
+ UsbOverCurrentPinSkip, //Port08: NC
+ UsbOverCurrentPinSkip, //Port09: NC
+ UsbOverCurrentPin6, //Port10: Front Panel
+ UsbOverCurrentPinSkip, //Port11: NC
+ UsbOverCurrentPin6, //Port12: Front Panel
+ UsbOverCurrentPinSkip, //Port13: NC
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB_OVERCURRENT_PIN TypeWilsonCitySMTUsb30OverCurrentMappings[PCH_MAX_USB3_PORTS] = {
+ UsbOverCurrentPin6, //Port01: Front Panel
+ UsbOverCurrentPin6, //Port02: Front Panel
+ UsbOverCurrentPin0, //Port03: Rear Panel
+ UsbOverCurrentPin1, //Port04: Rear Panel
+ UsbOverCurrentPin1, //Port05: Rear Panel
+ UsbOverCurrentPinSkip, //Port06: NC
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB2_PHY_PARAMETERS TypeWilsonCitySMTUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS] = {
+ {3, 0, 3, 1}, // PP0
+ {5, 0, 3, 1}, // PP1
+ {3, 0, 3, 1}, // PP2
+ {0, 5, 1, 1}, // PP3
+ {3, 0, 3, 1}, // PP4
+ {3, 0, 3, 1}, // PP5
+ {3, 0, 3, 1}, // PP6
+ {3, 0, 3, 1}, // PP7
+ {2, 2, 1, 0}, // PP8
+ {6, 0, 2, 1}, // PP9
+ {2, 2, 1, 0}, // PP10
+ {6, 0, 2, 1}, // PP11
+ {0, 5, 1, 1}, // PP12
+ {7, 0, 2, 1}, // PP13
+ };
+
+EFI_STATUS
+TypeWilsonCitySMTPlatformUsbOcUpdateCallback (
+ IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings,
+ IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings,
+ IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams
+)
+{
+ *Usb20OverCurrentMappings = &TypeWilsonCitySMTUsb20OverCurrentMappings[0];
+ *Usb30OverCurrentMappings = &TypeWilsonCitySMTUsb30OverCurrentMappings[0];
+
+ *Usb20AfeParams = TypeWilsonCitySMTUsb20AfeParams;
+ return EFI_SUCCESS;
+}
+
+PLATFORM_USBOC_UPDATE_TABLE TypeWilsonCitySMTUsbOcUpdate =
+{
+ PLATFORM_USBOC_UPDATE_SIGNATURE,
+ PLATFORM_USBOC_UPDATE_VERSION,
+ TypeWilsonCitySMTPlatformUsbOcUpdateCallback
+};
+
+/**
+ The Driver Entry Point.
+
+ The function is the driver Entry point.
+
+ @param ImageHandle A handle for the image that is initializing this driver
+ @param SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS: Driver initialized successfully
+ @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded
+ @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+UsbOcUpdateEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status;
+ UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;
+
+ DEBUG((DEBUG_INFO, "UBA:UsbOcUpdate-TypeWilsonCitySMT\n"));
+ Status = gBS->LocateProtocol (
+ &gUbaConfigDatabaseProtocolGuid,
+ NULL,
+ &UbaConfigProtocol
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gDxePlatformUbaOcConfigDataGuid,
+ &TypeWilsonCitySMTUsbOcUpdate,
+ sizeof(TypeWilsonCitySMTUsbOcUpdate)
+ );
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h
new file mode 100644
index 0000000000..3813eadae9
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h
@@ -0,0 +1,27 @@
+/** @file
+
+ @copyright
+ Copyright 2015 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _USBOC_UPDATE_DXE_H_
+#define _USBOC_UPDATE_DXE_H_
+
+#include <Base.h>
+#include <Uefi.h>
+
+#include <Protocol/UbaCfgDb.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+
+
+#endif //_USBOC_UPDATE_DXE_H_
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
new file mode 100644
index 0000000000..ef80d3ec56
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
@@ -0,0 +1,44 @@
+## @file
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = UsbOcUpdateDxeWilsonCitySMT
+ FILE_GUID = 5861D662-4CE8-F72D-B0E4-258B859BF9F5
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = UsbOcUpdateEntry
+
+[sources]
+ UsbOcUpdateDxe.c
+ UsbOcUpdateDxe.h
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ UefiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[Guids]
+
+[Protocols]
+ gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+ gEfiPlatformTypeWilsonCitySMTProtocolGuid
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/AcpiTablePcds.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/AcpiTablePcds.c
new file mode 100644
index 0000000000..437cb211b6
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/AcpiTablePcds.c
@@ -0,0 +1,51 @@
+/** @file
+ ACPI table pcds update.
+
+ @copyright
+ Copyright 2015 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+#include <Guid/PlatformInfo.h>
+#include <UncoreCommonIncludes.h>
+#include <Cpu/CpuIds.h>
+
+EFI_STATUS
+TypeWilsonCitySMTPlatformUpdateAcpiTablePcds (
+ VOID
+ )
+{
+ CHAR8 AcpiName10nm[] = "EPRP10NM"; // USED for identify ACPI table for 10nm in systmeboard dxe driver
+ CHAR8 OemTableIdXhci[] = "xh_nccrb";
+
+ UINTN Size;
+ EFI_STATUS Status;
+
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+ //#
+ //#ACPI items
+ //#
+ Size = AsciiStrSize (AcpiName10nm);
+ Status = PcdSetPtrS (PcdOemSkuAcpiName , &Size, AcpiName10nm);
+ DEBUG ((DEBUG_INFO, "%a TypeWilsonCitySMT ICX\n", __FUNCTION__));
+ ASSERT_EFI_ERROR (Status);
+
+ Size = AsciiStrSize (OemTableIdXhci);
+ Status = PcdSetPtrS (PcdOemTableIdXhci , &Size, OemTableIdXhci);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/GpioTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/GpioTable.c
new file mode 100644
index 0000000000..f8e6051df2
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/GpioTable.c
@@ -0,0 +1,327 @@
+/** @file
+
+ @copyright
+ Copyright 2020 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaGpioUpdateLib.h>
+
+#include <Library/GpioLib.h>
+#include <Library/UbaGpioInitLib.h>
+#include <GpioPinsSklH.h>
+#include <Library/PcdLib.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+//
+// Board : Wilson City SMT
+//
+static GPIO_INIT_CONFIG mGpioTableWilsonCitySMT [] =
+ {
+ {GPIO_SKL_H_GPP_A0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N
+ {GPIO_SKL_H_GPP_A1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_1_LPC_LAD0_ESPI_IO0
+ {GPIO_SKL_H_GPP_A2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_2_LPC_LAD1_ESPI_IO1
+ {GPIO_SKL_H_GPP_A3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_3_LPC_LAD2_ESPI_IO2
+ {GPIO_SKL_H_GPP_A4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_4_LPC_LAD3_ESPI_IO3
+ {GPIO_SKL_H_GPP_A5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
+ {GPIO_SKL_H_GPP_A6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
+ {GPIO_SKL_H_GPP_A7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
+ {GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_8_FM_LPC_CLKRUN_N
+ {GPIO_SKL_H_GPP_A9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_9_CLK_24M_66M_LPC0_ESPI
+ {GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_10_TP_PCH_GPP_A_10
+ {GPIO_SKL_H_GPP_A11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_11_FM_LPC_PME_N
+ {GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_12_IRQ_PCH_SCI_WHEA_N
+ {GPIO_SKL_H_GPP_A13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_13_FM_EUP_LOT6_N
+ {GPIO_SKL_H_GPP_A14, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_14_RST_ESPI_RESET_N
+ {GPIO_SKL_H_GPP_A15, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_15_FM_SUSACK_N
+ {GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_16_TP_PCH_GPP_A_16
+ {GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_17_TP_PCH_GPP_A_16
+ {GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_18_FM_BIOS_ADV_FUNCTIONS
+ {GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_20_TP_PCH_GPP_A_20
+ {GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_21_TP_PCH_GPP_A_21
+ {GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_22_TP_PCH_GPP_A_22
+ {GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_23_TP_PCH_GPP_A_23
+ {GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_0_FM_PCH_CORE_VID_0
+ {GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_1_FM_PCH_CORE_VID_1
+ {GPIO_SKL_H_GPP_B2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_2_PU_PCH_VRALERT_N
+ {GPIO_SKL_H_GPP_B3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_3_FM_QAT_ENABLE_N
+ {GPIO_SKL_H_GPP_B4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_4_FM_QAT_SEL
+ {GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_5_FM_PCH_INTERPOSER_SEL1
+ {GPIO_SKL_H_GPP_B6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_6_FM_PCH_INTERPOSER_SEL2
+ {GPIO_SKL_H_GPP_B7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_7_TP_PCH_GPP_B_7
+ {GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_8_TP_PCH_GPP_B_8
+ {GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_9_FM_BOARD_REV_ID2
+ {GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_10_FM_TPM_MOD_PRES_N
+ {GPIO_SKL_H_GPP_B11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_11_FM_PMBUS_ALERT_B_EN
+ {GPIO_SKL_H_GPP_B12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_12_TP_SLP_S0_N
+ {GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_13_RST_PLTRST_N
+ {GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
+ {GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_15_FM_CPU_ERR0_PCH_N
+ {GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_16_FM_CPU_ERR1_PCH_N
+ {GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_17_FM_CPU_ERR2_PCH_N
+ {GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_18_FM_NO_REBOOT
+ {GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_19_FM_BOARD_SKU_ID5
+ {GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioPadConfigLock}},//GPP_B_20_FM_BIOS_POST_CMPLT_N
+ {GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_21_TP_PCH_GPP_B_21
+ {GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_22_FM_PCH_BOOT_BIOS_DEVICE
+ {GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_23_FM_PCH_BMC_THERMTRIP_EXI_STRAP_N
+ {GPIO_SKL_H_GPP_C2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_2_PU_PCH_TLS_ENABLE_STRAP
+ {GPIO_SKL_H_GPP_C5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_5_IRQ_SML0_ALERT_N
+ {GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_8_FM_PASSWORD_CLEAR_N
+ {GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_9_FM_MFG_MODE
+ {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//GPP_C_10_FM_PCH_SATA_RAID_KEY
+ {GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_11_TP_FP_AUD_DETECT_N
+ {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_12_FM_BOARD_REV_ID0
+ {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_13_FM_BOARD_REV_ID1
+ {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_14_FM_BMC_PCH_SCI_LPC_N
+ {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_15_FM_RISER1_ID_0
+ {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_16_FM_RISER1_ID_1
+ {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_17_FM_RISER2_ID_0
+ {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_18_FM_RISER2_ID_1
+ {GPIO_SKL_H_GPP_C19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_19_RST_SMB_HOST_PCH_MUX_N
+ {GPIO_SKL_H_GPP_C20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_20_FM_THROTTLE_N
+ {GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_21_RST_PCH_MIC_MUX_N
+ {GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_22_IRQ_BMC_PCH_SMI_LPC_N
+ {GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_23_FM_CPU_CATERR_DLY_LVT3_N
+ {GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI
+ {GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_1_FP_PWR_LED_N
+ {GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_2_FM_TBT_FORCE_PWR
+ {GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_3_FM_TBT_SCI_EVENT
+ {GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_4_FM_PLD_PCH_DATA
+ {GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_5_TP_PCH_GPP_D_5
+ {GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_6_TP_PCH_GPP_D_6
+ {GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_7_TP_PCH_GPP_D_7
+ {GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_8_FM_UPLINK_SEL
+ {GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_9_TP_PCH_GPP_D_9
+ {GPIO_SKL_H_GPP_D10, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_10_FM_M2_2_SSD_DEVSLP
+ {GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_11_TP_PCH_GPP_D_11
+ {GPIO_SKL_H_GPP_D12, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_12_SGPIO_SSATA_DATA1
+ {GPIO_SKL_H_GPP_D13, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_13_SMB_SMLINK5_STBY_LVC3_R_SCL
+ {GPIO_SKL_H_GPP_D14, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_14_SMB_SMLINK5_STBY_LVC3_R_SDA
+ {GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_15_SGPIO_SSATA_DATA0
+ {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_16_FM_ME_PFR_1
+ {GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_17_FM_ME_PFR_2
+ {GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_18_MCP_RESET_CTRL_N
+ {GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_19_FM_PS_PWROK_DLY_SEL_R
+ {GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_20_TP_PCH_GPP_D_20
+ {GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_21_TP_PCH_GPP_D_21
+ {GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_22_TP_PCH_GPP_D_22
+ {GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_23_TP_PCH_GPP_D_23
+ {GPIO_SKL_H_GPP_E0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_0_FM_QAT_ENABLE_N
+ {GPIO_SKL_H_GPP_E1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_1_FM_QAT_ENABLE_N
+ {GPIO_SKL_H_GPP_E2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_2_FM_QAT_ENABLE_N
+ {GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_3_FM_ADR_TRIGGER_N
+ {GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_4_TP_PCH_GPP_E_4
+ {GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_5_TP_PCH_GPP_E_5
+ {GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_6_TP_PCH_GPP_E_6
+ {GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_7_FM_ADR_SMI_GPIO_R_N
+ {GPIO_SKL_H_GPP_E8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_8_LED_PCH_SATA_HDD_N
+ {GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_9_FM_OC0_USB_N
+ {GPIO_SKL_H_GPP_E10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_10_FM_OC1_USB_N
+ {GPIO_SKL_H_GPP_E11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_11_PU_OC2_USB_N
+ {GPIO_SKL_H_GPP_E12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_12_PU_OC3_USB_N
+ {GPIO_SKL_H_GPP_F0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_0_FM_QAT_ENABLE_N
+ {GPIO_SKL_H_GPP_F1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_1_FM_QAT_ENABLE_N
+ {GPIO_SKL_H_GPP_F2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_2_FM_QAT_ENABLE_N
+ {GPIO_SKL_H_GPP_F3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_3_FM_QAT_ENABLE_N
+ {GPIO_SKL_H_GPP_F4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_4_FM_QAT_ENABLE_N
+ {GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_5_IRQ_TPM_SPI_N
+ {GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_6_JTAG_PCH_PLD_TCK
+ {GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_7_JTAG_PCH_PLD_TDI
+ {GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_8_JTAG_PCH_PLD_TMS
+ {GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_9_JTAG_PCH_PLD_TDO
+ {GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_10_SGPIO_SATA_CLOCK
+ {GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_11_SGPIO_SATA_LOAD
+ {GPIO_SKL_H_GPP_F12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_12_SGPIO_SATA_DATA1
+ {GPIO_SKL_H_GPP_F13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_13_SGPIO_SATA_DATA0
+ {GPIO_SKL_H_GPP_F14, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_14_LED_PCH_SSATA_HDD_N
+ {GPIO_SKL_H_GPP_F15, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_15_FM_OC4_USB_N
+ {GPIO_SKL_H_GPP_F16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_16_PU_OC5_USB_N
+ {GPIO_SKL_H_GPP_F17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_17_FM_OC6_USB_N
+ {GPIO_SKL_H_GPP_F18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_18_PU_OC7_USB_N
+ {GPIO_SKL_H_GPP_F19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_19_SMB_GBE_STBY_LVC3_SCL
+ {GPIO_SKL_H_GPP_F20, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_20_SMB_GBE_STBY_LVC3_SDA
+ {GPIO_SKL_H_GPP_F21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_21_TP_PCH_GPP_F_21
+ {GPIO_SKL_H_GPP_F22, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_22_SGPIO_SSATA_CLOCK
+ {GPIO_SKL_H_GPP_F23, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_23_SGPIO_SSATA_LOAD
+ {GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_0_TP_FAN_PCH_TACH0
+ {GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_1_TP_FAN_PCH_TACH1
+ {GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_2_TP_FAN_PCH_TACH2
+ {GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_3_TP_FAN_PCH_TACH3
+ {GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_4_TP_FAN_PCH_TACH4
+ {GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_5_TP_FAN_PCH_TACH5
+ {GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_6_TP_FAN_PCH_TACH6
+ {GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_7_TP_FAN_PCH_TACH7
+ {GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_8_TP_FAN_PCH_PWM0
+ {GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_9_TP_FAN_PCH_PWM1
+ {GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_10_TP_FAN_PCH_PWM2
+ {GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_11_TP_FAN_PCH_PWM3
+ {GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_12_FM_BOARD_SKU_ID0
+ {GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_13_FM_BOARD_SKU_ID1
+ {GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_14_FM_BOARD_SKU_ID2
+ {GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_15_FM_BOARD_SKU_ID3
+ {GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_16_FM_BOARD_SKU_ID4
+ {GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_17_FM_ADR_COMPLETE
+ {GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_18_IRQ_NMI_EVENT_N
+ {GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_19_IRQ_SMI_ACTIVE_N
+ {GPIO_SKL_H_GPP_G20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_20_IRQ_SML1_PMBUS_ALERT_N
+ {GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_21_FM_BIOS_IMAGE_SWAP_N
+ {GPIO_SKL_H_GPP_G22, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_22_FM_M2_2_SSD_DEVSLP
+ {GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_23_TP_PCH_GPP_G_23
+ {GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_0_FM_PCH_MGPIO_TEST2
+ {GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_1_FM_SWAP_OVERRIDE_N
+ {GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_2_FM_PCH_MGPIO_TEST0
+ {GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_3_FM_PCH_MGPIO_TEST1
+ {GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_4_FM_PCH_MGPIO_TEST4
+ {GPIO_SKL_H_GPP_H6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_6_FM_CLKREQ_M2_2_N
+ {GPIO_SKL_H_GPP_H7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_7_FM_PCH_MGPIO_TEST3
+ {GPIO_SKL_H_GPP_H8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_8_FM_CLKREQ_NIC1_N
+ {GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_9_FM_PCH_MGPIO_TEST5
+ {GPIO_SKL_H_GPP_H10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_10_SMB_SMLINK2_STBY_LVC3_R_SCL
+ {GPIO_SKL_H_GPP_H11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_11_SMB_SMLINK2_STBY_LVC3_R_SDA
+ {GPIO_SKL_H_GPP_H12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_12_FM_ESPI_FLASH_MODE
+ {GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_15_PU_ADR_TIMER_HOLD_OFF_N
+ {GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_18_FM_LT_KEY_DOWNGRADE_N
+ {GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_19_FM_PCH_10GBE_PCI_DISABLE_N
+ {GPIO_SKL_H_GPP_H20, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_20_FM_SSATA_PCIE_M2_1_SEL
+ {GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_21_FM_PCH_10GBE_LAN_DISABLE_N
+ {GPIO_SKL_H_GPP_H22, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_22_FM_SSATA_PCIE_M2_2_SEL
+ {GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_23_TP_PCH_GPP_H_23
+ {GPIO_SKL_H_GPP_I0, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_0_TP_PCH_GPP_I_0
+ {GPIO_SKL_H_GPP_I1, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_1_TP_PCH_GPP_I_1
+ {GPIO_SKL_H_GPP_I2, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_2_TP_PCH_GPP_I_2
+ {GPIO_SKL_H_GPP_I3, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_3_TP_PCH_GPP_I_3
+ {GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_4_TP_PCH_GPP_I_4
+ {GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_5_TP_PCH_GPP_I_5
+ {GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_6_TP_PCH_GPP_I_6
+ {GPIO_SKL_H_GPP_I7, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_7_TP_PCH_GPP_I_7
+ {GPIO_SKL_H_GPP_I8, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_8_FM_PCH_10GBE_PCI_DISABLE_N
+ {GPIO_SKL_H_GPP_I9, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_9_FM_PCH_10GBE_LAN_DISABLE_N
+ {GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_10_TP_PCH_GPP_I_10
+// {GPIO_SKL_H_GPP_I11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_11_PD_3P3_RCOMP
+ {GPIO_SKL_H_GPD0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_0_FM_FIVRBREAK_N
+ {GPIO_SKL_H_GPD1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_1_PU_ACPRESENT
+ {GPIO_SKL_H_GPD2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_2_FM_LAN_WAKE_N
+ {GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_3_FM_PCH_PWRBTN_N
+ {GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_4_FM_SLPS3_N
+ {GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_5_FM_SLPS4_N
+ {GPIO_SKL_H_GPD6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_6_FM_SLPA_N
+ {GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_7_TP_GPD_7
+ {GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_8_TP_GPD_8_SUSCLK
+ {GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_9_TP_GPD_9_SLP
+ {GPIO_SKL_H_GPD10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_10_FM_SLPS5_N
+ {GPIO_SKL_H_GPD11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_11_FM_PHY_DISABLE_N
+ {GPIO_SKL_H_GPP_J0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_0_TP_PCH_GPP_J_0
+ {GPIO_SKL_H_GPP_J1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_1_TP_PCH_GPP_J_1
+ {GPIO_SKL_H_GPP_J2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_2_TP_PCH_GPP_J_2
+ {GPIO_SKL_H_GPP_J3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_3_TP_PCH_GPP_J_3
+ {GPIO_SKL_H_GPP_J4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_4_TP_PCH_GPP_J_4
+ {GPIO_SKL_H_GPP_J5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_5_TP_PCH_GPP_J_5
+ {GPIO_SKL_H_GPP_J6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_6_TP_PCH_GPP_J_6
+ {GPIO_SKL_H_GPP_J7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_7_TP_PCH_GPP_J_7
+ {GPIO_SKL_H_GPP_J8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_8_TP_PCH_GPP_J_8
+ {GPIO_SKL_H_GPP_J9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_9_TP_PCH_GPP_J_9
+ {GPIO_SKL_H_GPP_J10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_10_TP_PCH_GPP_J_10
+ {GPIO_SKL_H_GPP_J11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_11_TP_PCH_GPP_J_11
+ {GPIO_SKL_H_GPP_J12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_12_TP_PCH_GPP_J_12
+ {GPIO_SKL_H_GPP_J13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_13_TP_PCH_GPP_J_13
+ {GPIO_SKL_H_GPP_J14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_14_TP_PCH_GPP_J_14
+ {GPIO_SKL_H_GPP_J15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_15_TP_PCH_GPP_J_15
+ {GPIO_SKL_H_GPP_J16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_16_TP_PCH_GPP_J_16
+ {GPIO_SKL_H_GPP_J17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_17_TP_PCH_GPP_J_17
+ {GPIO_SKL_H_GPP_J18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_18_TP_PCH_GPP_J_18
+ {GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_19_TP_PCH_GPP_J_19
+ {GPIO_SKL_H_GPP_J20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_20_TP_PCH_GPP_J_20
+ {GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_21_TP_PCH_GPP_J_21
+ {GPIO_SKL_H_GPP_J22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_22_TP_PCH_GPP_J_22
+ {GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_23_TP_PCH_GPP_J_23
+ {GPIO_SKL_H_GPP_K0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_0_CLK_50M_CKMNG_PCH
+ {GPIO_SKL_H_GPP_K1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_1_RMII_BMC_PCH_TXD0
+ {GPIO_SKL_H_GPP_K2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_2_RMII_BMC_PCH_TXD1
+ {GPIO_SKL_H_GPP_K3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_3_RMII_BMC_PCH_TX_EN
+ {GPIO_SKL_H_GPP_K4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_4_RMII_PCH_BMC_CRS_DV
+ {GPIO_SKL_H_GPP_K5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_5_RMII_PCH_BMC_RXD0
+ {GPIO_SKL_H_GPP_K6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_6_RMII_PCH_BMC_RXD1
+ {GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_7_RMII_PCH_BMC_RX_ER
+ {GPIO_SKL_H_GPP_K8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_8_RMII_PCH_CONN_ARB_IN
+ {GPIO_SKL_H_GPP_K9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_9_RMII_PCH_CONN_ARB_OUT
+ {GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_10_RST_PCIE_PCH_PERST_N
+// {GPIO_SKL_H_GPP_K11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_11_PD_1P8_3P3_RCOMP
+ {GPIO_SKL_H_GPP_L2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_2_TRC_2CH0_D0
+ {GPIO_SKL_H_GPP_L3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_3_TRC_2CH0_D1
+ {GPIO_SKL_H_GPP_L4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_4_TRC_2CH0_D2
+ {GPIO_SKL_H_GPP_L5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_5_TRC_2CH0_D3
+ {GPIO_SKL_H_GPP_L6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_6_TRC_2CH0_D4
+ {GPIO_SKL_H_GPP_L7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_7_TRC_2CH0_D5
+ {GPIO_SKL_H_GPP_L8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_8_TRC_2CH0_D6
+ {GPIO_SKL_H_GPP_L9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_9_TRC_2CH0_D7
+ {GPIO_SKL_H_GPP_L10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_10_TRC_2CH0_CLK
+ {GPIO_SKL_H_GPP_L11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_11_TRC_2CH1_D0
+ {GPIO_SKL_H_GPP_L12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_12_TRC_2CH1_D1
+ {GPIO_SKL_H_GPP_L13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_13_TRC_2CH1_D2
+ {GPIO_SKL_H_GPP_L14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_14_TRC_2CH1_D3
+ {GPIO_SKL_H_GPP_L15, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_15_TRC_2CH1_D4
+ {GPIO_SKL_H_GPP_L16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_16_TRC_2CH1_D5
+ {GPIO_SKL_H_GPP_L17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_17_TRC_2CH1_D6
+ {GPIO_SKL_H_GPP_L18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_18_TRC_2CH1_D7
+ {GPIO_SKL_H_GPP_L19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_19_TRC_2CH1_CLK
+};
+
+static GPIO_INIT_CONFIG mGpioTableWilsonCitySMTMiniPch [] =
+{
+ {GPIO_SKL_H_GPP_C5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone, GpioPadConfigLock}},//GPP_C_5
+ {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirInOut, GpioOutHigh, GpioIntDis,GpioResetNormal,GpioTermNone}},//GPP_C_10_FM_PCH_SATA_RAID_KEY
+ {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, GpioTermNone, GpioPadConfigLock}},//GPP_C_12_FM_BOARD_REV_ID0
+ {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, GpioTermNone, GpioPadConfigLock}},//GPP_C_13_FM_BOARD_REV_ID1
+ {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntNmi,GpioResetNormal, GpioTermNone, GpioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI
+ {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone, GpioPadConfigLock}},//GPP_G_12_FM_BOARD_SKU_ID0
+ {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone, GpioPadConfigLock}},//GPP_G_13_FM_BOARD_SKU_ID1
+ {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone, GpioPadConfigLock}},//GPP_G_14_FM_BOARD_SKU_ID2
+ {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone, GpioPadConfigLock}},//GPP_G_15_FM_BOARD_SKU_ID3
+ {GPIO_SKL_H_GPP_C19, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone, GpioPadConfigLock}},//GPP_G_16_FM_BOARD_SKU_ID4
+ {GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntNmi,GpioResetNormal, GpioTermNone, GpioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI
+ {GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetNormal,GpioTermNone, GpioPadConfigLock}},//GPP_D_4
+ {GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, GpioOutHigh, GpioIntDis,GpioResetNormal,GpioTermNone, GpioPadConfigLock}},//GPP_B_20_FM_BIOS_POST_CMPLT_N
+ {GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntLevel | GpioIntApic,GpioResetNormal, GpioTermNone, GpioPadConfigLock}},//GPP_F_5_IRQ_TPM_SPI_N
+ {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntSci,GpioResetNormal, GpioTermNone}},//GPP_A_12_IRQ_PCH_SCI_WHEA_N
+ {GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, GpioOutDefault, GpioIntDis,GpioResetDeep, GpioTermNone, GpioPadConfigLock}},//GPP_E_7_FM_ADR_SMI_GPIO_N
+};
+
+
+
+EFI_STATUS
+TypeWilsonCitySMTInstallGpioData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ if (DynamicSiLibraryPpi->GetPchSeries () == PchMini) {
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformGpioInitDataGuid,
+ &mGpioTableWilsonCitySMTMiniPch,
+ sizeof(mGpioTableWilsonCitySMTMiniPch)
+ );
+ Status = PcdSet32S (PcdOemSku_GPIO_TABLE_SIZE, sizeof (mGpioTableWilsonCitySMTMiniPch));
+ } else {
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformGpioInitDataGuid,
+ &mGpioTableWilsonCitySMT,
+ sizeof(mGpioTableWilsonCitySMT)
+ );
+ Status = PcdSet32S (PcdOemSku_GPIO_TABLE_SIZE, sizeof (mGpioTableWilsonCitySMT));
+ }
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/IioBifurInit.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/IioBifurInit.c
new file mode 100644
index 0000000000..32de972eb6
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/IioBifurInit.c
@@ -0,0 +1,249 @@
+/** @file
+ IIO Config Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaIioConfigLib.h>
+#include <IioPlatformData.h>
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 = 0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Iou3,
+ Iio_Iou4,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ VPP_PORT_0 = 0,
+ VPP_PORT_1,
+ VPP_PORT_2,
+ VPP_PORT_3
+} VPP_PORT;
+
+#define ENABLE 1
+#define DISABLE 0
+
+//
+// WilsonCitySMT should has the same settings like WilsomCity-LCC
+//
+
+//
+// config file : Wilson_City_PCIe_Slot_Config_1p70.xlsx
+// config sheet : WilsonCity_ICX
+//
+static IIO_BIFURCATION_DATA_ENTRY_EX IioBifurcationTable[] =
+{
+
+ { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket0, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, 0 , 0x76 , 0xE2 , 4 },
+ { Iio_Socket0, Iio_Iou4, IIO_BIFURCATE_x4x4x4x4, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+
+ { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, 0 , 0x70 , 0xE2 , 4 },
+ { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16, 0 , 0x7C , 0xE2 , 4 },
+ { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket1, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket1, Iio_Iou4, IIO_BIFURCATE_x4x4x4x4, 0 , 0x74 , 0xE2 , 4 }
+};
+
+static IIO_SLOT_CONFIG_DATA_ENTRY_EX IioSlotTable[] = {
+ // Port Index | Slot |Interlock |power |Power |Hotplug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD |Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer |Retimer |Mux |Mux |ExtnCard |ExtnCard |ExtnCard |ExtnCard |ExtnCard Retimer|ExtnCard Retimer|ExtnCard |ExtnCard Hotplug|ExtnCard Hotplug|Max Retimer|
+ // | | |Limit Scale |Limit Value |Cap | | |Cap |Port |Address | |Clock | |Port | |Address |Channel |Width |Address |Channel |Support |SMBus Port |SMBus Addr |Retimer |SMBus Address |Width |Hotplug |Vpp Port |Vpp Address | |
+ {SOCKET_0_INDEX +
+ PORT_1A_INDEX, 6 , DISABLE , 0 , 75 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2A_INDEX, 7 , DISABLE , 0 , 75 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_4A_INDEX, 2 , DISABLE , 0 , 200 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x76 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_0 , 0x40 , 0x1 },
+ {SOCKET_0_INDEX +
+ PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x76 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_1 , 0x40 , 0x1 },
+ {SOCKET_0_INDEX +
+ PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x76 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_0 , 0x42 , 0x1 },
+ {SOCKET_0_INDEX +
+ PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x76 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_1 , 0x42 , 0x1 },
+ {SOCKET_0_INDEX +
+ PORT_5A_INDEX, 10 , DISABLE , 0 , 25 , ENABLE , VPP_PORT_0 , 0x4C , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x26 , 2 , 16 , 0xe2 , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x1 },
+ {SOCKET_0_INDEX +
+ PORT_5B_INDEX, 11 , DISABLE , 0 , 25 , ENABLE , VPP_PORT_1 , 0x4C , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x26 , 2 , 16 , 0xe2 , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x1 },
+ {SOCKET_0_INDEX +
+ PORT_5C_INDEX, 12 , DISABLE , 0 , 25 , ENABLE , VPP_PORT_0 , 0x4E , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x26 , 2 , 16 , 0xe2 , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x1 },
+ {SOCKET_0_INDEX +
+ PORT_5D_INDEX, 13 , DISABLE , 0 , 25 , ENABLE , VPP_PORT_1 , 0x4E , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x26 , 2 , 16 , 0xe2 , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x1 },
+
+ {SOCKET_1_INDEX +
+ PORT_1A_INDEX, 4 , ENABLE , 0 , 25 , ENABLE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x70 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_0 , 0x40 , 0x1 },
+ {SOCKET_1_INDEX +
+ PORT_1B_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x70 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_1 , 0x40 , 0x1 },
+ {SOCKET_1_INDEX +
+ PORT_1C_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x70 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_0 , 0x42 , 0x1 },
+ {SOCKET_1_INDEX +
+ PORT_1D_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x70 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_1 , 0x42 , 0x1 },
+ {SOCKET_1_INDEX +
+ PORT_2A_INDEX, 9 , DISABLE , 0 , 25 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x7C , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_0 , 0x44 , 0x1 },
+ {SOCKET_1_INDEX +
+ PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x7C , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_1 , 0x44 , 0x1 },
+ {SOCKET_1_INDEX +
+ PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x7C , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_0 , 0x46 , 0x1 },
+ {SOCKET_1_INDEX +
+ PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x7C , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_1 , 0x46 , 0x1 },
+ {SOCKET_1_INDEX +
+ PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4A_INDEX, 8 , DISABLE , 0 , 25 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_5A_INDEX, 14 , DISABLE , 0 , 25 , ENABLE , VPP_PORT_0 , 0x4C , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x20 , 2 , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x74 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_0 , 0x40 , 0x1 },
+ {SOCKET_1_INDEX +
+ PORT_5B_INDEX, 15 , DISABLE , 0 , 25 , ENABLE , VPP_PORT_1 , 0x4C , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x20 , 2 , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x74 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_1 , 0x40 , 0x1 },
+ {SOCKET_1_INDEX +
+ PORT_5C_INDEX, 16 , DISABLE , 0 , 25 , ENABLE , VPP_PORT_0 , 0x4E , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x20 , 2 , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x74 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_0 , 0x42 , 0x1 },
+ {SOCKET_1_INDEX +
+ PORT_5D_INDEX, 17 , DISABLE , 0 , 25 , ENABLE , VPP_PORT_1 , 0x4E , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , ENABLE , 0x20 , 2 , 16 , 0xe2 , 4 , ENABLE , VPP_PORT_0 , 0x74 , ENABLE , SMB_ADDR_MAX , NOT_EXIST , ENABLE , VPP_PORT_1 , 0x42 , 0x1 }
+};
+
+EFI_STATUS
+UpdateWilsonCitySMTIioConfig (
+ IN IIO_GLOBALS *IioGlobalData
+ )
+{
+ return EFI_SUCCESS;
+}
+
+PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX TypeWilsonCitySMTIioConfigTable =
+{
+ PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE,
+ PLATFORM_IIO_CONFIG_UPDATE_VERSION_2,
+
+ IioBifurcationTable,
+ sizeof(IioBifurcationTable),
+ UpdateWilsonCitySMTIioConfig,
+ IioSlotTable,
+ sizeof(IioSlotTable)
+};
+
+/**
+ Entry point function for the PEIM
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS If we installed our PPI
+
+**/
+EFI_STATUS
+TypeWilsonCitySMTIioPortBifurcationInit (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+ PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX *PlatformIioInfoPtr;
+ UINTN PlatformIioInfoSize;
+
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+
+ //
+ // This is config for ICX
+ //
+ PlatformIioInfoPtr = &TypeWilsonCitySMTIioConfigTable;
+ PlatformIioInfoSize = sizeof(TypeWilsonCitySMTIioConfigTable);
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid_1,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid_2,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid_3,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/KtiEparam.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/KtiEparam.c
new file mode 100644
index 0000000000..9c0c75f47f
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/KtiEparam.c
@@ -0,0 +1,79 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <KtiSetupDefinitions.h>
+#include <UbaKti.h>
+
+extern EFI_GUID gPlatformKtiEparamUpdateDataGuid;
+
+ALL_LANES_EPARAM_LINK_INFO KtiWilsonCitySMTIcxAllLanesEparamTable[] = {
+ //
+ // SocketID, Freq, Link, TXEQL, CTLEPEAK
+ //
+ //
+ // Socket 0
+ //
+ {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2B33373F, ADAPTIVE_CTLE},
+ {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK1), 0x2A33363F, ADAPTIVE_CTLE},
+ {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK2), 0x2B34363F, ADAPTIVE_CTLE},
+ //
+ // Socket 1
+ //
+ {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2A31383F, ADAPTIVE_CTLE},
+ {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK1), 0x2A30393F, ADAPTIVE_CTLE},
+ {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK2), 0x2C34373F, ADAPTIVE_CTLE},
+ //
+ // Socket 2
+ //
+ {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2D37353F, ADAPTIVE_CTLE},
+ {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK1), 0x2F3A343F, ADAPTIVE_CTLE},
+ {0x2, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK2), 0x2F3A343F, ADAPTIVE_CTLE},
+ //
+ // Socket 3
+ //
+ {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2D37353F, ADAPTIVE_CTLE},
+ {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK1), 0x2F3A343F, ADAPTIVE_CTLE},
+ {0x3, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK2), 0x2F3A343F, ADAPTIVE_CTLE}
+};
+
+PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeWilsonCitySMTIcxKtiEparamUpdate = {
+ PLATFORM_KTIEP_UPDATE_SIGNATURE,
+ PLATFORM_KTIEP_UPDATE_VERSION,
+ KtiWilsonCitySMTIcxAllLanesEparamTable,
+ sizeof (KtiWilsonCitySMTIcxAllLanesEparamTable),
+ NULL,
+ 0
+};
+
+
+EFI_STATUS
+TypeWilsonCitySMTInstallKtiEparamData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformKtiEparamUpdateDataGuid,
+ &TypeWilsonCitySMTIcxKtiEparamUpdate,
+ sizeof(TypeWilsonCitySMTIcxKtiEparamUpdate)
+ );
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PcdData.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PcdData.c
new file mode 100644
index 0000000000..5ad03c93c7
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PcdData.c
@@ -0,0 +1,273 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <ImonVrSvid.h>
+#include <Library/MemVrSvidMapLib.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/UbaPcdUpdateLib.h>
+#include <Library/PcdLib.h>
+#include <UncoreCommonIncludes.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+#include <CpuAndRevisionDefines.h>
+
+#define GPIO_SKL_H_GPP_B20 0x01010014
+
+VOID TypeWilsonCitySMTPlatformUpdateVrIdAddress (VOID);
+
+/**
+ Update WilsonCity IMON SVID Information
+
+ retval N/A
+**/
+VOID
+TypeWilsonCitySMTPlatformUpdateImonAddress (
+ VOID
+ )
+{
+ VCC_IMON *VccImon = NULL;
+ UINTN Size = 0;
+
+ Size = sizeof (VCC_IMON);
+ VccImon = (VCC_IMON *) PcdGetPtr (PcdImonAddr);
+ if (VccImon == NULL) {
+ DEBUG ((DEBUG_ERROR, "UpdateImonAddress() - PcdImonAddr == NULL\n"));
+ return;
+ }
+
+ VccImon->VrSvid[0] = PcdGet8 (PcdWilsonCitySvidVrP1V8);
+ VccImon->VrSvid[1] = PcdGet8 (PcdWilsonCitySvidVrVccAna);
+ VccImon->VrSvid[2] = IMON_ADDR_LIST_END; // End array with 0xFF
+
+ PcdSetPtrS (PcdImonAddr, &Size, (VOID *) VccImon);
+}
+
+/**
+ Update WilsonCity VR ID SVID Information
+
+ retval N/A
+**/
+VOID
+TypeWilsonCitySMTPlatformUpdateVrIdAddress (
+ VOID
+ )
+{
+ MEM_SVID_MAP *MemSvidMap = NULL;
+ UINTN Size = 0;
+
+ Size = sizeof (MEM_SVID_MAP);
+ MemSvidMap = (MEM_SVID_MAP *) PcdGetPtr (PcdMemSrvidMap);
+ if (MemSvidMap == NULL) {
+ DEBUG ((DEBUG_ERROR, "UpdateVrIdAddress() - PcdMemSrvidMap == NULL\n"));
+ return;
+ }
+ /*
+ Map VR ID Address to Memory controller
+ The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14, and 0x16.
+ Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs (VR ID's 0x10 and 0x12).
+ Those are typically shared such that MC0/MC2 share the same DDR VR (as they are on the same side of the CPU)
+ and MC1/MC3 share the other. Depending on motherboard layout and other design constraints, this could change
+ BIT 4 => 0 or 1, SVID BUS\Interface 0 or 1 respectively
+ BIT 0:3 => SVID ADDRESS
+ */
+ MemSvidMap->Socket[0].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[0].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[1].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[1].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[2].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[2].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[3].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[3].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[4].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[4].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[5].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[5].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[6].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[6].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[7].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[7].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+
+ PcdSetPtrS (PcdMemSrvidMap, &Size, (VOID *) MemSvidMap);
+}
+
+EFI_STATUS
+TypeWilsonCitySMTPlatformPcdUpdateCallback (
+ VOID
+)
+{
+ CHAR8 FamilyName[] = "Whitley";
+
+ CHAR8 BoardName[] = "EPRP";
+ UINT32 Data32;
+ UINTN Size;
+ UINTN PlatformFeatureFlag = 0;
+
+ CHAR16 PlatformName[] = L"TypeWilsonCitySMT";
+ UINTN PlatformNameSize = 0;
+ EFI_STATUS Status;
+
+ //#Integer for BoardID, must match the SKU number and be unique.
+ Status = PcdSet16S (PcdOemSkuBoardID , TypeWilsonCitySMT);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSet16S (PcdOemSkuBoardFamily , 0x30);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ // Number of Sockets on Board.
+ Status = PcdSet32S (PcdOemSkuBoardSocketCount, 2);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ // Max channel and max DIMM
+ Status = PcdSet32S (PcdOemSkuMaxChannel , 8);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSet32S (PcdOemSkuMaxDimmPerChannel , 2);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSetBoolS (PcdOemSkuDimmLayout, TRUE);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //Update Onboard Video Controller PCI Ven_id, Dev_id
+ Status = PcdSet16S (PcdOnboardVideoPciVendorId, 0x1A03);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = PcdSet16S (PcdOnboardVideoPciDeviceId, 0x2000);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //#
+ //# Misc.
+ //#
+ //# V_PCIE_PORT_PXPSLOTCTRL_ATNLED_OFF
+ Status = PcdSet16S (PcdOemSkuMrlAttnLed , 0xc0);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //SDP Active Flag
+ Status = PcdSet8S (PcdOemSkuSdpActiveFlag , 0x0);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# Zero terminated string to ID family
+ Size = AsciiStrSize (FamilyName);
+ Status = PcdSetPtrS (PcdOemSkuFamilyName , &Size, FamilyName);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# Zero terminated string to Board Name
+ Size = AsciiStrSize (BoardName);
+ Status = PcdSetPtrS (PcdOemSkuBoardName , &Size, BoardName);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ PlatformNameSize = sizeof (PlatformName);
+ Status = PcdSet32S (PcdOemSkuPlatformNameSize , (UINT32)PlatformNameSize);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSetPtrS (PcdOemSkuPlatformName , &PlatformNameSize, PlatformName);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# FeaturesBasedOnPlatform
+ Status = PcdSet32S (PcdOemSkuPlatformFeatureFlag , (UINT32)PlatformFeatureFlag);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# Assert GPIO
+ Data32 = 0;
+ Status = PcdSet32S (PcdOemSkuAssertPostGPIOValue, Data32);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSet32S (PcdOemSkuAssertPostGPIO, GPIO_SKL_H_GPP_B20);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# UplinkPortIndex
+ Status = PcdSet8S (PcdOemSkuUplinkPortIndex, 5);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ DEBUG ((DEBUG_INFO, "Uba Callback: PlatformPcdUpdateCallback is called!\n"));
+ Status = TypeWilsonCitySMTPlatformUpdateAcpiTablePcds ();
+ //# BMC Pcie Port Number
+ PcdSet8S (PcdOemSkuBmcPciePortNumber, 5);
+ ASSERT_EFI_ERROR(Status);
+
+ //# Board Type Bit Mask
+ PcdSet32S (PcdBoardTypeBitmask, CPU_TYPE_F_MASK | (CPU_TYPE_F_MASK << 4));
+ ASSERT_EFI_ERROR(Status);
+
+ //Update IMON Address
+ TypeWilsonCitySMTPlatformUpdateImonAddress ();
+
+ return Status;
+}
+
+PLATFORM_PCD_UPDATE_TABLE TypeWilsonCitySMTPcdUpdateTable =
+{
+ PLATFORM_PCD_UPDATE_SIGNATURE,
+ PLATFORM_PCD_UPDATE_VERSION,
+ TypeWilsonCitySMTPlatformPcdUpdateCallback
+};
+
+EFI_STATUS
+TypeWilsonCitySMTInstallPcdData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPcdConfigDataGuid,
+ &TypeWilsonCitySMTPcdUpdateTable,
+ sizeof(TypeWilsonCitySMTPcdUpdateTable)
+ );
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PchEarlyUpdate.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PchEarlyUpdate.c
new file mode 100644
index 0000000000..6e2d6df7d7
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PchEarlyUpdate.c
@@ -0,0 +1,103 @@
+/** @file
+ Pch Early update.
+
+ @copyright
+ Copyright 2019 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+
+#include <Library/UbaPchEarlyUpdateLib.h>
+
+#include <PchAccess.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioLib.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+EFI_STATUS
+TypeWilsonCitySMTPchLanConfig (
+ IN SYSTEM_CONFIGURATION *SystemConfig
+)
+{
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+ EFI_STATUS Status;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ DynamicSiLibraryPpi->GpioSetOutputValue (GPIO_SKL_H_GPP_I9, (UINT32)SystemConfig->LomDisableByGpio);
+ DynamicSiLibraryPpi->PchDisableGbe ();
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+TypeWilsonCitySMTOemInitLateHook (
+ IN SYSTEM_CONFIGURATION *SystemConfig
+)
+{
+ return EFI_SUCCESS;
+}
+
+
+PLATFORM_PCH_EARLY_UPDATE_TABLE TypeWilsonCitySMTPchEarlyUpdateTable =
+{
+ PLATFORM_PCH_EARLY_UPDATE_SIGNATURE,
+ PLATFORM_PCH_EARLY_UPDATE_VERSION,
+ TypeWilsonCitySMTPchLanConfig,
+ TypeWilsonCitySMTOemInitLateHook
+};
+
+
+/**
+ Entry point function for the PEIM
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS If we installed our PPI
+
+**/
+EFI_STATUS
+EFIAPI
+TypeWilsonCitySMTPchEarlyUpdate(
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ if (DynamicSiLibraryPpi->GetPchSeries () == PchMini) {
+ return EFI_SUCCESS;
+ }
+
+ Status = PeiServicesLocatePpi (
+ &gUbaConfigDatabasePpiGuid,
+ 0,
+ NULL,
+ &UbaConfigPpi
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPchEarlyConfigDataGuid,
+ &TypeWilsonCitySMTPchEarlyUpdateTable,
+ sizeof(TypeWilsonCitySMTPchEarlyUpdateTable)
+ );
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInit.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInit.h
new file mode 100644
index 0000000000..1471d62c3d
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInit.h
@@ -0,0 +1,79 @@
+/** @file
+ PeiBoardInit.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_BOARD_INIT_PEIM_H_
+#define _PEI_BOARD_INIT_PEIM_H_
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Ppi/UbaCfgDb.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/HobLib.h>
+#include <Cpu/CpuIds.h>
+
+// TypeWilsonCitySMT
+EFI_STATUS
+TypeWilsonCitySMTPlatformUpdateUsbOcMappings (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeWilsonCitySMTPlatformUpdateAcpiTablePcds (
+ VOID
+);
+
+EFI_STATUS
+TypeWilsonCitySMTInstallClockgenData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeWilsonCitySMTInstallPcdData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeWilsonCitySMTPchEarlyUpdate (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeWilsonCitySMTIioPortBifurcationInit (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeWilsonCitySMTInstallSlotTableData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeWilsonCitySMTInstallKtiEparamData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+// TypeWilsonCitySMT
+EFI_STATUS
+TypeWilsonCitySMTInstallGpioData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeWilsonCitySMTInstallSoftStrapData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeWilsonCitySMTQATIioPortBifurcationInit (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+#endif // _PEI_BOARD_INIT_PEIM_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInitLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInitLib.c
new file mode 100644
index 0000000000..c368f5d143
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInitLib.c
@@ -0,0 +1,123 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+
+/**
+ The constructor function for Board Init Libray.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS Table initialization successfully.
+ @retval EFI_OUT_OF_RESOURCES No enough memory to initialize table.
+**/
+
+#include "PeiBoardInit.h"
+#include <UncoreCommonIncludes.h>
+#include <Library/PchMultiPchBase.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+EFI_STATUS
+EFIAPI
+TypeWilsonCitySMTPeiBoardInitLibConstructor (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UBA_CONFIG_DATABASE_PPI *UbaConfigPpi;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+ UINT8 SocketIndex;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA(GuidHob);
+
+ if (PlatformInfo->BoardId == TypeWilsonCitySMT) {
+
+ DEBUG ((DEBUG_INFO, "PEI UBA init BoardId 0x%X: WilsonCitySMT\n", PlatformInfo->BoardId));
+
+ Status = PeiServicesLocatePpi (
+ &gUbaConfigDatabasePpiGuid,
+ 0,
+ NULL,
+ &UbaConfigPpi
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->InitSku (
+ UbaConfigPpi,
+ PlatformInfo->BoardId,
+ NULL,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = TypeWilsonCitySMTInstallGpioData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeWilsonCitySMTInstallPcdData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeWilsonCitySMTInstallSoftStrapData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeWilsonCitySMTPchEarlyUpdate (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeWilsonCitySMTPlatformUpdateUsbOcMappings (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeWilsonCitySMTInstallSlotTableData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeWilsonCitySMTInstallKtiEparamData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //
+ // Set default memory type connector to DimmConnectorSmt
+ //
+ (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType, sizeof (PlatformInfo->MemoryConnectorType), DimmConnectorSmt);
+
+ //
+ // Initialize InterposerType to InterposerUnknown
+ //
+ for (SocketIndex = 0; SocketIndex < MAX_SOCKET; ++SocketIndex) {
+ PlatformInfo->InterposerType[SocketIndex] = InterposerUnknown;
+ }
+
+ //
+ // TypeWilsonCitySMTIioPortBifurcationInit will use PlatformInfo->InterposerType for PPO.
+ //
+ Status = TypeWilsonCitySMTIioPortBifurcationInit (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ }
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInitLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInitLib.inf
new file mode 100644
index 0000000000..240f7f82a8
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInitLib.inf
@@ -0,0 +1,166 @@
+## @file
+# Component information file for BoardInitLib in PEI post memory phase.
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation.
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+# @par Specification Reference:
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = TypeWilsonCitySMTPeiBoardInitLib
+ FILE_GUID = 4A17DF4D-47B2-F538-CEE5-88A2FB46C5D3
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL|PEIM
+ CONSTRUCTOR = TypeWilsonCitySMTPeiBoardInitLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PeiServicesLib
+ HobLib
+ PeiServicesTablePointerLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+
+[Sources]
+ PeiBoardInitLib.c
+ GpioTable.c
+ PcdData.c
+ UsbOC.c
+ AcpiTablePcds.c
+ IioBifurInit.c
+ SlotTable.c
+ KtiEparam.c
+ PchEarlyUpdate.c
+ SoftStrapFixup.c
+ PeiBoardInit.h
+
+[FixedPcd]
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardID
+ gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardName
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel
+ gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel
+ gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed
+ gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag
+
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE
+
+ gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag
+ gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO
+ gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue
+ gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber
+ gOemSkuTokenSpaceGuid.PcdOemTableIdXhci
+ gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex
+ gPlatformTokenSpaceGuid.PcdBoardTypeBitmask
+ gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8
+ gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna
+ gEfiCpRcPkgTokenSpaceGuid.PcdImonAddr
+ gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap
+
+ gPlatformTokenSpaceGuid.PcdMemInterposerMap
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId
+
+[Ppis]
+ gUbaConfigDatabasePpiGuid
+ gDynamicSiLibraryPpiGuid ## CONSUMES
+
+[Guids]
+ gPlatformGpioInitDataGuid
+
+[Depex]
+ gDynamicSiLibraryPpiGuid
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/SlotTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/SlotTable.c
new file mode 100644
index 0000000000..e9d7c62576
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/SlotTable.c
@@ -0,0 +1,171 @@
+/** @file
+ Slot Table Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaSlotUpdateLib.h>
+#include <IioPlatformData.h>
+
+#define PCI_DEVICE_ON_BOARD_TRUE 0
+#define PCI_DEVICE_ON_BOARD_FALSE 1
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 =0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Iou3,
+ Iio_Iou4,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ Bw5_Addr_0 = 0,
+ Bw5_Addr_1,
+ Bw5_Addr_2,
+ Bw5_Addr_3,
+ Bw5_Addr_Max
+} BW5_ADDRESS;
+
+static UINT8 TypeWilsonCitySMTPchPciSlotImpementedTableData[] = {
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 0
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 1
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 2
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 3
+ PCI_DEVICE_ON_BOARD_TRUE, // Root Port 4
+ PCI_DEVICE_ON_BOARD_TRUE, // Root Port 5
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 6
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 7
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 8
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 9
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 10
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 11
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 12
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 13
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 14
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 15
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 16
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 17
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 18
+ PCI_DEVICE_ON_BOARD_FALSE // Root Port 19
+};
+
+UINT8
+GetTypeWilsonCitySMTIOU0Setting (
+ UINT8 IOU0Data
+)
+{
+ //
+ // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled.
+ //
+ IOU0Data = IIO_BIFURCATE_xxx8xxx8;
+ return IOU0Data;
+}
+
+UINT8
+GetTypeWilsonCitySMTIOU2Setting (
+ UINT8 SkuPersonalityType,
+ UINT8 IOU2Data
+)
+{
+ return IOU2Data;
+}
+
+static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeWilsonCitySMTBroadwayTable[] = {
+ {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 },
+ {Iio_Socket1, Iio_Iou1, Bw5_Addr_2},
+ {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 },
+};
+
+
+PLATFORM_SLOT_UPDATE_TABLE TypeWilsonCitySMTSlotTable =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeWilsonCitySMTBroadwayTable,
+ GetTypeWilsonCitySMTIOU0Setting,
+ 0
+};
+
+PLATFORM_SLOT_UPDATE_TABLE2 TypeWilsonCitySMTSlotTable2 =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeWilsonCitySMTBroadwayTable,
+ GetTypeWilsonCitySMTIOU0Setting,
+ 0,
+ GetTypeWilsonCitySMTIOU2Setting
+};
+
+PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE TypeWilsonCitySMTPchPciSlotImplementedTable = {
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ TypeWilsonCitySMTPchPciSlotImpementedTableData
+};
+
+/**
+ Entry point function for the PEIM
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS If we installed our PPI
+
+**/
+EFI_STATUS
+TypeWilsonCitySMTInstallSlotTableData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformSlotDataGuid,
+ &TypeWilsonCitySMTSlotTable,
+ sizeof(TypeWilsonCitySMTSlotTable)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformSlotDataGuid2,
+ &TypeWilsonCitySMTSlotTable2,
+ sizeof(TypeWilsonCitySMTSlotTable2)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPciSlotImplementedGuid,
+ &TypeWilsonCitySMTPchPciSlotImplementedTable,
+ sizeof(TypeWilsonCitySMTPchPciSlotImplementedTable)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/SoftStrapFixup.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/SoftStrapFixup.c
new file mode 100644
index 0000000000..e59e788ff0
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/SoftStrapFixup.c
@@ -0,0 +1,120 @@
+/** @file
+ Soft Strap update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaSoftStrapUpdateLib.h>
+
+PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY TypeWilsonCitySMTSoftStrapTable[] =
+{
+// SoftStrapNumber, LowBit, BitLength, Value
+ {3, 1, 1, 0x1 }, // Intel QuickAssist Endpoint 2 (EP[2]) Primary Mux Select
+ {4, 24, 1, 0x0 }, // 10 GbE MAC Power Gate Control
+ {15, 4, 2, 0x3 }, // sSATA / PCIe Select for Port 2 (SATA_PCIE_SP2)
+ {15, 6, 2, 0x1 }, // sSATA / PCIe Select for Port 3 (SATA_PCIE_SP3)
+ {15, 18, 1, 0x1 }, // Polarity of GPP_H20 (GPIO polarity of Select between sSATA Port 2 and PCIe Port 8)
+ {16, 4, 2, 0x3 }, // sSATA / PCIe GP Select for Port 2 (SATA_PCIE_GP2)
+ {16, 6, 2, 0x1 }, // sSATA / PCIe GP Select for Port 3 (SATA_PCIE_GP3)
+ {17, 6, 1, 0x0 }, // Intel (R) GbE Legacy PHY over PCIe Enabled
+ {17, 12, 2, 0x3 }, // sSATA / PCIe Combo Port 2
+ {18, 0, 2, 0x1 }, // sSATA / PCIe Combo Port 3
+ {18, 6, 2, 0x3 }, // SATA / PCIe Combo Port 0
+ {18, 8, 2, 0x3 }, // SATA / PCIe Combo Port 1
+ {18, 10, 2, 0x3 }, // SATA / PCIe Combo Port 2
+ {18, 12, 2, 0x3 }, // SATA / PCIe Combo Port 3
+ {18, 14, 2, 0x3 }, // SATA / PCIe Combo Port 4
+ {19, 2, 1, 0x1 }, // Polarity Select sSATA / PCIe Combo Port 2
+ {19, 16, 2, 0x3 }, // SATA / PCIe Combo Port 5
+ {19, 18, 2, 0x3 }, // SATA / PCIe Combo Port 6
+ {19, 20, 2, 0x3 }, // SATA / PCIe Combo Port 7
+ {19, 26, 1, 0x1 }, // Statically assign PCH PCIe NP8 Uplink to act as Downlink or Uplink(PCIEUDS)
+ {33, 24, 7, 0x17}, // IE SMLink1 I2C Target Address
+ {64, 24, 7, 0x17}, // ME SMLink1 I2C Target Address
+ {84, 24, 1, 0x0 }, // SMS1 Gbe Legacy MAC SMBus Address Enable
+ {85, 8, 3, 0x0 }, // SMS1 PMC SMBus Connect
+ {88, 8, 2, 0x3 }, // Root Port Configuration 0
+ {93, 0, 2, 0x3 }, // Flex IO Port 18 AUXILLARY Mux Select between SATA Port 0 and PCIe Port 12
+ {93, 2, 2, 0x3 }, // Flex IO Port 19 AUXILLARY Mux Select between SATA Port 1 and PCIe Port 13
+ {93, 4, 2, 0x3 }, // Flex IO Port 20 AUXILLARY Mux Select between SATA Port 2 and PCIe Port 14
+ {94, 0, 2, 0x3 }, // Flex IO Port 21 AUXILLARY Mux Select between SATA Port 3 and PCIe Port 15
+ {94, 2, 2, 0x3 }, // Flex IO Port 22 AUXILLARY Mux Select between SATA Port 4 and PCIe Port 16
+ {94, 4, 2, 0x3 }, // Flex IO Port 23 AUXILLARY Mux Select between SATA Port 5 and PCIe Port 17
+ {94, 6, 2, 0x3 }, // Flex IO Port 24 AUXILLARY Mux Select between SATA Port 6 and PCIe Port 18
+ {94, 8, 2, 0x3 }, // Flex IO Port 25 AUXILLARY Mux Select between SATA Port 7 and PCIe Port 19
+ {102, 0, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 0 and PCIe Port 12
+ {102, 2, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 1 and PCIe Port 13
+ {102, 4, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 2 and PCIe Port 14
+ {102, 6, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 3 and PCIe Port 15
+ {102, 8, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 4 and PCIe Port 16
+ {102, 10, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 5 and PCIe Port 17
+ {102, 12, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 6 and PCIe Port 18
+ {102, 14, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 7 and PCIe Port 19
+ {103, 16, 3, 0x0 }, // GbE Legacy PHY Smbus Connection
+ {103, 26, 1, 0x0 }, // GbE Legacy LCD SMBus PHY Address Enabled
+ {103, 27, 1, 0x0 }, // GbE Legacy LC SMBus Address Enabled
+// {133, 1, 1, 0x1 }, // Dual I/O Read Enabled
+// {133, 2, 1, 0x1 }, // Quad Output Read Enabled
+// {133, 3, 1, 0x1 }, // Quad I/O Read Enabled
+// {136, 10, 2, 0x3 }, // eSPI / EC Maximum I/O Mode
+// {136, 12, 1, 0x1 }, // Slave 1 (2nd eSPI device) Enable
+// {136, 16, 3, 0x4 }, // eSPI / EC Slave 1 Device Bus Frequency
+// {136, 19, 2, 0x3 }, // eSPI / EC Slave Device Maximum I/O Mode
+
+//
+// END OF LIST
+//
+ {0, 0, 0, 0}
+};
+
+UINT32
+TypeWilsonCitySMTSystemBoardRevIdValue (VOID)
+{
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT(GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return 0xFF;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA(GuidHob);
+ return PlatformInfo->TypeRevisionId;
+}
+
+VOID
+TypeWilsonCitySMTPlatformSpecificUpdate (
+ IN OUT UINT8 *FlashDescriptorCopy
+ )
+{
+}
+
+PLATFORM_PCH_SOFTSTRAP_UPDATE TypeWilsonCitySMTSoftStrapUpdate =
+{
+ PLATFORM_SOFT_STRAP_UPDATE_SIGNATURE,
+ PLATFORM_SOFT_STRAP_UPDATE_VERSION,
+ TypeWilsonCitySMTSoftStrapTable,
+ TypeWilsonCitySMTPlatformSpecificUpdate
+};
+
+EFI_STATUS
+TypeWilsonCitySMTInstallSoftStrapData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+ )
+{
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPchSoftStrapConfigDataGuid,
+ &TypeWilsonCitySMTSoftStrapUpdate,
+ sizeof(TypeWilsonCitySMTSoftStrapUpdate)
+ );
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/UsbOC.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/UsbOC.c
new file mode 100644
index 0000000000..d95fd5490e
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeWilsonCitySMT/Pei/UsbOC.c
@@ -0,0 +1,126 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+
+
+#include <Library/PcdLib.h>
+#include <Library/UbaUsbOcUpdateLib.h>
+#include <PchLimits.h>
+#include <ConfigBlock/UsbConfig.h>
+#include <ConfigBlock/Usb2PhyConfig.h>
+
+USB_OVERCURRENT_PIN TypeWilsonCitySMTUsb20OverCurrentMappings[PCH_MAX_USB2_PORTS] = {
+ UsbOverCurrentPin0,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin2,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPin7,
+ UsbOverCurrentPin7,
+ UsbOverCurrentPin6,
+ UsbOverCurrentPin4,
+ UsbOverCurrentPin6,
+ UsbOverCurrentPin4,
+ UsbOverCurrentPin5,
+ UsbOverCurrentPin4,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB_OVERCURRENT_PIN TypeWilsonCitySMTUsb30OverCurrentMappings[PCH_MAX_USB3_PORTS] = {
+ UsbOverCurrentPin0,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin2,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB2_PHY_PARAMETERS TypeWilsonCitySMTUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS] = {
+ {3, 0, 3, 1}, // PP0
+ {5, 0, 3, 1}, // PP1
+ {3, 0, 3, 1}, // PP2
+ {0, 5, 1, 1}, // PP3
+ {3, 0, 3, 1}, // PP4
+ {3, 0, 3, 1}, // PP5
+ {3, 0, 3, 1}, // PP6
+ {3, 0, 3, 1}, // PP7
+ {2, 2, 1, 0}, // PP8
+ {6, 0, 2, 1}, // PP9
+ {2, 2, 1, 0}, // PP10
+ {6, 0, 2, 1}, // PP11
+ {0, 5, 1, 1}, // PP12
+ {7, 0, 2, 1}, // PP13
+ };
+
+EFI_STATUS
+TypeWilsonCitySMTPlatformUsbOcUpdateCallback (
+ IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings,
+ IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings,
+ IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams
+)
+{
+ *Usb20OverCurrentMappings = &TypeWilsonCitySMTUsb20OverCurrentMappings[0];
+ *Usb30OverCurrentMappings = &TypeWilsonCitySMTUsb30OverCurrentMappings[0];
+
+ *Usb20AfeParams = TypeWilsonCitySMTUsb20AfeParams;
+ return EFI_SUCCESS;
+}
+
+PLATFORM_USBOC_UPDATE_TABLE TypeWilsonCitySMTUsbOcUpdate =
+{
+ PLATFORM_USBOC_UPDATE_SIGNATURE,
+ PLATFORM_USBOC_UPDATE_VERSION,
+ TypeWilsonCitySMTPlatformUsbOcUpdateCallback
+};
+
+EFI_STATUS
+TypeWilsonCitySMTPlatformUpdateUsbOcMappings (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ //#
+ //# USB, see PG 104 in GZP SCH
+ //#
+
+// USB2 USB3 Port OC
+//
+//Port00: PORT5 Back Panel ,OC0#
+//Port01: PORT2 Back Panel ,OC0#
+//Port02: PORT3 Back Panel ,OC1#
+//Port03: PORT0 NOT USED ,NA
+//Port04: BMC1.0 ,NA
+//Port05: INTERNAL_2X5_A ,OC2#
+//Port06: INTERNAL_2X5_A ,OC2#
+//Port07: NOT USED ,NA
+//Port08: EUSB (AKA SSD) ,NA
+//Port09: INTERNAL_TYPEA ,OC6#
+//Port10: PORT1 Front Panel ,OC5#
+//Port11: NOT USED ,NA
+//Port12: BMC2.0 ,NA
+//Port13: PORT4 Front Panel ,OC5#
+
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPeiPlatformUbaOcConfigDataGuid,
+ &TypeWilsonCitySMTUsbOcUpdate,
+ sizeof(TypeWilsonCitySMTUsbOcUpdate)
+ );
+
+ return Status;
+}
+
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
index 6f367b58e7..f37093bccd 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
@@ -15,6 +15,7 @@ $(RP_PKG)/Uba/BoardInit/Pei/BoardInitPei.inf {
<LibraryClasses>
NULL|$(RP_PKG)/Uba/UbaMain/TypeWilsonCityRP/Pei/PeiBoardInitLib.inf
NULL|$(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Pei/PeiBoardInitLib.inf
+ NULL|$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInitLib.inf
#
#### NO PLATFORM SPECIFIC LIBRARY CLASSES AFTER THIS LINE!!!!
#
@@ -42,3 +43,10 @@ $(RP_PKG)/Uba/UbaMain/TypeWilsonCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.i
$(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
$(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
$(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
+
+#
+# Platform TypeWilsonCitySMT
+#
+$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
+$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
+$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
--
2.27.0.windows.1


Re: [PATCH v3 1/1] MdeModulePkg/Console: Improve encoding of box drawing characters

Nate DeSimone
 

HI Caden,

You accidentally added a bunch of trailing white space on line 371, but that should be fixable during the check-in process.

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...>

-----Original Message-----
From: Caden Kline <cadenkline9@...>
Sent: Sunday, August 22, 2021 7:44 PM
To: devel@edk2.groups.io
Cc: Wang, Jian J <jian.j.wang@...>; Wu, Hao A <hao.a.wu@...>; Gao, Zhichao <zhichao.gao@...>; Ni, Ray <ray.ni@...>; Desimone, Nathaniel L <nathaniel.l.desimone@...>
Subject: [PATCH v3 1/1] MdeModulePkg/Console: Improve encoding of box drawing characters

Improved encoding of box drawing characters for different terminal types.
This includes Dec special graphics mode and more utf8.
Changes are made according to the below issue

https://bugzilla.tianocore.org/show_bug.cgi?id=3580

Cc: Jian J Wang <jian.j.wang@...>
Cc: Hao A Wu <hao.a.wu@...>
Cc: Zhichao Gao <zhichao.gao@...>
Cc: Ray Ni <ray.ni@...>
Signed-off-by: Caden Kline <cadenkline9@...>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...>
---
MdeModulePkg/Universal/Console/TerminalDxe/Terminal.h | 26 +-
MdeModulePkg/Universal/Console/TerminalDxe/Ansi.c | 2 +-
MdeModulePkg/Universal/Console/TerminalDxe/TerminalConOut.c | 295 +++++++++++++++-----
3 files changed, 243 insertions(+), 80 deletions(-)

diff --git a/MdeModulePkg/Universal/Console/TerminalDxe/Terminal.h b/MdeModulePkg/Universal/Console/TerminalDxe/Terminal.h
index 360e58e84743..1eab439531dc 100644
--- a/MdeModulePkg/Universal/Console/TerminalDxe/Terminal.h
+++ b/MdeModulePkg/Universal/Console/TerminalDxe/Terminal.h
@@ -122,7 +122,12 @@ typedef struct {
EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL SimpleInputEx;

LIST_ENTRY NotifyList;

EFI_EVENT KeyNotifyProcessEvent;

+ BOOLEAN DecSpecialGraphicsMode;

} TERMINAL_DEV;

+//

+// This the length the escape sequences for entering and exiting Dec Special Graphics Mode

+//

+#define LENGTH_DEC_ESCAPE 0x03



#define INPUT_STATE_DEFAULT 0x00

#define INPUT_STATE_ESC 0x01

@@ -169,6 +174,7 @@ typedef struct {
UINT16 Unicode;

CHAR8 PcAnsi;

CHAR8 Ascii;

+ CHAR8 DecSpecialGraphics;

} UNICODE_TO_CHAR;



//

@@ -1367,20 +1373,22 @@ Utf8ToUnicode (
/**

Detects if a Unicode char is for Box Drawing text graphics.



- @param Graphic Unicode char to test.

- @param PcAnsi Optional pointer to return PCANSI equivalent of

- Graphic.

- @param Ascii Optional pointer to return ASCII equivalent of

- Graphic.

-

- @retval TRUE If Graphic is a supported Unicode Box Drawing character.

+ @param Graphic Unicode char to test.

+ @param PcAnsi Optional pointer to return PCANSI equivalent of

+ Graphic.

+ @param Ascii Optional pointer to return ASCII equivalent of

+ Graphic.

+ @param DecSpecialGraphics Optional pointer to return Dec Special Graphics equivalent of

+ Graphic.

+ @retval TRUE If Graphic is a supported Unicode Box Drawing character.



**/

BOOLEAN

TerminalIsValidTextGraphics (

IN CHAR16 Graphic,

- OUT CHAR8 *PcAnsi, OPTIONAL

- OUT CHAR8 *Ascii OPTIONAL

+ OUT CHAR8 *PcAnsi, OPTIONAL

+ OUT CHAR8 *Ascii, OPTIONAL

+ OUT CHAR8 *DecSpecialGraphics OPTIONAL

);



/**

diff --git a/MdeModulePkg/Universal/Console/TerminalDxe/Ansi.c b/MdeModulePkg/Universal/Console/TerminalDxe/Ansi.c
index f117d90b9de3..5ae5a4f0212e 100644
--- a/MdeModulePkg/Universal/Console/TerminalDxe/Ansi.c
+++ b/MdeModulePkg/Universal/Console/TerminalDxe/Ansi.c
@@ -63,7 +63,7 @@ AnsiTestString (


if ( !(TerminalIsValidAscii (*WString) ||

TerminalIsValidEfiCntlChar (*WString) ||

- TerminalIsValidTextGraphics (*WString, &GraphicChar, NULL) )) {

+ TerminalIsValidTextGraphics (*WString, &GraphicChar, NULL, NULL) )) {



return EFI_UNSUPPORTED;

}

diff --git a/MdeModulePkg/Universal/Console/TerminalDxe/TerminalConOut.c b/MdeModulePkg/Universal/Console/TerminalDxe/TerminalConOut.c
index aae470e9562c..7b328162325e 100644
--- a/MdeModulePkg/Universal/Console/TerminalDxe/TerminalConOut.c
+++ b/MdeModulePkg/Universal/Console/TerminalDxe/TerminalConOut.c
@@ -16,61 +16,59 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
//

//

UNICODE_TO_CHAR UnicodeToPcAnsiOrAscii[] = {

- { BOXDRAW_HORIZONTAL, 0xc4, L'-' },

- { BOXDRAW_VERTICAL, 0xb3, L'|' },

- { BOXDRAW_DOWN_RIGHT, 0xda, L'/' },

- { BOXDRAW_DOWN_LEFT, 0xbf, L'\\' },

- { BOXDRAW_UP_RIGHT, 0xc0, L'\\' },

- { BOXDRAW_UP_LEFT, 0xd9, L'/' },

- { BOXDRAW_VERTICAL_RIGHT, 0xc3, L'|' },

- { BOXDRAW_VERTICAL_LEFT, 0xb4, L'|' },

- { BOXDRAW_DOWN_HORIZONTAL, 0xc2, L'+' },

- { BOXDRAW_UP_HORIZONTAL, 0xc1, L'+' },

- { BOXDRAW_VERTICAL_HORIZONTAL, 0xc5, L'+' },

- { BOXDRAW_DOUBLE_HORIZONTAL, 0xcd, L'-' },

- { BOXDRAW_DOUBLE_VERTICAL, 0xba, L'|' },

- { BOXDRAW_DOWN_RIGHT_DOUBLE, 0xd5, L'/' },

- { BOXDRAW_DOWN_DOUBLE_RIGHT, 0xd6, L'/' },

- { BOXDRAW_DOUBLE_DOWN_RIGHT, 0xc9, L'/' },

- { BOXDRAW_DOWN_LEFT_DOUBLE, 0xb8, L'\\' },

- { BOXDRAW_DOWN_DOUBLE_LEFT, 0xb7, L'\\' },

- { BOXDRAW_DOUBLE_DOWN_LEFT, 0xbb, L'\\' },

- { BOXDRAW_UP_RIGHT_DOUBLE, 0xd4, L'\\' },

- { BOXDRAW_UP_DOUBLE_RIGHT, 0xd3, L'\\' },

- { BOXDRAW_DOUBLE_UP_RIGHT, 0xc8, L'\\' },

- { BOXDRAW_UP_LEFT_DOUBLE, 0xbe, L'/' },

- { BOXDRAW_UP_DOUBLE_LEFT, 0xbd, L'/' },

- { BOXDRAW_DOUBLE_UP_LEFT, 0xbc, L'/' },

- { BOXDRAW_VERTICAL_RIGHT_DOUBLE, 0xc6, L'|' },

- { BOXDRAW_VERTICAL_DOUBLE_RIGHT, 0xc7, L'|' },

- { BOXDRAW_DOUBLE_VERTICAL_RIGHT, 0xcc, L'|' },

- { BOXDRAW_VERTICAL_LEFT_DOUBLE, 0xb5, L'|' },

- { BOXDRAW_VERTICAL_DOUBLE_LEFT, 0xb6, L'|' },

- { BOXDRAW_DOUBLE_VERTICAL_LEFT, 0xb9, L'|' },

- { BOXDRAW_DOWN_HORIZONTAL_DOUBLE, 0xd1, L'+' },

- { BOXDRAW_DOWN_DOUBLE_HORIZONTAL, 0xd2, L'+' },

- { BOXDRAW_DOUBLE_DOWN_HORIZONTAL, 0xcb, L'+' },

- { BOXDRAW_UP_HORIZONTAL_DOUBLE, 0xcf, L'+' },

- { BOXDRAW_UP_DOUBLE_HORIZONTAL, 0xd0, L'+' },

- { BOXDRAW_DOUBLE_UP_HORIZONTAL, 0xca, L'+' },

- { BOXDRAW_VERTICAL_HORIZONTAL_DOUBLE, 0xd8, L'+' },

- { BOXDRAW_VERTICAL_DOUBLE_HORIZONTAL, 0xd7, L'+' },

- { BOXDRAW_DOUBLE_VERTICAL_HORIZONTAL, 0xce, L'+' },

+ { BOXDRAW_HORIZONTAL, 0xc4, L'-', 0x71 },

+ { BOXDRAW_VERTICAL, 0xb3, L'|', 0x78 },

+ { BOXDRAW_DOWN_RIGHT, 0xda, L'/', 0x6c },

+ { BOXDRAW_DOWN_LEFT, 0xbf, L'\\', 0x6b },

+ { BOXDRAW_UP_RIGHT, 0xc0, L'\\', 0x6d },

+ { BOXDRAW_UP_LEFT, 0xd9, L'/', 0x6a },

+ { BOXDRAW_VERTICAL_RIGHT, 0xc3, L'|', 0x74 },

+ { BOXDRAW_VERTICAL_LEFT, 0xb4, L'|', 0x75 },

+ { BOXDRAW_DOWN_HORIZONTAL, 0xc2, L'+', 0x77 },

+ { BOXDRAW_UP_HORIZONTAL, 0xc1, L'+', 0x76 },

+ { BOXDRAW_VERTICAL_HORIZONTAL, 0xc5, L'+', 0x6e },

+ { BOXDRAW_DOUBLE_HORIZONTAL, 0xcd, L'-', 0x71 },

+ { BOXDRAW_DOUBLE_VERTICAL, 0xba, L'|', 0x78 },

+ { BOXDRAW_DOWN_RIGHT_DOUBLE, 0xd5, L'/', 0x6c },

+ { BOXDRAW_DOWN_DOUBLE_RIGHT, 0xd6, L'/', 0x6c },

+ { BOXDRAW_DOUBLE_DOWN_RIGHT, 0xc9, L'/', 0x6c },

+ { BOXDRAW_DOWN_LEFT_DOUBLE, 0xb8, L'\\', 0x6b },

+ { BOXDRAW_DOWN_DOUBLE_LEFT, 0xb7, L'\\', 0x6b },

+ { BOXDRAW_DOUBLE_DOWN_LEFT, 0xbb, L'\\', 0x6b },

+ { BOXDRAW_UP_RIGHT_DOUBLE, 0xd4, L'\\', 0x6d },

+ { BOXDRAW_UP_DOUBLE_RIGHT, 0xd3, L'\\', 0x6d },

+ { BOXDRAW_DOUBLE_UP_RIGHT, 0xc8, L'\\', 0x6d },

+ { BOXDRAW_UP_LEFT_DOUBLE, 0xbe, L'/', 0x6a },

+ { BOXDRAW_UP_DOUBLE_LEFT, 0xbd, L'/', 0x6a },

+ { BOXDRAW_DOUBLE_UP_LEFT, 0xbc, L'/', 0x6a },

+ { BOXDRAW_VERTICAL_RIGHT_DOUBLE, 0xc6, L'|', 0x74 },

+ { BOXDRAW_VERTICAL_DOUBLE_RIGHT, 0xc7, L'|', 0x74 },

+ { BOXDRAW_DOUBLE_VERTICAL_RIGHT, 0xcc, L'|', 0x74 },

+ { BOXDRAW_VERTICAL_LEFT_DOUBLE, 0xb5, L'|', 0x75 },

+ { BOXDRAW_VERTICAL_DOUBLE_LEFT, 0xb6, L'|', 0x75 },

+ { BOXDRAW_DOUBLE_VERTICAL_LEFT, 0xb9, L'|', 0x75 },

+ { BOXDRAW_DOWN_HORIZONTAL_DOUBLE, 0xd1, L'+', 0x77 },

+ { BOXDRAW_DOWN_DOUBLE_HORIZONTAL, 0xd2, L'+', 0x77 },

+ { BOXDRAW_DOUBLE_DOWN_HORIZONTAL, 0xcb, L'+', 0x77 },

+ { BOXDRAW_UP_HORIZONTAL_DOUBLE, 0xcf, L'+', 0x76 },

+ { BOXDRAW_UP_DOUBLE_HORIZONTAL, 0xd0, L'+', 0x76 },

+ { BOXDRAW_DOUBLE_UP_HORIZONTAL, 0xca, L'+', 0x76 },

+ { BOXDRAW_VERTICAL_HORIZONTAL_DOUBLE, 0xd8, L'+', 0x6e },

+ { BOXDRAW_VERTICAL_DOUBLE_HORIZONTAL, 0xd7, L'+', 0x6e },

+ { BOXDRAW_DOUBLE_VERTICAL_HORIZONTAL, 0xce, L'+', 0x6e },



- { BLOCKELEMENT_FULL_BLOCK, 0xdb, L'*' },

- { BLOCKELEMENT_LIGHT_SHADE, 0xb0, L'+' },

+ { BLOCKELEMENT_FULL_BLOCK, 0xdb, L'*', 0x61 },

+ { BLOCKELEMENT_LIGHT_SHADE, 0xb0, L'+', 0x61 },



- { GEOMETRICSHAPE_UP_TRIANGLE, '^', L'^' },

- { GEOMETRICSHAPE_RIGHT_TRIANGLE, '>', L'>' },

- { GEOMETRICSHAPE_DOWN_TRIANGLE, 'v', L'v' },

- { GEOMETRICSHAPE_LEFT_TRIANGLE, '<', L'<' },

+ { GEOMETRICSHAPE_UP_TRIANGLE, '^', L'^', L'^' },

+ { GEOMETRICSHAPE_RIGHT_TRIANGLE, '>', L'>', L'>' },

+ { GEOMETRICSHAPE_DOWN_TRIANGLE, 'v', L'v', L'v' },

+ { GEOMETRICSHAPE_LEFT_TRIANGLE, '<', L'<', L'<' },



- { ARROW_LEFT, '<', L'<' },

- { ARROW_UP, '^', L'^' },

- { ARROW_RIGHT, '>', L'>' },

- { ARROW_DOWN, 'v', L'v' },

-

- { 0x0000, 0x00, L'\0' }

+ { ARROW_LEFT, '<', L'<', L'<' },

+ { ARROW_UP, '^', L'^', L'^' },

+ { ARROW_RIGHT, '>', L'>', L'>' },

+ { ARROW_DOWN, 'v', L'v', L'v' },

};



CHAR16 mSetModeString[] = { ESC, '[', '=', '3', 'h', 0 };

@@ -80,6 +78,8 @@ CHAR16 mSetCursorPositionString[] = { ESC, '[', '0', '0', ';', '0', '0', 'H', 0
CHAR16 mCursorForwardString[] = { ESC, '[', '0', '0', 'C', 0 };

CHAR16 mCursorBackwardString[] = { ESC, '[', '0', '0', 'D', 0 };



+CHAR8 SetDecModeString[] = {ESC, 0x28, 0x30};

+CHAR8 ExitDecModeString[] = {ESC, 0x28, 0x42};

//

// Body of the ConOut functions

//

@@ -183,16 +183,19 @@ TerminalConOutOutputString (
EFI_STATUS Status;

UINT8 ValidBytes;

CHAR8 CrLfStr[2];

+ CHAR8 DecChar;

+ UINTN ModeSwitchLength;

//

// flag used to indicate whether condition happens which will cause

// return EFI_WARN_UNKNOWN_GLYPH

//

BOOLEAN Warning;



- ValidBytes = 0;

- Warning = FALSE;

- AsciiChar = 0;

-

+ ValidBytes = 0;

+ Warning = FALSE;

+ AsciiChar = 0;

+ DecChar = 0;

+ ModeSwitchLength = LENGTH_DEC_ESCAPE;

//

// get Terminal device data structure pointer.

//

@@ -217,17 +220,104 @@ TerminalConOutOutputString (
for (; *WString != CHAR_NULL; WString++) {



switch (TerminalDevice->TerminalType) {

-

case TerminalTypePcAnsi:

- case TerminalTypeVt100:

- case TerminalTypeVt100Plus:

- case TerminalTypeTtyTerm:

- case TerminalTypeLinux:

+ if (!TerminalIsValidTextGraphics (*WString, &GraphicChar, &AsciiChar, NULL)) {

+ //

+ // If it's not a graphic character convert Unicode to ASCII.

+ //

+ GraphicChar = (CHAR8)*WString;

+

+ if (!(TerminalIsValidAscii (GraphicChar) || TerminalIsValidEfiCntlChar (GraphicChar))) {

+ //

+ // when this driver use the OutputString to output control string,

+ // TerminalDevice->OutputEscChar is set to let the Esc char

+ // to be output to the terminal emulation software.

+ //

+ if ((GraphicChar == ESC) && TerminalDevice->OutputEscChar) {

+ GraphicChar = ESC;

+ } else {

+ GraphicChar = '?';

+ Warning = TRUE;

+ }

+ }

+

+ AsciiChar = GraphicChar;

+ }

+ Length = 1;

+ Status = TerminalDevice->SerialIo->Write (

+ TerminalDevice->SerialIo,

+ &Length,

+ &GraphicChar

+ );

+

+ if (EFI_ERROR (Status)) {

+ goto OutputError;

+ }

+

+ break;

case TerminalTypeXtermR6:

- case TerminalTypeVt400:

case TerminalTypeSCO:

+ //

+ // Box graphics are split into 2 types simple and advanced.

+ // Simple are drawn with dec special graphics.

+ // Advanced are drawn with utf8.

+ // This checks for simple because they have a lower value than the advanced.

+ //

+ if (TerminalIsValidTextGraphics (*WString, NULL, NULL, &DecChar) && *WString < BOXDRAW_DOUBLE_HORIZONTAL) {

+ if (!TerminalDevice->DecSpecialGraphicsMode) {

+ ModeSwitchLength = LENGTH_DEC_ESCAPE;

+ Status = TerminalDevice->SerialIo->Write (

+ TerminalDevice->SerialIo,

+ &ModeSwitchLength,

+ (UINT8 *)SetDecModeString

+ );

+ if (EFI_ERROR (Status)) {

+ goto OutputError;

+ }

+ TerminalDevice->DecSpecialGraphicsMode = TRUE;

+ }



- if (!TerminalIsValidTextGraphics (*WString, &GraphicChar, &AsciiChar)) {

+ GraphicChar = DecChar;

+ Length = 1;

+ } else {

+ if (TerminalDevice->DecSpecialGraphicsMode) {

+ Status = TerminalDevice->SerialIo->Write (

+ TerminalDevice->SerialIo,

+ &ModeSwitchLength,

+ (UINT8 *)ExitDecModeString

+ );

+ if (EFI_ERROR (Status)) {

+ goto OutputError;

+ }

+

+ TerminalDevice->DecSpecialGraphicsMode = FALSE;

+ }

+ UnicodeToUtf8 (*WString, &Utf8Char, &ValidBytes);

+ Length = ValidBytes;

+ }

+

+ if (ValidBytes) {

+ Status = TerminalDevice->SerialIo->Write (

+ TerminalDevice->SerialIo,

+ &Length,

+ (UINT8 *)&Utf8Char

+ );

+ ValidBytes = 0;

+ } else {

+ Status = TerminalDevice->SerialIo->Write (

+ TerminalDevice->SerialIo,

+ &Length,

+ &GraphicChar

+ );

+ }

+ if (EFI_ERROR (Status)) {

+ goto OutputError;

+ }

+

+ break;

+ case TerminalTypeVt100:

+ case TerminalTypeTtyTerm:

+ if (!TerminalIsValidTextGraphics (*WString, &GraphicChar, &AsciiChar, NULL)) {

//

// If it's not a graphic character convert Unicode to ASCII.

//

@@ -239,8 +329,8 @@ TerminalConOutOutputString (
// TerminalDevice->OutputEscChar is set to let the Esc char

// to be output to the terminal emulation software.

//

- if ((GraphicChar == 27) && TerminalDevice->OutputEscChar) {

- GraphicChar = 27;

+ if ((GraphicChar == ESC) && TerminalDevice->OutputEscChar) {

+ GraphicChar = ESC;

} else {

GraphicChar = '?';

Warning = TRUE;

@@ -248,14 +338,73 @@ TerminalConOutOutputString (
}



AsciiChar = GraphicChar;

-

}



- if (TerminalDevice->TerminalType != TerminalTypePcAnsi) {

- GraphicChar = AsciiChar;

+ GraphicChar = AsciiChar;

+

+ Length = 1;

+

+ Status = TerminalDevice->SerialIo->Write (

+ TerminalDevice->SerialIo,

+ &Length,

+ &GraphicChar

+ );

+

+ if (EFI_ERROR (Status)) {

+ goto OutputError;

}



+ break;

+ case TerminalTypeVt100Plus:

+ case TerminalTypeVt400:

Length = 1;

+ if (TerminalIsValidTextGraphics (*WString, NULL, NULL, &DecChar)) {

+ if (!TerminalDevice->DecSpecialGraphicsMode) {

+ ModeSwitchLength = LENGTH_DEC_ESCAPE;

+ Status = TerminalDevice->SerialIo->Write (

+ TerminalDevice->SerialIo,

+ &ModeSwitchLength,

+ (UINT8 *)SetDecModeString

+ );

+ if (EFI_ERROR (Status)) {

+ goto OutputError;

+ }

+ TerminalDevice->DecSpecialGraphicsMode = TRUE;

+ }

+

+ GraphicChar = DecChar;

+ } else {

+ if (TerminalDevice->DecSpecialGraphicsMode) {

+ ModeSwitchLength = LENGTH_DEC_ESCAPE;

+ Status = TerminalDevice->SerialIo->Write (

+ TerminalDevice->SerialIo,

+ &ModeSwitchLength,

+ (UINT8 *)ExitDecModeString

+ );

+

+ if (EFI_ERROR (Status)) {

+ goto OutputError;

+ }

+

+ TerminalDevice->DecSpecialGraphicsMode = FALSE;

+ }

+

+ GraphicChar = (CHAR8)*WString;

+

+ if (!(TerminalIsValidAscii (GraphicChar) || TerminalIsValidEfiCntlChar (GraphicChar))) {

+ //

+ // when this driver use the OutputString to output control string,

+ // TerminalDevice->OutputEscChar is set to let the Esc char

+ // to be output to the terminal emulation software.

+ //

+ if ((GraphicChar == ESC) && TerminalDevice->OutputEscChar) {

+ GraphicChar = ESC;

+ } else {

+ GraphicChar = '?';

+ Warning = TRUE;

+ }

+ }

+ }



Status = TerminalDevice->SerialIo->Write (

TerminalDevice->SerialIo,

@@ -268,7 +417,7 @@ TerminalConOutOutputString (
}



break;

-

+ case TerminalTypeLinux:

case TerminalTypeVtUtf8:

UnicodeToUtf8 (*WString, &Utf8Char, &ValidBytes);

Length = ValidBytes;

@@ -280,8 +429,10 @@ TerminalConOutOutputString (
if (EFI_ERROR (Status)) {

goto OutputError;

}

+

break;

}

+

//

// Update cursor position.

//

@@ -875,7 +1026,8 @@ BOOLEAN
TerminalIsValidTextGraphics (

IN CHAR16 Graphic,

OUT CHAR8 *PcAnsi, OPTIONAL

- OUT CHAR8 *Ascii OPTIONAL

+ OUT CHAR8 *Ascii, OPTIONAL

+ OUT CHAR8 *DecSpecialGraphics OPTIONAL

)

{

UNICODE_TO_CHAR *Table;

@@ -897,6 +1049,9 @@ TerminalIsValidTextGraphics (
if (Ascii != NULL) {

*Ascii = Table->Ascii;

}

+ if (DecSpecialGraphics != NULL){

+ *DecSpecialGraphics = Table->DecSpecialGraphics;

+ }



return TRUE;

}

--
2.33.0


Re: [edk2-platforms][PATCH v3 0/7] KabylakeOpenBoardPkg: Add AspireVn7Dash572G

Nate DeSimone
 

Hi Benjamin,

 

Sounds good. I have pushed your patch.

 

Thanks,

Nate

 

From: Benjamin Doron <benjamin.doron00@...>
Sent: Wednesday, August 25, 2021 9:09 PM
To: Desimone, Nathaniel L <nathaniel.l.desimone@...>
Cc: devel@edk2.groups.io
Subject: Re: [edk2-devel] [edk2-platforms][PATCH v3 0/7] KabylakeOpenBoardPkg: Add AspireVn7Dash572G

 

Hi Nate,

Thanks for addressing the comment for me with https://edk2.groups.io/g/devel/message/79830.

 

Regarding copyrighting: I am not a lawyer and was unaware that a copyright was necessary. But if it's necessary for legal reasons, very well.

 

However, I suppose I will need to put my legal name on the copyrights, which is "Baruch Binyamin Doron." I'll send a patch as a fix-up for this?

 

Best regards,

Benjamin

 

 

On Wed, Aug 25, 2021 at 11:58 PM Desimone, Nathaniel L <nathaniel.l.desimone@...> wrote:

Hi Benjamin,

I have sent a separate patch to correct the comment that Michael pointed out: https://edk2.groups.io/g/devel/message/79830

For legal reasons I actually have to put "Copyright (c) 2021, Benjamin Doran" on the files that are brand new and are not a derivative of an existing file.

The reason for this is because in order to apply the BSD+Patent license, the code in question must be copyrighted. Without a copyright, the code would be considered part of the public domain, making it legally impossible to license it. In order for something to be copyrighted, it must be "owned" by a legal entity. Since the TianoCore project does not have a non-profit foundation representing it, from a legal perspective TianoCore does not actually exist as a legal entity. We workaround this by having the contributors to TianoCore copyright the code that they work on. This is only a problem for the files which Intel cannot claim a copyright on since we did no work there.

Accordingly, I have placed "Copyright (c) 2021, Benjamin Doran" into the header of the following files:

 * Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf
 * Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl
 * Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl
 * Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl
 * Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl
 * Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl
 * Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl
 * Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c
 * Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h
 * Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf
 * Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c
 * Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.c
 * Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.inf
 * Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c

I hope that is OK.

Thanks,
Nate

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Benjamin Doron
Sent: Wednesday, August 18, 2021 11:49 AM
To: devel@edk2.groups.io
Subject: [edk2-devel] [edk2-platforms][PATCH v3 0/7] KabylakeOpenBoardPkg: Add AspireVn7Dash572G

This patchset adds support for a Acer Aspire VN7-572G (SKL-U laptop) board to KabylakeOpenBoardPkg, based on Kabylake RVP 3. As stated in a later commit message, there is a second, similar board: VN7-792G.
- VN7-572G = "Rayleigh". Working, supported. Uses PCH-LP.
- VN7-792G = "Newgate". Assumed broken, not supported. Uses PCH-H.
  Also known as the "Black Edition" of the Aspire V Nitro.

Because VN7-792G uses a different PCH, routing and GPIO configuration are assumed to be different. Users are strongly warned against attempting to flash images to VN7-792G at this time. Support may be added later by reverse engineering, but logs from a running system will help.

Additional build depedencies:
- https://github.com/benjamindoron/edk2-non-osi/commit/7bf736989159b74012d9bf3a13a9f941036be97a
- https://github.com/benjamindoron/edk2/commit/db888a928c1c6fc94f6a7670f3402718c10c01d2

V2 changes:
- Whitespace changes and changes for coding guidelines compliance
- KabylakeOpenBoardPkg changes merged into "duplicate KabylakeRvp3"
  commit
- EC (ACPI): LGMR hooked-up (disabled), other changes.
- FSP-S configuration: Drop thermal changes not set by board, do not
  override UART2 mode (PCI by policy)
  - Set DspEndpointDmic so FSP produces correct configuration in HOB for
    PchInitDxe. (However, 1ch array DMIC may not be supported by the
    Linux driver. Also, presently NHLT is not installed in any case:
    DspEnable=0 in HOB.)
- Avoid indirect function calls for GPIO configuration and deduplicate
  HSIO tables
- Make board detection work and parse PCB version information
- Begin working on hardening platform and improving PCD
  - DXE stack guard, NX for stack, NULL pointer detection (DXE NX is
    broken)
  - Measure FSP to TPM (presently skipping FSP-S, there may be a bug
    where the first TPM command from this time will timeout waiting for
    goIdle)
  - UGA draw protocol and HII OS runtime disabled, fast PS/2 detection

V3 changes:
- Remove Intel Corporation copyright from header of new files (ACPI
  tables, BoardEcLib, board-specific policy)
- More whitespace changes and add more descriptive comments for EC and
  ACPI: particularly regarding reverse engineering work
- Address feedback on V2
- Use return values more and add more debug prints
- Finalise EC initialisation/notification function (now after FSP-S),
  which drops commented coreboot library functions from the beginning of
  porting
- Can perform EC time update (now in DXE). All commented coreboot
  function calls are now removed

Benjamin Doron (7):
  KabylakeOpenBoardPkg/BaseEcLib: Add some common EC commands
  KabylakeOpenBoardPkg/AspireVn7Dash572G: Duplicate KabylakeRvp3
    directory
  KabylakeOpenBoardPkg/AspireVn7Dash572G: Rename KabylakeRvp3 files
  Platform/Intel: Early hook-up Acer Aspire VN7-572G
  KabylakeOpenBoardPkg/AspireVn7Dash572G: Add initial support
  Maintainers.txt: Add myself as reviewer for AspireVn7Dash572G board
  Platform/Intel/Readme.md: Add AspireVn7Dash572G to supported boards

 Maintainers.txt                                                                                                                        |   4 +
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf                                                         |  16 +
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl                                                               |  33 +
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl                                                                      |  16 +
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl                                                                 | 408 +++++++++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl                                                                      | 439 ++++++++++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl                                                               |  79 +++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl                                                                 | 117 ++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c                | 104 +++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c           | 285 ++++++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c         |  82 +++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c          | 213 ++++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c             | 139 ++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h             |  26 +
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c       | 243 +++++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c              |  77 ++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h              |  29 +
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c        |  66 ++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf | 144 ++++
 Platform/Intel/KabylakeOpenBoardPkg/{KabylakeRvp3 => AspireVn7Dash572G}/Include/EcCommands.h                                           |   7 +-
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMapInclude.fdf                                                  |  50 ++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h                                                     | 104 +++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeAspireVn7Dash572GAcpiTableLib.c                          |  74 ++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c                                      |  28 +
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf                                    |  47 ++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmAspireVn7Dash572GAcpiEnableLib.c                         |  68 ++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c                                     |  55 ++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf                                   |  45 ++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c                                   | 165 +++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf                                                |  26 +
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c                                                  | 215 ++++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GGpioTable.c                                | 396 +++++++++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHdaVerbTables.c                            | 202 ++++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHsioPtssTables.c                           |  26 +
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.c                                           | 120 ++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.inf                                         |  28 +
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GDetect.c                                |  90 +++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitLib.h                               |  33 +
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPostMemLib.c                        | 157 +++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c                         | 292 ++++++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.c                                    |  40 ++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.inf                                  |  52 ++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.c                                     |  99 +++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf                                   | 125 ++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc                                                                 | 681 ++++++++++++++++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf                                                                 | 733 ++++++++++++++++++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBuildOption.dsc                                                      | 149 ++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc                                                              | 546 +++++++++++++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c                      | 185 +++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h                      |  37 +
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h                       |  63 ++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c                     |  63 ++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c             |  74 ++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf           |  52 ++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c                  | 328 +++++++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c             | 642 +++++++++++++++++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf           | 107 +++
 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg                                                                 |  34 +
 Platform/Intel/KabylakeOpenBoardPkg/Include/Library/EcLib.h                                                                            |  32 +
 Platform/Intel/KabylakeOpenBoardPkg/Include/PlatformBoardId.h                                                                          |   2 +
 Platform/Intel/KabylakeOpenBoardPkg/KabylakeRvp3/Include/EcCommands.h                                                                  |   2 +
 Platform/Intel/KabylakeOpenBoardPkg/Library/BaseEcLib/BaseEcLib.c                                                                      |   4 +-
 Platform/Intel/KabylakeOpenBoardPkg/Library/BaseEcLib/BaseEcLib.inf                                                                    |   1 +
 Platform/Intel/KabylakeOpenBoardPkg/Library/BaseEcLib/EcCommands.c                                                                     |  76 ++
 Platform/Intel/KabylakeOpenBoardPkg/OpenBoardPkg.dec                                                                                   |   1 +
 Platform/Intel/Readme.md                                                                                                               |   8 +
 Platform/Intel/build.cfg                                                                                                               |   1 +
 67 files changed, 8883 insertions(+), 2 deletions(-)  create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PcieDeviceTable.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspMiscUpdUpdateLib.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiFspPolicyUpdateLib.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdate.h
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiPchPolicyUpdatePreMem.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdate.h
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSaPolicyUpdatePreMem.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiSiliconPolicyUpdateLibFsp.inf
 copy Platform/Intel/KabylakeOpenBoardPkg/{KabylakeRvp3 => AspireVn7Dash572G}/Include/EcCommands.h (74%)  create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Fdf/FlashMapInclude.fdf
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeAspireVn7Dash572GAcpiTableLib.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/DxeBoardAcpiTableLib.inf
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmAspireVn7Dash572GAcpiEnableLib.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GGpioTable.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHdaVerbTables.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/AspireVn7Dash572GHsioPtssTables.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.inf
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GDetect.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitLib.h
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPostMemLib.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiAspireVn7Dash572GInitPreMemLib.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPostMemLib.inf
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/PeiBoardInitPreMemLib.inf
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.dsc
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkg.fdf
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgBuildOption.dsc
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/OpenBoardPkgPcd.dsc
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.h
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.h
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyUpdate.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.c
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiSiliconPolicyUpdateLib.inf
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/build_config.cfg
 create mode 100644 Platform/Intel/KabylakeOpenBoardPkg/Library/BaseEcLib/EcCommands.c

--
2.31.1






Re: [edk2-platforms][PATCH v1] KabylakeOpenBoardPkg/AspireVn7Dash572G: Correct my name on copyrights

Nate DeSimone
 

-----Original Message-----
From: Benjamin Doron <benjamin.doron00@...>
Sent: Thursday, August 26, 2021 9:49 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@...>; Desimone, Nathaniel L <nathaniel.l.desimone@...>
Subject: [edk2-platforms][PATCH v1] KabylakeOpenBoardPkg/AspireVn7Dash572G: Correct my name on copyrights

Use my correct, legal name for copyright purposes.

Cc: Chasel Chiu <chasel.chiu@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Signed-off-by: Benjamin Doron <benjamin.doron00@...>
---
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.c | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.inf | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c | 2 +-
14 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf
index 2bfad5c86403..806c0d2575c8 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf
@@ -1,7 +1,7 @@
## @file

# Component description file for the Acer Aspire VN7-572G board ACPI tables

#

-# Copyright (c) 2021, Benjamin Doran

+# Copyright (c) 2021, Baruch Binyamin Doron

# SPDX-License-Identifier: BSD-2-Clause-Patent

#

##

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl
index 77f869492989..cdec0434883e 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl
@@ -1,7 +1,7 @@
/** @file

This file contains the Aspire VN7-572G SSDT Table ASL code.



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl
index 7253915d6cc1..126c5b53a470 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl
@@ -1,6 +1,6 @@
/** @file



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl
index 72dc036eb7aa..5ae4bdca89d5 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl
@@ -1,6 +1,6 @@
/** @file



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl
index bc1e612a92fc..df71dd69b491 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl
@@ -1,6 +1,6 @@
/** @file



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl
index 9febe7c385a8..7a73d37429d0 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl
@@ -1,6 +1,6 @@
/** @file



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl
index f829c62020d2..805ee0700cd0 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl
@@ -1,6 +1,6 @@
/** @file



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c
index c8ab26eaf645..81cd8b940f05 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c
@@ -1,7 +1,7 @@
/** @file

This file configures Aspire VN7-572G board-specific FSP UPDs.



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h
index c99adc189745..2e7e0573900a 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h
@@ -1,7 +1,7 @@
/** @file

Board-specific EC library



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf
index 01fee8916b36..56527c3b9a3c 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf
@@ -1,7 +1,7 @@
## @file

# Component information file for Aspire VN7-572G EC library

#

-# Copyright (c) 2021, Benjamin Doran

+# Copyright (c) 2021, Baruch Binyamin Doron

# SPDX-License-Identifier: BSD-2-Clause-Patent

#

##

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c
index 7650a6b21575..09b2b5ee9180 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c
@@ -1,7 +1,7 @@
/** @file

Board-specific EC commands.



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.c
index 1281391ed36f..906b2d265092 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.c
@@ -1,7 +1,7 @@
/** @file

Aspire VN7-572G Board Initialization DXE library



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.inf
index 000ec8a1b56d..9a868ee15fb2 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.inf
@@ -1,7 +1,7 @@
## @file

# Component information file for AspireVn7Dash572GInitLib in DXE phase.

#

-# Copyright (c) 2021, Benjamin Doran

+# Copyright (c) 2021, Baruch Binyamin Doron

# SPDX-License-Identifier: BSD-2-Clause-Patent

#

##

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c
index b72bc56f1d0d..95b7c4ad5f77 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c
@@ -1,7 +1,7 @@
/** @file

This file configures Aspire VN7-572G board-specific policies.



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

--
2.31.1


Re: [edk2-platforms][PATCH v1] KabylakeOpenBoardPkg/AspireVn7Dash572G: Correct my name on copyrights

Nate DeSimone
 

Reviewed-by: Nate DeSimone <nathaniel.l.desimone@...>

-----Original Message-----
From: Benjamin Doron <benjamin.doron00@...>
Sent: Thursday, August 26, 2021 9:49 AM
To: devel@edk2.groups.io
Cc: Chiu, Chasel <chasel.chiu@...>; Desimone, Nathaniel L <nathaniel.l.desimone@...>
Subject: [edk2-platforms][PATCH v1] KabylakeOpenBoardPkg/AspireVn7Dash572G: Correct my name on copyrights

Use my correct, legal name for copyright purposes.

Cc: Chasel Chiu <chasel.chiu@...>
Cc: Nate DeSimone <nathaniel.l.desimone@...>
Signed-off-by: Benjamin Doron <benjamin.doron00@...>
---
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.c | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.inf | 2 +-
Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c | 2 +-
14 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf
index 2bfad5c86403..806c0d2575c8 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardAcpiTables.inf
@@ -1,7 +1,7 @@
## @file

# Component description file for the Acer Aspire VN7-572G board ACPI tables

#

-# Copyright (c) 2021, Benjamin Doran

+# Copyright (c) 2021, Baruch Binyamin Doron

# SPDX-License-Identifier: BSD-2-Clause-Patent

#

##

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl
index 77f869492989..cdec0434883e 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/BoardSsdt.asl
@@ -1,7 +1,7 @@
/** @file

This file contains the Aspire VN7-572G SSDT Table ASL code.



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl
index 7253915d6cc1..126c5b53a470 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ac.asl
@@ -1,6 +1,6 @@
/** @file



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl
index 72dc036eb7aa..5ae4bdca89d5 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/battery.asl
@@ -1,6 +1,6 @@
/** @file



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl
index bc1e612a92fc..df71dd69b491 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/ec.asl
@@ -1,6 +1,6 @@
/** @file



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl
index 9febe7c385a8..7a73d37429d0 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/mainboard.asl
@@ -1,6 +1,6 @@
/** @file



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl
index f829c62020d2..805ee0700cd0 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Acpi/thermal.asl
@@ -1,6 +1,6 @@
/** @file



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c
index c8ab26eaf645..81cd8b940f05 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/FspWrapper/Library/PeiSiliconPolicyUpdateLibFsp/PeiBoardPolicyUpdate.c
@@ -1,7 +1,7 @@
/** @file

This file configures Aspire VN7-572G board-specific FSP UPDs.



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h
index c99adc189745..2e7e0573900a 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Include/Library/BoardEcLib.h
@@ -1,7 +1,7 @@
/** @file

Board-specific EC library



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf
index 01fee8916b36..56527c3b9a3c 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/BoardEcLib.inf
@@ -1,7 +1,7 @@
## @file

# Component information file for Aspire VN7-572G EC library

#

-# Copyright (c) 2021, Benjamin Doran

+# Copyright (c) 2021, Baruch Binyamin Doron

# SPDX-License-Identifier: BSD-2-Clause-Patent

#

##

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c
index 7650a6b21575..09b2b5ee9180 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardEcLib/EcCommands.c
@@ -1,7 +1,7 @@
/** @file

Board-specific EC commands.



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.c
index 1281391ed36f..906b2d265092 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.c
@@ -1,7 +1,7 @@
/** @file

Aspire VN7-572G Board Initialization DXE library



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.inf b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.inf
index 000ec8a1b56d..9a868ee15fb2 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.inf
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Library/BoardInitLib/DxeBoardInitLib.inf
@@ -1,7 +1,7 @@
## @file

# Component information file for AspireVn7Dash572GInitLib in DXE phase.

#

-# Copyright (c) 2021, Benjamin Doran

+# Copyright (c) 2021, Baruch Binyamin Doron

# SPDX-License-Identifier: BSD-2-Clause-Patent

#

##

diff --git a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c
index b72bc56f1d0d..95b7c4ad5f77 100644
--- a/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c
+++ b/Platform/Intel/KabylakeOpenBoardPkg/AspireVn7Dash572G/Policy/Library/PeiSiliconPolicyUpdateLib/PeiBoardPolicyUpdate.c
@@ -1,7 +1,7 @@
/** @file

This file configures Aspire VN7-572G board-specific policies.



- Copyright (c) 2021, Benjamin Doran

+ Copyright (c) 2021, Baruch Binyamin Doron

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

--
2.31.1