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[edk2-platforms PATCH 2/7] Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables
Marcin Wojtas
BBR 1.0 spec says that _STA is required for each device in DSDT or SSDT.
Fix that for all platforms with the Marvell SoC's. Signed-off-by: Marcin Wojtas <mw@...> --- Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 ++++++= +++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++= ++++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 72 ++++++= +++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 ++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 56 ++++++= +++++++++ 5 files changed, 272 insertions(+) diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl index 345c1e4dd6..88e38efeeb 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA7K", 3) {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x000) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU1)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x001) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU2)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x100) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU3)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x101) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D =0D Device (AHC0)=0D @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A7K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A7K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -96,6 +120,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA7K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -123,6 +151,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -142,6 +174,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -160,6 +196,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) {=0D Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress=0D Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D {=0D @@ -186,6 +226,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -208,6 +252,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D @@ -286,6 +334,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x00) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D @@ -312,6 +364,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA7K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment=0D Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_PRT, Package () // _PRT: PCI Routing Table=0D {=0D Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl b/= Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl index 91401c74c8..77d3aebaf1 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x000) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU1)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x001) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU2)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x100) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU3)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x101) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D =0D Device (AHC0)=0D @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -92,6 +116,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -122,6 +150,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -151,6 +183,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -170,6 +206,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x02) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -207,6 +251,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress=0D Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D {=0D @@ -233,6 +281,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -251,6 +303,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D @@ -309,6 +365,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -327,6 +387,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)=0D @@ -385,6 +449,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x00) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D @@ -405,6 +473,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x01) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)=0D @@ -431,6 +503,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment=0D Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_PRT, Package () // _PRT: PCI Routing Table=0D {=0D Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D diff --git a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl= b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl index d26945d933..1ecbd0309c 100644 --- a/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl +++ b/Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl @@ -19,21 +19,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x000) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU1)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x001) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU2)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x100) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU3)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x101) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D =0D Device (AHC0)=0D @@ -41,6 +57,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMAD= A8K", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -91,6 +111,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARMA= DA8K", 3) Name (_HID, "MRVL0002") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -122,6 +146,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -150,6 +178,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -169,6 +201,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -188,6 +224,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x02) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -206,6 +246,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress=0D Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D {=0D @@ -232,6 +276,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -249,6 +297,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "MRVL0101") // _HID: H= ardware ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -283,6 +335,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D @@ -322,6 +378,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)=0D @@ -400,6 +460,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x00) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D @@ -420,6 +484,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x01) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF4760000, 0x7D)=0D @@ -446,6 +514,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "ARM= ADA8K", 3) Name (_SEG, 0x00) // _SEG: PCI Segment=0D Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_PRT, Package () // _PRT: PCI Routing Table=0D {=0D Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl index 8377b13763..d6619e367b 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl @@ -20,6 +20,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -45,6 +49,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x02) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -63,6 +71,10 @@ DefinitionBlock ("Cn9131DbASsdt.aml", "SSDT", 2, "MVEBU = ", "CN9131", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x01) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf4000000 , 0x100000)=0D diff --git a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl b/S= ilicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl index d76a2a902b..536df8ab4b 100644 --- a/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl +++ b/Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl @@ -20,21 +20,37 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91= 30", 3) {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x000) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU1)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x001) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU2)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x100) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D Device (CPU3)=0D {=0D Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardw= are ID=0D Name (_UID, 0x101) // _UID: Unique ID=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D }=0D =0D Device (AHC0)=0D @@ -42,6 +58,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN913= 0", 3) Name (_HID, "LNRO001E") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CLS, Package (0x03) // _CLS: Class Code=0D {=0D 0x01,=0D @@ -67,6 +87,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN913= 0", 3) Name (_HID, "MRVL0003") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -98,6 +122,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN91= 30", 3) Name (_HID, "MRVL0004") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -126,6 +154,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x00) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -145,6 +177,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "PNP0D10") // _HID: Hardware ID=0D Name (_UID, 0x01) // _UID: Unique ID=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute= =0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D =0D Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings=0D {=0D @@ -163,6 +199,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) {=0D Name (_HID, "MRVL0001") // _HID: H= ardware ID=0D Name (_CID, "HISI0031") // _CID: C= ompatible ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_ADR, FixedPcdGet64(PcdSerialRegisterBase)) // _ADR: A= ddress=0D Name (_CRS, ResourceTemplate () // _CRS: C= urrent Resource Settings=0D {=0D @@ -189,6 +229,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) {=0D Name (_HID, "MRVL0100") // _HID: H= ardware ID=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite,=0D @@ -211,6 +255,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_HID, "MRVL0110") // _HID: H= ardware ID=0D Name (_CCA, 0x01) // Cache-c= oherent controller=0D Name (_UID, 0x00) // _UID: U= nique ID=0D + Method (_STA) // _STA: D= evice status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xf2000000 , 0x100000)=0D @@ -289,6 +337,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) {=0D Name (_HID, "PRP0001") // _HID= : Hardware ID=0D Name (_UID, 0x00) // _UID= : Unique ID=0D + Method (_STA) // _STA= : Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_CRS, ResourceTemplate ()=0D {=0D Memory32Fixed (ReadWrite, 0xF2760000, 0x7D)=0D @@ -315,6 +367,10 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "MVEBU ", "CN9= 130", 3) Name (_SEG, 0x00) // _SEG: PCI Segment=0D Name (_BBN, 0x00) // _BBN: BIOS Bus Number=0D Name (_CCA, 0x01) // _CCA: Cache Coherency Attribute=0D + Method (_STA) // _STA: Device status=0D + {=0D + Return (0xF)=0D + }=0D Name (_PRT, Package () // _PRT: PCI Routing Table=0D {=0D Package () { 0xFFFF, 0x0, 0x0, 0x40 },=0D --=20 2.29.0
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[edk2-platforms PATCH 1/7] Marvell: Armada7k8k: Add missing VariablePolicyHelperLib resolution
Marcin Wojtas
From: Grzegorz Bernacki <gjb@...>
The latest changes in MdeModulePkg/Universal/BdsDxe require VariablePolicyHelperLib resolution. Fix that for all platforms based on the Marvell SoCs. Signed-off-by: Marcin Wojtas <mw@...> --- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc b/Silicon/Marvel= l/Armada7k8k/Armada7k8k.dsc.inc index 939fbf14d9..c919d4bfab 100644 --- a/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc +++ b/Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc @@ -175,6 +175,7 @@ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf=0D NonDiscoverableDeviceRegistrationLib|MdeModulePkg/Library/NonDiscoverabl= eDeviceRegistrationLib/NonDiscoverableDeviceRegistrationLib.inf=0D DtPlatformDtbLoaderLib|EmbeddedPkg/Library/DxeDtPlatformDtbLoaderLibDefa= ult/DxeDtPlatformDtbLoaderLibDefault.inf=0D + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf=0D =0D [LibraryClasses.common.UEFI_APPLICATION]=0D PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.= inf=0D @@ -197,6 +198,7 @@ !endif=0D DebugLib|MdePkg/Library/DxeRuntimeDebugLibSerialPort/DxeRuntimeDebugLibS= erialPort.inf=0D VariablePolicyLib|MdeModulePkg/Library/VariablePolicyLib/VariablePolicyL= ibRuntimeDxe.inf=0D + VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib/Var= iablePolicyHelperLib.inf=0D =0D [LibraryClasses.ARM, LibraryClasses.AARCH64]=0D #=0D @@ -563,7 +565,6 @@ NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf=0D TpmMeasurementLib|MdeModulePkg/Library/TpmMeasurementLibNull/TpmMeas= urementLibNull.inf=0D VarCheckLib|MdeModulePkg/Library/VarCheckLib/VarCheckLib.inf=0D - VariablePolicyHelperLib|MdeModulePkg/Library/VariablePolicyHelperLib= /VariablePolicyHelperLib.inf=0D }=0D =0D # UEFI application (Shell Embedded Boot Loader)=0D --=20 2.29.0
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[edk2-platforms PATCH 0/7] Marvell ACS improvements
Marcin Wojtas
Hi,
This new series comes with the remaining improvements that allow the ACS3.0 test suite to pass the SBSA/FWTS/SCT to the maximum non-HW related extent. Missing _STA methods and DBG2 description are added to the ACPI tables. Moreover all platforms start using the maintained MonotonicCounterRuntimeDxe. Also a build fix is added for the VariablePolicyHelperLib resolution, that is required after the recent changes in edk2. Last but not least the SMBIOS Type0 description is updated with the actual EDK2 firmare vendor and version strings. More details can be found in the commit logs. The patchest is publicly available in the github: https://github.com/semihalf-wojtas-marcin/edk2-platforms/commits/marvell-acs-r20210719 Best regards, Marcin Grzegorz Bernacki (2): Marvell: Armada7k8k: Add missing VariablePolicyHelperLib resolution Marvell: Armada7k8k/OcteonTx: Switch to MonotonicCounterRuntimeDxe Marcin Wojtas (5): Marvell: Armada7k8k/OcteonTx: Add missing _STA methods in ACPI tables Marvell/Cn913xDbA: AcpiTables: Introduce DBG2 table SolidRun/Armada80x0McBin: AcpiTables: Introduce DBG2 table Marvell/Drivers: SmbiosPlatformDxe: Update Type0 information Marvell: Armada7k8k/OcteonTx: Bump firmware to "EDK2 SH 1.0" revision Silicon/Marvell/Marvell.dec | 2 + Platform/Marvell/Cn913xDb/Cn9130DbA.dsc.inc | 4 +- Silicon/Marvell/Armada7k8k/Armada7k8k.dsc.inc | 8 +- Silicon/Marvell/Armada7k8k/Armada7k8k.fdf | 2 +- Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin.inf | 1 + Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 2 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9130DbA.inf | 1 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA.inf | 1 + Silicon/Marvell/Armada7k8k/AcpiTables/AcpiHeader.h | 2 + Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h | 9 ++ Silicon/Marvell/Armada7k8k/AcpiTables/IcuInterrupts.h | 2 + Silicon/Marvell/OcteonTx/AcpiTables/T91/AcpiHeader.h | 2 + Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h | 9 ++ Silicon/Marvell/OcteonTx/AcpiTables/T91/IcuInterrupts.h | 2 + Silicon/Marvell/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c | 6 +- Silicon/Marvell/Armada7k8k/AcpiTables/Armada70x0Db/Dsdt.asl | 56 +++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0Db/Dsdt.asl | 76 ++++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc | 74 ++++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dsdt.asl | 105 ++++++++++++++++++++ Silicon/Marvell/Armada7k8k/AcpiTables/Spcr.aslc | 2 - Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn9131DbA/Ssdt.asl | 12 +++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc | 74 ++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dsdt.asl | 89 +++++++++++++++++ Silicon/Marvell/OcteonTx/AcpiTables/T91/Spcr.aslc | 2 - 24 files changed, 530 insertions(+), 13 deletions(-) create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.h create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.h create mode 100644 Silicon/Marvell/Armada7k8k/AcpiTables/Armada80x0McBin/Dbg2.aslc create mode 100644 Silicon/Marvell/OcteonTx/AcpiTables/T91/Cn913xDbA/Dbg2.aslc -- 2.29.0
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Re: [PATCH v4 0/3] Enable Cloud Hypervisor support in edk2
Sami Mujawar
Hi Ard,
On 16/07/2021, 18:28, "Ard Biesheuvel" <ardb@...> wrote: On Fri, 16 Jul 2021 at 19:25, Ard Biesheuvel <ardb@...> wrote: > > On Mon, 5 Jul 2021 at 12:06, Jianyong Wu <jianyong.wu@...> wrote: > > > > Cloud Hypervisor is an open source Virtual Machine Monitor (VMM) that > > runs on top of KVM. Cloud Hypervisor is implemented in Rust and is based > > on the rust-vmm crates. See [1] to find more. > > > > To support UEFI, Cloud Hypervisor is introduced here. > > There are 2 parts to be considered to do this enablement, that is: > > 1. specific ACPI service implementation compared with qemu, there is no > > device like Fw-cfg, so we have no elegant way to get the RSDP address. > > A specific ACPI implementation is introduced here. > > > > 2. build configuration file for Cloud Hypervisor > > > > Change log: > > > > v3 to v4: > > (1) remove Tpm support in dsc file > > (2) refine Acpi table install code base on Sami's comments in v3 > > > > v2 to v3: > > (1) reuse qemu's memory initialization lib as they are in nearly the same > > memory laout. > > (2) split Acpi implemetation into PlatformHasAcpi and > > InstallAcpiTable. > > (3) remove lots of dependencies from qemu like "*Fwcfg*" lib. > > (4) lots of code cleanup work to let it more approach to edk2 code > > style. > > > > [1] https://github.com/cloud-hypervisor/cloud-hypervisor > > > > Jianyong Wu (3): > > Acpi: reimplement PlatformHasAcpi for Cloud Hypervisor > > Acpi: Install Acpi tables for Cloud hypervisor > > ArmVirtCloudHv: support Cloud Hypervisor in edk2 > > > > Sami, any thoughts on this code? > ... or did you already merge the entire series? (My mailbox is overflowing a bit after 4 weeks of vacation :-)) [SAMI] I have merged this series. Regards, Sami Mujawar > > > ArmVirtPkg/ArmVirtPkg.dec | 6 + > > ArmVirtPkg/ArmVirtCloudHv.dsc | 364 ++++++++++++++++++ > > ArmVirtPkg/ArmVirtCloudHv.fdf | 258 +++++++++++++ > > .../CloudHvAcpiPlatformDxe.inf | 47 +++ > > .../CloudHvHasAcpiDtDxe.inf | 43 +++ > > .../CloudHvAcpiPlatformDxe/CloudHvAcpi.c | 155 ++++++++ > > .../CloudHvHasAcpiDtDxe.c | 69 ++++ > > 7 files changed, 942 insertions(+) > > create mode 100644 ArmVirtPkg/ArmVirtCloudHv.dsc > > create mode 100644 ArmVirtPkg/ArmVirtCloudHv.fdf > > create mode 100644 ArmVirtPkg/CloudHvAcpiPlatformDxe/CloudHvAcpiPlatformDxe.inf > > create mode 100644 ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.inf > > create mode 100644 ArmVirtPkg/CloudHvAcpiPlatformDxe/CloudHvAcpi.c > > create mode 100644 ArmVirtPkg/CloudHvPlatformHasAcpiDtDxe/CloudHvHasAcpiDtDxe.c > > > > -- > > 2.17.1 > > IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.
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Re: [PATCH v5 1/4] OvmfPkg/BaseMemEncryptLib: Support to issue unencrypted hypercall
Dov Murik
On 16/07/2021 15:29, Ashish Kalra wrote:
Hello Dov,Put the first argument on its own line. AsciiStrCmp will stop at the first '\0' char. So adding those threeI don't understand what do you mean by "KVMKVMKVM\0YZ", this is+ NULL,I assume this will also match if Signature is "KVMKVMKVM\0YZ". I don't '\0' at the end is pointless (the compiler will add one '\0' at the end of a literal string). Instead, you can use: if (CompareMem (Signature, "KVMKVMKVM\0\0\0", 12) == 0) and then you are sure to compare all 12 signature bytes. I'm not sure this matters at all, maybe a simple: if (AsciiStrCmp (Signature, "KVMKVMKVM") == 0) is good enough. I see similar code to detect Xen in OvmfPkg/XenPlatformPei/Xen.c . s/%s/%a/+ DEBUG (( (edk2 format strings are confusing.) OK. So fix the comment above the function (which says: "The physicalOk.+ __FUNCTION__,I'd write: "%a: SEV Live Migration feature supported\n" address is expected to be PAGE_SIZE aligned.") Even clearer than a literal 0 -- pass a ClearCBit as the third argumentOk.+ Ret = RETURN_UNSUPPORTED;Simpler: (assuming you're changing the argument type to MAP_RANGE_MODE). -Dov Thanks,
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[edk2-test][PATCH v1 1/1] uefi-sct/SctPkg: Update page alignment calculations
Sunny Wang
This is to fix the SCT BS.AllocatePages failures (not found) with the
case that the Start address is not aligned to 64k. For example, The following is available memory region for testing: 0000000082012000-00000000EB6D9FFF 00000000000696C8 With the current page alignment calculation, we will get: Start address is 0x82020000 PageNum is 0x696B8 In BS.AllocatePages, it will make the end address align with 64k, so PageNum will be changed from 0x696B8 to 0x696C0. Therefore, the end address will become 0xEB6E0000 which is larger than 0xEB6D9FFF, so we get not found error in the end. Therefore, the calculation for getting the PageNum should be updated to PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000)) so that we won't get a wrong PageNum to allocate a memory with a size larger than available space's size. With this solution, the example above will get 0x696A8 as calculated PageNum. Then, in BS.AllocatePages, the PageNum will be changed from 0x696A8 to 0x696B0. Therefore, the end address will become 0xEB6D0000 that is smaller than 0xEB6D9FFF, so we get not found error in the end. I also tested this solution on two ARM platforms (NXP1046A and RPi4). Cc: Samer El-Haj-Mahmoud <samer.el-haj-mahmoud@...> Cc: G Edhaya Chandran <edhaya.chandran@...> Cc: Barton Gao <gaojie@...> Signed-off-by: Sunny Wang <sunny.wang@...> --- .../MemoryAllocationServicesBBTestFunction.c | 110 +++++++++++------- 1 file changed, 66 insertions(+), 44 deletions(-) diff --git a/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocat= ionServices/BlackBoxTest/MemoryAllocationServicesBBTestFunction.c b/uefi-= sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServices/BlackB= oxTest/MemoryAllocationServicesBBTestFunction.c index bf8cd3b3..cdfac992 100644 --- a/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServ= ices/BlackBoxTest/MemoryAllocationServicesBBTestFunction.c +++ b/uefi-sct/SctPkg/TestCase/UEFI/EFI/BootServices/MemoryAllocationServ= ices/BlackBoxTest/MemoryAllocationServicesBBTestFunction.c @@ -2,6 +2,7 @@ =20 Copyright 2006 - 2013 Unified EFI, Inc.<BR> Copyright (c) 2010 - 2013, Intel Corporation. All rights reserved.<BR> + Copyright (c) 2021, ARM Limited. All rights reserved. =20 This program and the accompanying materials are licensed and made available under the terms and conditions of the = BSD License @@ -24,7 +25,7 @@ Abstract: =20 --*/ =20 -#include "SctLib.h" +#include "SctLib.h" #include "MemoryAllocationServicesBBTestMain.h" =20 #define ALLOCATEPAGES_MEMORYTYPE_NUM 16 @@ -700,14 +701,17 @@ BBTestAllocatePagesInterfaceTest ( PageNum =3D (UINTN)Descriptor.NumberOfPages; Start =3D Descriptor.PhysicalStart; =20 - // - // Some memory types need more alignment than 4K, so - // - if (PageNum <=3D 0x10) { + // + // Calculate New Start address and PageNum with 64k alignment to + // cover the case that some memory types' alignment is more than + // 4k. If the available memory is less than 192k, the memory + // allocation call will be skipped. + // + if (PageNum < (3 * EFI_SIZE_TO_PAGES(0x10000))) { break; } - Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000; - PageNum =3D PageNum - EFI_SIZE_TO_PAGES(0x10000); + Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000; + PageNum =3D PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000)); =20 Memory =3D Start; =20 @@ -830,14 +834,17 @@ BBTestAllocatePagesInterfaceTest ( PageNum =3D (UINTN)Descriptor.NumberOfPages; Start =3D Descriptor.PhysicalStart; =20 - // - // Some memory types need more alignment than 4K, so - // - if (PageNum <=3D 0x10) { + // + // Calculate New Start address and PageNum with 64k alignment to + // cover the case that some memory types' alignment is more than + // 4k. If the available memory is less than 192k, the memory + // allocation call will be skipped. + // + if (PageNum < (3 * EFI_SIZE_TO_PAGES(0x10000))) { break; } - Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000; - PageNum =3D PageNum - EFI_SIZE_TO_PAGES(0x10000); + Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000; + PageNum =3D PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000)); =20 Memory =3D Start; =20 @@ -953,14 +960,17 @@ BBTestAllocatePagesInterfaceTest ( PageNum =3D (UINTN)Descriptor.NumberOfPages; Start =3D Descriptor.PhysicalStart; =20 - // - // Some memory types need more alignment than 4K, so - // - if (PageNum <=3D 0x10) { + // + // Calculate New Start address and PageNum with 64k alignment to + // cover the case that some memory types' alignment is more than + // 4k. If the available memory is less than 192k, the memory + // allocation call will be skipped. + // + if (PageNum < (3 * EFI_SIZE_TO_PAGES(0x10000))) { break; } - Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000; - PageNum =3D PageNum - EFI_SIZE_TO_PAGES(0x10000); + Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000; + PageNum =3D PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000)); =20 Memory =3D Start + (SctLShiftU64 (PageNum/3, EFI_PAGE_SHIFT) & 0= xFFFFFFFFFFFF0000); =20 @@ -1076,14 +1086,17 @@ BBTestAllocatePagesInterfaceTest ( PageNum =3D (UINTN)Descriptor.NumberOfPages; Start =3D Descriptor.PhysicalStart; =20 - // - // Some memory types need more alignment than 4K, so - // - if (PageNum <=3D 0x10) { + // + // Calculate New Start address and PageNum with 64k alignment to + // cover the case that some memory types' alignment is more than + // 4k. If the available memory is less than 192k, the memory + // allocation call will be skipped. + // + if (PageNum < (3 * EFI_SIZE_TO_PAGES(0x10000))) { break; } - Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000; - PageNum =3D PageNum - EFI_SIZE_TO_PAGES(0x10000); + Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000; + PageNum =3D PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000)); =20 Memory =3D Start + (SctLShiftU64 (PageNum * 2 / 3, EFI_PAGE_SHI= FT) & 0xFFFFFFFFFFFF0000); =20 @@ -1206,14 +1219,17 @@ BBTestAllocatePagesInterfaceTest ( PageNum =3D (UINTN)Descriptor.NumberOfPages; Start =3D Descriptor.PhysicalStart; =20 - // - // Some memory types need more alignment than 4K, so - // - if (PageNum <=3D 0x10) { + // + // Calculate New Start address and PageNum with 64k alignment to + // cover the case that some memory types' alignment is more than + // 4k. If the available memory is less than 192k, the memory + // allocation call will be skipped. + // + if (PageNum < (3 * EFI_SIZE_TO_PAGES(0x10000))) { break; } - Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000; - PageNum =3D PageNum - EFI_SIZE_TO_PAGES(0x10000); + Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000; + PageNum =3D PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000)); =20 Memory =3D Start; =20 @@ -1329,14 +1345,17 @@ BBTestAllocatePagesInterfaceTest ( PageNum =3D (UINTN)Descriptor.NumberOfPages; Start =3D Descriptor.PhysicalStart; =20 - // - // Some memory types need more alignment than 4K, so - // - if (PageNum <=3D 0x10) { + // + // Calculate New Start address and PageNum with 64k alignment to + // cover the case that some memory types' alignment is more than + // 4k. If the available memory is less than 192k, the memory + // allocation call will be skipped. + // + if (PageNum < (3 * EFI_SIZE_TO_PAGES(0x10000))) { break; } - Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000; - PageNum =3D PageNum - EFI_SIZE_TO_PAGES(0x10000); + Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000; + PageNum =3D PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000)); =20 Memory =3D Start; =20 @@ -1468,14 +1487,17 @@ BBTestAllocatePagesInterfaceTest ( PageNum =3D (UINTN)Descriptor.NumberOfPages; Start =3D Descriptor.PhysicalStart; =20 - // - // Some memory types need more alignment than 4K, so - // - if (PageNum <=3D 0x10) { + // + // Calculate New Start address and PageNum with 64k alignment to + // cover the case that some memory types' alignment is more than + // 4k. If the available memory is less than 192k, the memory + // allocation call will be skipped. + // + if (PageNum < (3 * EFI_SIZE_TO_PAGES(0x10000))) { break; } - Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000; - PageNum =3D PageNum - EFI_SIZE_TO_PAGES(0x10000); + Start =3D (Start + 0xFFFF) & 0xFFFFFFFFFFFF0000; + PageNum =3D PageNum - (2 * EFI_SIZE_TO_PAGES(0x10000)); =20 Memory =3D Start; =20 @@ -1923,4 +1945,4 @@ BBTestFreePoolInterfaceTest ( =20 FreeMemoryMap (); return EFI_SUCCESS; -} +} --=20 2.31.0.windows.1
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Re: [PATCH v1 1/1] ArmPlatformPkg/Scripts: Create add-symbol-file commands from UEFI console
Ard Biesheuvel
On Fri, 9 Jul 2021 at 11:03, PierreGondois <pierre.gondois@...> wrote:
Merged as #1821 Thanks,
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Re: [PATCH] OvmfPkg/OvmfXen: add QemuKernelLoaderFsDxe
Ard Biesheuvel
On Fri, 9 Jul 2021 at 05:24, Gary Lin <glin@...> wrote:
I don't understand Xen on x86 well enough to decide whether we should care about QEMU in the first place. Xen folks, please have a look. ---
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Re: [RFC PATCH] OvmfPkg/OvmfXen: set PcdAcpiS3Enable at initialization
Ard Biesheuvel
On Thu, 8 Jul 2021 at 06:05, Gary Lin <glin@...> wrote:
This needs an ack from the Xen folks. ---
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Re: [PATCH v5 4/4] OvmfPkg/AmdSevDxe: Add support for SEV live migration.
Dov Murik
Ashish,
On 08/07/2021 17:09, Ashish Kalra wrote: From: Ashish Kalra <ashish.kalra@...> Why is this indirect notification needed? Why not simply call gRT->SetVariable in AmdSevDxeEntryPoint (instead of calling CreateEventEx)? If this is needed, please add a clarification (in the commit message and before the CreateEventEx call). Signed-off-by: Ashish Kalra <ashish.kalra@...>Should be: sizeof SevLiveMigrationEnabled, + &SevLiveMigrationEnabledRemove debug print. +} Should the filename, GUID #define name, and global var name include "AMD" or "SEV" in them? (and similarly in the corresponding Linux patch) Or: maybe the new "SevLiveMigrationEnabled" variable can be set in the confidential computing GUID? (not sure what are the guidelines for creating or reusing GUIDs). @@ -0,0 +1,20 @@typos: environment, associated + -Dov
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Re: [edk2-platforms PATCH 0/4] ACPI MDIO support for Marvell SoCs
Ard Biesheuvel
On Fri, 16 Jul 2021 at 19:32, Ard Biesheuvel <ardb@...> wrote:
Pushed as bfabeef4c9a6..955187a12a8b Thanks all.
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Re: [PATCH] UefiCpuPkg: SecCoreNative without ResetVector
Hi., Ray
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BIOS boot to OS verified in Simics Successfully with the following changes. 1. SecCoreNative.inf with new GUID. 2. Removed IA32 resetvector code from SecCoreNative. 3. Removed the ResetVector Code from PlatformSecLib 4. Consumed the ResetVector Code from UefiCpuPkg/ResetVector The reason for this change: Currently SecCore and ResetVector are using the Same GUID (BFV guid), which will block the usage of both SecCore and UefiCpuPkg/ResetVector at a same time. Advantage of this patch: 1. Provided the Backward compatibility by keeping the original SecCore 2. User can use both SecCoreNative and ResetVector at a same time. 3. User can choose to avoid resetvector code maintenance at the platform level. Regards, Ashraf Ali S Intel Technology India Pvt. Ltd.
-----Original Message-----
From: Ni, Ray <ray.ni@...> Sent: Monday, July 19, 2021 8:13 AM To: S, Ashraf Ali <ashraf.ali.s@...>; devel@edk2.groups.io Cc: Kumar, Rahul1 <rahul1.kumar@...>; De, Debkumar <debkumar.de@...>; Han, Harry <harry.han@...>; West, Catharine <catharine.west@...>; Solanki, Digant H <digant.h.solanki@...>; V, Sangeetha <sangeetha.v@...> Subject: RE: [PATCH] UefiCpuPkg: SecCoreNative without ResetVector Ashraf, What unit tests have you performed with this native SecCore? Thanks, Ray -----Original Message----- From: S, Ashraf Ali <ashraf.ali.s@...> Sent: Wednesday, July 14, 2021 5:48 PM To: devel@edk2.groups.io Cc: S, Ashraf Ali <ashraf.ali.s@...>; Ni, Ray <ray.ni@...>; Kumar, Rahul1 <rahul1.kumar@...>; De, Debkumar <debkumar.de@...>; Han, Harry <harry.han@...>; West, Catharine <catharine.west@...>; Solanki, Digant H <digant.h.solanki@...>; V, Sangeetha <sangeetha.v@...> Subject: [PATCH] UefiCpuPkg: SecCoreNative without ResetVector REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3492 Currently SecCore.inf having the resetvector code under IA32. if the user wants to use both SecCore and UefiCpuPkg ResetVector it's not possible, since SecCore and ResetVector(VTF0.INF/ResetVector.inf) are sharing the same GUID which is BFV. to overcome this issue we can create the Duplicate version of the SecCore.inf as SecCoreNative.inf which contains pure SecCore Native functionality without resetvector. SecCoreNative.inf should have the Unique GUID so that it can be used along with UefiCpuPkg ResetVector in there implementation. Signed-off-by: Ashraf Ali S <ashraf.ali.s@...> Cc: Ray Ni <ray.ni@...> Cc: Rahul Kumar <rahul1.kumar@...> Cc: Debkumar De <debkumar.de@...> Cc: Harry Han <harry.han@...> Cc: Catharine West <catharine.west@...> Cc: Digant H Solanki <digant.h.solanki@...> Cc: Sangeetha V <sangeetha.v@...> --- UefiCpuPkg/SecCore/SecCoreNative.inf | 80 ++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 UefiCpuPkg/SecCore/SecCoreNative.inf diff --git a/UefiCpuPkg/SecCore/SecCoreNative.inf b/UefiCpuPkg/SecCore/SecCoreNative.inf new file mode 100644 index 0000000000..f89a0e5f38 --- /dev/null +++ b/UefiCpuPkg/SecCore/SecCoreNative.inf @@ -0,0 +1,80 @@ +## @file +# SecCoreNative module that implements the SEC phase. +# +# This is the first module taking control after the reset vector. +# The entry point function is _ModuleEntryPoint in PlatformSecLib. +# The entry point function will start with protected mode, since the # +the transistion to flat mode it done by the resetvector, enable # +temporary memory and call into SecStartup(). +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> # +SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SecCore + MODULE_UNI_FILE = SecCore.uni + FILE_GUID = 43CA74CA-7D29-49A0-B3B9-20F84015B27D + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 EBC +# + +[Sources] + SecMain.c + SecMain.h + FindPeiCore.c + SecBist.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + PlatformSecLib + PcdLib + DebugAgentLib + UefiCpuLib + PeCoffGetEntryPointLib + PeCoffExtraActionLib + CpuExceptionHandlerLib + ReportStatusCodeLib + PeiServicesLib + PeiServicesTablePointerLib + HobLib + +[Ppis] + ## SOMETIMES_CONSUMES + ## PRODUCES + gEfiSecPlatformInformationPpiGuid + ## SOMETIMES_CONSUMES + ## SOMETIMES_PRODUCES + gEfiSecPlatformInformation2PpiGuid + gEfiTemporaryRamDonePpiGuid ## PRODUCES + ## NOTIFY + ## SOMETIMES_CONSUMES + gPeiSecPerformancePpiGuid + gEfiPeiCoreFvLocationPpiGuid + ## CONSUMES + gRepublishSecPpiPpiGuid + +[Guids] + ## SOMETIMES_PRODUCES ## HOB + gEfiFirmwarePerformanceGuid + +[Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdMigrateTemporaryRamFirmwareVolumes +## CONSUMES + +[UserExtensions.TianoCore."ExtraFiles"] + SecCoreExtra.uni -- 2.30.2.windows.1
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Re: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity
Ard Biesheuvel
On Mon, 19 Jul 2021 at 05:14, Ni, Ray <ray.ni@...> wrote:
I don't have a clue, sorry, and I wouldn't know where to begin looking. Brijesh, Dov, James, Erdem: after Laszlo's sudden departure, I will be needing help reviewing OVMF patches that are highly specific to SEV/SNP or x86 in general. Please take a look. To Prince,
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Re: [PATCH v2 1/1] MdeModulePkg: Print which PCD was unable to be found
Wu, Hao A
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-----Original Message----- The change looks good to me. Reviewed-by: Hao A Wu <hao.a.wu@...> I will wait a couple days before merging to see if there are comments from the Core services modules reviewers. Best Regards, Hao Wu ASSERT (FALSE);
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Re: [PATCH] Fix variables may be used uninitialize
Ni, Ray
Wesley,
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When applying the patch in my local tree, I found your patch is using unix style of EOL. Can you please send a V2 patch that uses the windows style of EOL? Thanks, Ray
-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Ni, Ray Sent: Monday, July 19, 2021 11:15 AM To: Hsu, WesleyX <wesleyx.hsu@...>; devel@edk2.groups.io Cc: Chaganty, Rangasai V <rangasai.v.chaganty@...> Subject: Re: [edk2-devel] [PATCH] Fix variables may be used uninitialize Reviewed-by: Ray Ni <ray.ni@...> -----Original Message----- From: Hsu, WesleyX <wesleyx.hsu@...> Sent: Friday, July 16, 2021 2:38 PM To: devel@edk2.groups.io Cc: Hsu, WesleyX <wesleyx.hsu@...>; Ni, Ray <ray.ni@...>; Chaganty, Rangasai V <rangasai.v.chaganty@...> Subject: [PATCH] Fix variables may be used uninitialize REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3491 Initialize variables may be used uninitialized after adding "-ffat-lto-objects" option in GCC5 tool chain. Change-Id: Iec8c9a884bac5cf1ce7258867c074c4668e5fa44 Signed-off-by: WesleyX Hsu <wesleyx.hsu@...> Cc: Ray Ni <ray.ni@...> Cc: Rangasai V Chaganty <rangasai.v.chaganty@...> --- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c | 5 +++++ Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c | 7 ++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c index 341e2beb..2a5fa637 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Translat +++ ionTable.c @@ -107,6 +107,11 @@ CreateSecondLevelPagingEntryTable ( UINT64 EndAddress; BOOLEAN Is5LevelPaging; + Lvl4PagesStart = 0; + Lvl4PagesEnd = 0; + Lvl4PtEntry = NULL; + Lvl5PtEntry = NULL; + if (MemoryLimit == 0) { return EFI_SUCCESS; } diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c index d152039f..01375139 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationT +++ able.c @@ -133,7 +133,7 @@ CreateContextEntry ( mVtdUnitInformation[VtdIndex].Is5LevelPaging = TRUE; if ((mAcpiDmarTable->HostAddressWidth <= 48) && ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) != 0)) { - mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE; + mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE; } } else if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) { DEBUG((DEBUG_ERROR, "!!!! Page-table type is not supported on VTD %d !!!!\n", VtdIndex)); @@ -195,6 +195,11 @@ CreateSecondLevelPagingEntryTable ( UINT64 BaseAddress; UINT64 EndAddress; + Lvl4PagesStart = 0; + Lvl4PagesEnd = 0; + Lvl4PtEntry = NULL; + Lvl5PtEntry = NULL; + if (MemoryLimit == 0) { return EFI_SUCCESS; } -- 2.26.2.windows.1
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Re: [PATCH] Fix variables may be used uninitialize
Ni, Ray
Reviewed-by: Ray Ni <ray.ni@...>
toggle quoted messageShow quoted text
-----Original Message-----
From: Hsu, WesleyX <wesleyx.hsu@...> Sent: Friday, July 16, 2021 2:38 PM To: devel@edk2.groups.io Cc: Hsu, WesleyX <wesleyx.hsu@...>; Ni, Ray <ray.ni@...>; Chaganty, Rangasai V <rangasai.v.chaganty@...> Subject: [PATCH] Fix variables may be used uninitialize REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3491 Initialize variables may be used uninitialized after adding "-ffat-lto-objects" option in GCC5 tool chain. Change-Id: Iec8c9a884bac5cf1ce7258867c074c4668e5fa44 Signed-off-by: WesleyX Hsu <wesleyx.hsu@...> Cc: Ray Ni <ray.ni@...> Cc: Rangasai V Chaganty <rangasai.v.chaganty@...> --- Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c | 5 +++++ Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c | 7 ++++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c index 341e2beb..2a5fa637 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/TranslationTable.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDmarPei/Translat +++ ionTable.c @@ -107,6 +107,11 @@ CreateSecondLevelPagingEntryTable ( UINT64 EndAddress; BOOLEAN Is5LevelPaging; + Lvl4PagesStart = 0; + Lvl4PagesEnd = 0; + Lvl4PtEntry = NULL; + Lvl5PtEntry = NULL; + if (MemoryLimit == 0) { return EFI_SUCCESS; } diff --git a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c index d152039f..01375139 100644 --- a/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationTable.c +++ b/Silicon/Intel/IntelSiliconPkg/Feature/VTd/IntelVTdDxe/TranslationT +++ able.c @@ -133,7 +133,7 @@ CreateContextEntry ( mVtdUnitInformation[VtdIndex].Is5LevelPaging = TRUE; if ((mAcpiDmarTable->HostAddressWidth <= 48) && ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) != 0)) { - mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE; + mVtdUnitInformation[VtdIndex].Is5LevelPaging = FALSE; } } else if ((mVtdUnitInformation[VtdIndex].CapReg.Bits.SAGAW & BIT2) == 0) { DEBUG((DEBUG_ERROR, "!!!! Page-table type is not supported on VTD %d !!!!\n", VtdIndex)); @@ -195,6 +195,11 @@ CreateSecondLevelPagingEntryTable ( UINT64 BaseAddress; UINT64 EndAddress; + Lvl4PagesStart = 0; + Lvl4PagesEnd = 0; + Lvl4PtEntry = NULL; + Lvl5PtEntry = NULL; + if (MemoryLimit == 0) { return EFI_SUCCESS; } -- 2.26.2.windows.1
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Re: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity
Ni, Ray
This change generates the reset vector binary which only contains 1G page table. If a platform doesn't support 1G page table, this will cause system hang.
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To Ard and Jordan, Can you evaluate whether this change impacts OVMF? To Prince, Can you evaluate whether this change impacts SimicsOpenBoardPkg? Thanks, Ray
-----Original Message-----
From: S, Ashraf Ali <ashraf.ali.s@...> Sent: Friday, July 2, 2021 8:25 PM To: devel@edk2.groups.io Cc: S, Ashraf Ali <ashraf.ali.s@...>; Ni, Ray <ray.ni@...>; Kumar, Rahul1 <rahul1.kumar@...>; De, Debkumar <debkumar.de@...>; Han, Harry <harry.han@...>; West, Catharine <catharine.west@...>; V, Sangeetha <sangeetha.v@...> Subject: [PATCH] UefiCpuPkg VTF0 X64: Build page tables using 1-GByte Page Granularity REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3473 X64 Reset Vector Code can access the memory range till 4GB using the Linear-Address Translation to a 2-MByte Page, when user wants to use more than 4G using 2M Page it will leads to use more number of Page table entries. using the 1-GByte Page table user can use more than 4G Memory by reducing the page table entries using 1-GByte Page, this patch attached can access memory range till 512GByte. Build Scrips for Reset Vector currently based on Python 2 which is already EOL, needs to modify the build script based on Python 3, update the Binary accordingly. Cc: Ray Ni <ray.ni@...> Cc: Rahul Kumar <rahul1.kumar@...> Cc: Debkumar De <debkumar.de@...> Cc: Harry Han <harry.han@...> Cc: Catharine West <catharine.west@...> Cc: Sangeetha V <sangeetha.v@...> Signed-off-by: Ashraf Ali S <ashraf.ali.s@...> --- .../Vtf0/Bin/ResetVector.ia32.port80.raw | Bin 516 -> 484 bytes .../ResetVector/Vtf0/Bin/ResetVector.ia32.raw | Bin 484 -> 468 bytes .../Vtf0/Bin/ResetVector.ia32.serial.raw | Bin 884 -> 868 bytes .../Vtf0/Bin/ResetVector.x64.port80.raw | Bin 28676 -> 12292 bytes .../ResetVector/Vtf0/Bin/ResetVector.x64.raw | Bin 28676 -> 12292 bytes .../Vtf0/Bin/ResetVector.x64.serial.raw | Bin 28676 -> 12292 bytes UefiCpuPkg/ResetVector/Vtf0/Build.py | 11 +-- .../ResetVector/Vtf0/Ia32/PageTables64.asm | 2 +- UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt | 2 +- .../Vtf0/Tools/FixupForRawSection.py | 4 +- UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb | 4 +- .../ResetVector/Vtf0/X64/1GPageTables.asm | 64 ++++++++++++++++++ .../X64/{PageTables.asm => 2MPageTables.asm} | 0 13 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z-Zx!yl|1K~Y5VAFw*NPu>jxZ8+LiY1s~6g>m;cwT=R9KT36I!%{N<l{UHrsdZ+qPr zUiqjqr>}eRnR`C$a6KFj?aVu#beNVK<DPuX;Vf^NM}9E3U2{y&zGnLu9^;vN9v64r ze^=i%cRg^|TTWhbn5#=qjXJ!?&o3@lC-CZc=zrnA?0X*e>weB}jn}{MWe<MP>p$^j z58iO*;u}u#y@!kU<R`D3Jo?JXOW%9t%E>M7JAA3bjNX3F;bkBC7rNV@_NLpP_Qu<v j_J-Rp&Xu=6c;CbCb@e@7{+Tb1OP3z}mY;w3OP78Y>oK+# diff --git a/UefiCpuPkg/ResetVector/Vtf0/Build.py b/UefiCpuPkg/ResetVector/Vtf0/Build.py index 343c53b5ff..29f29ff0c2 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Build.py +++ b/UefiCpuPkg/ResetVector/Vtf0/Build.py @@ -1,7 +1,7 @@ ## @file # Automate the process of building the various reset vector types # -# Copyright (c) 2009, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2009 - 2021, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -32,16 +32,19 @@ for arch in ('ia32', 'x64'): '-o', output, 'Vtf0.nasmb', ) + print(f"Command : {' '.join(commandLine)}") ret = RunCommand(commandLine) - print '\tASM\t' + output - if ret != 0: sys.exit(ret) + if ret != 0: + print(f"something went wrong while executing the {commandLine[-1]}") + sys.exit() + print('\tASM\t' + output) commandLine = ( 'python', 'Tools/FixupForRawSection.py', output, ) - print '\tFIXUP\t' + output + print('\tFIXUP\t' + output) ret = RunCommand(commandLine) if ret != 0: sys.exit(ret) diff --git a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm index 87a4125d4b..9cc6f56c17 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm +++ b/UefiCpuPkg/ResetVector/Vtf0/Ia32/PageTables64.asm @@ -15,7 +15,7 @@ BITS 32 SetCr3ForPageTables64: ; - ; These pages are built into the ROM image in X64/PageTables.asm + ; These pages are built into the ROM image in X64/1GPageTables.asm ; mov eax, ADDR_OF(TopLevelPageDirectory) mov cr3, eax diff --git a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt index e6e5b54243..eb9dd24ee2 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt +++ b/UefiCpuPkg/ResetVector/Vtf0/ReadMe.txt @@ -29,7 +29,7 @@ EBP/RBP - Pointer to the start of the Boot Firmware Volume === HOW TO BUILD VTF0 === Dependencies: -* Python 2.5~2.7 +* Python 3.0 or newer * Nasm 2.03 or newer To rebuild the VTF0 binaries: diff --git a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py index c77438a0ce..de771eba22 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py +++ b/UefiCpuPkg/ResetVector/Vtf0/Tools/FixupForRawSection.py @@ -1,7 +1,7 @@ ## @file # Apply fixup to VTF binary image for FFS Raw section # -# Copyright (c) 2008, Intel Corporation. All rights reserved.<BR> +# Copyright (c) 2008 - 2021, Intel Corporation. All rights +reserved.<BR> # # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -15,6 +15,6 @@ c = ((len(d) + 4 + 7) & ~7) - 4 if c > len(d): c -= len(d) f = open(sys.argv[1], 'wb') - f.write('\x90' * c) + f.write(b'\x90' * c) f.write(d) f.close() diff --git a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb index 493738c79c..0625efc456 100644 --- a/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb +++ b/UefiCpuPkg/ResetVector/Vtf0/Vtf0.nasmb @@ -2,7 +2,7 @@ ; @file ; This file includes all other code files to assemble the reset vector code ; -; Copyright (c) 2008 - 2013, Intel Corporation. All rights reserved.<BR> +; Copyright (c) 2008 - 2021, Intel Corporation. All rights +reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; ;------------------------------------------------------------------------------ @@ -36,7 +36,7 @@ %include "PostCodes.inc" %ifdef ARCH_X64 -%include "X64/PageTables.asm" +%include "X64/1GPageTables.asm" %endif %ifdef DEBUG_PORT80 diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm new file mode 100644 index 0000000000..8ae6c4c98c --- /dev/null +++ b/UefiCpuPkg/ResetVector/Vtf0/X64/1GPageTables.asm @@ -0,0 +1,64 @@ +;---------------------------------------------------------------------- +-------- +; @file +; Emits Page Tables for 1:1 mapping of the addresses 0 - 0x8000000000 +(512GB) ; ; Copyright (c) 2021, Intel Corporation. All rights +reserved.<BR> ; SPDX-License-Identifier: BSD-2-Clause-Patent ; +Linear-Address Translation to a 1-GByte Page ; +;---------------------------------------------------------------------- +-------- + +BITS 64 + +%define ALIGN_TOP_TO_4K_FOR_PAGING + +%define PAGE_PRESENT 0x01 +%define PAGE_READ_WRITE 0x02 +%define PAGE_USER_SUPERVISOR 0x04 +%define PAGE_WRITE_THROUGH 0x08 +%define PAGE_CACHE_DISABLE 0x010 +%define PAGE_ACCESSED 0x020 +%define PAGE_DIRTY 0x040 +%define PAGE_PAT 0x080 +%define PAGE_GLOBAL 0x0100 +%define PAGE_1G 0x80 + +%define PAGE_PDP_ATTR (PAGE_ACCESSED + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT) + +%define PAGE_PDP_1G_ATTR (PAGE_ACCESSED + \ + PAGE_READ_WRITE + \ + PAGE_PRESENT + \ + PAGE_1G) + +%define PGTBLS_OFFSET(x) ((x) - TopLevelPageDirectory) %define +PGTBLS_ADDR(x) (ADDR_OF(TopLevelPageDirectory) + (x)) + +%define PDP(offset) (ADDR_OF(TopLevelPageDirectory) + (offset) + \ + PAGE_PDP_ATTR) + +%define PDP_1G(x) ((x << 30) + PAGE_PDP_1G_ATTR) + +ALIGN 16 + +TopLevelPageDirectory: + + ; + ; Top level Page Directory Pointers (1 * 512GB entry) + ; + DQ PDP(0x1000) + + + TIMES 0x1000-PGTBLS_OFFSET($) DB 0 + ; + ; Next level Page Directory Pointers (512 * 1GB entries => 512GB) + ; +%assign i 0 +%rep 512 + DQ PDP_1G(i) + %assign i i+1 +%endrep + + +EndOfPageTables: diff --git a/UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm b/UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm similarity index 100% rename from UefiCpuPkg/ResetVector/Vtf0/X64/PageTables.asm rename to UefiCpuPkg/ResetVector/Vtf0/X64/2MPageTables.asm -- 2.32.0.windows.1
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Re: [PATCH] UefiCpuPkg: SecCoreNative without ResetVector
Ni, Ray
Ashraf,
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What unit tests have you performed with this native SecCore? Thanks, Ray
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From: S, Ashraf Ali <ashraf.ali.s@...> Sent: Wednesday, July 14, 2021 5:48 PM To: devel@edk2.groups.io Cc: S, Ashraf Ali <ashraf.ali.s@...>; Ni, Ray <ray.ni@...>; Kumar, Rahul1 <rahul1.kumar@...>; De, Debkumar <debkumar.de@...>; Han, Harry <harry.han@...>; West, Catharine <catharine.west@...>; Solanki, Digant H <digant.h.solanki@...>; V, Sangeetha <sangeetha.v@...> Subject: [PATCH] UefiCpuPkg: SecCoreNative without ResetVector REF:https://bugzilla.tianocore.org/show_bug.cgi?id=3492 Currently SecCore.inf having the resetvector code under IA32. if the user wants to use both SecCore and UefiCpuPkg ResetVector it's not possible, since SecCore and ResetVector(VTF0.INF/ResetVector.inf) are sharing the same GUID which is BFV. to overcome this issue we can create the Duplicate version of the SecCore.inf as SecCoreNative.inf which contains pure SecCore Native functionality without resetvector. SecCoreNative.inf should have the Unique GUID so that it can be used along with UefiCpuPkg ResetVector in there implementation. Signed-off-by: Ashraf Ali S <ashraf.ali.s@...> Cc: Ray Ni <ray.ni@...> Cc: Rahul Kumar <rahul1.kumar@...> Cc: Debkumar De <debkumar.de@...> Cc: Harry Han <harry.han@...> Cc: Catharine West <catharine.west@...> Cc: Digant H Solanki <digant.h.solanki@...> Cc: Sangeetha V <sangeetha.v@...> --- UefiCpuPkg/SecCore/SecCoreNative.inf | 80 ++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 UefiCpuPkg/SecCore/SecCoreNative.inf diff --git a/UefiCpuPkg/SecCore/SecCoreNative.inf b/UefiCpuPkg/SecCore/SecCoreNative.inf new file mode 100644 index 0000000000..f89a0e5f38 --- /dev/null +++ b/UefiCpuPkg/SecCore/SecCoreNative.inf @@ -0,0 +1,80 @@ +## @file +# SecCoreNative module that implements the SEC phase. +# +# This is the first module taking control after the reset vector. +# The entry point function is _ModuleEntryPoint in PlatformSecLib. +# The entry point function will start with protected mode, since the # +the transistion to flat mode it done by the resetvector, enable # +temporary memory and call into SecStartup(). +# +# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR> # +SPDX-License-Identifier: BSD-2-Clause-Patent # ## + +[Defines] + INF_VERSION = 0x00010005 + BASE_NAME = SecCore + MODULE_UNI_FILE = SecCore.uni + FILE_GUID = 43CA74CA-7D29-49A0-B3B9-20F84015B27D + MODULE_TYPE = SEC + VERSION_STRING = 1.0 + + +# +# The following information is for reference only and not required by the build tools. +# +# VALID_ARCHITECTURES = IA32 X64 EBC +# + +[Sources] + SecMain.c + SecMain.h + FindPeiCore.c + SecBist.c + +[Packages] + MdePkg/MdePkg.dec + MdeModulePkg/MdeModulePkg.dec + UefiCpuPkg/UefiCpuPkg.dec + +[LibraryClasses] + BaseMemoryLib + DebugLib + PlatformSecLib + PcdLib + DebugAgentLib + UefiCpuLib + PeCoffGetEntryPointLib + PeCoffExtraActionLib + CpuExceptionHandlerLib + ReportStatusCodeLib + PeiServicesLib + PeiServicesTablePointerLib + HobLib + +[Ppis] + ## SOMETIMES_CONSUMES + ## PRODUCES + gEfiSecPlatformInformationPpiGuid + ## SOMETIMES_CONSUMES + ## SOMETIMES_PRODUCES + gEfiSecPlatformInformation2PpiGuid + gEfiTemporaryRamDonePpiGuid ## PRODUCES + ## NOTIFY + ## SOMETIMES_CONSUMES + gPeiSecPerformancePpiGuid + gEfiPeiCoreFvLocationPpiGuid + ## CONSUMES + gRepublishSecPpiPpiGuid + +[Guids] + ## SOMETIMES_PRODUCES ## HOB + gEfiFirmwarePerformanceGuid + +[Pcd] + gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize ## CONSUMES + gEfiMdeModulePkgTokenSpaceGuid.PcdMigrateTemporaryRamFirmwareVolumes +## CONSUMES + +[UserExtensions.TianoCore."ExtraFiles"] + SecCoreExtra.uni -- 2.30.2.windows.1
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Re: [PATCH EDK2 v1 1/1] MdeModulePkg: Modify PCD default value
Ni, Ray
Wenyi,
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Can you explain a bit more about "if 52 bit physical address need to be supported, page size should also be set to 64KB alignment"? Can the platform DSC override this value instead of changing the default value in MdeModulePkg.dec which impacts all platforms? Thanks, Ray
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From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of wenyi,xie via groups.io Sent: Thursday, July 15, 2021 8:25 PM To: devel@edk2.groups.io; Wang, Jian J <jian.j.wang@...>; Wu, Hao A <hao.a.wu@...> Cc: songdongkuang@...; wanghuiqiang@...; xiewenyi2@... Subject: [edk2-devel] [PATCH EDK2 v1 1/1] MdeModulePkg: Modify PCD default value From: "wenyi.xie" <xiewenyi2@...> The default value of PcdSrIovSystemPageSize is 0x1, it means the memory BAR is 4KB alignment. When page size of OS is set to 64KB, as the resource partitions are different between OS and BIOS, it will cause pcie failture. And if 52 bit physical address need to be supported, page size should also be set to 64KB alignment. So modify the default vaule of PcdSrIovSystemPageSize to 0x10 can meet the requirement above. And even if the OS is 4KB alignment, new value of PCD is compatible for this situation. Cc: Jian J Wang <jian.j.wang@...> Cc: Hao A Wu <hao.a.wu@...> Signed-off-by: Wenyi Xie <xiewenyi2@...> --- MdeModulePkg/MdeModulePkg.dec | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MdeModulePkg/MdeModulePkg.dec b/MdeModulePkg/MdeModulePkg.dec index ad84421cf3..426ea1b6cc 100644 --- a/MdeModulePkg/MdeModulePkg.dec +++ b/MdeModulePkg/MdeModulePkg.dec @@ -1853,7 +1853,7 @@ # BIT0 set indicates 4KB alignment<BR> # BIT1 set indicates 8KB alignment<BR> # @Prompt SRIOV system page size. - gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x1|UINT32|0x10000047 + + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x10|UINT32|0x10 + 000047 ## SMBIOS version. # @Prompt SMBIOS version. -- 2.20.1.windows.1
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Re: [PATCH v2 07/11] OvmfPkg/QemuKernelLoaderFsDxe: call VerifyBlob after fetch from fw_cfg
Brijesh Singh
On 7/6/21 3:54 AM, Dov Murik wrote:
In QemuKernelLoaderFsDxeEntrypoint we use FetchBlob to read the contentThe patch itself is okay. Just curious, do we also need to add a verification for the QEMU FW cfg file ?
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