Date   

Re: [PATCH 6/9] UefiPayloadPkg: Creat gPldSmbiosTableGuid Hob

Guo Dong
 

Reviewed-by: Guo Dong <guo.dong@intel.com>

-----Original Message-----
From: Liu, Zhiguang <zhiguang.liu@intel.com>
Sent: Monday, May 24, 2021 12:13 AM
To: devel@edk2.groups.io
Cc: Ma, Maurice <maurice.ma@intel.com>; Dong, Guo
<guo.dong@intel.com>; You, Benjamin <benjamin.you@intel.com>
Subject: [PATCH 6/9] UefiPayloadPkg: Creat gPldSmbiosTableGuid Hob

From SysTableInfo Hob, get Smbios table address, and creat
gPldSmbiosTableGuid Hob
to store it. Remove diretly adding smbios table to ConfigurationTable.
Dxe module SmbiosDxe will parse it and install smbios table from it.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Guo Dong <guo.dong@intel.com>
Cc: Benjamin You <benjamin.you@intel.com>
Signed-off-by: Zhiguang Liu <zhiguang.liu@intel.com>
---
UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c | 11 +----------
UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf | 3 +--
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c | 12 +++++++++++-
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h | 3 ++-
UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf | 3 ++-
5 files changed, 17 insertions(+), 15 deletions(-)

diff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
index a746d0581e..56b85b8e6d 100644
--- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
+++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.c
@@ -2,7 +2,7 @@
This driver will report some MMIO/IO resources to dxe core, extract smbios
and acpi

tables from bootloader.



- Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>

+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

@@ -129,15 +129,6 @@ BlDxeEntryPoint (
ASSERT_EFI_ERROR (Status);

}



- //

- // Install Smbios Table

- //

- if (SystemTableInfo->SmbiosTableBase != 0 && SystemTableInfo-
SmbiosTableSize != 0) {
- DEBUG ((DEBUG_ERROR, "Install Smbios Table at 0x%lx, length 0x%x\n",
SystemTableInfo->SmbiosTableBase, SystemTableInfo->SmbiosTableSize));

- Status = gBS->InstallConfigurationTable (&gEfiSmbiosTableGuid, (VOID
*)(UINTN)SystemTableInfo->SmbiosTableBase);

- ASSERT_EFI_ERROR (Status);

- }

-

//

// Find the frame buffer information and update PCDs

//

diff --git a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
index cebc811355..30f41f8c39 100644
--- a/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
+++ b/UefiPayloadPkg/BlSupportDxe/BlSupportDxe.inf
@@ -3,7 +3,7 @@
#

# Report some MMIO/IO resources to dxe core, extract smbios and acpi
tables

#

-# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>

+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>

#

# SPDX-License-Identifier: BSD-2-Clause-Patent

#

@@ -43,7 +43,6 @@


[Guids]

gEfiAcpiTableGuid

- gEfiSmbiosTableGuid

gUefiSystemTableInfoGuid

gUefiAcpiBoardInfoGuid

gEfiGraphicsInfoHobGuid

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
index 805f5448d9..7b71d37f94 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.c
@@ -1,6 +1,6 @@
/** @file



- Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>

+ Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

@@ -234,6 +234,7 @@ BuildHobFromBl (
EFI_PEI_GRAPHICS_INFO_HOB *NewGfxInfo;

EFI_PEI_GRAPHICS_DEVICE_INFO_HOB GfxDeviceInfo;

EFI_PEI_GRAPHICS_DEVICE_INFO_HOB *NewGfxDeviceInfo;

+ PLD_SMBIOS_TABLE *SmBiosTableHob;



//

// Parse memory info and build memory HOBs

@@ -276,6 +277,15 @@ BuildHobFromBl (
DEBUG ((DEBUG_INFO, "Detected Acpi Table at 0x%lx, length 0x%x\n",
SysTableInfo.AcpiTableBase, SysTableInfo.AcpiTableSize));

DEBUG ((DEBUG_INFO, "Detected Smbios Table at 0x%lx, length 0x%x\n",
SysTableInfo.SmbiosTableBase, SysTableInfo.SmbiosTableSize));

}

+ //

+ // Creat SmBios table Hob

+ //

+ SmBiosTableHob = BuildGuidHob (&gPldSmbiosTableGuid, sizeof
(PLD_SMBIOS_TABLE));

+ ASSERT (SmBiosTableHob != NULL);

+ SmBiosTableHob->PldHeader.Revision = PLD_SMBIOS_TABLE_REVISION;

+ SmBiosTableHob->PldHeader.Length = sizeof (PLD_SMBIOS_TABLE);

+ SmBiosTableHob->SmBiosEntryPoint = SysTableInfo.SmbiosTableBase;

+ DEBUG ((DEBUG_INFO, "Create smbios table gPldSmbiosTableGuid guid
hob\n"));



//

// Create guid hob for acpi board information

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
index 2c84d6ed53..e7d0d15118 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.h
@@ -1,6 +1,6 @@
/** @file

*

-* Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>

+* Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

*

* SPDX-License-Identifier: BSD-2-Clause-Patent

*

@@ -31,6 +31,7 @@
#include <Guid/MemoryMapInfoGuid.h>

#include <Guid/AcpiBoardInfoGuid.h>

#include <Guid/GraphicsInfoHob.h>

+#include <UniversalPayload/SmbiosTable.h>





#define LEGACY_8259_MASK_REGISTER_MASTER 0x21

diff --git a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
index cc59f1903b..444f39acf3 100644
--- a/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
+++ b/UefiPayloadPkg/UefiPayloadEntry/UefiPayloadEntry.inf
@@ -1,7 +1,7 @@
## @file

# This is the first module for UEFI payload.

#

-# Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>

+# Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>

# Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>

#

# SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -64,6 +64,7 @@
gEfiGraphicsInfoHobGuid

gEfiGraphicsDeviceInfoHobGuid

gUefiAcpiBoardInfoGuid

+ gPldSmbiosTableGuid



[FeaturePcd.IA32]

gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode ##
CONSUMES

--
2.30.0.windows.2


Re: [PATCH v3 1/1] UefiCpuPkg/CpuCommonFeaturesLib: Update processor location info

Ni, Ray
 

When reviewing V2, I only focused on whether the C code change is good.

I am ok that this patch contains not just processor location check logic update, but also updates to comments
that are not related to the location check.

2 minor comments:
1. Change the commit message title to "UefiCpuPkg/CpuCommonFeaturesLib: correct the CPU location check"
2. Update the commit message body to mention the other changes you did to comments.

-----Original Message-----
From: Li, Daoxiang <daoxiang.li@intel.com>
Sent: Wednesday, June 2, 2021 10:25 AM
To: devel@edk2.groups.io
Cc: Li, Daoxiang <daoxiang.li@intel.com>; Dong, Eric <eric.dong@intel.com>;
Ni, Ray <ray.ni@intel.com>; Laszlo Ersek <lersek@redhat.com>; Kumar,
Rahul1 <rahul1.kumar@intel.com>
Subject: [PATCH v3 1/1] UefiCpuPkg/CpuCommonFeaturesLib: Update
processor location info

From: Daoxiang Li <daoxiang.li@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3424

Processor location information check needs to updated
When Core 0 is disabled

Signed-off-by: Daoxiang Li <daoxiang.li@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
---
UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 4 ++--
UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c | 4 ++--
UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c | 6 +++---
3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
index e6e5db75917c..6f9685733202 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
@@ -63,9 +63,9 @@ C1eInitialize (
{

//

// The scope of C1EEnable bit in the MSR_NEHALEM_POWER_CTL is
Package, only program

- // MSR_FEATURE_CONFIG for thread 0 core 0 in each package.

+ // MSR_NEHALEM_POWER_CTL once for each package.

//

- if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo-
ProcessorInfo.Location.Core != 0)) {
+ if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {

return RETURN_SUCCESS;

}



diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
index bb5d983d1f4b..a3a2861cee5b 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
@@ -152,10 +152,10 @@ McaInitialize (


//

// The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is package
for below processor type, only program

- // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 core 0 in
each package.

+ // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS once for each package.

//

if (IS_NEHALEM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo-
DisplayModel)) {
- if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo-
ProcessorInfo.Location.Core != 0)) {
+ if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {

return RETURN_SUCCESS;

}

}

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
index 8450c7ea3eaf..3c4c1bc706ba 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
@@ -130,10 +130,10 @@ PpinInitialize (
// Support function already check the processor which support PPIN
feature, so this function not need

// to check the processor again.

//

- // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only
program MSR_IVY_BRIDGE_PPIN_CTL for

- // thread 0 core 0 in each package.

+ // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only
program MSR_IVY_BRIDGE_PPIN_CTL

+ // once for each package.

//

- if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo-
ProcessorInfo.Location.Core != 0)) {
+ if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {

return RETURN_SUCCESS;

}



--
2.28.0.windows.1


Re: 回复: 回复: 回复: [edk2-devel] [PATCH v1 1/1] Add MemoryFence implementation for RiscV64

Daniel Schaefer
 

On 6/2/21 10:16 AM, gaoliming wrote:
Laszlo:
Thanks for the detail information about QemuFwCfgLib. So, this library is arch generic. Now, it is only consumed by ARM and AARCH64.
Daniel:
Can you show more on how RiscV64 uses this QemuFwCfgLib?
See below. QEMU for the generic RISCV64 platform is implemented almost like Arm with device tree and fw-cfg device, quite unlike X64 which uses port-mapped I/O and doesn't have device trees.

Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Laszlo Ersek
发送时间: 2021年6月1日 15:58
收件人: gaoliming <gaoliming@byosoft.com.cn>; devel@edk2.groups.io;
daniel.schaefer@hpe.com; ardb@kernel.org
抄送: 'Chang, Abner (HPS SW/FW Technologist)' <abner.chang@hpe.com>;
'Michael D Kinney' <michael.d.kinney@intel.com>; 'Zhiguang Liu'
<zhiguang.liu@intel.com>; 'Leif Lindholm' <leif@nuviainc.com>
主题: Re: 回复: 回复: [edk2-devel] [PATCH v1 1/1] Add MemoryFence
implementation for RiscV64

On 06/01/21 02:56, gaoliming wrote:
Seemly, Edk2\ArmVirtPkg\Library\QemuFwCfgLib\QemuFwCfgLib.inf is not
arch
specific library. It can also be used in RISCV64.



Ard and Laszlo:

If ArmVirtPkg\Library\QemuFwCfgLib is arch generic, can it be moved
from
ArmVirtPkg into OvmfPkg?
ArmVirtPkg/Library/QemuFwCfgLib is a QemuFwCfgLib instance that is
currently only used by the ArmVirtQemu and ArmVirtQemuKernel platforms.
​Yes, but we're in the process of Creating RiscvVirtPkg that just like ArmVirtPkg supports the generic "virt" machine type of qemu-system-riscv64.

It depends on the FDT_CLIENT_PROTOCOL, from
"ArmVirtPkg/ArmVirtPkg.dec"
and "ArmVirtPkg/Include/Protocol/FdtClient.h", to locate the fw_cfg
device. The protocol is ArmVirtPkg specific. Due to the protocol depex,
the library is also DXE_DRIVER and UEFI_DRIVER only.
​Yes, we also use that in our RiscvVirtPkg ;)

The library uses the MMIO data registers of the fw_cfg device by
default; if the DMA interface is supported, then it uses the DMA
interface. In both cases, some registers are accessed with 64-bit
accesses if MDE_CPU_AARCH64 is defined, and with 32-bit accesses
otherwise.

I don't see how RISCV could reuse this library verbatim.
​Why not? We can boot perfectly fine from virtio (which is PCI) with these lines in our RIscvVirt.dsc:

# Flattened Device Tree (FDT) access library
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf

# PCI Libraries
PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
PciExpressLib|ArmVirtPkg/Library/BaseCachingPciExpressLib/BaseCachingPciExpressLib.inf
PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
PciCapLib|OvmfPkg/Library/BasePciCapLib/BasePciCapLib.inf
PciCapPciSegmentLib|OvmfPkg/Library/BasePciCapPciSegmentLib/BasePciCapPciSegmentLib.inf
PciCapPciIoLib|OvmfPkg/Library/UefiPciCapPciIoLib/UefiPciCapPciIoLib.inf

# Virtio Support
VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf
VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf
QemuFwCfgLib|ArmVirtPkg/Library/QemuFwCfgLib/QemuFwCfgLib.inf
QemuFwCfgS3Lib|OvmfPkg/Library/QemuFwCfgS3Lib/BaseQemuFwCfgS3LibNull.inf
QemuFwCfgSimpleParserLib|OvmfPkg/Library/QemuFwCfgSimpleParserLib/QemuFwCfgSimpleParserLib.inf
QemuLoadImageLib|OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.inf

# PCI support
PciPcdProducerLib|ArmVirtPkg/Library/FdtPciPcdProducerLib/FdtPciPcdProducerLib.inf
PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
PciHostBridgeLib|ArmVirtPkg/Library/FdtPciHostBridgeLib/FdtPciHostBridgeLib.inf
PciHostBridgeUtilityLib|OvmfPkg/Library/PciHostBridgeUtilityLib/PciHostBridgeUtilityLib.inf

Excerpt from the edk2 boot log:

InvalidateInstructionCacheRange:RISC-V unsupported function.
Loading driver at 0x000BF7EC000 EntryPoint=0x000BF7EC28A PciHostBridgeDxe.efi
InstallProtocolInterface: BC62157E-3E33-4FEC-9920-2D3B36D750DF BF31EF18
ProtectUefiImageCommon - 0xBF334BC0
- 0x00000000BF7EC000 - 0x0000000000014080
PROGRESS CODE: V03040002 I0
Found FwCfg @ 0x10100008/0x10100000
Found FwCfg DMA @ 0x10100010
ProcessPciHost: Config[0x30000000+0x10000000) Bus[0x0..0xFF] Io[0x0+0x10000)@0x3000000 Mem32[0x40000000+0x40000000)@00

​If you look at the source code of the QEMU implementation of riscv64 virt and compare it to aarch64 they are very similar, but quite different from x64.

The linked patch at
<https://github.com/riscv/riscv-edk2/commit/8c7960ef860c65f2646912c3dc
cbb308a>
is a no-go; the MDE_CPU_RISCV64 macro has no place in an ArmVirtPkg
library.

The library can be moved to the new directory

OvmfPkg/Library/DxeQemuFwCfgLibFdtMmio

(note the rename in the last pathname component), but it needs to be
done in multiple steps. The FDT protocol GUID and structure definition
has to be moved at first, separately from the library, and every move
operation (i.e., each one of the protocol move and the library muve)
must be implemented with *at least* three steps -- copy the original to
OvmfPkg (updating BASE_NAME at once), update DSC references under
ArmVirtPkg, remove the original under ArmVirtPkg. Only then can you add
customizations.
Okay, I understand and agree. We'll think about all of the Arm modules and libraries we're currently using, how to move those and send an RFC soon. We have not encountered any other issues, other than this change, when using the Arm code.

Regarding the processor type macros, I believe Mike recently introduced
ISA-independent macros, for expressing 64-bit vs. 32-bit. I'm not
exactly sure about the details, but I think we now have a macro under
MdePkg that says "64-bit processor" without having to state AARCH64 or
RISCV64.
I found some at
CryptoPkg/Library/Include/CrtLibSupport.h
and
RedfishPkg/PrivateInclude/Library/RedfishCrtLib.h
called SIXTY_FOUR_BIT and THIRTY_TWO_BIT.

Not sure if they are for general consumption?
It seems that Mike suggests those to be defined in the platform's DSC?
See d0bf83e1cca

Thanks
Laszlo





Thanks

Liming

发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Daniel
Schaefer
发送时间: 2021年5月21日 20:46
收件人: devel@edk2.groups.io; gaoliming@byosoft.com.cn
抄送: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>;
'Michael
D Kinney' <michael.d.kinney@intel.com>; 'Zhiguang Liu'
<zhiguang.liu@intel.com>; 'Leif Lindholm' <leif@nuviainc.com>
主题: Re: 回复: [edk2-devel] [PATCH v1 1/1] Add MemoryFence
implementation
for RiscV64



It's not required to go into that tag.

We need two more patches that we haven't submitted yet to boot on
Qemu.



Would it be okay if we used a library from ArmVirtPkg for RISCV64?

See:
https://github.com/riscv/riscv-edk2/commit/8c7960ef860c65f2646912c3dcc
bb308a
98e0cc3

Or does it have to be moved to some other place first?

_____

From: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
<devel@edk2.groups.io <mailto:devel@edk2.groups.io> > on behalf of
gaoliming
<gaoliming@byosoft.com.cn <mailto:gaoliming@byosoft.com.cn> >
Sent: Friday, May 21, 2021 14:35
To: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
<devel@edk2.groups.io <mailto:devel@edk2.groups.io> >; Schaefer, Daniel
<daniel.schaefer@hpe.com <mailto:daniel.schaefer@hpe.com> >
Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com
<mailto:abner.chang@hpe.com> >; 'Michael D Kinney'
<michael.d.kinney@intel.com <mailto:michael.d.kinney@intel.com> >;
'Zhiguang
Liu' <zhiguang.liu@intel.com <mailto:zhiguang.liu@intel.com> >; 'Leif
Lindholm' <leif@nuviainc.com <mailto:leif@nuviainc.com> >
Subject: 回复: 回复: [edk2-devel] [PATCH v1 1/1] Add MemoryFence
implementation for RiscV64



Daniel:

Thanks for your information. Acked-by: Liming Gao
<gaoliming@byosoft.com.cn
<mailto:gaoliming@byosoft.com.cn> >



And, do you request to merge this patch for edk2 stable tag 202105?



Thanks

Liming

发件人: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
<devel@edk2.groups.io <mailto:devel@edk2.groups.io> > 代表 Daniel
Schaefer
发送时间: 2021年5月21日 13:27
收件人: devel@edk2.groups.io <mailto:devel@edk2.groups.io> ;
gaoliming@byosoft.com.cn <mailto:gaoliming@byosoft.com.cn>
抄送: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com
<mailto:abner.chang@hpe.com> >; 'Michael D Kinney'
<michael.d.kinney@intel.com <mailto:michael.d.kinney@intel.com> >;
'Zhiguang
Liu' <zhiguang.liu@intel.com <mailto:zhiguang.liu@intel.com> >; 'Leif
Lindholm' <leif@nuviainc.com <mailto:leif@nuviainc.com> >
主题: Re: 回复: [edk2-devel] [PATCH v1 1/1] Add MemoryFence
implementation
for RiscV64



Great!



It is verified I can boot Linux from a virtio ESP using this patch on QEMU
virt machine.

See:
https://github.com/riscv/riscv-edk2-platforms/runs/2618819010?check_suite
_fo
cus=true



Thanks,

Daniel

_____

From: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
<devel@edk2.groups.io <mailto:devel@edk2.groups.io> > on behalf of
gaoliming
<gaoliming@byosoft.com.cn <mailto:gaoliming@byosoft.com.cn> >
Sent: Friday, May 21, 2021 13:14
To: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
<devel@edk2.groups.io <mailto:devel@edk2.groups.io> >; Schaefer, Daniel
<daniel.schaefer@hpe.com <mailto:daniel.schaefer@hpe.com> >
Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com
<mailto:abner.chang@hpe.com> >; 'Michael D Kinney'
<michael.d.kinney@intel.com <mailto:michael.d.kinney@intel.com> >;
'Zhiguang
Liu' <zhiguang.liu@intel.com <mailto:zhiguang.liu@intel.com> >; 'Leif
Lindholm' <leif@nuviainc.com <mailto:leif@nuviainc.com> >
Subject: 回复: 回复: [edk2-devel] [PATCH v1 1/1] Add MemoryFence
implementation for RiscV64



Daniel:
Now, it is clear to me. So, I suggest to merge this change when it is
verified on generic RISC-V QEMU virt machine. Is it OK?

Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
<devel@edk2.groups.io <mailto:devel@edk2.groups.io> > 代表 Daniel
Schaefer
发送时间: 2021年5月18日 10:35
收件人: devel@edk2.groups.io <mailto:devel@edk2.groups.io> ;
gaoliming@byosoft.com.cn <mailto:gaoliming@byosoft.com.cn>
抄送: 'Abner Chang' <abner.chang@hpe.com
<mailto:abner.chang@hpe.com> >;
'Michael D Kinney'
<michael.d.kinney@intel.com <mailto:michael.d.kinney@intel.com> >;
'Zhiguang Liu' <zhiguang.liu@intel.com <mailto:zhiguang.liu@intel.com> >;
'Leif
Lindholm' <leif@nuviainc.com <mailto:leif@nuviainc.com> >
主题: Re: 回复: [edk2-devel] [PATCH v1 1/1] Add MemoryFence
implementation for RiscV64

On 5/18/21 9:04 AM, gaoliming wrote:
Daniel:
Seemly, this API is missing in BaseLib for RiscV64 arch. How do you
detect
this issue?
What do you mean it's missing?
Yes MemoryFence() for RiscV64 is missing currently, that's why I'm adding
it
here.

Maybe you mean that it's not currently used? That's also true.
I'm enabling the generic QEMU virt machine (like OVMF or ArmVirtPkg) for
RISC-V.
At least QemuFwCfgLib and VirtioLib need it.
That's why I have the need to add this implementation now.

Does that clear it up?

Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
<devel@edk2.groups.io <mailto:devel@edk2.groups.io> > 代表 Daniel
Schaefer
发送时间: 2021年5月16日 2:13
收件人: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
抄送: Abner Chang <abner.chang@hpe.com
<mailto:abner.chang@hpe.com> >;
Michael D Kinney
<michael.d.kinney@intel.com <mailto:michael.d.kinney@intel.com> >;
Liming Gao <gaoliming@byosoft.com.cn
<mailto:gaoliming@byosoft.com.cn> >;
Zhiguang Liu <zhiguang.liu@intel.com
<mailto:zhiguang.liu@intel.com> >;
Leif Lindholm
<leif@nuviainc.com <mailto:leif@nuviainc.com> >
主题: [edk2-devel] [PATCH v1 1/1] Add MemoryFence implementation
for
RiscV64

Cc: Abner Chang <abner.chang@hpe.com
<mailto:abner.chang@hpe.com> >
Cc: Michael D Kinney <michael.d.kinney@intel.com
<mailto:michael.d.kinney@intel.com> >
Cc: Liming Gao <gaoliming@byosoft.com.cn
<mailto:gaoliming@byosoft.com.
cn> >
Cc: Zhiguang Liu <zhiguang.liu@intel.com
<mailto:zhiguang.liu@intel.com> >
Cc: Leif Lindholm <leif@nuviainc.com <mailto:leif@nuviainc.com> >
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com
<mailto:daniel.
schaefer@hpe.com> >
---
MdePkg/Library/BaseLib/BaseLib.inf | 1 +
MdePkg/Library/BaseLib/RiscV64/MemoryFence.S | 33
++++++++++++++++++++
2 files changed, 34 insertions(+)

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
b/MdePkg/Library/BaseLib/BaseLib.inf
index b76f3af380ea..b7ab5f632366 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -399,6 +399,7 @@
RiscV64/DisableInterrupts.c


RiscV64/EnableInterrupts.c


RiscV64/CpuPause.c


+ RiscV64/MemoryFence.S | GCC


RiscV64/RiscVSetJumpLongJump.S | GCC


RiscV64/RiscVCpuBreakpoint.S | GCC


RiscV64/RiscVCpuPause.S | GCC


diff --git a/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S
b/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S
new file mode 100644
index 000000000000..283df9356a9a
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S
@@ -0,0 +1,33 @@
+##-------------------------------------------------------------------------
-----


+#


+# MemoryFence() for RiscV64


+


+# Copyright (c) 2021, Hewlett Packard Enterprise Development. All
rights
reserved.


+#


+# SPDX-License-Identifier: BSD-2-Clause-Patent


+#


+##-------------------------------------------------------------------------
-----


+


+.text


+.p2align 2


+


+ASM_GLOBAL ASM_PFX(MemoryFence)


+


+


+#/**


+# Used to serialize load and store operations.


+#


+# All loads and stores that proceed calls to this function are
guaranteed to
be


+# globally visible when this function returns.


+#


+#**/


+#VOID


+#EFIAPI


+#MemoryFence (


+# VOID


+# );


+#


+ASM_PFX(MemoryFence):


+ // Fence on all memory and I/O


+ fence


+ ret


--
2.30.1

























回复: [PATCH v1 1/2] MdePkg/MdeModulePkg: Move AML_NAME_SEG_SIZE definition

gaoliming
 

Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>

-----邮件原件-----
发件人: Pierre.Gondois@arm.com <Pierre.Gondois@arm.com>
发送时间: 2021年6月2日 6:05
收件人: devel@edk2.groups.io; dandan.bi@intel.com;
gaoliming@byosoft.com.cn; michael.d.kinney@intel.com;
Sami.Mujawar@arm.com; Alexei.Fedorov@arm.com
主题: [PATCH v1 1/2] MdePkg/MdeModulePkg: Move AML_NAME_SEG_SIZE
definition

From: Pierre Gondois <Pierre.Gondois@arm.com>

A NameSeg is made 4 chars.
Cf. ACPI 6.4 s20.2.2 "Name Objects Encoding":
NameSeg := <leadnamechar namechar namechar namechar>
Notice that NameSegs shorter than 4 characters are filled
with trailing underscores (‘_’s).

AML_NAME_SEG_SIZE is currently defined in:
- DynamicTablesPkg/Library/Common/AmlLib/AmlDefines.h
- MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h
Since the value can be inferred from the ACPI specification
and to avoid multiple definitions, move it to
MdePkg/Include/IndustryStandard/

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
---
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h | 1 -
MdePkg/Include/IndustryStandard/AcpiAml.h | 7 ++++++-
2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h
b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h
index 50d4c96edb63..1b26729e71c3 100644
--- a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h
+++ b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h
@@ -56,7 +56,6 @@ typedef struct _EFI_AML_NODE_LIST
EFI_AML_NODE_LIST;
// Size is the total size of this ACPI node buffer.
// Children is the children linked list of this node.
//
-#define AML_NAME_SEG_SIZE 4

struct _EFI_AML_NODE_LIST {
UINT32 Signature;
diff --git a/MdePkg/Include/IndustryStandard/AcpiAml.h
b/MdePkg/Include/IndustryStandard/AcpiAml.h
index 74622e912ea4..4255ca3d7087 100644
--- a/MdePkg/Include/IndustryStandard/AcpiAml.h
+++ b/MdePkg/Include/IndustryStandard/AcpiAml.h
@@ -2,7 +2,7 @@
This file contains AML code definition in the latest ACPI spec.

Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
- Copyright (c) 2019, ARM Limited. All rights reserved.<BR>
+ Copyright (c) 2019 - 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent

**/
@@ -176,4 +176,9 @@
#define AML_FIELD_CONNECTION_OP 0x02
#define AML_FIELD_EXT_ACCESS_OP 0x03

+//
+// AML Name segment definitions
+//
+#define AML_NAME_SEG_SIZE 4
+
#endif
--
2.17.1


回复: [edk2-devel] [PATCH 1/4] BaseTools: Create CLANGDWARF toolchain

gaoliming
 

Ray:
Original CLANGELF tool chain is verified on CLANG8. Can you verify it to see whether it meet with your requirement?

If yes, this tool chain can be renamed to CLANGDWARF to match current CLANGPDB tool chain.

Thanks
Liming

-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Ni, Ray
发送时间: 2021年6月1日 23:11
收件人: devel@edk2.groups.io; gaoliming@byosoft.com.cn; Shi, Steven
<steven.shi@intel.com>
抄送: Leif Lindholm <leif@nuviainc.com>; Ard Biesheuvel
<ardb+tianocore@kernel.org>; 'Andrew Fish (afish@apple.com)'
<afish@apple.com>; Justen, Jordan L <jordan.l.justen@intel.com>
主题: Re: [edk2-devel] [PATCH 1/4] BaseTools: Create CLANGDWARF
toolchain

Liming,
I happen to notice the below patches which you sent out two years ago:
https://edk2.groups.io/g/devel/topic/31354044#41053

It seems to me that I can drop my CLANGDWARF change completely and use
your patches.

Correct?

Thanks,
Ray

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of gaoliming
Sent: Monday, May 31, 2021 11:23 AM
To: Ni, Ray <ray.ni@intel.com>; devel@edk2.groups.io; Shi, Steven
<steven.shi@intel.com>
Subject: 回复: [edk2-devel] [PATCH 1/4] BaseTools: Create CLANGDWARF
toolchain

Ray:
If the tool chain generates ELF image, its ELF image can be converted to EFI
image by Edk2 GenFw tool. Then, this tool chain can be used for EFI
development.

So, I propose to make CLANGDWARF tool chain generate ELF image and EFI
image both. It can support the usage of ELF image generation.

Thanks
Liming
发件人: Ni, Ray <mailto:ray.ni@intel.com>
发送时间: 2021年5月28日 22:31
收件人: mailto:devel@edk2.groups.io; mailto:gaoliming@byosoft.com.cn; Shi,
Steven <mailto:steven.shi@intel.com>
主题: Re: [edk2-devel] [PATCH 1/4] BaseTools: Create CLANGDWARF
toolchain

Liming,
that is not the intention of this new toolchain.
we want to have a toolchain that can generate elf. or can you suggest a new
name for this toolchain?

thanks,
ray
________________________________________
From: mailto:devel@edk2.groups.io <mailto:devel@edk2.groups.io> on
behalf of gaoliming <mailto:gaoliming@byosoft.com.cn>
Sent: Friday, May 28, 2021 10:52:06 AM
To: mailto:devel@edk2.groups.io <mailto:devel@edk2.groups.io>; Shi, Steven
<mailto:steven.shi@intel.com>; Ni, Ray <mailto:ray.ni@intel.com>
Subject: 回复: [edk2-devel] [PATCH 1/4] BaseTools: Create CLANGDWARF
toolchain

Ray:
I would like to suggest CLANGDWARF also generate EFI image. If so, the
people can use this tool chain for EFI development with DWARF format debug
symbol.

In dll generation phase, CLANGDWARF still generates dll image, then copy
dll image to elf image. In EFI generation phase, dll image will be converted to
EFI image.

Thanks
Liming
发件人: mailto:devel@edk2.groups.io <mailto:devel@edk2.groups.io> 代表
Steven Shi
发送时间: 2021年5月26日 19:35
收件人: mailto:devel@edk2.groups.io; Ni, Ray <mailto:ray.ni@intel.com>
主题: Re: [edk2-devel] [PATCH 1/4] BaseTools: Create CLANGDWARF
toolchain

Some suggestions:

1. There are many blanks appending the line “+ "$(DLINK)" -o
${dst} $(DLINK_FLAGS) @$(STATIC_LIBRARY_FILES_LIST) “



2. We need a toolchain dependency descirption in the
BaseTools\Conf\tools_def.template. Below is the example for CLANGPDB.
Please add one for the CLANGDWARF.
# CLANGPDB -Linux, Windows, Mac- Requires:
# Clang 9 or above from
http://releases.llvm.org/
# Optional:
# Required to compile nasm
source:
# nasm compiler from
# NASM --
http://www.nasm.us/
# Required to build platforms or
ACPI tables:
# Intel(r) ACPI Compiler from
# https://acpica.org/download
s

3. We could merge the CLANG38 and the CLANGDWARF toolchains together
in the future.


Thanks
Steven Shi


-----Original Message-----
From: mailto:devel@edk2.groups.io <mailto:devel@edk2.groups.io> On
Behalf Of Ni, Ray
Sent: Wednesday, May 26, 2021 4:23 PM
To: mailto:devel@edk2.groups.io
Subject: [edk2-devel] [PATCH 1/4] BaseTools: Create CLANGDWARF
toolchain

Signed-off-by: Ray Ni <mailto:ray.ni@intel.com>
---
BaseTools/Conf/build_rule.template | 10 ++-
BaseTools/Conf/tools_def.template | 98
++++++++++++++++++++++++++++++
2 files changed, 107 insertions(+), 1 deletion(-)

diff --git a/BaseTools/Conf/build_rule.template
b/BaseTools/Conf/build_rule.template
index 1395792cd6..e69f963cc8 100755
--- a/BaseTools/Conf/build_rule.template
+++ b/BaseTools/Conf/build_rule.template
@@ -293,7 +293,10 @@
<ExtraDependency>

$(MAKE_FILE)



- <OutputFile>

+ <OutputFile.CLANGDWARF>

+ $(DEBUG_DIR)(+)$(MODULE_NAME).elf

+

+ <OutputFile.MSFT, OutputFile.INTEL, OutputFile.GCC>

$(DEBUG_DIR)(+)$(MODULE_NAME).dll



<Command.MSFT, Command.INTEL>

@@ -303,6 +306,11 @@
<Command.CLANGPDB>

"$(DLINK)" /OUT:${dst} $(DLINK_FLAGS) $(DLINK_SPATH)
@$(STATIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS)



+ <Command.CLANGDWARF>

+ "$(DLINK)" -o ${dst} $(DLINK_FLAGS)
@$(STATIC_LIBRARY_FILES_LIST)

+ "$(CP)" ${dst} $(DEBUG_DIR)(+)$(MODULE_NAME).debug

+ "$(OBJCOPY)" --strip-unneeded -R .eh_frame ${dst}

+

<Command.GCC>

"$(DLINK)" -o ${dst} $(DLINK_FLAGS) -Wl,--start-
group,@$(STATIC_LIBRARY_FILES_LIST),--end-group $(CC_FLAGS)
$(DLINK2_FLAGS)

"$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst}

diff --git a/BaseTools/Conf/tools_def.template
b/BaseTools/Conf/tools_def.template
index 498696e583..390e297cc1 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -2828,6 +2828,104 @@
NOOPT_CLANGPDB_X64_DLINK_FLAGS =
/NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:RE
NOOPT_CLANGPDB_X64_DLINK2_FLAGS =

NOOPT_CLANGPDB_X64_GENFW_FLAGS = --keepexceptiontable



+#########################################################
###########################

+#

+# CLANGDWARF - This configuration is used to compile under
Windows/Linux/Mac to produce

+# ELF binaries using LLVM/Clang/LLD with Link Time Optimization
enabled

+#

+#########################################################
###########################

+*_CLANGDWARF_*_*_FAMILY = GCC

+*_CLANGDWARF_*_*_BUILDRULEFAMILY = CLANGDWARF

+*_CLANGDWARF_*_MAKE_PATH =
ENV(CLANG_HOST_BIN)make

+*_CLANGDWARF_*_*_DLL =
ENV(CLANGPDB_DLL)

+*_CLANGDWARF_*_ASL_PATH = DEF(UNIX_IASL_BIN)

+

+*_CLANGDWARF_*_APP_FLAGS =

+*_CLANGDWARF_*_ASL_FLAGS =
DEF(DEFAULT_WIN_ASL_FLAGS)

+*_CLANGDWARF_*_ASL_OUTFLAGS =
DEF(DEFAULT_WIN_ASL_OUTFLAGS)

+*_CLANGDWARF_*_ASLDLINK_FLAGS =
DEF(MSFT_ASLDLINK_FLAGS)

+*_CLANGDWARF_*_DEPS_FLAGS =
DEF(GCC_DEPS_FLAGS)

+

+DEFINE CLANGDWARF_IA32_PREFIX = ENV(CLANG_BIN)

+DEFINE CLANGDWARF_X64_PREFIX = ENV(CLANG_BIN)

+

+DEFINE CLANGDWARF_IA32_TARGET = -target i686-pc-linux-gnu

+DEFINE CLANGDWARF_X64_TARGET = -target
x86_64-pc-linux-gnu

+

+DEFINE CLANGDWARF_WARNING_OVERRIDES = -Wno-parentheses-
equality -Wno-tautological-compare -Wno-tautological-constant-out-of-
range-compare -Wno-empty-body -Wno-unused-const-variable -Wno-
varargs -Wno-unknown-warning-option -Wno-microsoft-enum-forward-
reference

+DEFINE CLANGDWARF_ALL_CC_FLAGS =
DEF(GCC48_ALL_CC_FLAGS)
DEF(CLANGDWARF_WARNING_OVERRIDES) -fno-stack-protector -
funsigned-char -ftrap-
function=undefined_behavior_has_been_optimized_away_by_clang -Wno-
address -Wno-shift-negative-value -Wno-unknown-pragmas -Wno-
incompatible-library-redeclaration -Wno-null-dereference -mno-implicit-
float -mms-bitfields -mno-stack-arg-probe -nostdlib -nostdlibinc -fseh-
exceptions

+

+###########################

+# CLANGDWARF IA32 definitions

+###########################

+*_CLANGDWARF_IA32_CC_PATH =
DEF(CLANGDWARF_IA32_PREFIX)clang

+*_CLANGDWARF_IA32_SLINK_PATH =
DEF(CLANGDWARF_IA32_PREFIX)llvm-ar

+*_CLANGDWARF_IA32_DLINK_PATH =
DEF(CLANGDWARF_IA32_PREFIX)ld.lld

+*_CLANGDWARF_IA32_ASLDLINK_PATH =
DEF(CLANGDWARF_IA32_PREFIX)clang

+*_CLANGDWARF_IA32_ASM_PATH =
DEF(CLANGDWARF_IA32_PREFIX)clang

+*_CLANGDWARF_IA32_PP_PATH =
DEF(CLANGDWARF_IA32_PREFIX)clang

+*_CLANGDWARF_IA32_VFRPP_PATH =
DEF(CLANGDWARF_IA32_PREFIX)clang

+*_CLANGDWARF_IA32_ASLCC_PATH =
DEF(CLANGDWARF_IA32_PREFIX)clang

+*_CLANGDWARF_IA32_ASLPP_PATH =
DEF(CLANGDWARF_IA32_PREFIX)clang

+*_CLANGDWARF_IA32_OBJCOPY_PATH =
DEF(CLANGDWARF_IA32_PREFIX)llvm-objcopy

+

+*_CLANGDWARF_IA32_ASLCC_FLAGS =
DEF(GCC_ASLCC_FLAGS) -m32
-fno-lto DEF(CLANGDWARF_IA32_TARGET)

+*_CLANGDWARF_IA32_ASM_FLAGS =
DEF(GCC_ASM_FLAGS) -m32 -
march=i386 DEF(CLANGDWARF_IA32_TARGET)

+*_CLANGDWARF_IA32_OBJCOPY_FLAGS =

+*_CLANGDWARF_IA32_NASM_FLAGS = -f elf32

+*_CLANGDWARF_IA32_PP_FLAGS =
DEF(GCC_PP_FLAGS)
DEF(CLANGDWARF_IA32_TARGET)

+*_CLANGDWARF_IA32_ASLPP_FLAGS =
DEF(GCC_ASLPP_FLAGS)
DEF(CLANGDWARF_IA32_TARGET)

+*_CLANGDWARF_IA32_VFRPP_FLAGS =
DEF(GCC_VFRPP_FLAGS)
DEF(CLANGDWARF_IA32_TARGET)

+

+DEBUG_CLANGDWARF_IA32_CC_FLAGS =
DEF(CLANGDWARF_ALL_CC_FLAGS) -m32 -Oz -flto -march=i586
DEF(CLANGDWARF_IA32_TARGET) -g

+DEBUG_CLANGDWARF_IA32_DLINK_FLAGS = --eh-frame-hdr -q
--gc-
sections -z common-page-size=0x40 --entry $(IMAGE_ENTRY_POINT) -Map
$(DEST_DIR_DEBUG)/$(BASE_NAME).map --whole-archive -O3 -melf_i386
--
format=elf

+DEBUG_CLANGDWARF_IA32_DLINK2_FLAGS =

+

+RELEASE_CLANGDWARF_IA32_CC_FLAGS =
DEF(CLANGDWARF_ALL_CC_FLAGS) -m32 -Oz -flto -march=i586
DEF(CLANGDWARF_IA32_TARGET)

+RELEASE_CLANGDWARF_IA32_DLINK_FLAGS = --eh-frame-hdr -q
--gc-
sections -z common-page-size=0x40 --entry $(IMAGE_ENTRY_POINT) -Map
$(DEST_DIR_DEBUG)/$(BASE_NAME).map --whole-archive -O3 -melf_i386
--
format=elf

+RELEASE_CLANGDWARF_IA32_DLINK2_FLAGS =

+

+NOOPT_CLANGDWARF_IA32_CC_FLAGS =
DEF(CLANGDWARF_ALL_CC_FLAGS) -m32 -O0 -march=i586
DEF(CLANGDWARF_IA32_TARGET) -g

+NOOPT_CLANGDWARF_IA32_DLINK_FLAGS = --eh-frame-hdr -q
--gc-
sections -z common-page-size=0x40 --entry $(IMAGE_ENTRY_POINT) -Map
$(DEST_DIR_DEBUG)/$(BASE_NAME).map --whole-archive -O0 -melf_i386
--
format=elf

+NOOPT_CLANGDWARF_IA32_DLINK2_FLAGS =

+

+##########################

+# CLANGDWARF X64 definitions

+##########################

+*_CLANGDWARF_X64_CC_PATH =
DEF(CLANGDWARF_X64_PREFIX)clang

+*_CLANGDWARF_X64_SLINK_PATH =
DEF(CLANGDWARF_X64_PREFIX)llvm-ar

+*_CLANGDWARF_X64_DLINK_PATH =
DEF(CLANGDWARF_X64_PREFIX)ld.lld

+*_CLANGDWARF_X64_ASLDLINK_PATH =
DEF(CLANGDWARF_X64_PREFIX)clang

+*_CLANGDWARF_X64_ASM_PATH =
DEF(CLANGDWARF_X64_PREFIX)clang

+*_CLANGDWARF_X64_PP_PATH =
DEF(CLANGDWARF_X64_PREFIX)clang

+*_CLANGDWARF_X64_VFRPP_PATH =
DEF(CLANGDWARF_X64_PREFIX)clang

+*_CLANGDWARF_X64_ASLCC_PATH =
DEF(CLANGDWARF_X64_PREFIX)clang

+*_CLANGDWARF_X64_ASLPP_PATH =
DEF(CLANGDWARF_X64_PREFIX)clang

+*_CLANGDWARF_X64_OBJCOPY_PATH =
DEF(CLANGDWARF_IA32_PREFIX)llvm-objcopy

+

+*_CLANGDWARF_X64_ASLCC_FLAGS =
DEF(GCC_ASLCC_FLAGS) -m64
-fno-lto DEF(CLANGDWARF_X64_TARGET)

+*_CLANGDWARF_X64_ASM_FLAGS =
DEF(GCC_ASM_FLAGS) -m64
DEF(CLANGDWARF_X64_TARGET)

+*_CLANGDWARF_X64_OBJCOPY_FLAGS =

+*_CLANGDWARF_X64_NASM_FLAGS = -f elf64

+*_CLANGDWARF_X64_PP_FLAGS =
DEF(GCC_PP_FLAGS)
DEF(CLANGDWARF_X64_TARGET)

+*_CLANGDWARF_X64_ASLPP_FLAGS =
DEF(GCC_ASLPP_FLAGS)
DEF(CLANGDWARF_X64_TARGET)

+*_CLANGDWARF_X64_VFRPP_FLAGS =
DEF(GCC_VFRPP_FLAGS)
DEF(CLANGDWARF_X64_TARGET)

+

+DEBUG_CLANGDWARF_X64_CC_FLAGS =
DEF(CLANGDWARF_ALL_CC_FLAGS) -m64 "-
DEFIAPI=__attribute__((ms_abi))" -mno-red-zone -mcmodel=small -fpie -Oz
-flto DEF(CLANGDWARF_X64_TARGET) -g

+DEBUG_CLANGDWARF_X64_DLINK_FLAGS = --eh-frame-hdr -q
--gc-
sections -z common-page-size=0x40 --entry $(IMAGE_ENTRY_POINT) -Map
$(DEST_DIR_DEBUG)/$(BASE_NAME).map --whole-archive -O3 -
melf_x86_64 --format=elf -pie

+DEBUG_CLANGDWARF_X64_DLINK2_FLAGS =

+DEBUG_CLANGDWARF_X64_GENFW_FLAGS =
--keepexceptiontable

+

+RELEASE_CLANGDWARF_X64_CC_FLAGS =
DEF(CLANGDWARF_ALL_CC_FLAGS) -m64 "-
DEFIAPI=__attribute__((ms_abi))" -mno-red-zone -mcmodel=small -fpie -Oz
-flto DEF(CLANGDWARF_X64_TARGET)

+RELEASE_CLANGDWARF_X64_DLINK_FLAGS = --eh-frame-hdr -q
--gc-
sections -z common-page-size=0x40 --entry $(IMAGE_ENTRY_POINT) -Map
$(DEST_DIR_DEBUG)/$(BASE_NAME).map --whole-archive -O3 -
melf_x86_64 --format=elf -pie

+RELEASE_CLANGDWARF_X64_DLINK2_FLAGS =

+RELEASE_CLANGDWARF_X64_GENFW_FLAGS =

+

+NOOPT_CLANGDWARF_X64_CC_FLAGS =
DEF(CLANGDWARF_ALL_CC_FLAGS) -m64 "-
DEFIAPI=__attribute__((ms_abi))" -mno-red-zone -mcmodel=small -fpie -O0
DEF(CLANGDWARF_X64_TARGET) -g

+NOOPT_CLANGDWARF_X64_DLINK_FLAGS = --eh-frame-hdr -q
--gc-
sections -z common-page-size=0x40 --entry $(IMAGE_ENTRY_POINT) -Map
$(DEST_DIR_DEBUG)/$(BASE_NAME).map --whole-archive -O0 -
melf_x86_64 --format=elf -pie

+NOOPT_CLANGDWARF_X64_DLINK2_FLAGS =

+NOOPT_CLANGDWARF_X64_GENFW_FLAGS =
--keepexceptiontable

+

#

#

# XCODE5 support

--
2.31.1.windows.1



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回复: 回复: 回复: [edk2-devel] [PATCH v1 1/1] Add MemoryFence implementation for RiscV64

gaoliming
 

Laszlo:
Thanks for the detail information about QemuFwCfgLib. So, this library is arch generic. Now, it is only consumed by ARM and AARCH64.

Daniel:
Can you show more on how RiscV64 uses this QemuFwCfgLib?

Thanks
Liming

-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Laszlo Ersek
发送时间: 2021年6月1日 15:58
收件人: gaoliming <gaoliming@byosoft.com.cn>; devel@edk2.groups.io;
daniel.schaefer@hpe.com; ardb@kernel.org
抄送: 'Chang, Abner (HPS SW/FW Technologist)' <abner.chang@hpe.com>;
'Michael D Kinney' <michael.d.kinney@intel.com>; 'Zhiguang Liu'
<zhiguang.liu@intel.com>; 'Leif Lindholm' <leif@nuviainc.com>
主题: Re: 回复: 回复: [edk2-devel] [PATCH v1 1/1] Add MemoryFence
implementation for RiscV64

On 06/01/21 02:56, gaoliming wrote:
Seemly, Edk2\ArmVirtPkg\Library\QemuFwCfgLib\QemuFwCfgLib.inf is not
arch
specific library. It can also be used in RISCV64.



Ard and Laszlo:

If ArmVirtPkg\Library\QemuFwCfgLib is arch generic, can it be moved
from
ArmVirtPkg into OvmfPkg?
ArmVirtPkg/Library/QemuFwCfgLib is a QemuFwCfgLib instance that is
currently only used by the ArmVirtQemu and ArmVirtQemuKernel platforms.

It depends on the FDT_CLIENT_PROTOCOL, from
"ArmVirtPkg/ArmVirtPkg.dec"
and "ArmVirtPkg/Include/Protocol/FdtClient.h", to locate the fw_cfg
device. The protocol is ArmVirtPkg specific. Due to the protocol depex,
the library is also DXE_DRIVER and UEFI_DRIVER only.

The library uses the MMIO data registers of the fw_cfg device by
default; if the DMA interface is supported, then it uses the DMA
interface. In both cases, some registers are accessed with 64-bit
accesses if MDE_CPU_AARCH64 is defined, and with 32-bit accesses
otherwise.

I don't see how RISCV could reuse this library verbatim.

The linked patch at
<https://github.com/riscv/riscv-edk2/commit/8c7960ef860c65f2646912c3dc
cbb308a>
is a no-go; the MDE_CPU_RISCV64 macro has no place in an ArmVirtPkg
library.

The library can be moved to the new directory

OvmfPkg/Library/DxeQemuFwCfgLibFdtMmio

(note the rename in the last pathname component), but it needs to be
done in multiple steps. The FDT protocol GUID and structure definition
has to be moved at first, separately from the library, and every move
operation (i.e., each one of the protocol move and the library muve)
must be implemented with *at least* three steps -- copy the original to
OvmfPkg (updating BASE_NAME at once), update DSC references under
ArmVirtPkg, remove the original under ArmVirtPkg. Only then can you add
customizations.

Regarding the processor type macros, I believe Mike recently introduced
ISA-independent macros, for expressing 64-bit vs. 32-bit. I'm not
exactly sure about the details, but I think we now have a macro under
MdePkg that says "64-bit processor" without having to state AARCH64 or
RISCV64.

Thanks
Laszlo





Thanks

Liming

发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Daniel
Schaefer
发送时间: 2021年5月21日 20:46
收件人: devel@edk2.groups.io; gaoliming@byosoft.com.cn
抄送: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com>;
'Michael
D Kinney' <michael.d.kinney@intel.com>; 'Zhiguang Liu'
<zhiguang.liu@intel.com>; 'Leif Lindholm' <leif@nuviainc.com>
主题: Re: 回复: [edk2-devel] [PATCH v1 1/1] Add MemoryFence
implementation
for RiscV64



It's not required to go into that tag.

We need two more patches that we haven't submitted yet to boot on
Qemu.



Would it be okay if we used a library from ArmVirtPkg for RISCV64?

See:
https://github.com/riscv/riscv-edk2/commit/8c7960ef860c65f2646912c3dcc
bb308a
98e0cc3

Or does it have to be moved to some other place first?

_____

From: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
<devel@edk2.groups.io <mailto:devel@edk2.groups.io> > on behalf of
gaoliming
<gaoliming@byosoft.com.cn <mailto:gaoliming@byosoft.com.cn> >
Sent: Friday, May 21, 2021 14:35
To: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
<devel@edk2.groups.io <mailto:devel@edk2.groups.io> >; Schaefer, Daniel
<daniel.schaefer@hpe.com <mailto:daniel.schaefer@hpe.com> >
Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com
<mailto:abner.chang@hpe.com> >; 'Michael D Kinney'
<michael.d.kinney@intel.com <mailto:michael.d.kinney@intel.com> >;
'Zhiguang
Liu' <zhiguang.liu@intel.com <mailto:zhiguang.liu@intel.com> >; 'Leif
Lindholm' <leif@nuviainc.com <mailto:leif@nuviainc.com> >
Subject: 回复: 回复: [edk2-devel] [PATCH v1 1/1] Add MemoryFence
implementation for RiscV64



Daniel:

Thanks for your information. Acked-by: Liming Gao
<gaoliming@byosoft.com.cn
<mailto:gaoliming@byosoft.com.cn> >



And, do you request to merge this patch for edk2 stable tag 202105?



Thanks

Liming

发件人: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
<devel@edk2.groups.io <mailto:devel@edk2.groups.io> > 代表 Daniel
Schaefer
发送时间: 2021年5月21日 13:27
收件人: devel@edk2.groups.io <mailto:devel@edk2.groups.io> ;
gaoliming@byosoft.com.cn <mailto:gaoliming@byosoft.com.cn>
抄送: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com
<mailto:abner.chang@hpe.com> >; 'Michael D Kinney'
<michael.d.kinney@intel.com <mailto:michael.d.kinney@intel.com> >;
'Zhiguang
Liu' <zhiguang.liu@intel.com <mailto:zhiguang.liu@intel.com> >; 'Leif
Lindholm' <leif@nuviainc.com <mailto:leif@nuviainc.com> >
主题: Re: 回复: [edk2-devel] [PATCH v1 1/1] Add MemoryFence
implementation
for RiscV64



Great!



It is verified I can boot Linux from a virtio ESP using this patch on QEMU
virt machine.

See:
https://github.com/riscv/riscv-edk2-platforms/runs/2618819010?check_suite
_fo
cus=true



Thanks,

Daniel

_____

From: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
<devel@edk2.groups.io <mailto:devel@edk2.groups.io> > on behalf of
gaoliming
<gaoliming@byosoft.com.cn <mailto:gaoliming@byosoft.com.cn> >
Sent: Friday, May 21, 2021 13:14
To: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
<devel@edk2.groups.io <mailto:devel@edk2.groups.io> >; Schaefer, Daniel
<daniel.schaefer@hpe.com <mailto:daniel.schaefer@hpe.com> >
Cc: Chang, Abner (HPS SW/FW Technologist) <abner.chang@hpe.com
<mailto:abner.chang@hpe.com> >; 'Michael D Kinney'
<michael.d.kinney@intel.com <mailto:michael.d.kinney@intel.com> >;
'Zhiguang
Liu' <zhiguang.liu@intel.com <mailto:zhiguang.liu@intel.com> >; 'Leif
Lindholm' <leif@nuviainc.com <mailto:leif@nuviainc.com> >
Subject: 回复: 回复: [edk2-devel] [PATCH v1 1/1] Add MemoryFence
implementation for RiscV64



Daniel:
Now, it is clear to me. So, I suggest to merge this change when it is
verified on generic RISC-V QEMU virt machine. Is it OK?

Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
<devel@edk2.groups.io <mailto:devel@edk2.groups.io> > 代表 Daniel
Schaefer
发送时间: 2021年5月18日 10:35
收件人: devel@edk2.groups.io <mailto:devel@edk2.groups.io> ;
gaoliming@byosoft.com.cn <mailto:gaoliming@byosoft.com.cn>
抄送: 'Abner Chang' <abner.chang@hpe.com
<mailto:abner.chang@hpe.com> >;
'Michael D Kinney'
<michael.d.kinney@intel.com <mailto:michael.d.kinney@intel.com> >;
'Zhiguang Liu' <zhiguang.liu@intel.com <mailto:zhiguang.liu@intel.com> >;
'Leif
Lindholm' <leif@nuviainc.com <mailto:leif@nuviainc.com> >
主题: Re: 回复: [edk2-devel] [PATCH v1 1/1] Add MemoryFence
implementation for RiscV64

On 5/18/21 9:04 AM, gaoliming wrote:
Daniel:
Seemly, this API is missing in BaseLib for RiscV64 arch. How do you
detect
this issue?
What do you mean it's missing?
Yes MemoryFence() for RiscV64 is missing currently, that's why I'm adding
it
here.

Maybe you mean that it's not currently used? That's also true.
I'm enabling the generic QEMU virt machine (like OVMF or ArmVirtPkg) for
RISC-V.
At least QemuFwCfgLib and VirtioLib need it.
That's why I have the need to add this implementation now.

Does that clear it up?

Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
<devel@edk2.groups.io <mailto:devel@edk2.groups.io> > 代表 Daniel
Schaefer
发送时间: 2021年5月16日 2:13
收件人: devel@edk2.groups.io <mailto:devel@edk2.groups.io>
抄送: Abner Chang <abner.chang@hpe.com
<mailto:abner.chang@hpe.com> >;
Michael D Kinney
<michael.d.kinney@intel.com <mailto:michael.d.kinney@intel.com> >;
Liming Gao <gaoliming@byosoft.com.cn
<mailto:gaoliming@byosoft.com.cn> >;
Zhiguang Liu <zhiguang.liu@intel.com
<mailto:zhiguang.liu@intel.com> >;
Leif Lindholm
<leif@nuviainc.com <mailto:leif@nuviainc.com> >
主题: [edk2-devel] [PATCH v1 1/1] Add MemoryFence implementation
for
RiscV64

Cc: Abner Chang <abner.chang@hpe.com
<mailto:abner.chang@hpe.com> >
Cc: Michael D Kinney <michael.d.kinney@intel.com
<mailto:michael.d.kinney@intel.com> >
Cc: Liming Gao <gaoliming@byosoft.com.cn
<mailto:gaoliming@byosoft.com.
cn> >
Cc: Zhiguang Liu <zhiguang.liu@intel.com
<mailto:zhiguang.liu@intel.com> >
Cc: Leif Lindholm <leif@nuviainc.com <mailto:leif@nuviainc.com> >
Signed-off-by: Daniel Schaefer <daniel.schaefer@hpe.com
<mailto:daniel.
schaefer@hpe.com> >
---
MdePkg/Library/BaseLib/BaseLib.inf | 1 +
MdePkg/Library/BaseLib/RiscV64/MemoryFence.S | 33
++++++++++++++++++++
2 files changed, 34 insertions(+)

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
b/MdePkg/Library/BaseLib/BaseLib.inf
index b76f3af380ea..b7ab5f632366 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -399,6 +399,7 @@
RiscV64/DisableInterrupts.c


RiscV64/EnableInterrupts.c


RiscV64/CpuPause.c


+ RiscV64/MemoryFence.S | GCC


RiscV64/RiscVSetJumpLongJump.S | GCC


RiscV64/RiscVCpuBreakpoint.S | GCC


RiscV64/RiscVCpuPause.S | GCC


diff --git a/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S
b/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S
new file mode 100644
index 000000000000..283df9356a9a
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/MemoryFence.S
@@ -0,0 +1,33 @@
+##-------------------------------------------------------------------------
-----


+#


+# MemoryFence() for RiscV64


+


+# Copyright (c) 2021, Hewlett Packard Enterprise Development. All
rights
reserved.


+#


+# SPDX-License-Identifier: BSD-2-Clause-Patent


+#


+##-------------------------------------------------------------------------
-----


+


+.text


+.p2align 2


+


+ASM_GLOBAL ASM_PFX(MemoryFence)


+


+


+#/**


+# Used to serialize load and store operations.


+#


+# All loads and stores that proceed calls to this function are
guaranteed to
be


+# globally visible when this function returns.


+#


+#**/


+#VOID


+#EFIAPI


+#MemoryFence (


+# VOID


+# );


+#


+ASM_PFX(MemoryFence):


+ // Fence on all memory and I/O


+ fence


+ ret


--
2.30.1

























Re: [PATCH v2 1/1] UefiCpuPkg/CpuCommonFeaturesLib: Update processor location info

Zeng, Star
 

In C1e.c, the MSR_FEATURE_CONFIG is better to be corrected to MSR_NEHALEM_POWER_CTL.

Thanks,
Star

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Ni, Ray
Sent: Tuesday, June 1, 2021 11:25 PM
To: Li, Daoxiang <daoxiang.li@intel.com>; devel@edk2.groups.io
Cc: Dong, Eric <eric.dong@intel.com>; Laszlo Ersek <lersek@redhat.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>
Subject: Re: [edk2-devel] [PATCH v2 1/1] UefiCpuPkg/CpuCommonFeaturesLib: Update processor location info

Reviewed-by: Ray Ni <ray.ni@intel.com>

-----Original Message-----
From: Li, Daoxiang <daoxiang.li@intel.com>
Sent: Tuesday, June 1, 2021 3:25 PM
To: devel@edk2.groups.io
Cc: Li, Daoxiang <daoxiang.li@intel.com>; Dong, Eric
<eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Laszlo Ersek
<lersek@redhat.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>
Subject: [PATCH v2 1/1] UefiCpuPkg/CpuCommonFeaturesLib: Update
processor location info

From: Daoxiang Li <daoxiang.li@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3424

Processor location information check needs to updated When Core 0 is
disabled

Signed-off-by: Daoxiang Li <daoxiang.li@intel.com>
CC: Eric Dong <eric.dong@intel.com>
CC: Ray Ni <ray.ni@intel.com>
CC: Laszlo Ersek <lersek@redhat.com>
CC: Rahul Kumar <rahul1.kumar@intel.com>
---
UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 4 ++--
UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c | 4 ++--
UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c | 6 +++---
3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
index e6e5db75917c..c867802f0bb0 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
@@ -63,9 +63,9 @@ C1eInitialize (
{

//

// The scope of C1EEnable bit in the MSR_NEHALEM_POWER_CTL is
Package, only program

- // MSR_FEATURE_CONFIG for thread 0 core 0 in each package.

+ // MSR_FEATURE_CONFIG once for each package.

//

- if ((CpuInfo->ProcessorInfo.Location.Thread != 0) ||
(CpuInfo->ProcessorInfo.Location.Core != 0)) {

+ if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {

return RETURN_SUCCESS;

}



diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
index bb5d983d1f4b..a3a2861cee5b 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
@@ -152,10 +152,10 @@ McaInitialize (


//

// The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is package for
below processor type, only program

- // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 core 0 in each package.

+ // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS once for each package.

//

if (IS_NEHALEM_PROCESSOR (CpuInfo->DisplayFamily,
CpuInfo->DisplayModel)) {

- if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {

+ if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {

return RETURN_SUCCESS;

}

}

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
index 8450c7ea3eaf..3c4c1bc706ba 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
@@ -130,10 +130,10 @@ PpinInitialize (
// Support function already check the processor which support PPIN
feature, so this function not need

// to check the processor again.

//

- // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only
program MSR_IVY_BRIDGE_PPIN_CTL for

- // thread 0 core 0 in each package.

+ // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only
+ program MSR_IVY_BRIDGE_PPIN_CTL

+ // once for each package.

//

- if ((CpuInfo->ProcessorInfo.Location.Thread != 0) ||
(CpuInfo->ProcessorInfo.Location.Core != 0)) {

+ if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {

return RETURN_SUCCESS;

}



--
2.28.0.windows.1


[PATCH v1 2/2] DynamicTablesPkg: Use AML_NAME_SEG_SIZE define

PierreGondois
 

From: Pierre Gondois <Pierre.Gondois@arm.com>

Use the newly introduced defined value in:
MdePkg/Include/IndustryStandard/AcpiAml.h

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
---
.../Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.c | 4 ++--
.../AcpiSsdtSerialPortLibArm/SsdtSerialPortGenerator.c | 4 ++--
DynamicTablesPkg/Library/Common/AmlLib/AmlDefines.h | 9 +--------
3 files changed, 5 insertions(+), 12 deletions(-)

diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.c
index 97a5c55fa3f6..1e8c2bfca5de 100644
--- a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.c
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.c
@@ -1,7 +1,7 @@
/** @file
SSDT CMN-600 AML Table Generator.

- Copyright (c) 2020, Arm Limited. All rights reserved.<BR>
+ Copyright (c) 2020 - 2021, Arm Limited. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent

@@ -511,7 +511,7 @@ BuildSsdtCmn600TableEx (
UINT64 Index;
CM_ARM_CMN_600_INFO * Cmn600Info;
UINT32 Cmn600Count;
- CHAR8 NewName[5];
+ CHAR8 NewName[AML_NAME_SEG_SIZE + 1];
EFI_ACPI_DESCRIPTION_HEADER ** TableList;

ASSERT (This != NULL);
diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtSerialPortLibArm/SsdtSerialPortGenerator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtSerialPortLibArm/SsdtSerialPortGenerator.c
index 6a1e7487dfaf..570f53aacf16 100644
--- a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtSerialPortLibArm/SsdtSerialPortGenerator.c
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtSerialPortLibArm/SsdtSerialPortGenerator.c
@@ -1,7 +1,7 @@
/** @file
SSDT Serial Port Table Generator.

- Copyright (c) 2020, Arm Limited. All rights reserved.<BR>
+ Copyright (c) 2020 - 2021, Arm Limited. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -171,7 +171,7 @@ BuildSsdtSerialPortTableEx (
CM_ARM_SERIAL_PORT_INFO * SerialPortInfo;
UINT32 SerialPortCount;
UINTN Index;
- CHAR8 NewName[5];
+ CHAR8 NewName[AML_NAME_SEG_SIZE + 1];
UINT64 Uid;
EFI_ACPI_DESCRIPTION_HEADER ** TableList;

diff --git a/DynamicTablesPkg/Library/Common/AmlLib/AmlDefines.h b/DynamicTablesPkg/Library/Common/AmlLib/AmlDefines.h
index cbae14d78802..fff99e644b8d 100644
--- a/DynamicTablesPkg/Library/Common/AmlLib/AmlDefines.h
+++ b/DynamicTablesPkg/Library/Common/AmlLib/AmlDefines.h
@@ -1,7 +1,7 @@
/** @file
AML Defines.

- Copyright (c) 2020, Arm Limited. All rights reserved.<BR>
+ Copyright (c) 2020 - 2021, Arm Limited. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -138,13 +138,6 @@ typedef enum EAmlParseIndex {
*/
#define AML_FIELD_NAMED_OP 0x04

-/** Size of a NameSeg.
- Cf. ACPI 6.3 specification, s20.2.
-
- @ingroup TreeStructures
-*/
- #define AML_NAME_SEG_SIZE 4U
-
/** AML object types.

The ACPI specification defines several object types. They are listed
--
2.17.1


[PATCH v1 1/2] MdePkg/MdeModulePkg: Move AML_NAME_SEG_SIZE definition

PierreGondois
 

From: Pierre Gondois <Pierre.Gondois@arm.com>

A NameSeg is made 4 chars.
Cf. ACPI 6.4 s20.2.2 "Name Objects Encoding":
NameSeg := <leadnamechar namechar namechar namechar>
Notice that NameSegs shorter than 4 characters are filled
with trailing underscores (‘_’s).

AML_NAME_SEG_SIZE is currently defined in:
- DynamicTablesPkg/Library/Common/AmlLib/AmlDefines.h
- MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h
Since the value can be inferred from the ACPI specification
and to avoid multiple definitions, move it to
MdePkg/Include/IndustryStandard/

Signed-off-by: Pierre Gondois <Pierre.Gondois@arm.com>
---
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h | 1 -
MdePkg/Include/IndustryStandard/AcpiAml.h | 7 ++++++-
2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h
index 50d4c96edb63..1b26729e71c3 100644
--- a/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h
+++ b/MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h
@@ -56,7 +56,6 @@ typedef struct _EFI_AML_NODE_LIST EFI_AML_NODE_LIST;
// Size is the total size of this ACPI node buffer.
// Children is the children linked list of this node.
//
-#define AML_NAME_SEG_SIZE 4

struct _EFI_AML_NODE_LIST {
UINT32 Signature;
diff --git a/MdePkg/Include/IndustryStandard/AcpiAml.h b/MdePkg/Include/IndustryStandard/AcpiAml.h
index 74622e912ea4..4255ca3d7087 100644
--- a/MdePkg/Include/IndustryStandard/AcpiAml.h
+++ b/MdePkg/Include/IndustryStandard/AcpiAml.h
@@ -2,7 +2,7 @@
This file contains AML code definition in the latest ACPI spec.

Copyright (c) 2011, Intel Corporation. All rights reserved.<BR>
- Copyright (c) 2019, ARM Limited. All rights reserved.<BR>
+ Copyright (c) 2019 - 2021, Arm Limited. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent

**/
@@ -176,4 +176,9 @@
#define AML_FIELD_CONNECTION_OP 0x02
#define AML_FIELD_EXT_ACCESS_OP 0x03

+//
+// AML Name segment definitions
+//
+#define AML_NAME_SEG_SIZE 4
+
#endif
--
2.17.1


[PATCH v1 0/2] Define AML_NAME_SEG_SIZE

PierreGondois
 

From: Pierre Gondois <Pierre.Gondois@arm.com>

There is currently multiple AML_NAME_SEG_SIZE define in the edk2
repository. One in the MdeModulePkg and one in the DynamicTablesPkg
package. Since the value can be inferred from the ACPI specification,
it could be moved to MdePkg/Include/IndustryStandard/ and avoid
re-definitions

The two patches should be merged at once to avoid having
multiple definitions of AML_NAME_SEG_SIZE.

The changes can be seen at:
https://github.com/PierreARM/edk2/tree/1750_Add_AML_NAMESEG_SIZE_v1
The results of the CI can be seen at:
https://github.com/tianocore/edk2/pull/1681

Pierre Gondois (2):
MdePkg/MdeModulePkg: Move AML_NAME_SEG_SIZE definition
DynamicTablesPkg: Use AML_NAME_SEG_SIZE define

.../Acpi/Arm/AcpiSsdtCmn600LibArm/SsdtCmn600Generator.c | 4 ++--
.../AcpiSsdtSerialPortLibArm/SsdtSerialPortGenerator.c | 4 ++--
DynamicTablesPkg/Library/Common/AmlLib/AmlDefines.h | 9 +--------
MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiSdt.h | 1 -
MdePkg/Include/IndustryStandard/AcpiAml.h | 7 ++++++-
5 files changed, 11 insertions(+), 14 deletions(-)

--
2.17.1


Re: [edk2-platforms][PATCH V1 0/3] Platform/Sgi: enable support for UEFI secure boot

Thomas Abraham
 

On 5/24/21 10:52 PM, Sayanta Pattanayak via groups.io wrote:
This patch series adds secure boot support for Arm's reference design
platforms. The first patch refactors the existing StandaloneMM platform
description file and splits into three different files. This is required
to accomodate for changes register base addresses in RD-N2 platform and
the other supported platforms. The second path add support for NOR flash
platform library to be used with StandaloneMM execution context. The
third patch then enables the support for UEFI secure for all the
supported reference design platforms.

This patch series should be applied on top of the patch series
https://edk2.groups.io/g/devel/message/75368

Link to github branch with the patches in this series -
https://github.com/SayantaP-arm/edk2-
platforms/tree/rd_platform_secure_boot

Sayanta Pattanayak (3):
Platform/Sgi: refactor StandaloneMM platform description file
Platform/Sgi: add StandaloneMM usable NorFlashPlatformLib
Platform/Sgi: enable support for UEFI secure boot
For this patch series:
Reviewed-by: Thomas Abraham <thomas.abraham@arm.com>

[...]
IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.


Re: [edk2-platforms][PATCH V2 0/6] Platform/Sgi: Add initial support for RD-N2-Cfg1 platform

Sami Mujawar
 

Pushed as 8cdd4cb7c71e..f7c08b9bae56

Thanks.

Regards,

Sami Mujawar

On 25/05/2021 11:57 AM, Pranav Madhu wrote:
Changes since V1:
- Updated the MADT table to fix the incorrect base addresses mentioned
for GICC, GICR, GICV and GICH.
- Addressed comments from Sami
- Picked up Sami's reviewed-by tags.

RD-N2-Cfg1 platform is a variant of the RD-N2 platform. The platform
is based on 8xMP1 Neoverse N2 CPUs, CMN-700 interconnect 3x3 mesh,
multiple AXI expansion ports for I/O Coherent PCIe, Ethernet, offload
and Arm Cortex-M7 for System Control Processor (SCP) and Manageability
Control Processor (MCP).

The first patch in this series add Edk2 build system files and minimum
acpi changes required to boot the platform. The second patch add ACPI
PPTT table to describe the CPU and cache topology. The third patch in
this series enable idle state support (ACPI LPI) and the fourth patch
enables ACPI CPPC support to support the OS to scale CPU performance.
The last patch in this series adds SMBIOS support.

This patch series should be applied on top of the patch series
https://edk2.groups.io/g/devel/message/75533

Link to github branch with the patches in this series -
https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rdn2cfg1-initial-support

Aditya Angadi (1):
Platform/Sgi: Add initial support for RD-N2-Cfg1 platform

Pranav Madhu (5):
Platform/Sgi: ACPI PPTT table for RD-N2-Cfg1 platform
Platform/Sgi: Low Power Idle states for RD-N2-Cfg1
Platform/Sgi: ACPI CPPC support for RD-N2-Cfg1
Platform/Sgi: Define RD-N2-Cfg1 platform id values
Platform/Sgi: Extend SMBIOS support for RD-N2-Cfg1

Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc | 57 +++
.../SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf | 66 ++++
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 7 +-
.../Type1SystemInformation.c | 7 +-
.../Type4ProcessorInformation.c | 7 +-
.../SmbiosPlatformDxe/Type7CacheInformation.c | 18 +
.../SgiPkg/Library/PlatformLib/PlatformLib.c | 8 +-
.../ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl | 346 ++++++++++++++++++
.../ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc | 101 +++++
.../ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc | 166 +++++++++
Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc | 12 +
11 files changed, 789 insertions(+), 6 deletions(-)
create mode 100644 Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.dsc
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1AcpiTables.inf
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Dsdt.asl
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Madt.aslc
create mode 100644 Platform/ARM/SgiPkg/AcpiTables/RdN2Cfg1/Pptt.aslc
create mode 100644 Platform/ARM/SgiPkg/RdN2Cfg1/RdN2Cfg1.fdf.inc


Re: [PATCH v1 0/8] Measured SEV boot with kernel/initrd/cmdline

Laszlo Ersek
 

On 06/01/21 15:20, Ard Biesheuvel wrote:
On Tue, 1 Jun 2021 at 14:12, Laszlo Ersek <lersek@redhat.com> wrote:
...
- A major complication for hashing all three of: kernel, initrd,
cmdline, is that the *fetching* of this triplet is split between two
places. (Well, it is split between *three* places in fact, but I'm
going to ignore LinuxInitrdDynamicShellCommand for now, because the
AmdSevX64 platform sets BUILD_SHELL to FALSE for production.)

The kernel and the initrd are fetched in QemuKernelLoaderFsDxe, but
the command line is fetched in (both) QemuLoadImageLib instances.
This requires that all these modules be littered with hashing as
well, which I find *really bad*. Even if we factor out the actual
logic, I strongly dislike having *just hooks* for hashing in multiple
modules.

Now, please refer to efc52d67e157 ("OvmfPkg/QemuKernelLoaderFsDxe:
don't expose kernel command line", 2020-03-05). If we first

(a) reverted that commit, and

(b) modified *both* QemuLoadImageLib instances, to load the kernel
command line from the *synthetic filesystem* (rather than directly
from fw_cfg),

then we could centralize the hashing to just QemuKernelLoaderFsDxe.

Ard -- what's your thought on this?
I don't have any problems with that - I take it this means we can drop
the QemuFwCfgLib dependency from GenericQemuLoadImageLib altogether,
right?
A bit more work is needed for that (but I agree it should be done),
because we have this additionally:

QemuFwCfgSelectItem (QemuFwCfgItemInitrdSize);
InitrdSize = (UINTN)QemuFwCfgRead32 ();

if (InitrdSize > 0) {
//
// Append ' initrd=initrd' in UTF-16.
//
KernelLoadedImage->LoadOptionsSize += sizeof (L" initrd=initrd") - 2;
}

This should also be rebased on top of the synthetic filesystem [*], and
then no more QemuFwCfgLib calls should remain.

[*] From StubFileOpen() in "QemuKernelLoaderFsDxe.c", it seems that we
successfully open zero-sized fw_cfg files. (We also list them, when
reading the root directory, in StubFileRead()). That's not a problem
at all, but it means that, after opening the initrd file temporarily
in QemuLoadImageLib, EFI_FILE_PROTOCOL.GetInfo() should be used for
fetching an EFI_FILE_INFO, and then EFI_FILE_INFO.FileSize needs to
be compared to 0.




And then, we could eliminate the dynamic callback registration, plus
the separate SevFwCfgVerifier, SevHashFinderLib, and
SevQemuLoadImageLib stuff.

We'd only need one new lib class, with *statically linked* hooks for
QemuKernelLoaderFsDxe, and two instances of this new class, a Null
one, and an actual (SEV hash verifier) one. The latter instance would
locate the hash values, calculate the fresh hashes, and perform the
comparisons. Only the AmdSevX64 platform would use the non-Null
instance of this library class.

(NB QemuKernelLoaderFsDxe is used by some ArmVirtPkg platforms, so
resolutions to the Null instance would be required there too.)
This sounds like a good approach to me.
Thank you!
Laszlo





Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Jordan Justen <jordan.l.justen@intel.com>
Cc: Ashish Kalra <ashish.kalra@amd.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: James Bottomley <jejb@linux.ibm.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>

James Bottomley (8):
OvmfPkg/AmdSev/SecretDxe: fix header comment to generic naming
OvmfPkg: PlatformBootManagerLibGrub: Allow executing kernel via fw_cfg
OvmfPkg/AmdSev: add a page to the MEMFD for firmware config hashes
OvmfPkg/QemuKernelLoaderFsDxe: Add ability to verify loaded items
OvmfPkg/AmdSev: Add library to find encrypted hashes for the FwCfg
device
OvmfPkg/AmdSev: Add firmware file plugin to verifier
OvmfPkg: GenericQemuLoadImageLib: Allow verifying fw_cfg command line
OvmfPkg/AmdSev: add SevQemuLoadImageLib

OvmfPkg/OvmfPkg.dec | 10 ++
OvmfPkg/AmdSev/AmdSevX64.dsc | 9 +-
OvmfPkg/AmdSev/AmdSevX64.fdf | 3 +
OvmfPkg/AmdSev/Library/SevFwCfgVerifier/SevFwCfgVerifier.inf | 30 +++++
OvmfPkg/AmdSev/Library/SevHashFinderLib/SevHashFinderLib.inf | 34 ++++++
OvmfPkg/AmdSev/Library/SevQemuLoadImageLib/SevQemuLoadImageLib.inf | 30 +++++
OvmfPkg/Library/PlatformBootManagerLibGrub/PlatformBootManagerLibGrub.inf | 2 +
OvmfPkg/ResetVector/ResetVector.inf | 2 +
OvmfPkg/AmdSev/Include/Library/SevHashFinderLib.h | 47 ++++++++
OvmfPkg/Include/Library/QemuFwCfgLib.h | 35 ++++++
OvmfPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.h | 11 ++
OvmfPkg/AmdSev/Library/SevFwCfgVerifier/SevFwCfgVerifier.c | 60 ++++++++++
OvmfPkg/AmdSev/Library/SevHashFinderLib/SevHashFinderLib.c | 126 ++++++++++++++++++++
OvmfPkg/AmdSev/Library/SevQemuLoadImageLib/SevQemuLoadImageLib.c | 52 ++++++++
OvmfPkg/AmdSev/SecretDxe/SecretDxe.c | 2 +-
OvmfPkg/Library/GenericQemuLoadImageLib/GenericQemuLoadImageLib.c | 29 +++++
OvmfPkg/Library/PlatformBootManagerLibGrub/BdsPlatform.c | 5 +
OvmfPkg/Library/PlatformBootManagerLibGrub/QemuKernel.c | 50 ++++++++
OvmfPkg/QemuKernelLoaderFsDxe/QemuKernelLoaderFsDxe.c | 31 +++++
OvmfPkg/ResetVector/Ia16/ResetVectorVtf0.asm | 20 ++++
OvmfPkg/ResetVector/ResetVector.nasmb | 2 +
21 files changed, 587 insertions(+), 3 deletions(-)
create mode 100644 OvmfPkg/AmdSev/Library/SevFwCfgVerifier/SevFwCfgVerifier.inf
create mode 100644 OvmfPkg/AmdSev/Library/SevHashFinderLib/SevHashFinderLib.inf
create mode 100644 OvmfPkg/AmdSev/Library/SevQemuLoadImageLib/SevQemuLoadImageLib.inf
create mode 100644 OvmfPkg/AmdSev/Include/Library/SevHashFinderLib.h
create mode 100644 OvmfPkg/AmdSev/Library/SevFwCfgVerifier/SevFwCfgVerifier.c
create mode 100644 OvmfPkg/AmdSev/Library/SevHashFinderLib/SevHashFinderLib.c
create mode 100644 OvmfPkg/AmdSev/Library/SevQemuLoadImageLib/SevQemuLoadImageLib.c
create mode 100644 OvmfPkg/Library/PlatformBootManagerLibGrub/QemuKernel.c




Re: [PATCH v2 1/1] UefiCpuPkg/CpuCommonFeaturesLib: Update processor location info

Ni, Ray
 

Reviewed-by: Ray Ni <ray.ni@intel.com>

-----Original Message-----
From: Li, Daoxiang <daoxiang.li@intel.com>
Sent: Tuesday, June 1, 2021 3:25 PM
To: devel@edk2.groups.io
Cc: Li, Daoxiang <daoxiang.li@intel.com>; Dong, Eric <eric.dong@intel.com>; Ni, Ray <ray.ni@intel.com>; Laszlo Ersek
<lersek@redhat.com>; Kumar, Rahul1 <rahul1.kumar@intel.com>
Subject: [PATCH v2 1/1] UefiCpuPkg/CpuCommonFeaturesLib: Update processor location info

From: Daoxiang Li <daoxiang.li@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3424

Processor location information check needs to updated
When Core 0 is disabled

Signed-off-by: Daoxiang Li <daoxiang.li@intel.com>
CC: Eric Dong <eric.dong@intel.com>
CC: Ray Ni <ray.ni@intel.com>
CC: Laszlo Ersek <lersek@redhat.com>
CC: Rahul Kumar <rahul1.kumar@intel.com>
---
UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c | 4 ++--
UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c | 4 ++--
UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c | 6 +++---
3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
index e6e5db75917c..c867802f0bb0 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/C1e.c
@@ -63,9 +63,9 @@ C1eInitialize (
{

//

// The scope of C1EEnable bit in the MSR_NEHALEM_POWER_CTL is Package, only program

- // MSR_FEATURE_CONFIG for thread 0 core 0 in each package.

+ // MSR_FEATURE_CONFIG once for each package.

//

- if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {

+ if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {

return RETURN_SUCCESS;

}



diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
index bb5d983d1f4b..a3a2861cee5b 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/MachineCheck.c
@@ -152,10 +152,10 @@ McaInitialize (


//

// The scope of MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS is package for below processor type, only program

- // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS for thread 0 core 0 in each package.

+ // MSR_IA32_MC*_CTL/MSR_IA32_MC*_STATUS once for each package.

//

if (IS_NEHALEM_PROCESSOR (CpuInfo->DisplayFamily, CpuInfo->DisplayModel)) {

- if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {

+ if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {

return RETURN_SUCCESS;

}

}

diff --git a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
index 8450c7ea3eaf..3c4c1bc706ba 100644
--- a/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
+++ b/UefiCpuPkg/Library/CpuCommonFeaturesLib/Ppin.c
@@ -130,10 +130,10 @@ PpinInitialize (
// Support function already check the processor which support PPIN feature, so this function not need

// to check the processor again.

//

- // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only program MSR_IVY_BRIDGE_PPIN_CTL for

- // thread 0 core 0 in each package.

+ // The scope of the MSR_IVY_BRIDGE_PPIN_CTL is package level, only program MSR_IVY_BRIDGE_PPIN_CTL

+ // once for each package.

//

- if ((CpuInfo->ProcessorInfo.Location.Thread != 0) || (CpuInfo->ProcessorInfo.Location.Core != 0)) {

+ if ((CpuInfo->First.Thread == 0) || (CpuInfo->First.Core == 0)) {

return RETURN_SUCCESS;

}



--
2.28.0.windows.1


Re: [PATCH 1/4] BaseTools: Create CLANGDWARF toolchain

Ni, Ray
 

Liming,
I happen to notice the below patches which you sent out two years ago:
https://edk2.groups.io/g/devel/topic/31354044#41053

It seems to me that I can drop my CLANGDWARF change completely and use your patches.

Correct?

Thanks,
Ray

From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of gaoliming
Sent: Monday, May 31, 2021 11:23 AM
To: Ni, Ray <ray.ni@intel.com>; devel@edk2.groups.io; Shi, Steven <steven.shi@intel.com>
Subject: 回复: [edk2-devel] [PATCH 1/4] BaseTools: Create CLANGDWARF toolchain

Ray:
 If the tool chain generates ELF image, its ELF image can be converted to EFI image by Edk2 GenFw tool. Then, this tool chain can be used for EFI development.

 So, I propose to make CLANGDWARF tool chain generate ELF image and EFI image both. It can support the usage of ELF image generation.

Thanks
Liming
发件人: Ni, Ray <mailto:ray.ni@intel.com>
发送时间: 2021年5月28日 22:31
收件人: mailto:devel@edk2.groups.io; mailto:gaoliming@byosoft.com.cn; Shi, Steven <mailto:steven.shi@intel.com>
主题: Re: [edk2-devel] [PATCH 1/4] BaseTools: Create CLANGDWARF toolchain

Liming,
that is not the intention of this new toolchain.
we want to have a toolchain that can generate elf. or can you suggest a new name for this toolchain?

thanks,
ray
________________________________________
From: mailto:devel@edk2.groups.io <mailto:devel@edk2.groups.io> on behalf of gaoliming <mailto:gaoliming@byosoft.com.cn>
Sent: Friday, May 28, 2021 10:52:06 AM
To: mailto:devel@edk2.groups.io <mailto:devel@edk2.groups.io>; Shi, Steven <mailto:steven.shi@intel.com>; Ni, Ray <mailto:ray.ni@intel.com>
Subject: 回复: [edk2-devel] [PATCH 1/4] BaseTools: Create CLANGDWARF toolchain
 
Ray:
 I would like to suggest CLANGDWARF also generate EFI image. If so, the people can use this tool chain for EFI development with DWARF format debug symbol.
  
  In dll generation phase, CLANGDWARF still generates dll image, then copy dll image to elf image. In EFI generation phase, dll image will be converted to EFI image.
 
Thanks
Liming
发件人: mailto:devel@edk2.groups.io <mailto:devel@edk2.groups.io> 代表 Steven Shi
发送时间: 2021年5月26日 19:35
收件人: mailto:devel@edk2.groups.io; Ni, Ray <mailto:ray.ni@intel.com>
主题: Re: [edk2-devel] [PATCH 1/4] BaseTools: Create CLANGDWARF toolchain
 
Some suggestions:
 
1. There are many blanks appending the line “+        "$(DLINK)" -o ${dst} $(DLINK_FLAGS) @$(STATIC_LIBRARY_FILES_LIST)        “
 

 
2. We need a toolchain dependency descirption in the BaseTools\Conf\tools_def.template. Below is the example for CLANGPDB. Please add one for the CLANGDWARF.
#   CLANGPDB -Linux, Windows, Mac-  Requires:
#                             Clang 9 or above from http://releases.llvm.org/
#                        Optional:
#                             Required to compile nasm source:
#                               nasm compiler from
#                               NASM -- http://www.nasm.us/
#                             Required to build platforms or ACPI tables:
#                               Intel(r) ACPI Compiler from
#                               https://acpica.org/downloads
 
3. We could merge the CLANG38 and the CLANGDWARF toolchains together in the future.
 
 
Thanks
Steven Shi
 
 
-----Original Message-----
From: mailto:devel@edk2.groups.io <mailto:devel@edk2.groups.io> On Behalf Of Ni, Ray
Sent: Wednesday, May 26, 2021 4:23 PM
To: mailto:devel@edk2.groups.io
Subject: [edk2-devel] [PATCH 1/4] BaseTools: Create CLANGDWARF
toolchain

Signed-off-by: Ray Ni <mailto:ray.ni@intel.com>
---
 BaseTools/Conf/build_rule.template | 10 ++-
 BaseTools/Conf/tools_def.template  | 98
++++++++++++++++++++++++++++++
 2 files changed, 107 insertions(+), 1 deletion(-)

diff --git a/BaseTools/Conf/build_rule.template
b/BaseTools/Conf/build_rule.template
index 1395792cd6..e69f963cc8 100755
--- a/BaseTools/Conf/build_rule.template
+++ b/BaseTools/Conf/build_rule.template
@@ -293,7 +293,10 @@
     <ExtraDependency>

         $(MAKE_FILE)



-    <OutputFile>

+    <OutputFile.CLANGDWARF>

+        $(DEBUG_DIR)(+)$(MODULE_NAME).elf

+

+    <OutputFile.MSFT, OutputFile.INTEL, OutputFile.GCC>

         $(DEBUG_DIR)(+)$(MODULE_NAME).dll



     <Command.MSFT, Command.INTEL>

@@ -303,6 +306,11 @@
     <Command.CLANGPDB>

         "$(DLINK)" /OUT:${dst} $(DLINK_FLAGS) $(DLINK_SPATH)
@$(STATIC_LIBRARY_FILES_LIST) $(DLINK2_FLAGS)



+    <Command.CLANGDWARF>

+        "$(DLINK)" -o ${dst} $(DLINK_FLAGS) @$(STATIC_LIBRARY_FILES_LIST)

+        "$(CP)" ${dst} $(DEBUG_DIR)(+)$(MODULE_NAME).debug

+        "$(OBJCOPY)" --strip-unneeded -R .eh_frame ${dst}

+

     <Command.GCC>

         "$(DLINK)" -o ${dst} $(DLINK_FLAGS) -Wl,--start-
group,@$(STATIC_LIBRARY_FILES_LIST),--end-group $(CC_FLAGS)
$(DLINK2_FLAGS)

         "$(OBJCOPY)" $(OBJCOPY_FLAGS) ${dst}

diff --git a/BaseTools/Conf/tools_def.template
b/BaseTools/Conf/tools_def.template
index 498696e583..390e297cc1 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -2828,6 +2828,104 @@ NOOPT_CLANGPDB_X64_DLINK_FLAGS      =
/NOLOGO /NODEFAULTLIB /IGNORE:4001 /OPT:RE
 NOOPT_CLANGPDB_X64_DLINK2_FLAGS     =

 NOOPT_CLANGPDB_X64_GENFW_FLAGS      = --keepexceptiontable



+#########################################################
###########################

+#

+# CLANGDWARF - This configuration is used to compile under
Windows/Linux/Mac to produce

+#  ELF binaries using LLVM/Clang/LLD with Link Time Optimization enabled

+#

+#########################################################
###########################

+*_CLANGDWARF_*_*_FAMILY             = GCC

+*_CLANGDWARF_*_*_BUILDRULEFAMILY    = CLANGDWARF

+*_CLANGDWARF_*_MAKE_PATH            = ENV(CLANG_HOST_BIN)make

+*_CLANGDWARF_*_*_DLL                = ENV(CLANGPDB_DLL)

+*_CLANGDWARF_*_ASL_PATH             = DEF(UNIX_IASL_BIN)

+

+*_CLANGDWARF_*_APP_FLAGS            =

+*_CLANGDWARF_*_ASL_FLAGS            = DEF(DEFAULT_WIN_ASL_FLAGS)

+*_CLANGDWARF_*_ASL_OUTFLAGS         =
DEF(DEFAULT_WIN_ASL_OUTFLAGS)

+*_CLANGDWARF_*_ASLDLINK_FLAGS       = DEF(MSFT_ASLDLINK_FLAGS)

+*_CLANGDWARF_*_DEPS_FLAGS           = DEF(GCC_DEPS_FLAGS)

+

+DEFINE CLANGDWARF_IA32_PREFIX       = ENV(CLANG_BIN)

+DEFINE CLANGDWARF_X64_PREFIX        = ENV(CLANG_BIN)

+

+DEFINE CLANGDWARF_IA32_TARGET       = -target i686-pc-linux-gnu

+DEFINE CLANGDWARF_X64_TARGET        = -target x86_64-pc-linux-gnu

+

+DEFINE CLANGDWARF_WARNING_OVERRIDES = -Wno-parentheses-
equality -Wno-tautological-compare -Wno-tautological-constant-out-of-
range-compare -Wno-empty-body -Wno-unused-const-variable -Wno-
varargs -Wno-unknown-warning-option -Wno-microsoft-enum-forward-
reference

+DEFINE CLANGDWARF_ALL_CC_FLAGS      = DEF(GCC48_ALL_CC_FLAGS)
DEF(CLANGDWARF_WARNING_OVERRIDES) -fno-stack-protector -
funsigned-char -ftrap-
function=undefined_behavior_has_been_optimized_away_by_clang -Wno-
address -Wno-shift-negative-value -Wno-unknown-pragmas -Wno-
incompatible-library-redeclaration -Wno-null-dereference -mno-implicit-
float -mms-bitfields -mno-stack-arg-probe -nostdlib -nostdlibinc -fseh-
exceptions

+

+###########################

+# CLANGDWARF IA32 definitions

+###########################

+*_CLANGDWARF_IA32_CC_PATH              =
DEF(CLANGDWARF_IA32_PREFIX)clang

+*_CLANGDWARF_IA32_SLINK_PATH           =
DEF(CLANGDWARF_IA32_PREFIX)llvm-ar

+*_CLANGDWARF_IA32_DLINK_PATH           =
DEF(CLANGDWARF_IA32_PREFIX)ld.lld

+*_CLANGDWARF_IA32_ASLDLINK_PATH        =
DEF(CLANGDWARF_IA32_PREFIX)clang

+*_CLANGDWARF_IA32_ASM_PATH             =
DEF(CLANGDWARF_IA32_PREFIX)clang

+*_CLANGDWARF_IA32_PP_PATH              =
DEF(CLANGDWARF_IA32_PREFIX)clang

+*_CLANGDWARF_IA32_VFRPP_PATH           =
DEF(CLANGDWARF_IA32_PREFIX)clang

+*_CLANGDWARF_IA32_ASLCC_PATH           =
DEF(CLANGDWARF_IA32_PREFIX)clang

+*_CLANGDWARF_IA32_ASLPP_PATH           =
DEF(CLANGDWARF_IA32_PREFIX)clang

+*_CLANGDWARF_IA32_OBJCOPY_PATH         =
DEF(CLANGDWARF_IA32_PREFIX)llvm-objcopy

+

+*_CLANGDWARF_IA32_ASLCC_FLAGS          = DEF(GCC_ASLCC_FLAGS) -m32
-fno-lto DEF(CLANGDWARF_IA32_TARGET)

+*_CLANGDWARF_IA32_ASM_FLAGS            = DEF(GCC_ASM_FLAGS) -m32 -
march=i386 DEF(CLANGDWARF_IA32_TARGET)

+*_CLANGDWARF_IA32_OBJCOPY_FLAGS        =

+*_CLANGDWARF_IA32_NASM_FLAGS           = -f elf32

+*_CLANGDWARF_IA32_PP_FLAGS             = DEF(GCC_PP_FLAGS)
DEF(CLANGDWARF_IA32_TARGET)

+*_CLANGDWARF_IA32_ASLPP_FLAGS          = DEF(GCC_ASLPP_FLAGS)
DEF(CLANGDWARF_IA32_TARGET)

+*_CLANGDWARF_IA32_VFRPP_FLAGS          = DEF(GCC_VFRPP_FLAGS)
DEF(CLANGDWARF_IA32_TARGET)

+

+DEBUG_CLANGDWARF_IA32_CC_FLAGS         =
DEF(CLANGDWARF_ALL_CC_FLAGS) -m32 -Oz -flto -march=i586
DEF(CLANGDWARF_IA32_TARGET) -g

+DEBUG_CLANGDWARF_IA32_DLINK_FLAGS      = --eh-frame-hdr -q --gc-
sections -z common-page-size=0x40 --entry $(IMAGE_ENTRY_POINT) -Map
$(DEST_DIR_DEBUG)/$(BASE_NAME).map --whole-archive -O3 -melf_i386 --
format=elf

+DEBUG_CLANGDWARF_IA32_DLINK2_FLAGS     =

+

+RELEASE_CLANGDWARF_IA32_CC_FLAGS       =
DEF(CLANGDWARF_ALL_CC_FLAGS) -m32 -Oz -flto -march=i586
DEF(CLANGDWARF_IA32_TARGET)

+RELEASE_CLANGDWARF_IA32_DLINK_FLAGS    = --eh-frame-hdr -q --gc-
sections -z common-page-size=0x40 --entry $(IMAGE_ENTRY_POINT) -Map
$(DEST_DIR_DEBUG)/$(BASE_NAME).map --whole-archive -O3 -melf_i386 --
format=elf

+RELEASE_CLANGDWARF_IA32_DLINK2_FLAGS   =

+

+NOOPT_CLANGDWARF_IA32_CC_FLAGS         =
DEF(CLANGDWARF_ALL_CC_FLAGS) -m32 -O0 -march=i586
DEF(CLANGDWARF_IA32_TARGET) -g

+NOOPT_CLANGDWARF_IA32_DLINK_FLAGS      = --eh-frame-hdr -q --gc-
sections -z common-page-size=0x40 --entry $(IMAGE_ENTRY_POINT) -Map
$(DEST_DIR_DEBUG)/$(BASE_NAME).map --whole-archive -O0 -melf_i386 --
format=elf

+NOOPT_CLANGDWARF_IA32_DLINK2_FLAGS     =

+

+##########################

+# CLANGDWARF X64 definitions

+##########################

+*_CLANGDWARF_X64_CC_PATH              =
DEF(CLANGDWARF_X64_PREFIX)clang

+*_CLANGDWARF_X64_SLINK_PATH           =
DEF(CLANGDWARF_X64_PREFIX)llvm-ar

+*_CLANGDWARF_X64_DLINK_PATH           =
DEF(CLANGDWARF_X64_PREFIX)ld.lld

+*_CLANGDWARF_X64_ASLDLINK_PATH        =
DEF(CLANGDWARF_X64_PREFIX)clang

+*_CLANGDWARF_X64_ASM_PATH             =
DEF(CLANGDWARF_X64_PREFIX)clang

+*_CLANGDWARF_X64_PP_PATH              =
DEF(CLANGDWARF_X64_PREFIX)clang

+*_CLANGDWARF_X64_VFRPP_PATH           =
DEF(CLANGDWARF_X64_PREFIX)clang

+*_CLANGDWARF_X64_ASLCC_PATH           =
DEF(CLANGDWARF_X64_PREFIX)clang

+*_CLANGDWARF_X64_ASLPP_PATH           =
DEF(CLANGDWARF_X64_PREFIX)clang

+*_CLANGDWARF_X64_OBJCOPY_PATH         =
DEF(CLANGDWARF_IA32_PREFIX)llvm-objcopy

+

+*_CLANGDWARF_X64_ASLCC_FLAGS          = DEF(GCC_ASLCC_FLAGS) -m64
-fno-lto DEF(CLANGDWARF_X64_TARGET)

+*_CLANGDWARF_X64_ASM_FLAGS            = DEF(GCC_ASM_FLAGS) -m64
DEF(CLANGDWARF_X64_TARGET)

+*_CLANGDWARF_X64_OBJCOPY_FLAGS        =

+*_CLANGDWARF_X64_NASM_FLAGS           = -f elf64

+*_CLANGDWARF_X64_PP_FLAGS             = DEF(GCC_PP_FLAGS)
DEF(CLANGDWARF_X64_TARGET)

+*_CLANGDWARF_X64_ASLPP_FLAGS          = DEF(GCC_ASLPP_FLAGS)
DEF(CLANGDWARF_X64_TARGET)

+*_CLANGDWARF_X64_VFRPP_FLAGS          = DEF(GCC_VFRPP_FLAGS)
DEF(CLANGDWARF_X64_TARGET)

+

+DEBUG_CLANGDWARF_X64_CC_FLAGS         =
DEF(CLANGDWARF_ALL_CC_FLAGS) -m64 "-
DEFIAPI=__attribute__((ms_abi))" -mno-red-zone -mcmodel=small -fpie -Oz
-flto DEF(CLANGDWARF_X64_TARGET) -g

+DEBUG_CLANGDWARF_X64_DLINK_FLAGS      = --eh-frame-hdr -q --gc-
sections -z common-page-size=0x40 --entry $(IMAGE_ENTRY_POINT) -Map
$(DEST_DIR_DEBUG)/$(BASE_NAME).map --whole-archive -O3 -
melf_x86_64 --format=elf -pie

+DEBUG_CLANGDWARF_X64_DLINK2_FLAGS     =

+DEBUG_CLANGDWARF_X64_GENFW_FLAGS      = --keepexceptiontable

+

+RELEASE_CLANGDWARF_X64_CC_FLAGS       =
DEF(CLANGDWARF_ALL_CC_FLAGS) -m64 "-
DEFIAPI=__attribute__((ms_abi))" -mno-red-zone -mcmodel=small -fpie -Oz
-flto DEF(CLANGDWARF_X64_TARGET)

+RELEASE_CLANGDWARF_X64_DLINK_FLAGS    = --eh-frame-hdr -q --gc-
sections -z common-page-size=0x40 --entry $(IMAGE_ENTRY_POINT) -Map
$(DEST_DIR_DEBUG)/$(BASE_NAME).map --whole-archive -O3 -
melf_x86_64 --format=elf -pie

+RELEASE_CLANGDWARF_X64_DLINK2_FLAGS   =

+RELEASE_CLANGDWARF_X64_GENFW_FLAGS    =

+

+NOOPT_CLANGDWARF_X64_CC_FLAGS         =
DEF(CLANGDWARF_ALL_CC_FLAGS) -m64 "-
DEFIAPI=__attribute__((ms_abi))" -mno-red-zone -mcmodel=small -fpie -O0
DEF(CLANGDWARF_X64_TARGET) -g

+NOOPT_CLANGDWARF_X64_DLINK_FLAGS      = --eh-frame-hdr -q --gc-
sections -z common-page-size=0x40 --entry $(IMAGE_ENTRY_POINT) -Map
$(DEST_DIR_DEBUG)/$(BASE_NAME).map --whole-archive -O0 -
melf_x86_64 --format=elf -pie

+NOOPT_CLANGDWARF_X64_DLINK2_FLAGS     =

+NOOPT_CLANGDWARF_X64_GENFW_FLAGS      = --keepexceptiontable

+

 #

 #

 # XCODE5 support

--
2.31.1.windows.1



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Re: [edk2-platforms][PATCH V4 00/11] Add SMBIOS tables for Arm's Reference Design platforms

Sami Mujawar
 

Pushed as 86984c17d562..8cdd4cb7c71e, with minor changes to patch 4 and 7.

Thanks.

Regards,

Sami Mujawar

On 24/05/2021 03:28 PM, Pranav Madhu wrote:
Changes since V3:
- Add UpdateMemorySize API to update memory size information as suggested by Sami.

Changes since V2:
- Addressed comments from Sami
- Picked up Sami's reviewed-by tags.

Changes since V1:
- Rebase the patches on top of latest master branch

SMBIOS provides basic hardware and firmware configuration information
through table-driven data structure. This patch series adds SMBIOS
support for Arm's SGI/RD platforms.

The first patch in this series defines platform-id values for the
RD-N2 platform library header. The second patch add SgiGetProductId API,
which is used by the SMBIOS driver to distinguish between the platforms,
and install the right table. The third patch in this series adds SMBIOS
driver support that allows for installation of multiple SMBIOS tables.
And subsequent patches in this series add SMBIOS tables, which are
mandatory as per Arm serverready SBBR specification.

Link to github branch with the patches in this series -
https://github.com/Pranav-Madhu/edk2-platforms/tree/topics/rd_smbios

Pranav Madhu (11):
Platform/Sgi: Define RD-N2 platform id values
Platform/Sgi: Add GetProductId API for SGI/RD Platforms
Platform/Sgi: Add Initial SMBIOS support
Platform/Sgi: Add SMBIOS Type1 Table
Platform/Sgi: Add SMBIOS Type3 Table
Platform/Sgi: Add SMBIOS Type4 Table
Platform/Sgi: Add SMBIOS Type7 Table
Platform/Sgi: Add SMBIOS Type16 Table
Platform/Sgi: Add SMBIOS Type17 Table
Platform/Sgi: Add SMBIOS Type19 Table
Platform/Sgi: Add SMBIOS Type32 Table

Platform/ARM/SgiPkg/SgiPlatform.dsc.inc | 11 +
Platform/ARM/SgiPkg/SgiPlatform.fdf | 8 +-
.../SmbiosPlatformDxe/SmbiosPlatformDxe.inf | 62 +++
.../SmbiosPlatformDxe/SmbiosPlatformDxe.h | 197 +++++++++
Platform/ARM/SgiPkg/Include/SgiPlatform.h | 36 +-
.../SmbiosPlatformDxe/SmbiosPlatformDxe.c | 106 +++++
.../SmbiosPlatformDxe/Type0BiosInformation.c | 135 ++++++
.../Type16PhysicalMemoryArray.c | 106 +++++
.../SmbiosPlatformDxe/Type17MemoryDevice.c | 409 ++++++++++++++++++
.../Type19MemoryArrayMappedAddress.c | 97 +++++
.../Type1SystemInformation.c | 142 ++++++
.../Type32SystemBootInformation.c | 84 ++++
.../SmbiosPlatformDxe/Type3SystemEnclosure.c | 103 +++++
.../Type4ProcessorInformation.c | 219 ++++++++++
.../SmbiosPlatformDxe/Type7CacheInformation.c | 342 +++++++++++++++
.../SgiPkg/Library/PlatformLib/PlatformLib.c | 86 +++-
16 files changed, 2140 insertions(+), 3 deletions(-)
create mode 100644 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.inf
create mode 100644 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.h
create mode 100644 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/SmbiosPlatformDxe.c
create mode 100644 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type0BiosInformation.c
create mode 100644 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type16PhysicalMemoryArray.c
create mode 100644 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type17MemoryDevice.c
create mode 100644 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type19MemoryArrayMappedAddress.c
create mode 100644 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type1SystemInformation.c
create mode 100644 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type32SystemBootInformation.c
create mode 100644 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type3SystemEnclosure.c
create mode 100644 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type4ProcessorInformation.c
create mode 100644 Platform/ARM/SgiPkg/Drivers/SmbiosPlatformDxe/Type7CacheInformation.c


Re: [PATCH v2] Platform/ARM: Update Readme.md

Sami Mujawar
 

Hi Rebecca,

Thank you for this patch.

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar

On 28/05/2021 07:29 PM, Rebecca Cran wrote:
The repo with the Visual Studio support no longer exists.
fiptool from the prebuilt_tools repo doesn't work due to a missing
dependency on libcrypto.so.1.0.0, so tell users to build it from the
trusted-firmware-a repo instead.
There's a newer version of fvp-uefi.zip that was released in 2020.

Signed-off-by: Rebecca Cran <rebecca@bsdio.com>
Reviewed-by: Chris Jones <christopher.jones@arm.com>
---
Platform/ARM/Readme.md | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)

diff --git a/Platform/ARM/Readme.md b/Platform/ARM/Readme.md
index e1a405b700..fae854fe6d 100644
--- a/Platform/ARM/Readme.md
+++ b/Platform/ARM/Readme.md
@@ -8,10 +8,8 @@ can be found here:

##Requirements

- A 32-bit or 64-bit Linux host machine.

-- Visual Studio is not officially supported, experimental support can be found here:

-[https://git.linaro.org/people/leif.lindholm/edk2.git/log/?h=aarch64-vs]


-# Build EDK2 Tianocore

+# Build EDK2 TianoCore


`build -a AARCH64 -p Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc -t GCC5`


@@ -26,7 +24,7 @@ prebuilt edk2 image.

We will also rely on the "run_model" script that comes with the prebuilts, it

is entirely possible to run the model without this but would require quite a bit

-of knowledge regarding the areguments ARM fastmodel (documentation can be found here:

+of knowledge regarding the arguments of the ARM fastmodel (documentation can be found here:

[https://developer.arm.com/docs/100966/1101/programming-reference-for-base-fvps/base-platform-revc-features])

however the manual set of the FVP is outside the scope of this document. If you are interested

please consult the documentation.

@@ -40,16 +38,18 @@ the binaries in the same directory.
- Select Armv8-A Base Platform FVP based on Fast Models 11.4

- It has a click through license but is free.


-2. Download the 18.10 Linaro ARM Landing Team release for FVP booting UEFI

-https://releases.linaro.org/members/arm/platforms/18.10/fvp-uefi.zip

+2. Download the 20.01 Linaro ARM Landing Team release for FVP booting UEFI

+https://releases.linaro.org/members/arm/platforms/20.01/fvp-uefi.zip


-3. Download the prebuilt fiptool from https://git.linaro.org/landing-teams/working/arm/prebuilt_tools.git

+3. Clone the trusted firmware repo from https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git


-4. Update the fip.bin image from fvp-uefi.zip by running the following command:

+4. Build fiptool: `make -C trusted-firmware-a/tools/fiptool`


- `fiptool update --nt-fw=[path to binary built above] fip.bin`

+5. Update the fip.bin image from fvp-uefi.zip by running the following command:


-5. Execute the FVP run_model.sh script from fvp-uefi.zip and provide a path to the FVP binaries

+ `./trusted-firmware-a/tools/fiptool/fiptool update --nt-fw=[path to binary built above] fip.bin`

+

+6. Execute the FVP run_model.sh script from fvp-uefi.zip and provide a path to the FVP binaries

downloaded in step 1):


`MODEL=[path to FVP binary] ./run_model.sh`


[PATCH V0 4/4] Platform/NXP/LS1046aFrwyPkg: Add OEM specific DSDT generator

Vikas Singh
 

This patch adds platform specific DSDT generator
and Clk dsdt properties for LS1046AFRWY platform.

Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
---
.../AcpiTablesInclude/Dsdt/Clk.asl | 60 ++++++++
.../AcpiTablesInclude/Dsdt/Dsdt.asl | 15 ++
.../AcpiTablesInclude/PlatformAcpiDsdtLib.inf | 39 +++++
.../PlatformAcpiDsdtLib/RawDsdtGenerator.c | 138 ++++++++++++++++++
.../AcpiTablesInclude/PlatformAcpiLib.h | 23 +++
.../NXP/LS1046aFrwyPkg/Include/Platform.h | 6 +-
.../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 1 +
7 files changed, 281 insertions(+), 1 deletion(-)
create mode 100644 Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Clk.=
asl
create mode 100644 Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Dsdt=
.asl
create mode 100644 Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformA=
cpiDsdtLib.inf
create mode 100644 Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformA=
cpiDsdtLib/RawDsdtGenerator.c
create mode 100644 Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformA=
cpiLib.h

diff --git a/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Clk.asl b/P=
latform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Clk.asl
new file mode 100644
index 0000000000..58541c3019
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Clk.asl
@@ -0,0 +1,60 @@
+/** @file=0D
+* DSDT : Dynamic Clock ACPI Information=0D
+*=0D
+* Copyright 2021 NXP=0D
+* Copyright 2021 Puresoftware Ltd.=0D
+*=0D
+* SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+*=0D
+**/=0D
+=0D
+Scope(_SB)=0D
+{=0D
+ Device(PCLK) {=0D
+ Name(_HID, "NXP0017")=0D
+ Name(CLK, 0) // Maximum Platform Clock (Hz)=0D
+ Name(CCLK, 0) // Maximum CPU Core Clock (MHz)=0D
+ Name(AVBL, 0)=0D
+ OperationRegion(RCWS, SystemMemory, DCFG_BASE, DCFG_LEN)=0D
+ Method(_REG,2) {=0D
+ if (Arg0 =3D=3D "RCWS") {=0D
+ Store(Arg1, AVBL)=0D
+ }=0D
+ }=0D
+ Field (RCWS, ByteAcc, NoLock, Preserve) {=0D
+ /* The below table provides the func of diff bits in 512 bits RCW da=
ta:=0D
+ SYS_PLL_CFG : 0-1 bits=0D
+ SYS_PLL_RAT : 2-6 bits=0D
+ SYSCLK_FREQ : 472-481 bits etc.=0D
+ Refer LS1046ARM for more info.=0D
+ For LS1046 RCWSRs are read as RCW[0:31] .=0D
+ */=0D
+ offset(0x100),=0D
+ RESV, 1,=0D
+ PRAT, 5,=0D
+ PCFG, 2,=0D
+ offset(0x103),=0D
+ CPRT, 6, // Cluster Group PLL Multiplier ratio=0D
+ offset(0x13B),=0D
+ HFRQ, 8, // Higher 8 bits of SYSCLK_FREQ=0D
+ RESX, 6,=0D
+ LFRQ, 2 // Lower bits of SYSCLK_FREQ=0D
+ }=0D
+=0D
+ Method(_INI, 0, NotSerialized) {=0D
+ /* Calculating Platform Clock */=0D
+ Local0 =3D (HFRQ<<2 | LFRQ) // Concatinating LFRQ at end of HFRQ=0D
+ Multiply(Local0, 500000, Local0)=0D
+ Multiply(Local0, PRAT, Local0)=0D
+ Divide(Local0, 3, , Local0)=0D
+ Store(Local0, CLK)=0D
+=0D
+ /* Calculating Maximum Core Clock */=0D
+ Local0 =3D (HFRQ<<2 | LFRQ) // Concatinating LFRQ at end of HFRQ=0D
+ Multiply(Local0, 500000, Local0)=0D
+ Divide(Local0, 3, , Local0)=0D
+ Divide(Local0, 1000000, , Local0) //Just the MHz part of SYSCLK.=0D
+ Multiply(Local0, CPRT, CCLK) // PLL_Ratio * SYSCLK, Max freq of clus=
ter=0D
+ }=0D
+ } // end of device PCLK=0D
+}=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Dsdt.asl b/=
Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Dsdt.asl
new file mode 100644
index 0000000000..19f3f1c0e8
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Dsdt/Dsdt.asl
@@ -0,0 +1,15 @@
+/** @file=0D
+ Differentiated System Description Table Fields (DSDT)=0D
+=0D
+ Copyright 2021 NXP=0D
+ Copyright 2021 Puresoftware Ltd.=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include "Platform.h"=0D
+=0D
+DefinitionBlock("DsdtTable.aml", "DSDT", 2, "NXP ", "LS1046 ", EFI_ACPI_=
ARM_OEM_REVISION) {=0D
+ include ("Clk.asl")=0D
+}=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdt=
Lib.inf b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib=
.inf
new file mode 100644
index 0000000000..ed5f9dd442
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib.inf
@@ -0,0 +1,39 @@
+## @file=0D
+# Raw Table Generator=0D
+#=0D
+# Copyright 2021 NXP=0D
+# Copyright 2021 Puresoftware Ltd=0D
+#=0D
+# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+##=0D
+=0D
+[Defines]=0D
+ INF_VERSION =3D 0x00010019=0D
+ BASE_NAME =3D PlatformAcpiDsdtLib=0D
+ FILE_GUID =3D A97F70AC-3BB4-4596-B4D2-9F948EC12D17=0D
+ VERSION_STRING =3D 1.0=0D
+ MODULE_TYPE =3D DXE_DRIVER=0D
+ LIBRARY_CLASS =3D NULL|DXE_DRIVER=0D
+ CONSTRUCTOR =3D AcpiDsdtLibConstructor=0D
+ DESTRUCTOR =3D AcpiDsdtLibDestructor=0D
+=0D
+[Sources]=0D
+ PlatformAcpiDsdtLib/RawDsdtGenerator.c=0D
+ Dsdt/Dsdt.asl=0D
+=0D
+[Packages]=0D
+ DynamicTablesPkg/DynamicTablesPkg.dec=0D
+ EmbeddedPkg/EmbeddedPkg.dec=0D
+ MdePkg/MdePkg.dec=0D
+ MdeModulePkg/MdeModulePkg.dec=0D
+ Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dec=0D
+ Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerPkg.dec=0D
+=0D
+[LibraryClasses]=0D
+ BaseLib=0D
+=0D
+[Pcd]=0D
+=0D
+[Protocols]=0D
+=0D
+[Guids]=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdt=
Lib/RawDsdtGenerator.c b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/Plat=
formAcpiDsdtLib/RawDsdtGenerator.c
new file mode 100644
index 0000000000..7d886396ca
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsdtLib/Raw=
DsdtGenerator.c
@@ -0,0 +1,138 @@
+/** @file=0D
+ Raw DSDT Table Generator=0D
+=0D
+ Copyright 2021 NXP=0D
+ Copyright 2021 Puresoftware Ltd.=0D
+=0D
+ SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+=0D
+**/=0D
+=0D
+#include <Library/AcpiLib.h>=0D
+#include <Library/DebugLib.h>=0D
+#include <Protocol/AcpiTable.h>=0D
+=0D
+// Module specific include files.=0D
+#include <AcpiTableGenerator.h>=0D
+#include <ConfigurationManagerObject.h>=0D
+#include <ConfigurationManagerHelper.h>=0D
+#include <Library/TableHelperLib.h>=0D
+#include <Protocol/ConfigurationManagerProtocol.h>=0D
+=0D
+#include "PlatformAcpiLib.h"=0D
+=0D
+/** Construct the ACPI table using the ACPI table data provided.=0D
+ This function invokes the Configuration Manager protocol interface=0D
+ to get the required hardware information for generating the ACPI=0D
+ table.=0D
+ If this function allocates any resources then they must be freed=0D
+ in the FreeXXXXTableResources function.=0D
+ @param [in] This Pointer to the table generator.=0D
+ @param [in] AcpiTableInfo Pointer to the ACPI Table Info.=0D
+ @param [in] CfgMgrProtocol Pointer to the Configuration Manager=0D
+ Protocol Interface.=0D
+ @param [out] Table Pointer to the constructed ACPI Table.=0D
+ @retval EFI_SUCCESS Table generated successfully.=0D
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.=0D
+**/=0D
+STATIC=0D
+EFI_STATUS=0D
+EFIAPI=0D
+BuildRawDsdtTable (=0D
+ IN CONST ACPI_TABLE_GENERATOR * CONST This,=0D
+ IN CONST CM_STD_OBJ_ACPI_TABLE_INFO * CONST AcpiTableInfo,=0D
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST CfgMgrProtocol,=
=0D
+ OUT EFI_ACPI_DESCRIPTION_HEADER ** CONST Table=0D
+ )=0D
+{=0D
+ ASSERT (This !=3D NULL);=0D
+ ASSERT (AcpiTableInfo !=3D NULL);=0D
+ ASSERT (CfgMgrProtocol !=3D NULL);=0D
+ ASSERT (Table !=3D NULL);=0D
+ ASSERT (AcpiTableInfo->TableGeneratorId =3D=3D This->GeneratorID);=0D
+=0D
+ if (AcpiTableInfo->AcpiTableData =3D=3D NULL) {=0D
+ // Add the dsdt aml code here.=0D
+ *Table =3D (EFI_ACPI_DESCRIPTION_HEADER *)&dsdt_aml_code;=0D
+ }=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
+/** This macro defines the Raw Generator revision.=0D
+*/=0D
+#define DSDT_GENERATOR_REVISION CREATE_REVISION (1, 0)=0D
+=0D
+/** The interface for the Raw Table Generator.=0D
+*/=0D
+STATIC=0D
+CONST=0D
+ACPI_TABLE_GENERATOR RawDsdtGenerator =3D {=0D
+ // Generator ID=0D
+ CREATE_OEM_ACPI_TABLE_GEN_ID (PlatAcpiTableIdDsdt),=0D
+ // Generator Description=0D
+ L"ACPI.OEM.RAW.DSDT.GENERATOR",=0D
+ // ACPI Table Signature - Unused=0D
+ 0,=0D
+ // ACPI Table Revision - Unused=0D
+ 0,=0D
+ // Minimum ACPI Table Revision - Unused=0D
+ 0,=0D
+ // Creator ID=0D
+ TABLE_GENERATOR_CREATOR_ID_ARM,=0D
+ // Creator Revision=0D
+ DSDT_GENERATOR_REVISION,=0D
+ // Build Table function=0D
+ BuildRawDsdtTable,=0D
+ // No additional resources are allocated by the generator.=0D
+ // Hence the Free Resource function is not required.=0D
+ NULL,=0D
+ // Extended build function not needed=0D
+ NULL,=0D
+ // Extended build function not implemented by the generator.=0D
+ // Hence extended free resource function is not required.=0D
+ NULL=0D
+};=0D
+=0D
+/** Register the Generator with the ACPI Table Factory.=0D
+ @param [in] ImageHandle The handle to the image.=0D
+ @param [in] SystemTable Pointer to the System Table.=0D
+ @retval EFI_SUCCESS The Generator is registered.=0D
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.=0D
+ @retval EFI_ALREADY_STARTED The Generator for the Table ID=0D
+ is already registered.=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+AcpiDsdtLibConstructor (=0D
+ IN CONST EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE * CONST SystemTable=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ Status =3D RegisterAcpiTableGenerator (&RawDsdtGenerator);=0D
+ DEBUG ((DEBUG_INFO, "OEM: Register DSDT Generator. Status =3D %r\n", Sta=
tus));=0D
+ ASSERT_EFI_ERROR (Status);=0D
+ return Status;=0D
+}=0D
+=0D
+/** Deregister the Generator from the ACPI Table Factory.=0D
+ @param [in] ImageHandle The handle to the image.=0D
+ @param [in] SystemTable Pointer to the System Table.=0D
+ @retval EFI_SUCCESS The Generator is deregistered.=0D
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.=0D
+ @retval EFI_NOT_FOUND The Generator is not registered.=0D
+**/=0D
+EFI_STATUS=0D
+EFIAPI=0D
+AcpiDsdtLibDestructor (=0D
+ IN CONST EFI_HANDLE ImageHandle,=0D
+ IN EFI_SYSTEM_TABLE * CONST SystemTable=0D
+ )=0D
+{=0D
+ EFI_STATUS Status;=0D
+ Status =3D DeregisterAcpiTableGenerator (&RawDsdtGenerator);=0D
+ DEBUG ((DEBUG_INFO, "OEM: Deregister DSDT Generator. Status =3D %r\n", S=
tatus));=0D
+ ASSERT_EFI_ERROR (Status);=0D
+ return Status;=0D
+}=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiLib.=
h b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiLib.h
new file mode 100644
index 0000000000..e5f907a7d4
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiLib.h
@@ -0,0 +1,23 @@
+/** @file=0D
+ * Acpi lib headers=0D
+ *=0D
+ * Copyright 2021 NXP=0D
+ * Copyright 2021 Puresoftware Ltd=0D
+ *=0D
+ * SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+ *=0D
+**/=0D
+=0D
+=0D
+#ifndef LS1046AFRWY_PLATFORM_ACPI_LIB_H=0D
+#define LS1046AFRWY_PLATFORM_ACPI_LIB_H=0D
+=0D
+#include <PlatformAcpiTableGenerator.h>=0D
+=0D
+/** C array containing the compiled AML template.=0D
+ These symbols are defined in the auto generated C file=0D
+ containing the AML bytecode array.=0D
+*/=0D
+extern CHAR8 dsdt_aml_code[];=0D
+=0D
+#endif=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h b/Platform/NXP/=
LS1046aFrwyPkg/Include/Platform.h
index 19e879ec6d..b21e875f20 100644
--- a/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h
+++ b/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h
@@ -20,6 +20,10 @@
#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)=0D
#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)=0D
=0D
+// PCLK : Dynamic Clock=0D
+#define DCFG_BASE 0x1EE0000 /* Device configuration da=
ta Base Address */=0D
+#define DCFG_LEN 0xFFF /* Device configuration da=
ta length */=0D
+=0D
// Gic=0D
#define GIC_VERSION 2=0D
#define GICD_BASE 0x1410000=0D
@@ -62,7 +66,7 @@
#define CFG_MGR_TABLE_ID SIGNATURE_64 ('L','S','1','0','4','6',' ',' ')=0D
=0D
// Specify the OEM defined tables=0D
-#define OEM_ACPI_TABLES 0=0D
+#define OEM_ACPI_TABLES 1 // Added DSDT=0D
=0D
#define PLAT_PCI_SEG0 LS1046A_PCI_SEG0=0D
#define PLAT_PCI_SEG1_CONFIG_BASE LS1046A_PCI_SEG1_CONFIG_BASE=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/=
LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
index 20111e6037..7041d15da5 100755
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -65,6 +65,7 @@
NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiMadtLibArm/AcpiMadtLibA=
rm.inf=0D
NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiMcfgLibArm/AcpiMcfgLibA=
rm.inf=0D
NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiSpcrLibArm/AcpiSpcrLibA=
rm.inf=0D
+ NULL|Platform/NXP/LS1046aFrwyPkg/AcpiTablesInclude/PlatformAcpiDsd=
tLib.inf=0D
}=0D
!endif=0D
=0D
--=20
2.25.1


[PATCH V0 3/4] Platform/NXP/LS1046aFrwyPkg: Extend Dynamic ACPI support

Vikas Singh
 

This patch set extends Configuration Manager (CM) and
its services to leverage the Dynamic ACPI support for
NXP's LS1046aFrwy platform.

Refer-https://edk2.groups.io/g/devel/message/71710

Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
---
.../NXP/LS1046aFrwyPkg/Include/Platform.h | 155 ++++++++++++++++++
.../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc | 28 ++++
.../NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf | 13 ++
Silicon/NXP/LS1046A/LS1046A.dsc.inc | 10 ++
4 files changed, 206 insertions(+)
create mode 100644 Platform/NXP/LS1046aFrwyPkg/Include/Platform.h

diff --git a/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h b/Platform/NXP/=
LS1046aFrwyPkg/Include/Platform.h
new file mode 100644
index 0000000000..19e879ec6d
--- /dev/null
+++ b/Platform/NXP/LS1046aFrwyPkg/Include/Platform.h
@@ -0,0 +1,155 @@
+/** @file=0D
+ * Platform headers=0D
+ *=0D
+ * Copyright 2021 NXP=0D
+ * Copyright 2021 Puresoftware Ltd=0D
+ *=0D
+ * SPDX-License-Identifier: BSD-2-Clause-Patent=0D
+ *=0D
+**/=0D
+=0D
+=0D
+#ifndef LS1046AFRWY_PLATFORM_H=0D
+#define LS1046AFRWY_PLATFORM_H=0D
+=0D
+#define EFI_ACPI_ARM_OEM_REVISION 0x00000000=0D
+=0D
+// Soc defines=0D
+#define PLAT_SOC_NAME "LS1046AFRWY"=0D
+#define SVR_SOC_VER(svr) (((svr) >> 8) & 0xFFFFFE)=0D
+#define SVR_MAJOR(svr) (((svr) >> 4) & 0xf)=0D
+#define SVR_MINOR(svr) (((svr) >> 0) & 0xf)=0D
+=0D
+// Gic=0D
+#define GIC_VERSION 2=0D
+#define GICD_BASE 0x1410000=0D
+#define GICC_BASE 0x142f000=0D
+#define GICH_BASE 0x1440000=0D
+#define GICV_BASE 0x1460000=0D
+=0D
+// UART=0D
+#define UART0_BASE 0x21C0500=0D
+#define UART0_IT 86=0D
+#define UART0_LENGTH 0x100=0D
+#define SPCR_FLOW_CONTROL_NONE 0=0D
+=0D
+// Timer=0D
+#define TIMER_BLOCK_COUNT 1=0D
+#define TIMER_FRAME_COUNT 4=0D
+#define TIMER_WATCHDOG_COUNT 1=0D
+#define TIMER_BASE_ADDRESS 0x23E0000 // a.k.a CNTControlBase=0D
+#define TIMER_READ_BASE_ADDRESS 0x23F0000 // a.k.a CNTReadBase=0D
+#define TIMER_SEC_IT 29=0D
+#define TIMER_NON_SEC_IT 30=0D
+#define TIMER_VIRT_IT 27=0D
+#define TIMER_HYP_IT 26=0D
+#define TIMER_FRAME0_IT 78=0D
+#define TIMER_FRAME1_IT 79=0D
+#define TIMER_FRAME2_IT 92=0D
+=0D
+// Mcfg=0D
+#define LS1046A_PCI_SEG0_CONFIG_BASE 0x4000000000=0D
+#define LS1046A_PCI_SEG0 0x0=0D
+#define LS1046A_PCI_SEG_BUSNUM_MIN 0x0=0D
+#define LS1046A_PCI_SEG_BUSNUM_MAX 0xff=0D
+#define LS1046A_PCI_SEG1_CONFIG_BASE 0x4800000000=0D
+#define LS1046A_PCI_SEG2_CONFIG_BASE 0x5000000000=0D
+#define LS1046A_PCI_SEG1 0x1=0D
+#define LS1046A_PCI_SEG2 0x2=0D
+=0D
+// Platform specific info needed by Configuration Manager=0D
+=0D
+#define CFG_MGR_TABLE_ID SIGNATURE_64 ('L','S','1','0','4','6',' ',' ')=0D
+=0D
+// Specify the OEM defined tables=0D
+#define OEM_ACPI_TABLES 0=0D
+=0D
+#define PLAT_PCI_SEG0 LS1046A_PCI_SEG0=0D
+#define PLAT_PCI_SEG1_CONFIG_BASE LS1046A_PCI_SEG1_CONFIG_BASE=0D
+#define PLAT_PCI_SEG1 LS1046A_PCI_SEG1=0D
+#define PLAT_PCI_SEG_BUSNUM_MIN LS1046A_PCI_SEG_BUSNUM_MIN=0D
+#define PLAT_PCI_SEG_BUSNUM_MAX LS1046A_PCI_SEG_BUSNUM_MAX=0D
+#define PLAT_PCI_SEG2_CONFIG_BASE LS1046A_PCI_SEG2_CONFIG_BASE=0D
+#define PLAT_PCI_SEG2 LS1046A_PCI_SEG2=0D
+=0D
+#define PLAT_GIC_VERSION GIC_VERSION=0D
+#define PLAT_GICD_BASE GICD_BASE=0D
+#define PLAT_GICI_BASE GICI_BASE=0D
+#define PLAT_GICR_BASE GICR_BASE=0D
+#define PLAT_GICR_LEN GICR_LEN=0D
+#define PLAT_GICC_BASE GICC_BASE=0D
+#define PLAT_GICH_BASE GICH_BASE=0D
+#define PLAT_GICV_BASE GICV_BASE=0D
+=0D
+#define PLAT_CPU_COUNT 4=0D
+#define PLAT_GTBLOCK_COUNT 0=0D
+#define PLAT_GTFRAME_COUNT 0=0D
+#define PLAT_PCI_CONFG_COUNT 2=0D
+=0D
+#define PLAT_WATCHDOG_COUNT 0=0D
+#define PLAT_GIC_REDISTRIBUTOR_COUNT 0=0D
+#define PLAT_GIC_ITS_COUNT 0=0D
+=0D
+/* GIC CPU Interface information=0D
+ GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, EnergyEfficiency=
)=0D
+ */=0D
+#define PLAT_GIC_CPU_INTERFACE { \=0D
+ GICC_ENTRY (0, GET_MPID (0, 0), 138, 0x19, 0), \=0D
+ GICC_ENTRY (1, GET_MPID (0, 1), 139, 0x19, 0), \=0D
+ GICC_ENTRY (2, GET_MPID (0, 2), 127, 0x19, 0), \=0D
+ GICC_ENTRY (3, GET_MPID (0, 3), 129, 0x19, 0), \=0D
+}=0D
+=0D
+#define PLAT_WATCHDOG_INFO \=0D
+ { \=0D
+ } \=0D
+=0D
+#define PLAT_TIMER_BLOCK_INFO \=0D
+ { \=0D
+ } \=0D
+=0D
+#define PLAT_TIMER_FRAME_INFO \=0D
+ { \=0D
+ } \=0D
+=0D
+#define PLAT_GIC_DISTRIBUTOR_INFO \=0D
+ { \=0D
+ PLAT_GICD_BASE, /* UINT64 PhysicalBaseAddress */ \=0D
+ 0, /* UINT32 SystemVectorBase */ \=0D
+ PLAT_GIC_VERSION /* UINT8 GicVersion */ \=0D
+ } \=0D
+=0D
+#define PLAT_GIC_REDISTRIBUTOR_INFO \=0D
+ { \=0D
+ } \=0D
+=0D
+#define PLAT_GIC_ITS_INFO \=0D
+ { \=0D
+ } \=0D
+=0D
+#define PLAT_MCFG_INFO \=0D
+ { \=0D
+ { \=0D
+ PLAT_PCI_SEG1_CONFIG_BASE, \=0D
+ PLAT_PCI_SEG1, \=0D
+ PLAT_PCI_SEG_BUSNUM_MIN, \=0D
+ PLAT_PCI_SEG_BUSNUM_MAX, \=0D
+ }, \=0D
+ { \=0D
+ PLAT_PCI_SEG2_CONFIG_BASE, \=0D
+ PLAT_PCI_SEG2, \=0D
+ PLAT_PCI_SEG_BUSNUM_MIN, \=0D
+ PLAT_PCI_SEG_BUSNUM_MAX, \=0D
+ } \=0D
+ } \=0D
+=0D
+#define PLAT_SPCR_INFO =
\=0D
+ { =
\=0D
+ UART0_BASE, =
\=0D
+ UART0_IT, =
\=0D
+ 115200, =
\=0D
+ 0, =
\=0D
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_16550 =
\=0D
+ } =
\=0D
+=0D
+#endif // LS1046AFRWY_PLATFORM_H=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc b/Platform/NXP/=
LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
index 67cf15cbe4..20111e6037 100755
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.dsc
@@ -3,6 +3,7 @@
# LS1046AFRWY Board package.=0D
#=0D
# Copyright 2019-2020 NXP=0D
+# Copyright 2021 Puresoftware Ltd=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -22,10 +23,18 @@
OUTPUT_DIRECTORY =3D Build/LS1046aFrwyPkg=0D
FLASH_DEFINITION =3D Platform/NXP/LS1046aFrwyPkg/LS1046aFr=
wyPkg.fdf=0D
=0D
+ # This flag controls the dynamic acpi generation=0D
+ #=0D
+ DEFINE DYNAMIC_ACPI_ENABLE =3D TRUE=0D
+=0D
!include Silicon/NXP/NxpQoriqLs.dsc.inc=0D
!include MdePkg/MdeLibs.dsc.inc=0D
!include Silicon/NXP/LS1046A/LS1046A.dsc.inc=0D
=0D
+!if $(DYNAMIC_ACPI_ENABLE) =3D=3D TRUE=0D
+ !include DynamicTablesPkg/DynamicTables.dsc.inc=0D
+!endif=0D
+=0D
[LibraryClasses.common]=0D
ArmPlatformLib|Platform/NXP/LS1046aFrwyPkg/Library/ArmPlatformLib/ArmPla=
tformLib.inf=0D
RealTimeClockLib|EmbeddedPkg/Library/VirtualRealTimeClockLib/VirtualReal=
TimeClockLib.inf=0D
@@ -46,4 +55,23 @@
=0D
Silicon/NXP/Drivers/UsbHcdInitDxe/UsbHcd.inf=0D
=0D
+ #=0D
+ # Dynamic Table Factory=0D
+ !if $(DYNAMIC_ACPI_ENABLE) =3D=3D TRUE=0D
+ DynamicTablesPkg/Drivers/DynamicTableFactoryDxe/DynamicTableFactoryDxe=
.inf {=0D
+ <LibraryClasses>=0D
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiFadtLibArm/AcpiFadtLibA=
rm.inf=0D
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiGtdtLibArm/AcpiGtdtLibA=
rm.inf=0D
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiMadtLibArm/AcpiMadtLibA=
rm.inf=0D
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiMcfgLibArm/AcpiMcfgLibA=
rm.inf=0D
+ NULL|DynamicTablesPkg/Library/Acpi/Arm/AcpiSpcrLibArm/AcpiSpcrLibA=
rm.inf=0D
+ }=0D
+ !endif=0D
+=0D
+ #=0D
+ # Acpi Support=0D
+ #=0D
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf=0D
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf=0D
+=0D
##=0D
diff --git a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf b/Platform/NXP/=
LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
index 34c4e5a025..f3cac033bc 100755
--- a/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
+++ b/Platform/NXP/LS1046aFrwyPkg/LS1046aFrwyPkg.fdf
@@ -3,6 +3,7 @@
# FLASH layout file for LS1046a board.=0D
#=0D
# Copyright 2019-2020 NXP=0D
+# Copyright 2021 Puresoftware Ltd=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -99,6 +100,18 @@ READ_LOCK_STATUS =3D TRUE
INF MdeModulePkg/Universal/Metronome/Metronome.inf=0D
INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf=0D
=0D
+=0D
+ #=0D
+ # Acpi Support=0D
+ #=0D
+ INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf=0D
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf=0D
+=0D
+ !if $(DYNAMIC_ACPI_ENABLE) =3D=3D TRUE=0D
+ INF Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/Confi=
gurationManagerDxe.inf=0D
+ !include DynamicTablesPkg/DynamicTables.fdf.inc=0D
+ !endif=0D
+=0D
#=0D
# Multiple Console IO support=0D
#=0D
diff --git a/Silicon/NXP/LS1046A/LS1046A.dsc.inc b/Silicon/NXP/LS1046A/LS10=
46A.dsc.inc
index 7004533ed5..98f999edfd 100644
--- a/Silicon/NXP/LS1046A/LS1046A.dsc.inc
+++ b/Silicon/NXP/LS1046A/LS1046A.dsc.inc
@@ -2,6 +2,7 @@
# LS1046A Soc package.=0D
#=0D
# Copyright 2017-2020 NXP=0D
+# Copyright 2021 Puresoftware Ltd=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -48,4 +49,13 @@
[Components.common]=0D
MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf=0D
=0D
+#=0D
+# Configuration Manager=0D
+!if $(DYNAMIC_ACPI_ENABLE) =3D=3D TRUE=0D
+ Platform/NXP/ConfigurationManagerPkg/ConfigurationManagerDxe/Configurati=
onManagerDxe.inf {=0D
+ <BuildOptions>=0D
+ *_*_*_PLATFORM_FLAGS =3D -I$(WORKSPACE)/Platform/NXP/LS1046aFrwyPkg/=
Include=0D
+ }=0D
+!endif=0D
+=0D
##=0D
--=20
2.25.1


[PATCH V0 2/4] Silicon/NXP: Add support of SVR handling for LS1046FRWY

Vikas Singh
 

This change set intend to add a generic method to get
access to SoC's Silicon Version Register (SVR) and its
handling for LS1046aFrwy platform.

Signed-off-by: Vikas Singh <vikas.singh@puresoftware.com>
---
Silicon/NXP/LS1046A/Library/SocLib/SocLib.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)

diff --git a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c b/Silicon/NXP/LS10=
46A/Library/SocLib/SocLib.c
index 8fa6a7dd00..003f5bd82f 100644
--- a/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
+++ b/Silicon/NXP/LS1046A/Library/SocLib/SocLib.c
@@ -2,6 +2,7 @@
SoC specific Library containg functions to initialize various SoC compon=
ents=0D
=0D
Copyright 2017-2020 NXP=0D
+ Copyright 2021 Puresoftware Ltd=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
@@ -64,6 +65,21 @@ SocGetClock (
return ReturnValue;=0D
}=0D
=0D
+/**=0D
+ Function to get SoC's System Version Register(SVR)=0D
+ **/=0D
+UINT32=0D
+SocGetSvr (=0D
+ VOID=0D
+ )=0D
+{=0D
+ LS1046A_DEVICE_CONFIG *Dcfg;=0D
+=0D
+ Dcfg =3D (LS1046A_DEVICE_CONFIG *)LS1046A_DCFG_ADDRESS;=0D
+=0D
+ return DcfgRead32 ((UINTN)&Dcfg->Svr);=0D
+}=0D
+=0D
/**=0D
Function to select pins depending upon pcd using supplemental=0D
configuration unit(SCFG) extended RCW controlled pinmux control=0D
--=20
2.25.1

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