Date   

[PATCH v2 19/34] .azurepipelines: Add LoongArch64 architecture on LoongArch64 EDK2 CI.

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

Add LoongArch64 architecture on LoongArch64 EDK2 CI.

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>

Signed-off-by: Chao Li <lichao@...>
---
.azurepipelines/Ubuntu-GCC5.yml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/.azurepipelines/Ubuntu-GCC5.yml b/.azurepipelines/Ubuntu-GCC5.=
yml
index 3760c6efe1..1acd8d2a46 100644
--- a/.azurepipelines/Ubuntu-GCC5.yml
+++ b/.azurepipelines/Ubuntu-GCC5.yml
@@ -3,6 +3,7 @@
#=0D
# Copyright (c) Microsoft Corporation.=0D
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights =
reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
##=0D
trigger:=0D
@@ -17,5 +18,5 @@ jobs:
parameters:=0D
tool_chain_tag: 'GCC5'=0D
vm_image: 'ubuntu-latest'=0D
- arch_list: "IA32,X64,ARM,AARCH64,RISCV64"=0D
+ arch_list: "IA32,X64,ARM,AARCH64,RISCV64,LOONGARCH64"=0D
=0D
--=20
2.27.0


[PATCH v2 18/34] BaseTools: Enable LoongArch64 architecture for LoongArch64 EDK2 CI.

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

EDK CI for LoongArch64 architecture

Enable LoongArch64 architecture for LoongArch64 EDK2 CI testing.

Cc: Bob Feng <bob.c.feng@...>
Cc: Liming Gao <gaoliming@...>
Cc: Yuwei Chen <yuwei.chen@...>

Signed-off-by: Chao Li <lichao@...>
---
...gcc_loongarch64_unknown_linux_ext_dep.yaml | 22 +++++++++++++
.../LinuxGcc5ToolChain/LinuxGcc5ToolChain.py | 31 +++++++++++++++++++
2 files changed, 53 insertions(+)
create mode 100644 BaseTools/Bin/gcc_loongarch64_unknown_linux_ext_dep.yaml

diff --git a/BaseTools/Bin/gcc_loongarch64_unknown_linux_ext_dep.yaml b/Bas=
eTools/Bin/gcc_loongarch64_unknown_linux_ext_dep.yaml
new file mode 100644
index 0000000000..ac18438080
--- /dev/null
+++ b/BaseTools/Bin/gcc_loongarch64_unknown_linux_ext_dep.yaml
@@ -0,0 +1,22 @@
+## @file
+# Download GCC LoongArch64 compiler from LoongArch GitHub release site
+# Set shell variable GCC5_LOONGARCH64_INSTALL to this folder
+#
+# This is only downloaded when a build activates scope gcc_loongarch64_unk=
nown_linux
+#
+# Copyright (c) Microsoft Corporation.
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights =
reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+{
+ "scope": "gcc_loongarch64_unknown_linux",
+ "type": "web",
+ "name": "gcc_loongarch64_unknown_linux",
+ "source":"https://github.com/loongson/build-tools/releases/download/2022=
.09.06/loongarch64-clfs-6.3-cross-tools-gcc-full.tar.xz",
+ "version": "13.0.0",
+ "sha256":"27a43c5bb127794f091d0e75da0003c4d0eec28a958d8f2cc7cd290a6e6133=
ab",
+ "compression_type": "tar",
+ "internal_path": "/cross-tools/",
+ "flags": ["set_shell_var", ],
+ "var_name": "GCC5_LOONGARCH64_INSTALL"
+}
diff --git a/BaseTools/Plugin/LinuxGcc5ToolChain/LinuxGcc5ToolChain.py b/Ba=
seTools/Plugin/LinuxGcc5ToolChain/LinuxGcc5ToolChain.py
index f0685d8040..dab7a87997 100644
--- a/BaseTools/Plugin/LinuxGcc5ToolChain/LinuxGcc5ToolChain.py
+++ b/BaseTools/Plugin/LinuxGcc5ToolChain/LinuxGcc5ToolChain.py
@@ -5,6 +5,7 @@
#=0D
# Copyright (c) Microsoft Corporation=0D
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights =
reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
##=0D
import os=0D
@@ -43,6 +44,12 @@ class LinuxGcc5ToolChain(IUefiBuildPlugin):
self.Logger.critical("Failed in check riscv64")=0D
return ret=0D
=0D
+ # Check LoongArch64 compiler=0D
+ ret =3D self._check_loongarch64()=0D
+ if ret !=3D 0:=0D
+ self.Logger.critical("Failed in check loongarch64")=0D
+ return ret=0D
+=0D
return 0=0D
=0D
def _check_arm(self):=0D
@@ -121,3 +128,27 @@ class LinuxGcc5ToolChain(IUefiBuildPlugin):
shell_environment.GetEnvironment().set_shell_var("LD_LIBRARY_PATH"=
, prefix)=0D
=0D
return 0=0D
+=0D
+ def _check_loongarch64(self):=0D
+ # check to see if full path already configured=0D
+ if shell_environment.GetEnvironment().get_shell_var("GCC5_LOONGARC=
H64_PREFIX") is not None:=0D
+ self.Logger.info("GCC5_LOONGARCH64_PREFIX is already set.")=0D
+=0D
+ else:=0D
+ # now check for install dir. If set then set the Prefix=0D
+ install_path =3D shell_environment.GetEnvironment(=0D
+ ).get_shell_var("GCC5_LOONGARCH64_INSTALL")=0D
+ if install_path is None:=0D
+ return 0=0D
+=0D
+ # make GCC5_LOONGARCH64_PREFIX to align with tools_def.txt=0D
+ prefix =3D os.path.join(install_path, "bin", "loongarch64-unkn=
own-linux-gnu-")=0D
+ shell_environment.GetEnvironment().set_shell_var("GCC5_LOONGAR=
CH64_PREFIX", prefix)=0D
+=0D
+ # now confirm it exists=0D
+ if not os.path.exists(shell_environment.GetEnvironment().get_shell=
_var("GCC5_LOONGARCH64_PREFIX") + "gcc"):=0D
+ self.Logger.error(=0D
+ "Path for GCC5_LOONGARCH64_PREFIX toolchain is invalid")=0D
+ return -2=0D
+=0D
+ return 0=0D
--=20
2.27.0


[PATCH v2 17/34] BaseTools: BaseTools changes for LoongArch platform.

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

Python code changes for building EDK2 LoongArch platform.

Cc: Bob Feng <bob.c.feng@...>
Cc: Liming Gao <gaoliming@...>
Cc: Yuwei Chen <yuwei.chen@...>

Signed-off-by: Chao Li <lichao@...>
Co-authored-by: Baoqi Zhang <zhangbaoqi@...>
---
BaseTools/Source/Python/Common/DataType.py | 21 ++++++++++++++--
.../Source/Python/UPT/Library/DataType.py | 24 ++++++++++++++++++-
BaseTools/Source/Python/build/buildoptions.py | 3 ++-
3 files changed, 44 insertions(+), 4 deletions(-)

diff --git a/BaseTools/Source/Python/Common/DataType.py b/BaseTools/Source/=
Python/Common/DataType.py
index dc49623333..48dbf16495 100644
--- a/BaseTools/Source/Python/Common/DataType.py
+++ b/BaseTools/Source/Python/Common/DataType.py
@@ -4,6 +4,7 @@
# Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>=0D
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>=0D
# Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. =
All rights reserved.<BR>=0D
+# Portions Copyright (c) 2022, Loongson Technology Corporation Limited. Al=
l rights reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
##=0D
@@ -52,10 +53,10 @@ TAB_ARCH_X64 =3D 'X64'
TAB_ARCH_ARM =3D 'ARM'=0D
TAB_ARCH_EBC =3D 'EBC'=0D
TAB_ARCH_AARCH64 =3D 'AARCH64'=0D
-=0D
TAB_ARCH_RISCV64 =3D 'RISCV64'=0D
+TAB_ARCH_LOONGARCH64 =3D 'LOONGARCH64'=0D
=0D
-ARCH_SET_FULL =3D {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC=
, TAB_ARCH_AARCH64, TAB_ARCH_RISCV64, TAB_ARCH_COMMON}=0D
+ARCH_SET_FULL =3D {TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_ARM, TAB_ARCH_EBC=
, TAB_ARCH_AARCH64, TAB_ARCH_RISCV64, TAB_ARCH_LOONGARCH64, TAB_ARCH_COMMON=
}=0D
=0D
SUP_MODULE_BASE =3D 'BASE'=0D
SUP_MODULE_SEC =3D 'SEC'=0D
@@ -138,6 +139,7 @@ TAB_SOURCES_X64 =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_=
X64
TAB_SOURCES_ARM =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_ARM=0D
TAB_SOURCES_EBC =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_EBC=0D
TAB_SOURCES_AARCH64 =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_AARCH64=0D
+TAB_SOURCES_LOONGARCH64 =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_LOONGARCH64=
=0D
=0D
TAB_BINARIES =3D 'Binaries'=0D
TAB_BINARIES_COMMON =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_COMMON=0D
@@ -146,6 +148,7 @@ TAB_BINARIES_X64 =3D TAB_BINARIES + TAB_SPLIT + TAB_ARC=
H_X64
TAB_BINARIES_ARM =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_ARM=0D
TAB_BINARIES_EBC =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_EBC=0D
TAB_BINARIES_AARCH64 =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_AARCH64=0D
+TAB_BINARIES_LOONGARCH64 =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_LOONGARCH=
64=0D
=0D
TAB_INCLUDES =3D 'Includes'=0D
TAB_INCLUDES_COMMON =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_COMMON=0D
@@ -154,6 +157,7 @@ TAB_INCLUDES_X64 =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARC=
H_X64
TAB_INCLUDES_ARM =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_ARM=0D
TAB_INCLUDES_EBC =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_EBC=0D
TAB_INCLUDES_AARCH64 =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_AARCH64=0D
+TAB_INCLUDES_LOONGARCH64 =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_LOONGARCH=
64=0D
=0D
TAB_GUIDS =3D 'Guids'=0D
TAB_GUIDS_COMMON =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_COMMON=0D
@@ -162,6 +166,7 @@ TAB_GUIDS_X64 =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_X64
TAB_GUIDS_ARM =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_ARM=0D
TAB_GUIDS_EBC =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_EBC=0D
TAB_GUIDS_AARCH64 =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_AARCH64=0D
+TAB_GUIDS_LOONGARCH64 =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_LOONGARCH64=0D
=0D
TAB_PROTOCOLS =3D 'Protocols'=0D
TAB_PROTOCOLS_COMMON =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_COMMON=0D
@@ -170,6 +175,7 @@ TAB_PROTOCOLS_X64 =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_A=
RCH_X64
TAB_PROTOCOLS_ARM =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_ARM=0D
TAB_PROTOCOLS_EBC =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_EBC=0D
TAB_PROTOCOLS_AARCH64 =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_AARCH64=0D
+TAB_PROTOCOLS_LOONGARCH64 =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_LOONGAR=
CH64=0D
=0D
TAB_PPIS =3D 'Ppis'=0D
TAB_PPIS_COMMON =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_COMMON=0D
@@ -178,6 +184,7 @@ TAB_PPIS_X64 =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_X64
TAB_PPIS_ARM =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_ARM=0D
TAB_PPIS_EBC =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_EBC=0D
TAB_PPIS_AARCH64 =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_AARCH64=0D
+TAB_PPIS_LOONGARCH64 =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_LOONGARCH64=0D
=0D
TAB_LIBRARY_CLASSES =3D 'LibraryClasses'=0D
TAB_LIBRARY_CLASSES_COMMON =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_=
COMMON=0D
@@ -186,6 +193,7 @@ TAB_LIBRARY_CLASSES_X64 =3D TAB_LIBRARY_CLASSES + TAB_S=
PLIT + TAB_ARCH_X64
TAB_LIBRARY_CLASSES_ARM =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_ARM=
=0D
TAB_LIBRARY_CLASSES_EBC =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_EBC=
=0D
TAB_LIBRARY_CLASSES_AARCH64 =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH=
_AARCH64=0D
+TAB_LIBRARY_CLASSES_LOONGARCH64 =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_=
ARCH_LOONGARCH64=0D
=0D
TAB_PACKAGES =3D 'Packages'=0D
TAB_PACKAGES_COMMON =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_COMMON=0D
@@ -194,6 +202,7 @@ TAB_PACKAGES_X64 =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARC=
H_X64
TAB_PACKAGES_ARM =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_ARM=0D
TAB_PACKAGES_EBC =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_EBC=0D
TAB_PACKAGES_AARCH64 =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_AARCH64=0D
+TAB_PACKAGES_LOONGARCH64 =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_LOONGARCH=
64=0D
=0D
TAB_PCDS =3D 'Pcds'=0D
TAB_PCDS_FIXED_AT_BUILD =3D 'FixedAtBuild'=0D
@@ -221,6 +230,7 @@ TAB_PCDS_FIXED_AT_BUILD_X64 =3D TAB_PCDS + TAB_PCDS_FIX=
ED_AT_BUILD + TAB_SPLIT + T
TAB_PCDS_FIXED_AT_BUILD_ARM =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_S=
PLIT + TAB_ARCH_ARM=0D
TAB_PCDS_FIXED_AT_BUILD_EBC =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + TAB_S=
PLIT + TAB_ARCH_EBC=0D
TAB_PCDS_FIXED_AT_BUILD_AARCH64 =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + T=
AB_SPLIT + TAB_ARCH_AARCH64=0D
+TAB_PCDS_FIXED_AT_BUILD_LOONGARCH64 =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD=
+ TAB_SPLIT + TAB_ARCH_LOONGARCH64=0D
=0D
TAB_PCDS_PATCHABLE_IN_MODULE_NULL =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MOD=
ULE=0D
TAB_PCDS_PATCHABLE_IN_MODULE_COMMON =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_M=
ODULE + TAB_SPLIT + TAB_ARCH_COMMON=0D
@@ -229,6 +239,7 @@ TAB_PCDS_PATCHABLE_IN_MODULE_X64 =3D TAB_PCDS + TAB_PCD=
S_PATCHABLE_IN_MODULE + TAB
TAB_PCDS_PATCHABLE_IN_MODULE_ARM =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODU=
LE + TAB_SPLIT + TAB_ARCH_ARM=0D
TAB_PCDS_PATCHABLE_IN_MODULE_EBC =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODU=
LE + TAB_SPLIT + TAB_ARCH_EBC=0D
TAB_PCDS_PATCHABLE_IN_MODULE_AARCH64 =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_=
MODULE + TAB_SPLIT + TAB_ARCH_AARCH64=0D
+TAB_PCDS_PATCHABLE_IN_MODULE_LOONGARCH64 =3D TAB_PCDS + TAB_PCDS_PATCHABLE=
_IN_MODULE + TAB_SPLIT + TAB_ARCH_LOONGARCH64=0D
=0D
TAB_PCDS_FEATURE_FLAG_NULL =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG=0D
TAB_PCDS_FEATURE_FLAG_COMMON =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SP=
LIT + TAB_ARCH_COMMON=0D
@@ -237,6 +248,7 @@ TAB_PCDS_FEATURE_FLAG_X64 =3D TAB_PCDS + TAB_PCDS_FEATU=
RE_FLAG + TAB_SPLIT + TAB_A
TAB_PCDS_FEATURE_FLAG_ARM =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT=
+ TAB_ARCH_ARM=0D
TAB_PCDS_FEATURE_FLAG_EBC =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT=
+ TAB_ARCH_EBC=0D
TAB_PCDS_FEATURE_FLAG_AARCH64 =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_S=
PLIT + TAB_ARCH_AARCH64=0D
+TAB_PCDS_FEATURE_FLAG_LOONGARCH64 =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + T=
AB_SPLIT + TAB_ARCH_LOONGARCH64=0D
=0D
TAB_PCDS_DYNAMIC_EX_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX=0D
TAB_PCDS_DYNAMIC_EX_DEFAULT_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX_DEFAUL=
T=0D
@@ -248,6 +260,7 @@ TAB_PCDS_DYNAMIC_EX_X64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC=
_EX + TAB_SPLIT + TAB_ARCH_
TAB_PCDS_DYNAMIC_EX_ARM =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + T=
AB_ARCH_ARM=0D
TAB_PCDS_DYNAMIC_EX_EBC =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + T=
AB_ARCH_EBC=0D
TAB_PCDS_DYNAMIC_EX_AARCH64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT=
+ TAB_ARCH_AARCH64=0D
+TAB_PCDS_DYNAMIC_EX_LOONGARCH64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_S=
PLIT + TAB_ARCH_LOONGARCH64=0D
=0D
TAB_PCDS_DYNAMIC_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC=0D
TAB_PCDS_DYNAMIC_DEFAULT_NULL =3D TAB_PCDS + TAB_PCDS_DYNAMIC_DEFAULT=0D
@@ -259,6 +272,7 @@ TAB_PCDS_DYNAMIC_X64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC + =
TAB_SPLIT + TAB_ARCH_X64
TAB_PCDS_DYNAMIC_ARM =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARC=
H_ARM=0D
TAB_PCDS_DYNAMIC_EBC =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARC=
H_EBC=0D
TAB_PCDS_DYNAMIC_AARCH64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB=
_ARCH_AARCH64=0D
+TAB_PCDS_DYNAMIC_LOONGARCH64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT +=
TAB_ARCH_LOONGARCH64=0D
=0D
TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_PEI_PAGE_SIZE =3D 'PcdLoadFixAddressPe=
iCodePageNumber'=0D
TAB_PCDS_PATCHABLE_LOAD_FIX_ADDRESS_PEI_PAGE_SIZE_DATA_TYPE =3D 'UINT32'=0D
@@ -285,6 +299,7 @@ TAB_DEPEX_X64 =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_X64
TAB_DEPEX_ARM =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_ARM=0D
TAB_DEPEX_EBC =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_EBC=0D
TAB_DEPEX_AARCH64 =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_AARCH64=0D
+TAB_DEPEX_LOONGARCH64 =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_LOONGARCH64=0D
=0D
TAB_SKUIDS =3D 'SkuIds'=0D
TAB_DEFAULT_STORES =3D 'DefaultStores'=0D
@@ -297,6 +312,7 @@ TAB_LIBRARIES_X64 =3D TAB_LIBRARIES + TAB_SPLIT + TAB_A=
RCH_X64
TAB_LIBRARIES_ARM =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_ARM=0D
TAB_LIBRARIES_EBC =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_EBC=0D
TAB_LIBRARIES_AARCH64 =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_AARCH64=0D
+TAB_LIBRARIES_LOONGARCH64 =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_LOONGAR=
CH64=0D
=0D
TAB_COMPONENTS =3D 'Components'=0D
TAB_COMPONENTS_COMMON =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_COMMON=0D
@@ -305,6 +321,7 @@ TAB_COMPONENTS_X64 =3D TAB_COMPONENTS + TAB_SPLIT + TAB=
_ARCH_X64
TAB_COMPONENTS_ARM =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_ARM=0D
TAB_COMPONENTS_EBC =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_EBC=0D
TAB_COMPONENTS_AARCH64 =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_AARCH64=0D
+TAB_COMPONENTS_LOONGARCH64 =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_LOONG=
ARCH64=0D
=0D
TAB_BUILD_OPTIONS =3D 'BuildOptions'=0D
=0D
diff --git a/BaseTools/Source/Python/UPT/Library/DataType.py b/BaseTools/So=
urce/Python/UPT/Library/DataType.py
index 2033149aa6..0e47f35670 100644
--- a/BaseTools/Source/Python/UPT/Library/DataType.py
+++ b/BaseTools/Source/Python/UPT/Library/DataType.py
@@ -2,6 +2,7 @@
# This file is used to define class for data type structure=0D
#=0D
# Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>=0D
+# Portions Copyright (c) 2022, Loongson Technology Corporation Limited. Al=
l rights reserved.=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
@@ -367,10 +368,11 @@ TAB_ARCH_IA32 =3D 'IA32'
TAB_ARCH_X64 =3D 'X64'=0D
TAB_ARCH_IPF =3D 'IPF'=0D
TAB_ARCH_ARM =3D 'ARM'=0D
+TAB_ARCH_LOONGARCH64 =3D 'LOONGARCH64'=0D
TAB_ARCH_EBC =3D 'EBC'=0D
=0D
ARCH_LIST =3D \=0D
-[TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_IPF, TAB_ARCH_ARM, TAB_ARCH_EBC]=0D
+[TAB_ARCH_IA32, TAB_ARCH_X64, TAB_ARCH_IPF, TAB_ARCH_ARM, TAB_ARCH_LOONGAR=
CH64, TAB_ARCH_EBC]=0D
=0D
SUP_MODULE_BASE =3D 'BASE'=0D
SUP_MODULE_SEC =3D 'SEC'=0D
@@ -454,6 +456,7 @@ TAB_SOURCES_IA32 =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH=
_IA32
TAB_SOURCES_X64 =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_X64=0D
TAB_SOURCES_IPF =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_IPF=0D
TAB_SOURCES_ARM =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_ARM=0D
+TAB_SOURCES_LOONGARCH64 =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_LOONGARCH64=
=0D
TAB_SOURCES_EBC =3D TAB_SOURCES + TAB_SPLIT + TAB_ARCH_EBC=0D
=0D
TAB_BINARIES =3D 'Binaries'=0D
@@ -462,6 +465,7 @@ TAB_BINARIES_IA32 =3D TAB_BINARIES + TAB_SPLIT + TAB_AR=
CH_IA32
TAB_BINARIES_X64 =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_X64=0D
TAB_BINARIES_IPF =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_IPF=0D
TAB_BINARIES_ARM =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_ARM=0D
+TAB_BINARIES_LOONGARCH64 =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_LOONGARCH=
64=0D
TAB_BINARIES_EBC =3D TAB_BINARIES + TAB_SPLIT + TAB_ARCH_EBC=0D
=0D
TAB_INCLUDES =3D 'Includes'=0D
@@ -470,6 +474,7 @@ TAB_INCLUDES_IA32 =3D TAB_INCLUDES + TAB_SPLIT + TAB_AR=
CH_IA32
TAB_INCLUDES_X64 =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_X64=0D
TAB_INCLUDES_IPF =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_IPF=0D
TAB_INCLUDES_ARM =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_ARM=0D
+TAB_INCLUDES_LOONGARCH64 =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_LOONGARCH=
64=0D
TAB_INCLUDES_EBC =3D TAB_INCLUDES + TAB_SPLIT + TAB_ARCH_EBC=0D
=0D
TAB_GUIDS =3D 'Guids'=0D
@@ -478,6 +483,7 @@ TAB_GUIDS_IA32 =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_IA32
TAB_GUIDS_X64 =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_X64=0D
TAB_GUIDS_IPF =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_IPF=0D
TAB_GUIDS_ARM =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_ARM=0D
+TAB_GUIDS_LOONGARCH64 =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_LOONGARCH64=0D
TAB_GUIDS_EBC =3D TAB_GUIDS + TAB_SPLIT + TAB_ARCH_EBC=0D
=0D
TAB_PROTOCOLS =3D 'Protocols'=0D
@@ -486,6 +492,7 @@ TAB_PROTOCOLS_IA32 =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_=
ARCH_IA32
TAB_PROTOCOLS_X64 =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_X64=0D
TAB_PROTOCOLS_IPF =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_IPF=0D
TAB_PROTOCOLS_ARM =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_ARM=0D
+TAB_PROTOCOLS_LOONGARCH64 =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_LOONGAR=
CH64=0D
TAB_PROTOCOLS_EBC =3D TAB_PROTOCOLS + TAB_SPLIT + TAB_ARCH_EBC=0D
=0D
TAB_PPIS =3D 'Ppis'=0D
@@ -494,6 +501,7 @@ TAB_PPIS_IA32 =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_IA32
TAB_PPIS_X64 =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_X64=0D
TAB_PPIS_IPF =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_IPF=0D
TAB_PPIS_ARM =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_ARM=0D
+TAB_PPIS_LOONGARCH64 =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_LOONGARCH64=0D
TAB_PPIS_EBC =3D TAB_PPIS + TAB_SPLIT + TAB_ARCH_EBC=0D
=0D
TAB_LIBRARY_CLASSES =3D 'LibraryClasses'=0D
@@ -502,6 +510,7 @@ TAB_LIBRARY_CLASSES_IA32 =3D TAB_LIBRARY_CLASSES + TAB_=
SPLIT + TAB_ARCH_IA32
TAB_LIBRARY_CLASSES_X64 =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_X64=
=0D
TAB_LIBRARY_CLASSES_IPF =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_IPF=
=0D
TAB_LIBRARY_CLASSES_ARM =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_ARM=
=0D
+TAB_LIBRARY_CLASSES_LOONGARCH64 =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_=
ARCH_LOONGARCH64=0D
TAB_LIBRARY_CLASSES_EBC =3D TAB_LIBRARY_CLASSES + TAB_SPLIT + TAB_ARCH_EBC=
=0D
=0D
TAB_PACKAGES =3D 'Packages'=0D
@@ -510,6 +519,7 @@ TAB_PACKAGES_IA32 =3D TAB_PACKAGES + TAB_SPLIT + TAB_AR=
CH_IA32
TAB_PACKAGES_X64 =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_X64=0D
TAB_PACKAGES_IPF =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_IPF=0D
TAB_PACKAGES_ARM =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_ARM=0D
+TAB_PACKAGES_LOONGARCH64 =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_LOONGARCH=
64=0D
TAB_PACKAGES_EBC =3D TAB_PACKAGES + TAB_SPLIT + TAB_ARCH_EBC=0D
=0D
TAB_PCDS =3D 'Pcds'=0D
@@ -548,6 +558,8 @@ TAB_PCDS_FIXED_AT_BUILD_IPF =3D TAB_PCDS + TAB_PCDS_FIX=
ED_AT_BUILD + \
TAB_SPLIT + TAB_ARCH_IPF=0D
TAB_PCDS_FIXED_AT_BUILD_ARM =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + \=0D
TAB_SPLIT + TAB_ARCH_ARM=0D
+TAB_PCDS_FIXED_AT_BUILD_LOONGARCH64 =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD=
+ \=0D
+TAB_SPLIT + TAB_ARCH_LOONGARCH64=0D
TAB_PCDS_FIXED_AT_BUILD_EBC =3D TAB_PCDS + TAB_PCDS_FIXED_AT_BUILD + \=0D
TAB_SPLIT + TAB_ARCH_EBC=0D
=0D
@@ -562,6 +574,8 @@ TAB_PCDS_PATCHABLE_IN_MODULE_IPF =3D TAB_PCDS + TAB_PCD=
S_PATCHABLE_IN_MODULE + \
TAB_SPLIT + TAB_ARCH_IPF=0D
TAB_PCDS_PATCHABLE_IN_MODULE_ARM =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODU=
LE + \=0D
TAB_SPLIT + TAB_ARCH_ARM=0D
+TAB_PCDS_PATCHABLE_IN_MODULE_LOONGARCH64 =3D TAB_PCDS + TAB_PCDS_PATCHABLE=
_IN_MODULE + \=0D
+TAB_SPLIT + TAB_ARCH_LOONGARCH64=0D
TAB_PCDS_PATCHABLE_IN_MODULE_EBC =3D TAB_PCDS + TAB_PCDS_PATCHABLE_IN_MODU=
LE + \=0D
TAB_SPLIT + TAB_ARCH_EBC=0D
=0D
@@ -576,6 +590,8 @@ TAB_PCDS_FEATURE_FLAG_IPF =3D TAB_PCDS + TAB_PCDS_FEATU=
RE_FLAG + TAB_SPLIT + \
TAB_ARCH_IPF=0D
TAB_PCDS_FEATURE_FLAG_ARM =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT=
+ \=0D
TAB_ARCH_ARM=0D
+TAB_PCDS_FEATURE_FLAG_LOONGARCH64 =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + T=
AB_SPLIT + \=0D
+TAB_ARCH_LOONGARCH64=0D
TAB_PCDS_FEATURE_FLAG_EBC =3D TAB_PCDS + TAB_PCDS_FEATURE_FLAG + TAB_SPLIT=
+ \=0D
TAB_ARCH_EBC=0D
=0D
@@ -593,6 +609,8 @@ TAB_PCDS_DYNAMIC_EX_IPF =3D TAB_PCDS + TAB_PCDS_DYNAMIC=
_EX + TAB_SPLIT + \
TAB_ARCH_IPF=0D
TAB_PCDS_DYNAMIC_EX_ARM =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + \=
=0D
TAB_ARCH_ARM=0D
+TAB_PCDS_DYNAMIC_EX_LOONGARCH64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_S=
PLIT + \=0D
+TAB_ARCH_LOONGARCH64=0D
TAB_PCDS_DYNAMIC_EX_EBC =3D TAB_PCDS + TAB_PCDS_DYNAMIC_EX + TAB_SPLIT + \=
=0D
TAB_ARCH_EBC=0D
=0D
@@ -606,6 +624,7 @@ TAB_PCDS_DYNAMIC_IA32 =3D TAB_PCDS + TAB_PCDS_DYNAMIC +=
TAB_SPLIT + TAB_ARCH_IA32
TAB_PCDS_DYNAMIC_X64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARC=
H_X64=0D
TAB_PCDS_DYNAMIC_IPF =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARC=
H_IPF=0D
TAB_PCDS_DYNAMIC_ARM =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARC=
H_ARM=0D
+TAB_PCDS_DYNAMIC_LOONGARCH64 =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT +=
TAB_ARCH_LOONGARCH64=0D
TAB_PCDS_DYNAMIC_EBC =3D TAB_PCDS + TAB_PCDS_DYNAMIC + TAB_SPLIT + TAB_ARC=
H_EBC=0D
=0D
TAB_PCD_DYNAMIC_TYPE_LIST =3D [TAB_PCDS_DYNAMIC_DEFAULT_NULL, \=0D
@@ -646,6 +665,7 @@ TAB_DEPEX_IA32 =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_IA32
TAB_DEPEX_X64 =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_X64=0D
TAB_DEPEX_IPF =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_IPF=0D
TAB_DEPEX_ARM =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_ARM=0D
+TAB_DEPEX_LOONGARCH64 =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_LOONGARCH64=0D
TAB_DEPEX_EBC =3D TAB_DEPEX + TAB_SPLIT + TAB_ARCH_EBC=0D
=0D
TAB_SKUIDS =3D 'SkuIds'=0D
@@ -656,6 +676,7 @@ TAB_LIBRARIES_IA32 =3D TAB_LIBRARIES + TAB_SPLIT + TAB_=
ARCH_IA32
TAB_LIBRARIES_X64 =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_X64=0D
TAB_LIBRARIES_IPF =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_IPF=0D
TAB_LIBRARIES_ARM =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_ARM=0D
+TAB_LIBRARIES_LOONGARCH64 =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_LOONGAR=
CH64=0D
TAB_LIBRARIES_EBC =3D TAB_LIBRARIES + TAB_SPLIT + TAB_ARCH_EBC=0D
=0D
TAB_COMPONENTS =3D 'Components'=0D
@@ -664,6 +685,7 @@ TAB_COMPONENTS_IA32 =3D TAB_COMPONENTS + TAB_SPLIT + TA=
B_ARCH_IA32
TAB_COMPONENTS_X64 =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_X64=0D
TAB_COMPONENTS_IPF =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_IPF=0D
TAB_COMPONENTS_ARM =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_ARM=0D
+TAB_COMPONENTS_LOONGARCH64 =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_LOONG=
ARCH64=0D
TAB_COMPONENTS_EBC =3D TAB_COMPONENTS + TAB_SPLIT + TAB_ARCH_EBC=0D
=0D
TAB_BUILD_OPTIONS =3D 'BuildOptions'=0D
diff --git a/BaseTools/Source/Python/build/buildoptions.py b/BaseTools/Sour=
ce/Python/build/buildoptions.py
index 39d92cff20..8334604b46 100644
--- a/BaseTools/Source/Python/build/buildoptions.py
+++ b/BaseTools/Source/Python/build/buildoptions.py
@@ -4,6 +4,7 @@
# Copyright (c) 2014, Hewlett-Packard Development Company, L.P.<BR>=0D
# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>=
=0D
# Copyright (c) 2018 - 2020, Hewlett Packard Enterprise Development, L.P.=
<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights=
reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -41,7 +42,7 @@ class MyOptionParser():
def GetOption(self):=0D
Parser =3D OptionParser(description=3D__copyright__, version=3D__v=
ersion__, prog=3D"build.exe", usage=3D"%prog [options] [all|fds|genc|genmak=
e|clean|cleanall|cleanlib|modules|libraries|run]")=0D
Parser.add_option("-a", "--arch", action=3D"append", dest=3D"Targe=
tArch",=0D
- help=3D"ARCHS is one of list: IA32, X64, ARM, AARCH64, RISCV64=
or EBC, which overrides target.txt's TARGET_ARCH definition. To specify mo=
re archs, please repeat this option.")=0D
+ help=3D"ARCHS is one of list: IA32, X64, ARM, AARCH64, RISCV64=
, LOONGARCH64 or EBC, which overrides target.txt's TARGET_ARCH definition. =
To specify more archs, please repeat this option.")=0D
Parser.add_option("-p", "--platform", action=3D"callback", type=3D=
"string", dest=3D"PlatformFile", callback=3DSingleCheckCallback,=0D
help=3D"Build the platform specified by the DSC file name argu=
ment, overriding target.txt's ACTIVE_PLATFORM definition.")=0D
Parser.add_option("-m", "--module", action=3D"callback", type=3D"s=
tring", dest=3D"ModuleFile", callback=3DSingleCheckCallback,=0D
--=20
2.27.0


[PATCH v2 16/34] BaseTools: BaseTools changes for LoongArch platform.

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

BaseTools define template files changes for building EDK2 LoongArch
platform.

Cc: Bob Feng <bob.c.feng@...>
Cc: Liming Gao <gaoliming@...>
Cc: Yuwei Chen <yuwei.chen@...>

Signed-off-by: Chao Li <lichao@...>
Co-authored-by: Dongyan Qian <qiandongyan@...>
Co-authored-by: Baoqi Zhang <zhangbaoqi@...>
---
BaseTools/Conf/tools_def.template | 54 +++++++++++++++++++++++++++----
1 file changed, 48 insertions(+), 6 deletions(-)

diff --git a/BaseTools/Conf/tools_def.template b/BaseTools/Conf/tools_def.t=
emplate
index 5ed19810b7..9ceadeaa59 100755
--- a/BaseTools/Conf/tools_def.template
+++ b/BaseTools/Conf/tools_def.template
@@ -4,6 +4,7 @@
# Portions copyright (c) 2011 - 2019, ARM Ltd. All rights reserved.<BR>=0D
# Copyright (c) 2015, Hewlett-Packard Development Company, L.P.<BR>=0D
# (C) Copyright 2020, Hewlett Packard Enterprise Development LP<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights=
reserved.<BR>=0D
# Copyright (c) Microsoft Corporation=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
@@ -267,7 +268,7 @@ DEFINE DTC_BIN =3D ENV(DTC_PREFIX)dtc
# Intel(r) ACPI Compiler from=0D
# https://acpica.org/downloads=0D
# GCC5 -Linux,Windows- Requires:=0D
-# GCC 5 with LTO support, targeting x86_64-lin=
ux-gnu, aarch64-linux-gnu, arm-linux-gnueabi or riscv64-linux-gnu=0D
+# GCC 5 with LTO support, targeting x86_64-lin=
ux-gnu, aarch64-linux-gnu, arm-linux-gnueabi, riscv64-linux-gnu or loongarc=
h64-linux-gnu=0D
# Optional:=0D
# Required to build platforms or ACPI tables:=
=0D
# Intel(r) ACPI Compiler from=0D
@@ -1852,6 +1853,7 @@ DEFINE GCC_ALL_CC_FLAGS =3D -g -Os -fshort=
-wchar -fno-builtin -fno-stri
DEFINE GCC_IA32_CC_FLAGS =3D DEF(GCC_ALL_CC_FLAGS) -m32 -malign-=
double -freorder-blocks -freorder-blocks-and-partition -O2 -mno-stack-arg-p=
robe=0D
DEFINE GCC_X64_CC_FLAGS =3D DEF(GCC_ALL_CC_FLAGS) -mno-red-zone=
-Wno-address -mno-stack-arg-probe=0D
DEFINE GCC_ARM_CC_FLAGS =3D DEF(GCC_ALL_CC_FLAGS) -mlittle-endi=
an -mabi=3Daapcs -fno-short-enums -funsigned-char -ffunction-sections -fdat=
a-sections -fomit-frame-pointer -Wno-address -mthumb -mfloat-abi=3Dsoft -fn=
o-pic -fno-pie=0D
+DEFINE GCC_LOONGARCH64_CC_FLAGS =3D DEF(GCC_ALL_CC_FLAGS) -mabi=3Dlp64d=
-fno-asynchronous-unwind-tables -fno-plt -Wno-address -fno-short-enums -fs=
igned-char -ffunction-sections -fdata-sections=0D
DEFINE GCC_ARM_CC_XIPFLAGS =3D -mno-unaligned-access=0D
DEFINE GCC_AARCH64_CC_FLAGS =3D DEF(GCC_ALL_CC_FLAGS) -mlittle-endi=
an -fno-short-enums -fverbose-asm -funsigned-char -ffunction-sections -fda=
ta-sections -Wno-address -fno-asynchronous-unwind-tables -fno-unwind-tables=
-fno-pic -fno-pie -ffixed-x18=0D
DEFINE GCC_AARCH64_CC_XIPFLAGS =3D -mstrict-align -mgeneral-regs-only=
=0D
@@ -1859,12 +1861,15 @@ DEFINE GCC_DLINK_FLAGS_COMMON =3D -nostdlib --=
pie
DEFINE GCC_DLINK2_FLAGS_COMMON =3D -Wl,--script=3D$(EDK_TOOLS_PATH)/Sc=
ripts/GccBase.lds=0D
DEFINE GCC_IA32_X64_DLINK_COMMON =3D DEF(GCC_DLINK_FLAGS_COMMON) --gc-se=
ctions=0D
DEFINE GCC_ARM_AARCH64_DLINK_COMMON=3D -Wl,--emit-relocs -nostdlib -Wl,--g=
c-sections -u $(IMAGE_ENTRY_POINT) -Wl,-e,$(IMAGE_ENTRY_POINT),-Map,$(DEST_=
DIR_DEBUG)/$(BASE_NAME).map=0D
+DEFINE GCC_LOONGARCH64_DLINK_COMMON=3D -Wl,--emit-relocs -nostdlib -Wl,--g=
c-sections -u $(IMAGE_ENTRY_POINT) -Wl,-e,$(IMAGE_ENTRY_POINT),-Map,$(DEST_=
DIR_DEBUG)/$(BASE_NAME).map=0D
DEFINE GCC_ARM_DLINK_FLAGS =3D DEF(GCC_ARM_AARCH64_DLINK_COMMON) -=
z common-page-size=3D0x20 -Wl,--pic-veneer=0D
DEFINE GCC_AARCH64_DLINK_FLAGS =3D DEF(GCC_ARM_AARCH64_DLINK_COMMON) -=
z common-page-size=3D0x20=0D
+DEFINE GCC_LOONGARCH64_DLINK_FLAGS =3D DEF(GCC_LOONGARCH64_DLINK_COMMON) -=
z common-page-size=3D0x20=0D
DEFINE GCC_ARM_AARCH64_ASLDLINK_FLAGS =3D -Wl,--defsym=3DPECOFF_HEADER_SIZ=
E=3D0 DEF(GCC_DLINK2_FLAGS_COMMON) -z common-page-size=3D0x20=0D
DEFINE GCC_IA32_X64_ASLDLINK_FLAGS =3D DEF(GCC_IA32_X64_DLINK_COMMON) --en=
try _ReferenceAcpiTable -u $(IMAGE_ENTRY_POINT)=0D
DEFINE GCC_ARM_ASLDLINK_FLAGS =3D DEF(GCC_ARM_DLINK_FLAGS) -Wl,--entr=
y,ReferenceAcpiTable -u $(IMAGE_ENTRY_POINT) DEF(GCC_ARM_AARCH64_ASLDLINK_F=
LAGS)=0D
DEFINE GCC_AARCH64_ASLDLINK_FLAGS =3D DEF(GCC_AARCH64_DLINK_FLAGS) -Wl,--=
entry,ReferenceAcpiTable -u $(IMAGE_ENTRY_POINT) DEF(GCC_ARM_AARCH64_ASLDLI=
NK_FLAGS)=0D
+DEFINE GCC_LOONGARCH64_ASLDLINK_FLAGS =3D DEF(GCC_LOONGARCH64_DLINK_FLAGS)=
--entry ReferenceAcpiTable -u $(IMAGE_ENTRY_POINT)=0D
DEFINE GCC_IA32_X64_DLINK_FLAGS =3D DEF(GCC_IA32_X64_DLINK_COMMON) --en=
try _$(IMAGE_ENTRY_POINT) --file-alignment 0x20 --section-alignment 0x20 -M=
ap $(DEST_DIR_DEBUG)/$(BASE_NAME).map=0D
DEFINE GCC_ASM_FLAGS =3D -c -x assembler -imacros AutoGen.h=
=0D
DEFINE GCC_PP_FLAGS =3D -E -x assembler-with-cpp -include A=
utoGen.h=0D
@@ -1873,11 +1878,12 @@ DEFINE GCC_ASLPP_FLAGS =3D -x c -E -inc=
lude AutoGen.h
DEFINE GCC_ASLCC_FLAGS =3D -x c=0D
DEFINE GCC_WINDRES_FLAGS =3D -J rc -O coff=0D
DEFINE GCC_DTCPP_FLAGS =3D -E -x assembler-with-cpp -imacros A=
utoGen.h -nostdinc -undef=0D
-DEFINE GCC_IA32_RC_FLAGS =3D -I binary -O elf32-i386 -B=
i386 --rename-section .data=3D.hii=0D
-DEFINE GCC_X64_RC_FLAGS =3D -I binary -O elf64-x86-64 -B=
i386 --rename-section .data=3D.hii=0D
-DEFINE GCC_ARM_RC_FLAGS =3D -I binary -O elf32-littlearm -B=
arm --rename-section .data=3D.hii=0D
-DEFINE GCC_AARCH64_RC_FLAGS =3D -I binary -O elf64-littleaarch64 -B=
aarch64 --rename-section .data=3D.hii=0D
-DEFINE GCC_RISCV64_RC_FLAGS =3D -I binary -O elf64-littleriscv -B=
riscv --rename-section .data=3D.hii=0D
+DEFINE GCC_IA32_RC_FLAGS =3D -I binary -O elf32-i386 -B=
i386 --rename-section .data=3D.hii=0D
+DEFINE GCC_X64_RC_FLAGS =3D -I binary -O elf64-x86-64 -B=
i386 --rename-section .data=3D.hii=0D
+DEFINE GCC_ARM_RC_FLAGS =3D -I binary -O elf32-littlearm -B=
arm --rename-section .data=3D.hii=0D
+DEFINE GCC_AARCH64_RC_FLAGS =3D -I binary -O elf64-littleaarch64 -B=
aarch64 --rename-section .data=3D.hii=0D
+DEFINE GCC_RISCV64_RC_FLAGS =3D -I binary -O elf64-littleriscv -B=
riscv --rename-section .data=3D.hii=0D
+DEFINE GCC_LOONGARCH64_RC_FLAGS =3D -I binary -O elf64-loongarch -B=
loongarch64 --rename-section .data=3D.hii=0D
=0D
# GCC Build Flag for included header file list generation=0D
DEFINE GCC_DEPS_FLAGS =3D -MMD -MF $@.deps=0D
@@ -1967,6 +1973,14 @@ DEFINE GCC5_RISCV64_CC_FLAGS =3D DEF(G=
CC5_RISCV_ALL_CC_FLAGS) DEF(GC
DEFINE GCC5_RISCV64_DLINK_FLAGS =3D DEF(GCC5_RISCV_ALL_DLINK_FL=
AGS) -Wl,-melf64lriscv,--oformat=3Delf64-littleriscv,--no-relax=0D
DEFINE GCC5_RISCV64_DLINK2_FLAGS =3D DEF(GCC5_RISCV_ALL_DLINK2_F=
LAGS)=0D
DEFINE GCC5_RISCV64_ASM_FLAGS =3D DEF(GCC5_RISCV_ALL_ASM_FLAG=
S) -march=3DDEF(GCC5_RISCV64_ARCH) -mcmodel=3Dmedany -mabi=3Dlp64=0D
+=0D
+DEFINE GCC5_LOONGARCH64_CC_FLAGS =3D DEF(GCC_LOONGARCH64_CC_FLAG=
S) -march=3Dloongarch64 -mno-memcpy -Werror -Wno-maybe-uninitialized -Wno-s=
tringop-overflow -Wno-pointer-to-int-cast -no-pie -fno-stack-protector -mno=
-explicit-relocs=0D
+DEFINE GCC5_LOONGARCH64_DLINK_FLAGS =3D DEF(GCC_LOONGARCH64_DLINK_F=
LAGS)=0D
+DEFINE GCC5_LOONGARCH64_DLINK2_FLAGS =3D DEF(GCC_DLINK2_FLAGS_COMMON=
) -Wl,--defsym=3DPECOFF_HEADER_SIZE=3D0x228=0D
+DEFINE GCC5_LOONGARCH64_ASLDLINK_FLAGS =3D DEF(GCC_LOONGARCH64_ASLDLIN=
K_FLAGS)=0D
+DEFINE GCC5_LOONGARCH64_ASM_FLAGS =3D -x assembler-with-cpp -mabi=
=3Dlp64d -march=3Dloongarch64 -fno-builtin -c -Wall -mno-explicit-relocs=0D
+DEFINE GCC5_LOONGARCH64_PP_FLAGS =3D -mabi=3Dlp64d -march=3Dloon=
garch64 DEF(GCC_PP_FLAGS)=0D
+=0D
DEFINE GCC_PP_FLAGS =3D -E -x assembler-with-cpp -i=
nclude AutoGen.h DEF(GCC5_RISCV_OPENSBI_TYPES)=0D
=0D
##########################################################################=
##########=0D
@@ -2445,6 +2459,34 @@ RELEASE_GCC5_AARCH64_DLINK_XIPFLAGS =3D -z common-pa=
ge-size=3D0x20
*_GCC5_RISCV64_OBJCOPY_FLAGS =3D=0D
*_GCC5_RISCV64_DTCPP_FLAGS =3D DEF(GCC_DTCPP_FLAGS)=0D
=0D
+##################=0D
+# GCC5 LOONGARCH64 definitions=0D
+##################=0D
+*_GCC5_LOONGARCH64_OBJCOPY_PATH =3D ENV(GCC5_LOONGARCH64_PREFIX)ob=
jcopy=0D
+*_GCC5_LOONGARCH64_CC_PATH =3D ENV(GCC5_LOONGARCH64_PREFIX)gc=
c=0D
+*_GCC5_LOONGARCH64_SLINK_PATH =3D ENV(GCC5_LOONGARCH64_PREFIX)gc=
c-ar=0D
+*_GCC5_LOONGARCH64_DLINK_PATH =3D ENV(GCC5_LOONGARCH64_PREFIX)gc=
c=0D
+*_GCC5_LOONGARCH64_ASLDLINK_PATH =3D ENV(GCC5_LOONGARCH64_PREFIX)gc=
c=0D
+*_GCC5_LOONGARCH64_ASM_PATH =3D ENV(GCC5_LOONGARCH64_PREFIX)gc=
c=0D
+*_GCC5_LOONGARCH64_PP_PATH =3D ENV(GCC5_LOONGARCH64_PREFIX)gc=
c=0D
+*_GCC5_LOONGARCH64_VFRPP_PATH =3D ENV(GCC5_LOONGARCH64_PREFIX)gc=
c=0D
+*_GCC5_LOONGARCH64_ASLCC_PATH =3D ENV(GCC5_LOONGARCH64_PREFIX)gc=
c=0D
+*_GCC5_LOONGARCH64_ASLPP_PATH =3D ENV(GCC5_LOONGARCH64_PREFIX)gc=
c=0D
+*_GCC5_LOONGARCH64_RC_PATH =3D ENV(GCC5_LOONGARCH64_PREFIX)ob=
jcopy=0D
+=0D
+*_GCC5_LOONGARCH64_ASLCC_FLAGS =3D DEF(GCC_ASLCC_FLAGS)=0D
+*_GCC5_LOONGARCH64_ASLDLINK_FLAGS =3D DEF(GCC5_LOONGARCH64_ASLDLINK_=
FLAGS)=0D
+*_GCC5_LOONGARCH64_ASM_FLAGS =3D DEF(GCC5_LOONGARCH64_ASM_FLAGS=
)=0D
+*_GCC5_LOONGARCH64_DLINK_FLAGS =3D DEF(GCC5_LOONGARCH64_DLINK_FLA=
GS)=0D
+*_GCC5_LOONGARCH64_DLINK2_FLAGS =3D DEF(GCC5_LOONGARCH64_DLINK2_FL=
AGS)=0D
+*_GCC5_LOONGARCH64_RC_FLAGS =3D DEF(GCC_LOONGARCH64_RC_FLAGS)=
=0D
+*_GCC5_LOONGARCH64_OBJCOPY_FLAGS =3D=0D
+*_GCC5_LOONGARCH64_NASM_FLAGS =3D -f elf32=0D
+*_GCC5_LOONGARCH64_PP_FLAGS =3D DEF(GCC5_LOONGARCH64_PP_FLAGS)=
=0D
+=0D
+DEBUG_GCC5_LOONGARCH64_CC_FLAGS =3D DEF(GCC5_LOONGARCH64_CC_FLAGS)=
=0D
+RELEASE_GCC5_LOONGARCH64_CC_FLAGS =3D DEF(GCC5_LOONGARCH64_CC_FLAGS)=
-Wno-unused-but-set-variable -Wno-unused-variable=0D
+=0D
##########################################################################=
##########=0D
#=0D
# CLANG35 - This configuration is used to compile under Linux to produce=
=0D
--=20
2.27.0


[PATCH v2 15/34] BaseTools: BaseTools changes for LoongArch platform.

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

C code changes for building EDK2 LoongArch platform.

For definitions of PE/COFF and LOONGARCH relocation types, see the
"Machine Types" and "Basic Relocation Types" sections of this URL for
LOONGARCH values:
https://docs.microsoft.com/en-us/windows/win32/debug/pe-format

Cc: Bob Feng <bob.c.feng@...>
Cc: Liming Gao <gaoliming@...>
Cc: Yuwei Chen <yuwei.chen@...>

Signed-off-by: Chao Li <lichao@...>
Co-authored-by: Dongyan Qian <qiandongyan@...>
Co-authored-by: Baoqi Zhang <zhangbaoqi@...>
Co-authored-by: Yang Zhou <zhouyang@...>
Co-authored-by: Xiaotian Wu <wuxiaotian@...>
---
BaseTools/Source/C/Common/BasePeCoff.c | 15 +-
BaseTools/Source/C/Common/PeCoffLoaderEx.c | 79 +++++
BaseTools/Source/C/GenFv/GenFvInternalLib.c | 125 +++++++-
BaseTools/Source/C/GenFw/Elf64Convert.c | 293 +++++++++++++++++-
BaseTools/Source/C/GenFw/elf_common.h | 94 ++++++
.../C/Include/IndustryStandard/PeImage.h | 57 ++--
BaseTools/Source/C/Makefiles/header.makefile | 6 +
7 files changed, 636 insertions(+), 33 deletions(-)

diff --git a/BaseTools/Source/C/Common/BasePeCoff.c b/BaseTools/Source/C/Co=
mmon/BasePeCoff.c
index 62fbb2985c..30400d1341 100644
--- a/BaseTools/Source/C/Common/BasePeCoff.c
+++ b/BaseTools/Source/C/Common/BasePeCoff.c
@@ -5,6 +5,7 @@
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>=0D
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>=0D
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al=
l rights reserved.<BR>=0D
+Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All =
rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
**/=0D
@@ -68,6 +69,14 @@ PeCoffLoaderRelocateRiscVImage (
IN UINT64 Adjust=0D
);=0D
=0D
+RETURN_STATUS=0D
+PeCoffLoaderRelocateLoongArch64Image (=0D
+ IN UINT16 *Reloc,=0D
+ IN OUT CHAR8 *Fixup,=0D
+ IN OUT CHAR8 **FixupData,=0D
+ IN UINT64 Adjust=0D
+ );=0D
+=0D
STATIC=0D
RETURN_STATUS=0D
PeCoffLoaderGetPeHeader (=0D
@@ -184,7 +193,8 @@ Returns:
ImageContext->Machine !=3D EFI_IMAGE_MACHINE_ARMT && \=0D
ImageContext->Machine !=3D EFI_IMAGE_MACHINE_EBC && \=0D
ImageContext->Machine !=3D EFI_IMAGE_MACHINE_AARCH64 && \=0D
- ImageContext->Machine !=3D EFI_IMAGE_MACHINE_RISCV64) {=0D
+ ImageContext->Machine !=3D EFI_IMAGE_MACHINE_RISCV64 && \=0D
+ ImageContext->Machine !=3D EFI_IMAGE_MACHINE_LOONGARCH64) {=0D
if (ImageContext->Machine =3D=3D IMAGE_FILE_MACHINE_ARM) {=0D
//=0D
// There are two types of ARM images. Pure ARM and ARM/Thumb.=0D
@@ -815,6 +825,9 @@ Returns:
case EFI_IMAGE_MACHINE_RISCV64:=0D
Status =3D PeCoffLoaderRelocateRiscVImage (Reloc, Fixup, &FixupD=
ata, Adjust);=0D
break;=0D
+ case EFI_IMAGE_MACHINE_LOONGARCH64:=0D
+ Status =3D PeCoffLoaderRelocateLoongArch64Image (Reloc, Fixup, &=
FixupData, Adjust);=0D
+ break;=0D
default:=0D
Status =3D RETURN_UNSUPPORTED;=0D
break;=0D
diff --git a/BaseTools/Source/C/Common/PeCoffLoaderEx.c b/BaseTools/Source/=
C/Common/PeCoffLoaderEx.c
index 799f282970..2cc428d733 100644
--- a/BaseTools/Source/C/Common/PeCoffLoaderEx.c
+++ b/BaseTools/Source/C/Common/PeCoffLoaderEx.c
@@ -4,6 +4,7 @@ IA32 and X64 Specific relocation fixups
Copyright (c) 2004 - 2018, Intel Corporation. All rights reserved.<BR>=0D
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>=0D
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights =
reserved.<BR>=0D
+Copyright (c) 2022, Loongson Technology Corporation Limited. All rights re=
served.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
--*/=0D
@@ -332,3 +333,81 @@ PeCoffLoaderRelocateArmImage (
=0D
return RETURN_SUCCESS;=0D
}=0D
+=0D
+/**=0D
+ Performs a LoongArch specific relocation fixup.=0D
+=0D
+ @param[in] Reloc Pointer to the relocation record.=0D
+ @param[in, out] Fixup Pointer to the address to fix up.=0D
+ @param[in, out] FixupData Pointer to a buffer to log the fixups.=0D
+ @param[in] Adjust The offset to adjust the fixup.=0D
+=0D
+ @return Status code.=0D
+**/=0D
+RETURN_STATUS=0D
+PeCoffLoaderRelocateLoongArch64Image (=0D
+ IN UINT16 *Reloc,=0D
+ IN OUT CHAR8 *Fixup,=0D
+ IN OUT CHAR8 **FixupData,=0D
+ IN UINT64 Adjust=0D
+ )=0D
+{=0D
+ UINT8 RelocType;=0D
+ UINT64 Value;=0D
+ UINT64 Tmp1;=0D
+ UINT64 Tmp2;=0D
+=0D
+ RelocType =3D ((*Reloc) >> 12);=0D
+ Value =3D 0;=0D
+ Tmp1 =3D 0;=0D
+ Tmp2 =3D 0;=0D
+=0D
+ switch (RelocType) {=0D
+ case EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA:=0D
+ // The next four instructions are used to load a 64 bit address, rel=
ocate all of them=0D
+ Value =3D (*(UINT32 *)Fixup & 0x1ffffe0) << 7 | // lu12i.w 20b=
its from bit5=0D
+ (*((UINT32 *)Fixup + 1) & 0x3ffc00) >> 10; // ori 12bit=
s from bit10=0D
+ Tmp1 =3D *((UINT32 *)Fixup + 2) & 0x1ffffe0; // lu32i.d 20b=
its from bit5=0D
+ Tmp2 =3D *((UINT32 *)Fixup + 3) & 0x3ffc00; // lu52i.d 12b=
its from bit10=0D
+ Value =3D Value | (Tmp1 << 27) | (Tmp2 << 42);=0D
+ Value +=3D Adjust;=0D
+=0D
+ *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> 1=
2) & 0xfffff) << 5);=0D
+ if (*FixupData !=3D NULL) {=0D
+ *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UIN=
T32));=0D
+ *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup;=0D
+ *FixupData =3D *FixupData + sizeof (UINT32);=0D
+ }=0D
+=0D
+ Fixup +=3D sizeof (UINT32);=0D
+ *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x3ffc00) | ((Value & 0xff=
f) << 10);=0D
+ if (*FixupData !=3D NULL) {=0D
+ *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UIN=
T32));=0D
+ *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup;=0D
+ *FixupData =3D *FixupData + sizeof (UINT32);=0D
+ }=0D
+=0D
+ Fixup +=3D sizeof (UINT32);=0D
+ *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> 3=
2) & 0xfffff) << 5);=0D
+ if (*FixupData !=3D NULL) {=0D
+ *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UIN=
T32));=0D
+ *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup;=0D
+ *FixupData =3D *FixupData + sizeof (UINT32);=0D
+ }=0D
+=0D
+ Fixup +=3D sizeof (UINT32);=0D
+ *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x3ffc00) | (((Value >> 52=
) & 0xfff) << 10);=0D
+ if (*FixupData !=3D NULL) {=0D
+ *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UIN=
T32));=0D
+ *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup;=0D
+ *FixupData =3D *FixupData + sizeof (UINT32);=0D
+ }=0D
+=0D
+ break;=0D
+ default:=0D
+ Error (NULL, 0, 3000, "", "PeCoffLoaderRelocateLoongArch64Image: Fix=
up[0x%x] Adjust[0x%llx] *Reloc[0x%x], type[0x%x].", *(UINT32 *)Fixup, Adjus=
t, *Reloc, RelocType);=0D
+ return RETURN_UNSUPPORTED;=0D
+ }=0D
+=0D
+ return RETURN_SUCCESS;=0D
+}=0D
diff --git a/BaseTools/Source/C/GenFv/GenFvInternalLib.c b/BaseTools/Source=
/C/GenFv/GenFvInternalLib.c
index d650a527a5..575b99b6ad 100644
--- a/BaseTools/Source/C/GenFv/GenFvInternalLib.c
+++ b/BaseTools/Source/C/GenFv/GenFvInternalLib.c
@@ -5,6 +5,7 @@ Copyright (c) 2004 - 2018, Intel Corporation. All rights re=
served.<BR>
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>=0D
Portions Copyright (c) 2016 HP Development Company, L.P.<BR>=0D
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al=
l rights reserved.<BR>=0D
+Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All =
rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
**/=0D
@@ -57,6 +58,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
=0D
BOOLEAN mArm =3D FALSE;=0D
BOOLEAN mRiscV =3D FALSE;=0D
+BOOLEAN mLoongArch =3D FALSE;=0D
STATIC UINT32 MaxFfsAlignment =3D 0;=0D
BOOLEAN VtfFileFlag =3D FALSE;=0D
=0D
@@ -2416,6 +2418,98 @@ Returns:
return EFI_SUCCESS;=0D
}=0D
=0D
+EFI_STATUS=0D
+UpdateLoongArchResetVectorIfNeeded (=0D
+ IN MEMORY_FILE *FvImage,=0D
+ IN FV_INFO *FvInfo=0D
+ )=0D
+/*++=0D
+=0D
+Routine Description:=0D
+ This parses the FV looking for SEC and patches that address into the=0D
+ beginning of the FV header.=0D
+=0D
+ For LoongArch ISA, the reset vector is at 0x1c000000.=0D
+=0D
+ We relocate it to SecCoreEntry and copy the ResetVector code to the=0D
+ beginning of the FV.=0D
+=0D
+Arguments:=0D
+ FvImage Memory file for the FV memory image=0D
+ FvInfo Information read from INF file.=0D
+=0D
+Returns:=0D
+=0D
+ EFI_SUCCESS Function Completed successfully.=0D
+ EFI_ABORTED Error encountered.=0D
+ EFI_INVALID_PARAMETER A required parameter was NULL.=0D
+ EFI_NOT_FOUND PEI Core file not found.=0D
+=0D
+--*/=0D
+{=0D
+ EFI_STATUS Status;=0D
+ EFI_FILE_SECTION_POINTER SecPe32;=0D
+ BOOLEAN UpdateVectorSec =3D FALSE;=0D
+ UINT16 MachineType =3D 0;=0D
+ EFI_PHYSICAL_ADDRESS SecCoreEntryAddress =3D 0;=0D
+=0D
+ //=0D
+ // Verify input parameters=0D
+ //=0D
+ if (FvImage =3D=3D NULL || FvInfo =3D=3D NULL) {=0D
+ return EFI_INVALID_PARAMETER;=0D
+ }=0D
+=0D
+ //=0D
+ // Locate an SEC Core instance and if found extract the machine type and=
entry point address=0D
+ //=0D
+ Status =3D FindCorePeSection(FvImage->FileImage, FvInfo->Size, EFI_FV_FI=
LETYPE_SECURITY_CORE, &SecPe32);=0D
+ if (!EFI_ERROR(Status)) {=0D
+=0D
+ Status =3D GetCoreMachineType(SecPe32, &MachineType);=0D
+ if (EFI_ERROR(Status)) {=0D
+ Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 machine type=
for SEC Core.");=0D
+ return EFI_ABORTED;=0D
+ }=0D
+=0D
+ Status =3D GetCoreEntryPointAddress(FvImage->FileImage, FvInfo, SecPe3=
2, &SecCoreEntryAddress);=0D
+ if (EFI_ERROR(Status)) {=0D
+ Error(NULL, 0, 3000, "Invalid", "Could not get the PE32 entry point =
address for SEC Core.");=0D
+ return EFI_ABORTED;=0D
+ }=0D
+=0D
+ UpdateVectorSec =3D TRUE;=0D
+ }=0D
+=0D
+ if (!UpdateVectorSec)=0D
+ return EFI_SUCCESS;=0D
+=0D
+ if (MachineType =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) {=0D
+ UINT32 ResetVector[1];=0D
+=0D
+ memset(ResetVector, 0, sizeof (ResetVector));=0D
+=0D
+ /* if we found an SEC core entry point then generate a branch instruct=
ion */=0D
+ if (UpdateVectorSec) {=0D
+ VerboseMsg("UpdateLoongArchResetVectorIfNeeded updating LOONGARCH64 =
SEC vector");=0D
+=0D
+ ResetVector[0] =3D ((SecCoreEntryAddress - FvInfo->BaseAddress) & 0x=
3FFFFFF) >> 2;=0D
+ ResetVector[0] =3D ((ResetVector[0] & 0x0FFFF) << 10) | ((ResetVecto=
r[0] >> 16) & 0x3FF);=0D
+ ResetVector[0] |=3D 0x54000000; /* bl offset */=0D
+ }=0D
+=0D
+ //=0D
+ // Copy to the beginning of the FV=0D
+ //=0D
+ memcpy(FvImage->FileImage, ResetVector, sizeof (ResetVector));=0D
+ } else {=0D
+ Error(NULL, 0, 3000, "Invalid", "Unknown machine type");=0D
+ return EFI_ABORTED;=0D
+ }=0D
+=0D
+ return EFI_SUCCESS;=0D
+}=0D
+=0D
EFI_STATUS=0D
GetPe32Info (=0D
IN UINT8 *Pe32,=0D
@@ -2509,7 +2603,7 @@ Returns:
//=0D
if ((*MachineType !=3D EFI_IMAGE_MACHINE_IA32) && (*MachineType !=3D EF=
I_IMAGE_MACHINE_X64) && (*MachineType !=3D EFI_IMAGE_MACHINE_EBC) &&=0D
(*MachineType !=3D EFI_IMAGE_MACHINE_ARMT) && (*MachineType !=3D EFI=
_IMAGE_MACHINE_AARCH64) &&=0D
- (*MachineType !=3D EFI_IMAGE_MACHINE_RISCV64)) {=0D
+ (*MachineType !=3D EFI_IMAGE_MACHINE_RISCV64) && (*MachineType !=3D =
EFI_IMAGE_MACHINE_LOONGARCH64)) {=0D
Error (NULL, 0, 3000, "Invalid", "Unrecognized machine type in the PE3=
2 file.");=0D
return EFI_UNSUPPORTED;=0D
}=0D
@@ -2953,7 +3047,7 @@ Returns:
goto Finish;=0D
}=0D
=0D
- if (!mArm && !mRiscV) {=0D
+ if (!mArm && !mRiscV && !mLoongArch) {=0D
//=0D
// Update reset vector (SALE_ENTRY for IPF)=0D
// Now for IA32 and IA64 platform, the fv which has bsf file must ha=
ve the=0D
@@ -3004,6 +3098,19 @@ Returns:
FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, FvHea=
der->HeaderLength / sizeof (UINT16));=0D
}=0D
=0D
+ if (mLoongArch) {=0D
+ Status =3D UpdateLoongArchResetVectorIfNeeded (&FvImageMemoryFile, &mF=
vDataInfo);=0D
+ if (EFI_ERROR (Status)) {=0D
+ Error (NULL, 0, 3000, "Invalid", "Could not update the reset vector.=
");=0D
+ goto Finish;=0D
+ }=0D
+ //=0D
+ // Update Checksum for FvHeader=0D
+ //=0D
+ FvHeader->Checksum =3D 0;=0D
+ FvHeader->Checksum =3D CalculateChecksum16 ((UINT16 *) FvHeader, FvHea=
der->HeaderLength / sizeof (UINT16));=0D
+ }=0D
+=0D
//=0D
// Update FV Alignment attribute to the largest alignment of all the FFS=
files in the FV=0D
//=0D
@@ -3450,6 +3557,12 @@ Returns:
VerboseMsg("Located ARM/AArch64 SEC/PEI core in child FV");=0D
mArm =3D TRUE;=0D
}=0D
+=0D
+ // Machine type is LOONGARCH64, set a flag so LoongArch64 reset vect=
or processed.=0D
+ if ((MachineType =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64)) {=0D
+ VerboseMsg("Located LoongArch64 SEC core in child FV");=0D
+ mLoongArch =3D TRUE;=0D
+ }=0D
}=0D
=0D
//=0D
@@ -3608,6 +3721,10 @@ Returns:
mRiscV =3D TRUE;=0D
}=0D
=0D
+ if ( (ImageContext.Machine =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) ) {=0D
+ mLoongArch =3D TRUE;=0D
+ }=0D
+=0D
//=0D
// Keep Image Context for PE image in FV=0D
//=0D
@@ -3885,6 +4002,10 @@ Returns:
mArm =3D TRUE;=0D
}=0D
=0D
+ if ( (ImageContext.Machine =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64) ) {=0D
+ mLoongArch =3D TRUE;=0D
+ }=0D
+=0D
//=0D
// Keep Image Context for TE image in FV=0D
//=0D
diff --git a/BaseTools/Source/C/GenFw/Elf64Convert.c b/BaseTools/Source/C/G=
enFw/Elf64Convert.c
index ca3c8f8bee..ede2f0ef90 100644
--- a/BaseTools/Source/C/GenFw/Elf64Convert.c
+++ b/BaseTools/Source/C/GenFw/Elf64Convert.c
@@ -4,6 +4,7 @@ Elf64 convert solution
Copyright (c) 2010 - 2021, Intel Corporation. All rights reserved.<BR>=0D
Portions copyright (c) 2013-2022, ARM Ltd. All rights reserved.<BR>=0D
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al=
l rights reserved.<BR>=0D
+Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All =
rights reserved.<BR>=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
@@ -177,7 +178,7 @@ InitializeElf64 (
Error (NULL, 0, 3000, "Unsupported", "ELF e_type not ET_EXEC or ET_DYN=
");=0D
return FALSE;=0D
}=0D
- if (!((mEhdr->e_machine =3D=3D EM_X86_64) || (mEhdr->e_machine =3D=3D EM=
_AARCH64) || (mEhdr->e_machine =3D=3D EM_RISCV64))) {=0D
+ if (!((mEhdr->e_machine =3D=3D EM_X86_64) || (mEhdr->e_machine =3D=3D EM=
_AARCH64) || (mEhdr->e_machine =3D=3D EM_RISCV64) || (mEhdr->e_machine =3D=
=3D EM_LOONGARCH))) {=0D
Warning (NULL, 0, 3000, "Unsupported", "ELF e_machine is not Elf64 mac=
hine.");=0D
}=0D
if (mEhdr->e_version !=3D EV_CURRENT) {=0D
@@ -799,6 +800,7 @@ ScanSections64 (
case EM_X86_64:=0D
case EM_AARCH64:=0D
case EM_RISCV64:=0D
+ case EM_LOONGARCH:=0D
mCoffOffset +=3D sizeof (EFI_IMAGE_NT_HEADERS64);=0D
break;=0D
default:=0D
@@ -1088,6 +1090,10 @@ ScanSections64 (
NtHdr->Pe32Plus.FileHeader.Machine =3D EFI_IMAGE_MACHINE_RISCV64;=0D
NtHdr->Pe32Plus.OptionalHeader.Magic =3D EFI_IMAGE_NT_OPTIONAL_HDR64_M=
AGIC;=0D
break;=0D
+ case EM_LOONGARCH:=0D
+ NtHdr->Pe32Plus.FileHeader.Machine =3D EFI_IMAGE_MACHINE_LOONGARCH64;=
=0D
+ NtHdr->Pe32Plus.OptionalHeader.Magic =3D EFI_IMAGE_NT_OPTIONAL_HDR64_M=
AGIC;=0D
+ break;=0D
=0D
default:=0D
VerboseMsg ("%s unknown e_machine type. Assume X64", (UINTN)mEhdr->e_m=
achine);=0D
@@ -1333,10 +1339,10 @@ WriteSections64 (
}=0D
=0D
//=0D
- // Skip error on EM_RISCV64 becasue no symble name is built=0D
- // from RISC-V toolchain.=0D
+ // Skip error on EM_RISCV64 and EM_LOONGARCH because no symbol n=
ame is built=0D
+ // from RISC-V and LoongArch toolchain.=0D
//=0D
- if (mEhdr->e_machine !=3D EM_RISCV64) {=0D
+ if ((mEhdr->e_machine !=3D EM_RISCV64) && (mEhdr->e_machine !=3D=
EM_LOONGARCH)) {=0D
Error (NULL, 0, 3000, "Invalid",=0D
"%s: Bad definition for symbol '%s'@%#llx or unsupporte=
d symbol type. "=0D
"For example, absolute and undefined symbols are not su=
pported.",=0D
@@ -1618,6 +1624,178 @@ WriteSections64 (
// Write section for RISC-V 64 architecture.=0D
//=0D
WriteSectionRiscV64 (Rel, Targ, SymShdr, Sym);=0D
+ } else if (mEhdr->e_machine =3D=3D EM_LOONGARCH) {=0D
+ switch (ELF_R_TYPE(Rel->r_info)) {=0D
+ INT64 Offset;=0D
+ INT32 Lo, Hi;=0D
+=0D
+ case R_LARCH_SOP_PUSH_ABSOLUTE:=0D
+ //=0D
+ // Absolute relocation.=0D
+ //=0D
+ *(UINT64 *)Targ =3D *(UINT64 *)Targ - SymShdr->sh_addr + mCoff=
SectionsOffset[Sym->st_shndx];=0D
+ break;=0D
+=0D
+ case R_LARCH_MARK_LA:=0D
+ case R_LARCH_64:=0D
+ case R_LARCH_NONE:=0D
+ case R_LARCH_32:=0D
+ case R_LARCH_RELATIVE:=0D
+ case R_LARCH_COPY:=0D
+ case R_LARCH_JUMP_SLOT:=0D
+ case R_LARCH_TLS_DTPMOD32:=0D
+ case R_LARCH_TLS_DTPMOD64:=0D
+ case R_LARCH_TLS_DTPREL32:=0D
+ case R_LARCH_TLS_DTPREL64:=0D
+ case R_LARCH_TLS_TPREL32:=0D
+ case R_LARCH_TLS_TPREL64:=0D
+ case R_LARCH_IRELATIVE:=0D
+ case R_LARCH_MARK_PCREL:=0D
+ case R_LARCH_SOP_PUSH_PCREL:=0D
+ case R_LARCH_SOP_PUSH_DUP:=0D
+ case R_LARCH_SOP_PUSH_GPREL:=0D
+ case R_LARCH_SOP_PUSH_TLS_TPREL:=0D
+ case R_LARCH_SOP_PUSH_TLS_GOT:=0D
+ case R_LARCH_SOP_PUSH_TLS_GD:=0D
+ case R_LARCH_SOP_PUSH_PLT_PCREL:=0D
+ case R_LARCH_SOP_ASSERT:=0D
+ case R_LARCH_SOP_NOT:=0D
+ case R_LARCH_SOP_SUB:=0D
+ case R_LARCH_SOP_SL:=0D
+ case R_LARCH_SOP_SR:=0D
+ case R_LARCH_SOP_ADD:=0D
+ case R_LARCH_SOP_AND:=0D
+ case R_LARCH_SOP_IF_ELSE:=0D
+ case R_LARCH_SOP_POP_32_S_10_5:=0D
+ case R_LARCH_SOP_POP_32_U_10_12:=0D
+ case R_LARCH_SOP_POP_32_S_10_12:=0D
+ case R_LARCH_SOP_POP_32_S_10_16:=0D
+ case R_LARCH_SOP_POP_32_S_10_16_S2:=0D
+ case R_LARCH_SOP_POP_32_S_5_20:=0D
+ case R_LARCH_SOP_POP_32_S_0_5_10_16_S2:=0D
+ case R_LARCH_SOP_POP_32_S_0_10_10_16_S2:=0D
+ case R_LARCH_SOP_POP_32_U:=0D
+ case R_LARCH_ADD8:=0D
+ case R_LARCH_ADD16:=0D
+ case R_LARCH_ADD24:=0D
+ case R_LARCH_ADD32:=0D
+ case R_LARCH_ADD64:=0D
+ case R_LARCH_SUB8:=0D
+ case R_LARCH_SUB16:=0D
+ case R_LARCH_SUB24:=0D
+ case R_LARCH_SUB32:=0D
+ case R_LARCH_SUB64:=0D
+ case R_LARCH_GNU_VTINHERIT:=0D
+ case R_LARCH_GNU_VTENTRY:=0D
+ case R_LARCH_B16:=0D
+ case R_LARCH_B21:=0D
+ case R_LARCH_B26:=0D
+ case R_LARCH_ABS_HI20:=0D
+ case R_LARCH_ABS_LO12:=0D
+ case R_LARCH_ABS64_LO20:=0D
+ case R_LARCH_ABS64_HI12:=0D
+ case R_LARCH_PCALA_LO12:=0D
+ case R_LARCH_PCALA64_LO20:=0D
+ case R_LARCH_PCALA64_HI12:=0D
+ case R_LARCH_GOT_PC_LO12:=0D
+ case R_LARCH_GOT64_PC_LO20:=0D
+ case R_LARCH_GOT64_PC_HI12:=0D
+ case R_LARCH_GOT64_HI20:=0D
+ case R_LARCH_GOT64_LO12:=0D
+ case R_LARCH_GOT64_LO20:=0D
+ case R_LARCH_GOT64_HI12:=0D
+ case R_LARCH_TLS_LE_HI20:=0D
+ case R_LARCH_TLS_LE_LO12:=0D
+ case R_LARCH_TLS_LE64_LO20:=0D
+ case R_LARCH_TLS_LE64_HI12:=0D
+ case R_LARCH_TLS_IE_PC_HI20:=0D
+ case R_LARCH_TLS_IE_PC_LO12:=0D
+ case R_LARCH_TLS_IE64_PC_LO20:=0D
+ case R_LARCH_TLS_IE64_PC_HI12:=0D
+ case R_LARCH_TLS_IE64_HI20:=0D
+ case R_LARCH_TLS_IE64_LO12:=0D
+ case R_LARCH_TLS_IE64_LO20:=0D
+ case R_LARCH_TLS_IE64_HI12:=0D
+ case R_LARCH_TLS_LD_PC_HI20:=0D
+ case R_LARCH_TLS_LD64_HI20:=0D
+ case R_LARCH_TLS_GD_PC_HI20:=0D
+ case R_LARCH_TLS_GD64_HI20:=0D
+ case R_LARCH_RELAX:=0D
+ //=0D
+ // These types are not used or do not require fixup.=0D
+ //=0D
+ break;=0D
+=0D
+ case R_LARCH_GOT_PC_HI20:=0D
+ Offset =3D Sym->st_value - (UINTN)(Targ - mCoffFile);=0D
+ if (Offset < 0) {=0D
+ Offset =3D (UINTN)(Targ - mCoffFile) - Sym->st_value;=0D
+ Hi =3D (Offset / 0x1000) << 12;=0D
+ Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20;=0D
+ if ((Lo < 0) && (Lo > -2048)) {=0D
+ Hi +=3D 0x1000;=0D
+ Lo =3D ~(0x1000 - Lo) + 1;=0D
+ }=0D
+ Hi =3D ~Hi + 1;=0D
+ Lo =3D ~Lo + 1;=0D
+ } else {=0D
+ Hi =3D (Offset / 0x1000) << 12;=0D
+ Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20;=0D
+ if (Lo < 0) {=0D
+ Hi +=3D 0x1000;=0D
+ Lo =3D ~(0x1000 - Lo) + 1;=0D
+ }=0D
+ }=0D
+ // Re-encode the offset as an PCADD.D + ADDI.D(Convert LD.D) i=
nstruction=0D
+ *(UINT32 *)Targ &=3D 0x1f;=0D
+ *(UINT32 *)Targ |=3D 0x1c000000;=0D
+ *(UINT32 *)Targ |=3D (((Hi >> 12) & 0xfffff) << 5);=0D
+ *(UINT32 *)(Targ + 4) &=3D 0x3ff;=0D
+ *(UINT32 *)(Targ + 4) |=3D 0x2c00000 | ((Lo & 0xfff) << 10);=0D
+ break;=0D
+=0D
+ //=0D
+ // Attempt to convert instruction.=0D
+ //=0D
+ case R_LARCH_PCALA_HI20:=0D
+ // Decode the PCALAU12I + ADDI.D instruction=0D
+ Offset =3D ((INT32)((*(UINT32 *)Targ & 0x1ffffe0) << 7));=0D
+ Offset +=3D ((INT32)((*(UINT32 *)(Targ + 4) & 0x3ffc00) << 10)=
>> 20);=0D
+ //=0D
+ // PCALA offset is relative to the previous page boundary,=0D
+ // whereas PCADD offset is relative to the instruction itself.=
=0D
+ // So fix up the offset so it points to the page containing=0D
+ // the symbol.=0D
+ //=0D
+ Offset -=3D (UINTN)(Targ - mCoffFile) & 0xfff;=0D
+ if (Offset < 0) {=0D
+ Offset =3D -Offset;=0D
+ Hi =3D (Offset / 0x1000) << 12;=0D
+ Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20;=0D
+ if ((Lo < 0) && (Lo > -2048)) {=0D
+ Hi +=3D 0x1000;=0D
+ Lo =3D ~(0x1000 - Lo) + 1;=0D
+ }=0D
+ Hi =3D ~Hi + 1;=0D
+ Lo =3D ~Lo + 1;=0D
+ } else {=0D
+ Hi =3D (Offset / 0x1000) << 12;=0D
+ Lo =3D (INT32)((Offset & 0xfff) << 20) >> 20;=0D
+ if (Lo < 0) {=0D
+ Hi +=3D 0x1000;=0D
+ Lo =3D ~(0x1000 - Lo) + 1;=0D
+ }=0D
+ }=0D
+ // Re-encode the offset as an PCADD.D + ADDI.D instruction=0D
+ *(UINT32 *)Targ &=3D 0x1f;=0D
+ *(UINT32 *)Targ |=3D 0x1c000000;=0D
+ *(UINT32 *)Targ |=3D (((Hi >> 12) & 0xfffff) << 5);=0D
+ *(UINT32 *)(Targ + 4) &=3D 0xffc003ff;=0D
+ *(UINT32 *)(Targ + 4) |=3D (Lo & 0xfff) << 10;=0D
+ break;=0D
+ default:=0D
+ Error (NULL, 0, 3000, "Invalid", "WriteSections64(): %s unsupp=
orted ELF EM_LOONGARCH relocation 0x%x.", mInImageName, (unsigned) ELF64_R_=
TYPE(Rel->r_info));=0D
+ }=0D
} else {=0D
Error (NULL, 0, 3000, "Invalid", "Not a supported machine type")=
;=0D
}=0D
@@ -1850,6 +2028,113 @@ WriteRelocations64 (
default:=0D
Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): %s u=
nsupported ELF EM_RISCV64 relocation 0x%x.", mInImageName, (unsigned) ELF_R=
_TYPE(Rel->r_info));=0D
}=0D
+ } else if (mEhdr->e_machine =3D=3D EM_LOONGARCH) {=0D
+ switch (ELF_R_TYPE(Rel->r_info)) {=0D
+ case R_LARCH_MARK_LA:=0D
+ CoffAddFixup(=0D
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]=
=0D
+ + (Rel->r_offset - SecShdr->sh_addr)),=0D
+ EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA);=0D
+ break;=0D
+ case R_LARCH_64:=0D
+ CoffAddFixup(=0D
+ (UINT32) ((UINT64) mCoffSectionsOffset[RelShdr->sh_info]=
=0D
+ + (Rel->r_offset - SecShdr->sh_addr)),=0D
+ EFI_IMAGE_REL_BASED_DIR64);=0D
+ break;=0D
+ case R_LARCH_NONE:=0D
+ case R_LARCH_32:=0D
+ case R_LARCH_RELATIVE:=0D
+ case R_LARCH_COPY:=0D
+ case R_LARCH_JUMP_SLOT:=0D
+ case R_LARCH_TLS_DTPMOD32:=0D
+ case R_LARCH_TLS_DTPMOD64:=0D
+ case R_LARCH_TLS_DTPREL32:=0D
+ case R_LARCH_TLS_DTPREL64:=0D
+ case R_LARCH_TLS_TPREL32:=0D
+ case R_LARCH_TLS_TPREL64:=0D
+ case R_LARCH_IRELATIVE:=0D
+ case R_LARCH_MARK_PCREL:=0D
+ case R_LARCH_SOP_PUSH_PCREL:=0D
+ case R_LARCH_SOP_PUSH_ABSOLUTE:=0D
+ case R_LARCH_SOP_PUSH_DUP:=0D
+ case R_LARCH_SOP_PUSH_GPREL:=0D
+ case R_LARCH_SOP_PUSH_TLS_TPREL:=0D
+ case R_LARCH_SOP_PUSH_TLS_GOT:=0D
+ case R_LARCH_SOP_PUSH_TLS_GD:=0D
+ case R_LARCH_SOP_PUSH_PLT_PCREL:=0D
+ case R_LARCH_SOP_ASSERT:=0D
+ case R_LARCH_SOP_NOT:=0D
+ case R_LARCH_SOP_SUB:=0D
+ case R_LARCH_SOP_SL:=0D
+ case R_LARCH_SOP_SR:=0D
+ case R_LARCH_SOP_ADD:=0D
+ case R_LARCH_SOP_AND:=0D
+ case R_LARCH_SOP_IF_ELSE:=0D
+ case R_LARCH_SOP_POP_32_S_10_5:=0D
+ case R_LARCH_SOP_POP_32_U_10_12:=0D
+ case R_LARCH_SOP_POP_32_S_10_12:=0D
+ case R_LARCH_SOP_POP_32_S_10_16:=0D
+ case R_LARCH_SOP_POP_32_S_10_16_S2:=0D
+ case R_LARCH_SOP_POP_32_S_5_20:=0D
+ case R_LARCH_SOP_POP_32_S_0_5_10_16_S2:=0D
+ case R_LARCH_SOP_POP_32_S_0_10_10_16_S2:=0D
+ case R_LARCH_SOP_POP_32_U:=0D
+ case R_LARCH_ADD8:=0D
+ case R_LARCH_ADD16:=0D
+ case R_LARCH_ADD24:=0D
+ case R_LARCH_ADD32:=0D
+ case R_LARCH_ADD64:=0D
+ case R_LARCH_SUB8:=0D
+ case R_LARCH_SUB16:=0D
+ case R_LARCH_SUB24:=0D
+ case R_LARCH_SUB32:=0D
+ case R_LARCH_SUB64:=0D
+ case R_LARCH_GNU_VTINHERIT:=0D
+ case R_LARCH_GNU_VTENTRY:=0D
+ case R_LARCH_B16:=0D
+ case R_LARCH_B21:=0D
+ case R_LARCH_B26:=0D
+ case R_LARCH_ABS_HI20:=0D
+ case R_LARCH_ABS_LO12:=0D
+ case R_LARCH_ABS64_LO20:=0D
+ case R_LARCH_ABS64_HI12:=0D
+ case R_LARCH_PCALA_HI20:=0D
+ case R_LARCH_PCALA_LO12:=0D
+ case R_LARCH_PCALA64_LO20:=0D
+ case R_LARCH_PCALA64_HI12:=0D
+ case R_LARCH_GOT_PC_HI20:=0D
+ case R_LARCH_GOT_PC_LO12:=0D
+ case R_LARCH_GOT64_PC_LO20:=0D
+ case R_LARCH_GOT64_PC_HI12:=0D
+ case R_LARCH_GOT64_HI20:=0D
+ case R_LARCH_GOT64_LO12:=0D
+ case R_LARCH_GOT64_LO20:=0D
+ case R_LARCH_GOT64_HI12:=0D
+ case R_LARCH_TLS_LE_HI20:=0D
+ case R_LARCH_TLS_LE_LO12:=0D
+ case R_LARCH_TLS_LE64_LO20:=0D
+ case R_LARCH_TLS_LE64_HI12:=0D
+ case R_LARCH_TLS_IE_PC_HI20:=0D
+ case R_LARCH_TLS_IE_PC_LO12:=0D
+ case R_LARCH_TLS_IE64_PC_LO20:=0D
+ case R_LARCH_TLS_IE64_PC_HI12:=0D
+ case R_LARCH_TLS_IE64_HI20:=0D
+ case R_LARCH_TLS_IE64_LO12:=0D
+ case R_LARCH_TLS_IE64_LO20:=0D
+ case R_LARCH_TLS_IE64_HI12:=0D
+ case R_LARCH_TLS_LD_PC_HI20:=0D
+ case R_LARCH_TLS_LD64_HI20:=0D
+ case R_LARCH_TLS_GD_PC_HI20:=0D
+ case R_LARCH_TLS_GD64_HI20:=0D
+ case R_LARCH_RELAX:=0D
+ //=0D
+ // These types are not used or do not require fixup in PE =
format files.=0D
+ //=0D
+ break;=0D
+ default:=0D
+ Error (NULL, 0, 3000, "Invalid", "WriteRelocations64(): =
%s unsupported ELF EM_LOONGARCH relocation 0x%x.", mInImageName, (unsigned)=
ELF64_R_TYPE(Rel->r_info));=0D
+ }=0D
} else {=0D
Error (NULL, 0, 3000, "Not Supported", "This tool does not sup=
port relocations for ELF with e_machine %u (processor type).", (unsigned) m=
Ehdr->e_machine);=0D
}=0D
diff --git a/BaseTools/Source/C/GenFw/elf_common.h b/BaseTools/Source/C/Gen=
Fw/elf_common.h
index b67f59e7a0..7b7fdeb329 100644
--- a/BaseTools/Source/C/GenFw/elf_common.h
+++ b/BaseTools/Source/C/GenFw/elf_common.h
@@ -4,6 +4,7 @@ Ported ELF include files from FreeBSD
Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>=0D
Portions Copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>=0D
Portion Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All=
rights reserved.<BR>=0D
+Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All =
rights reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
=0D
@@ -181,6 +182,7 @@ typedef struct {
#define EM_AARCH64 183 /* ARM 64bit Architecture */=0D
#define EM_RISCV64 243 /* 64bit RISC-V Architecture */=0D
#define EM_RISCV 244 /* 32bit RISC-V Architecture */=0D
+#define EM_LOONGARCH 258 /* LoongArch Architecture */=0D
=0D
/* Non-standard or deprecated. */=0D
#define EM_486 6 /* Intel i486. */=0D
@@ -1042,4 +1044,96 @@ typedef struct {
#define R_RISCV_SET8 54=0D
#define R_RISCV_SET16 55=0D
#define R_RISCV_SET32 56=0D
+=0D
+/*=0D
+ * LoongArch relocation types=0D
+ */=0D
+#define R_LARCH_NONE 0=0D
+#define R_LARCH_32 1=0D
+#define R_LARCH_64 2=0D
+#define R_LARCH_RELATIVE 3=0D
+#define R_LARCH_COPY 4=0D
+#define R_LARCH_JUMP_SLOT 5=0D
+#define R_LARCH_TLS_DTPMOD32 6=0D
+#define R_LARCH_TLS_DTPMOD64 7=0D
+#define R_LARCH_TLS_DTPREL32 8=0D
+#define R_LARCH_TLS_DTPREL64 9=0D
+#define R_LARCH_TLS_TPREL32 10=0D
+#define R_LARCH_TLS_TPREL64 11=0D
+#define R_LARCH_IRELATIVE 12=0D
+#define R_LARCH_MARK_LA 20=0D
+#define R_LARCH_MARK_PCREL 21=0D
+#define R_LARCH_SOP_PUSH_PCREL 22=0D
+#define R_LARCH_SOP_PUSH_ABSOLUTE 23=0D
+#define R_LARCH_SOP_PUSH_DUP 24=0D
+#define R_LARCH_SOP_PUSH_GPREL 25=0D
+#define R_LARCH_SOP_PUSH_TLS_TPREL 26=0D
+#define R_LARCH_SOP_PUSH_TLS_GOT 27=0D
+#define R_LARCH_SOP_PUSH_TLS_GD 28=0D
+#define R_LARCH_SOP_PUSH_PLT_PCREL 29=0D
+#define R_LARCH_SOP_ASSERT 30=0D
+#define R_LARCH_SOP_NOT 31=0D
+#define R_LARCH_SOP_SUB 32=0D
+#define R_LARCH_SOP_SL 33=0D
+#define R_LARCH_SOP_SR 34=0D
+#define R_LARCH_SOP_ADD 35=0D
+#define R_LARCH_SOP_AND 36=0D
+#define R_LARCH_SOP_IF_ELSE 37=0D
+#define R_LARCH_SOP_POP_32_S_10_5 38=0D
+#define R_LARCH_SOP_POP_32_U_10_12 39=0D
+#define R_LARCH_SOP_POP_32_S_10_12 40=0D
+#define R_LARCH_SOP_POP_32_S_10_16 41=0D
+#define R_LARCH_SOP_POP_32_S_10_16_S2 42=0D
+#define R_LARCH_SOP_POP_32_S_5_20 43=0D
+#define R_LARCH_SOP_POP_32_S_0_5_10_16_S2 44=0D
+#define R_LARCH_SOP_POP_32_S_0_10_10_16_S2 45=0D
+#define R_LARCH_SOP_POP_32_U 46=0D
+#define R_LARCH_ADD8 47=0D
+#define R_LARCH_ADD16 48=0D
+#define R_LARCH_ADD24 49=0D
+#define R_LARCH_ADD32 50=0D
+#define R_LARCH_ADD64 51=0D
+#define R_LARCH_SUB8 52=0D
+#define R_LARCH_SUB16 53=0D
+#define R_LARCH_SUB24 54=0D
+#define R_LARCH_SUB32 55=0D
+#define R_LARCH_SUB64 56=0D
+#define R_LARCH_GNU_VTINHERIT 57=0D
+#define R_LARCH_GNU_VTENTRY 58=0D
+#define R_LARCH_B16 64=0D
+#define R_LARCH_B21 65=0D
+#define R_LARCH_B26 66=0D
+#define R_LARCH_ABS_HI20 67=0D
+#define R_LARCH_ABS_LO12 68=0D
+#define R_LARCH_ABS64_LO20 69=0D
+#define R_LARCH_ABS64_HI12 70=0D
+#define R_LARCH_PCALA_HI20 71=0D
+#define R_LARCH_PCALA_LO12 72=0D
+#define R_LARCH_PCALA64_LO20 73=0D
+#define R_LARCH_PCALA64_HI12 74=0D
+#define R_LARCH_GOT_PC_HI20 75=0D
+#define R_LARCH_GOT_PC_LO12 76=0D
+#define R_LARCH_GOT64_PC_LO20 77=0D
+#define R_LARCH_GOT64_PC_HI12 78=0D
+#define R_LARCH_GOT64_HI20 79=0D
+#define R_LARCH_GOT64_LO12 80=0D
+#define R_LARCH_GOT64_LO20 81=0D
+#define R_LARCH_GOT64_HI12 82=0D
+#define R_LARCH_TLS_LE_HI20 83=0D
+#define R_LARCH_TLS_LE_LO12 84=0D
+#define R_LARCH_TLS_LE64_LO20 85=0D
+#define R_LARCH_TLS_LE64_HI12 86=0D
+#define R_LARCH_TLS_IE_PC_HI20 87=0D
+#define R_LARCH_TLS_IE_PC_LO12 88=0D
+#define R_LARCH_TLS_IE64_PC_LO20 89=0D
+#define R_LARCH_TLS_IE64_PC_HI12 90=0D
+#define R_LARCH_TLS_IE64_HI20 91=0D
+#define R_LARCH_TLS_IE64_LO12 92=0D
+#define R_LARCH_TLS_IE64_LO20 93=0D
+#define R_LARCH_TLS_IE64_HI12 94=0D
+#define R_LARCH_TLS_LD_PC_HI20 95=0D
+#define R_LARCH_TLS_LD64_HI20 96=0D
+#define R_LARCH_TLS_GD_PC_HI20 97=0D
+#define R_LARCH_TLS_GD64_HI20 98=0D
+#define R_LARCH_RELAX 99=0D
#endif /* !_SYS_ELF_COMMON_H_ */=0D
diff --git a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h b/BaseTo=
ols/Source/C/Include/IndustryStandard/PeImage.h
index 21c968e650..77ded3f611 100644
--- a/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
+++ b/BaseTools/Source/C/Include/IndustryStandard/PeImage.h
@@ -7,6 +7,7 @@
Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>=0D
Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>=0D
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights =
reserved.<BR>=0D
=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
@@ -36,23 +37,25 @@
//=0D
// PE32+ Machine type for EFI images=0D
//=0D
-#define IMAGE_FILE_MACHINE_I386 0x014c=0D
-#define IMAGE_FILE_MACHINE_EBC 0x0EBC=0D
-#define IMAGE_FILE_MACHINE_X64 0x8664=0D
-#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only=0D
-#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thumb/T=
humb 2 Little Endian=0D
-#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, Lit=
tle Endian=0D
-#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA=0D
+#define IMAGE_FILE_MACHINE_I386 0x014c=0D
+#define IMAGE_FILE_MACHINE_EBC 0x0EBC=0D
+#define IMAGE_FILE_MACHINE_X64 0x8664=0D
+#define IMAGE_FILE_MACHINE_ARM 0x01c0 // Thumb only=0D
+#define IMAGE_FILE_MACHINE_ARMT 0x01c2 // 32bit Mixed ARM and Thum=
b/Thumb 2 Little Endian=0D
+#define IMAGE_FILE_MACHINE_ARM64 0xAA64 // 64bit ARM Architecture, =
Little Endian=0D
+#define IMAGE_FILE_MACHINE_RISCV64 0x5064 // 64bit RISC-V ISA=0D
+#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264 // 64bit LoongArch Architec=
ture=0D
=0D
//=0D
// Support old names for backward compatible=0D
//=0D
-#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386=0D
-#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC=0D
-#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64=0D
-#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT=0D
-#define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64=0D
-#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64=0D
+#define EFI_IMAGE_MACHINE_IA32 IMAGE_FILE_MACHINE_I386=0D
+#define EFI_IMAGE_MACHINE_EBC IMAGE_FILE_MACHINE_EBC=0D
+#define EFI_IMAGE_MACHINE_X64 IMAGE_FILE_MACHINE_X64=0D
+#define EFI_IMAGE_MACHINE_ARMT IMAGE_FILE_MACHINE_ARMT=0D
+#define EFI_IMAGE_MACHINE_AARCH64 IMAGE_FILE_MACHINE_ARM64=0D
+#define EFI_IMAGE_MACHINE_RISCV64 IMAGE_FILE_MACHINE_RISCV64=0D
+#define EFI_IMAGE_MACHINE_LOONGARCH64 IMAGE_FILE_MACHINE_LOONGARCH64=0D
=0D
#define EFI_IMAGE_DOS_SIGNATURE 0x5A4D // MZ=0D
#define EFI_IMAGE_OS2_SIGNATURE 0x454E // NE=0D
@@ -500,19 +503,21 @@ typedef struct {
//=0D
// Based relocation types.=0D
//=0D
-#define EFI_IMAGE_REL_BASED_ABSOLUTE 0=0D
-#define EFI_IMAGE_REL_BASED_HIGH 1=0D
-#define EFI_IMAGE_REL_BASED_LOW 2=0D
-#define EFI_IMAGE_REL_BASED_HIGHLOW 3=0D
-#define EFI_IMAGE_REL_BASED_HIGHADJ 4=0D
-#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5=0D
-#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5=0D
-#define EFI_IMAGE_REL_BASED_RISCV_HI20 5=0D
-#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7=0D
-#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7=0D
-#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8=0D
-#define EFI_IMAGE_REL_BASED_IA64_IMM64 9=0D
-#define EFI_IMAGE_REL_BASED_DIR64 10=0D
+#define EFI_IMAGE_REL_BASED_ABSOLUTE 0=0D
+#define EFI_IMAGE_REL_BASED_HIGH 1=0D
+#define EFI_IMAGE_REL_BASED_LOW 2=0D
+#define EFI_IMAGE_REL_BASED_HIGHLOW 3=0D
+#define EFI_IMAGE_REL_BASED_HIGHADJ 4=0D
+#define EFI_IMAGE_REL_BASED_MIPS_JMPADDR 5=0D
+#define EFI_IMAGE_REL_BASED_ARM_MOV32A 5=0D
+#define EFI_IMAGE_REL_BASED_RISCV_HI20 5=0D
+#define EFI_IMAGE_REL_BASED_ARM_MOV32T 7=0D
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7=0D
+#define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8=0D
+#define EFI_IMAGE_REL_BASED_LOONGARCH32_MARK_LA 8=0D
+#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA 8=0D
+#define EFI_IMAGE_REL_BASED_IA64_IMM64 9=0D
+#define EFI_IMAGE_REL_BASED_DIR64 10=0D
=0D
=0D
///=0D
diff --git a/BaseTools/Source/C/Makefiles/header.makefile b/BaseTools/Sourc=
e/C/Makefiles/header.makefile
index 0df728f327..4e88a4fbd8 100644
--- a/BaseTools/Source/C/Makefiles/header.makefile
+++ b/BaseTools/Source/C/Makefiles/header.makefile
@@ -31,6 +31,9 @@ ifndef HOST_ARCH
ifneq (,$(findstring riscv64,$(uname_m)))=0D
HOST_ARCH=3DRISCV64=0D
endif=0D
+ ifneq (,$(findstring loongarch64,$(uname_m)))=0D
+ HOST_ARCH=3DLOONGARCH64=0D
+ endif=0D
ifndef HOST_ARCH=0D
$(info Could not detected HOST_ARCH from uname results)=0D
$(error HOST_ARCH is not defined!)=0D
@@ -70,6 +73,9 @@ ARCH_INCLUDE =3D -I $(MAKEROOT)/Include/AArch64/
else ifeq ($(HOST_ARCH), RISCV64)=0D
ARCH_INCLUDE =3D -I $(MAKEROOT)/Include/RiscV64/=0D
=0D
+else ifeq ($(HOST_ARCH), LOONGARCH64)=0D
+ARCH_INCLUDE =3D -I $(MAKEROOT)/Include/LoongArch64/=0D
+=0D
else=0D
$(error Bad HOST_ARCH)=0D
endif=0D
--=20
2.27.0


[PATCH v2 14/34] .python/SpellCheck: Add "Loongson" and "LOONGARCH" to "words" section

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

Add Loongson and LOONGARCH to "words" section in cspell.base.yaml file
to avoid spelling check error.

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>

Signed-off-by: Chao Li <lichao@...>
---
.pytool/Plugin/SpellCheck/cspell.base.yaml | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/.pytool/Plugin/SpellCheck/cspell.base.yaml b/.pytool/Plugin/Sp=
ellCheck/cspell.base.yaml
index f0d5791876..92e65ec6f6 100644
--- a/.pytool/Plugin/SpellCheck/cspell.base.yaml
+++ b/.pytool/Plugin/SpellCheck/cspell.base.yaml
@@ -289,6 +289,8 @@
"unrecovered",=0D
"cmocka",=0D
"unenrolling",=0D
- "unconfigure"=0D
+ "unconfigure",=0D
+ "Loongson",=0D
+ "LOONGARCH"=0D
]=0D
}=0D
--=20
2.27.0


[PATCH v2 13/34] MdeModulePkg: Use LockBoxNullLib for LOONGARCH64

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

LoongArch doesn't have SMM by now.

Cc: Jian J Wang <jian.j.wang@...>
Cc: Liming Gao <gaoliming@...>

Signed-off-by: Chao Li <lichao@...>
---
MdeModulePkg/MdeModulePkg.dsc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MdeModulePkg/MdeModulePkg.dsc b/MdeModulePkg/MdeModulePkg.dsc
index 45a8ec84ad..659482ab73 100644
--- a/MdeModulePkg/MdeModulePkg.dsc
+++ b/MdeModulePkg/MdeModulePkg.dsc
@@ -15,7 +15,7 @@
PLATFORM_VERSION =3D 0.98=0D
DSC_SPECIFICATION =3D 0x00010005=0D
OUTPUT_DIRECTORY =3D Build/MdeModule=0D
- SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64|RISCV64=0D
+ SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64|RISCV64|LOON=
GARCH64=0D
BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT=0D
SKUID_IDENTIFIER =3D DEFAULT=0D
=0D
@@ -193,7 +193,7 @@
#=0D
NULL|MdePkg/Library/BaseStackCheckLib/BaseStackCheckLib.inf=0D
=0D
-[LibraryClasses.EBC, LibraryClasses.RISCV64]=0D
+[LibraryClasses.EBC, LibraryClasses.RISCV64, LibraryClasses.LOONGARCH64]=0D
LockBoxLib|MdeModulePkg/Library/LockBoxNullLib/LockBoxNullLib.inf=0D
=0D
[PcdsFeatureFlag]=0D
--=20
2.27.0


[PATCH v2 12/34] MdePkg/DxeServicesLib: Add LOONGARCH64 architecture

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

Add LOONGARCH64 architecture to MdePkg/DxeServiceLib.

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>

Signed-off-by: Chao Li <lichao@...>
---
MdePkg/Library/DxeServicesLib/DxeServicesLib.inf | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf b/MdePkg/Libr=
ary/DxeServicesLib/DxeServicesLib.inf
index ec3e8711c2..a93541847f 100644
--- a/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+++ b/MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
@@ -22,13 +22,13 @@
LIBRARY_CLASS =3D DxeServicesLib|DXE_CORE DXE_DRIVER DX=
E_RUNTIME_DRIVER DXE_SMM_DRIVER SMM_CORE UEFI_APPLICATION UEFI_DRIVER=0D
=0D
#=0D
-# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64=0D
+# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 LOON=
GARCH64=0D
#=0D
=0D
[Sources]=0D
DxeServicesLib.c=0D
=0D
-[Sources.IA32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64]=
=0D
+[Sources.IA32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64,=
Sources.LOONGARCH64]=0D
Allocate.c=0D
=0D
[Sources.X64]=0D
--=20
2.27.0


[PATCH v2 11/34] UnitTestFrameworkPkg: Add LOONGARCH64 architecture for EDK2 CI.

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

Add LOONGARCH64 architecture to UnitTestFramworkPkg for LOONGARCH64 EDK2
CI.

Cc: Michael D Kinney <michael.d.kinney@...>

Signed-off-by: Chao Li <lichao@...>
---
UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc b/UnitTestFramew=
orkPkg/UnitTestFrameworkPkg.dsc
index 23baef87d6..e4f9fb6eb6 100644
--- a/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc
+++ b/UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc
@@ -3,6 +3,7 @@
#=0D
# Copyright (c) 2019 - 2021, Intel Corporation. All rights reserved.<BR>=0D
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights =
reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -14,7 +15,7 @@
PLATFORM_VERSION =3D 1.00=0D
DSC_SPECIFICATION =3D 0x00010005=0D
OUTPUT_DIRECTORY =3D Build/UnitTestFrameworkPkg=0D
- SUPPORTED_ARCHITECTURES =3D IA32|X64|ARM|AARCH64|RISCV64=0D
+ SUPPORTED_ARCHITECTURES =3D IA32|X64|ARM|AARCH64|RISCV64|LOONGARCH64=0D
BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT=0D
SKUID_IDENTIFIER =3D DEFAULT=0D
=0D
--=20
2.27.0


[PATCH v2 02/34] MdePkg: Added LoongArch jump buffer register definition to MdePkg.ci.yaml

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

If the new Arch register is defined in BaseLib.h when running
the CI tests, it will give an ECC check error. Add the
LoongArch register defined in the IgnoreFiles field to make
the CI ECC check pass.

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>

Signed-off-by: Chao Li <lichao@...>
---
MdePkg/MdePkg.ci.yaml | 12 ++++++++++++
1 file changed, 12 insertions(+)

diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml
index 9d141aa3cb..19bc0138cb 100644
--- a/MdePkg/MdePkg.ci.yaml
+++ b/MdePkg/MdePkg.ci.yaml
@@ -27,6 +27,18 @@
"8005", "void",=0D
"8005", "va_list.__ap",=0D
"8005", "__stack_chk_guard",=0D
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S0",=0D
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S1",=0D
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S2",=0D
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S3",=0D
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S4",=0D
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S5",=0D
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S6",=0D
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S7",=0D
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.S8",=0D
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.SP",=0D
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.FP",=0D
+ "8005", "BASE_LIBRARY_JUMP_BUFFER.RA",=0D
"8001", "MSG_IPv6_DP",=0D
"8001", "MSG_IPv4_DP",=0D
"8001", "DEFAULT_ToS",=0D
--=20
2.27.0


[PATCH v2 10/34] ShellPkg: Add LOONGARCH64 architecture for EDK2 CI.

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

Add LOONGARCH64 architecture to ShellPkg for EDK2 CI testing.

Cc: Ray Ni <ray.ni@...>
Cc: Zhichao Gao <zhichao.gao@...>

Signed-off-by: Chao Li <lichao@...>
---
ShellPkg/ShellPkg.dsc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/ShellPkg/ShellPkg.dsc b/ShellPkg/ShellPkg.dsc
index 38fde3dc71..dd0d88603f 100644
--- a/ShellPkg/ShellPkg.dsc
+++ b/ShellPkg/ShellPkg.dsc
@@ -4,6 +4,7 @@
# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>=0D
# Copyright (c) 2018 - 2020, Arm Limited. All rights reserved.<BR>=0D
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights =
reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -15,7 +16,7 @@
PLATFORM_VERSION =3D 1.02=0D
DSC_SPECIFICATION =3D 0x00010006=0D
OUTPUT_DIRECTORY =3D Build/Shell=0D
- SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64|RISCV64=0D
+ SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64|RISCV64|LOON=
GARCH64=0D
BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT=0D
SKUID_IDENTIFIER =3D DEFAULT=0D
=0D
--=20
2.27.0


[PATCH v2 09/34] SecurityPkg: Add LOONGARCH64 architecture for EDK2 CI.

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

Add LOONGARCH64 architecture to SecurityPkg for EDK2 CI testing.

Cc: Jiewen Yao <jiewen.yao@...>
Cc: Jian J Wang <jian.j.wang@...>

Signed-off-by: Chao Li <lichao@...>
---
SecurityPkg/SecurityPkg.dsc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/SecurityPkg/SecurityPkg.dsc b/SecurityPkg/SecurityPkg.dsc
index f48187650f..6bf53c5658 100644
--- a/SecurityPkg/SecurityPkg.dsc
+++ b/SecurityPkg/SecurityPkg.dsc
@@ -3,6 +3,7 @@
#=0D
# Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.<BR>=0D
# (C) Copyright 2015-2020 Hewlett Packard Enterprise Development LP<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights =
reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
##=0D
@@ -13,7 +14,7 @@
PLATFORM_VERSION =3D 0.98=0D
DSC_SPECIFICATION =3D 0x00010005=0D
OUTPUT_DIRECTORY =3D Build/SecurityPkg=0D
- SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64|RISCV64=0D
+ SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64|RISCV64|LOON=
GARCH64=0D
BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT=0D
SKUID_IDENTIFIER =3D DEFAULT=0D
=0D
--=20
2.27.0


[PATCH v2 05/34] NetworkPkg: Add LOONGARCH64 architecture for EDK2 CI.

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

Add LOONGARCH64 architecture for EDK2 CI testing.

Cc: Maciej Rabeda <maciej.rabeda@...>
Cc: Jiaxin Wu <jiaxin.wu@...>
Cc: Siyuan Fu <siyuan.fu@...>

Signed-off-by: Chao Li <lichao@...>
---
NetworkPkg/NetworkPkg.dsc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/NetworkPkg/NetworkPkg.dsc b/NetworkPkg/NetworkPkg.dsc
index 762134023d..6c231c97b5 100644
--- a/NetworkPkg/NetworkPkg.dsc
+++ b/NetworkPkg/NetworkPkg.dsc
@@ -4,6 +4,7 @@
# (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>=0D
# Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.<BR>=0D
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights =
reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
##=0D
@@ -14,7 +15,7 @@
PLATFORM_VERSION =3D 0.98=0D
DSC_SPECIFICATION =3D 0x00010005=0D
OUTPUT_DIRECTORY =3D Build/NetworkPkg=0D
- SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64|RISCV64=0D
+ SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64|RISCV64|LOON=
GARCH64=0D
BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT=0D
SKUID_IDENTIFIER =3D DEFAULT=0D
=0D
--=20
2.27.0


[PATCH v2 07/34] CryptoPkg: Add LOONGARCH64 architecture for EDK2 CI.

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

Add LOONGARCH64 architecture for EDK2 CI testing.

Cc: Jiewen Yao <jiewen.yao@...>
Cc: Jian J Wang <jian.j.wang@...>
Cc: Xiaoyu Lu <xiaoyu1.lu@...>
Cc: Guomin Jiang <guomin.jiang@...>

Signed-off-by: Chao Li <lichao@...>
---
CryptoPkg/CryptoPkg.dsc | 3 ++-
CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf | 6 +++++-
CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf | 4 ++++
CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf | 3 ++-
CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf | 3 ++-
CryptoPkg/Library/BaseCryptLibOnProtocolPpi/PeiCryptLib.inf | 3 ++-
CryptoPkg/Library/Include/CrtLibSupport.h | 3 ++-
CryptoPkg/Library/OpensslLib/OpensslLib.inf | 2 ++
CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf | 2 ++
CryptoPkg/Library/TlsLib/TlsLib.inf | 3 ++-
CryptoPkg/Library/TlsLibNull/TlsLibNull.inf | 3 ++-
11 files changed, 27 insertions(+), 8 deletions(-)

diff --git a/CryptoPkg/CryptoPkg.dsc b/CryptoPkg/CryptoPkg.dsc
index 50e7721f25..c3a02aafb0 100644
--- a/CryptoPkg/CryptoPkg.dsc
+++ b/CryptoPkg/CryptoPkg.dsc
@@ -4,6 +4,7 @@
#=0D
# Copyright (c) 2009 - 2021, Intel Corporation. All rights reserved.<BR>=
=0D
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ=
ts reserved.<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights=
reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
##=0D
@@ -19,7 +20,7 @@
PLATFORM_VERSION =3D 0.98=0D
DSC_SPECIFICATION =3D 0x00010005=0D
OUTPUT_DIRECTORY =3D Build/CryptoPkg=0D
- SUPPORTED_ARCHITECTURES =3D IA32|X64|ARM|AARCH64|RISCV64=0D
+ SUPPORTED_ARCHITECTURES =3D IA32|X64|ARM|AARCH64|RISCV64|LOONGARC=
H64=0D
BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT=0D
SKUID_IDENTIFIER =3D DEFAULT=0D
=0D
diff --git a/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf b/CryptoPkg/Li=
brary/BaseCryptLib/BaseCryptLib.inf
index 3d7b917103..f8790d2c72 100644
--- a/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
+++ b/CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
@@ -8,6 +8,7 @@
#=0D
# Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>=
=0D
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ=
ts reserved.<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights=
reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
##=0D
@@ -24,7 +25,7 @@
#=0D
# The following information is for reference only and not required by the =
build tools.=0D
#=0D
-# VALID_ARCHITECTURES =3D IA32 X64 ARM AARCH64 RISCV64=0D
+# VALID_ARCHITECTURES =3D IA32 X64 ARM AARCH64 RISCV64 LOONGARC=
H64=0D
#=0D
=0D
[Sources]=0D
@@ -74,6 +75,9 @@
[Sources.RISCV64]=0D
Rand/CryptRand.c=0D
=0D
+[Sources.LOONGARCH64]=0D
+ Rand/CryptRand.c=0D
+=0D
[Packages]=0D
MdePkg/MdePkg.dec=0D
CryptoPkg/CryptoPkg.dec=0D
diff --git a/CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf b/CryptoPkg=
/Library/BaseCryptLib/RuntimeCryptLib.inf
index d28fb98b66..7da789d00e 100644
--- a/CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
+++ b/CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
@@ -13,6 +13,7 @@
#=0D
# Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>=
=0D
# Copyright (c) 2021, Hewlett Packard Enterprise Development LP. All righ=
ts reserved.<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights=
reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
##=0D
@@ -79,6 +80,9 @@
[Sources.RISCV64]=0D
Rand/CryptRand.c=0D
=0D
+[Sources.LOONGARCH64]=0D
+ Rand/CryptRand.c=0D
+=0D
[Packages]=0D
MdePkg/MdePkg.dec=0D
CryptoPkg/CryptoPkg.dec=0D
diff --git a/CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf b/Cryp=
toPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf
index 63d1d82d19..1d8b502813 100644
--- a/CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf
+++ b/CryptoPkg/Library/BaseCryptLibNull/BaseCryptLibNull.inf
@@ -8,6 +8,7 @@
#=0D
# Copyright (c) 2009 - 2022, Intel Corporation. All rights reserved.<BR>=
=0D
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ=
ts reserved.<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights=
reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
##=0D
@@ -24,7 +25,7 @@
#=0D
# The following information is for reference only and not required by the =
build tools.=0D
#=0D
-# VALID_ARCHITECTURES =3D IA32 X64 ARM AARCH64 RISCV64=0D
+# VALID_ARCHITECTURES =3D IA32 X64 ARM AARCH64 RISCV64 LOONGARC=
H64=0D
#=0D
=0D
[Sources]=0D
diff --git a/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf b/=
CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf
index baa4433cbe..b4945de336 100644
--- a/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf
+++ b/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/DxeCryptLib.inf
@@ -4,6 +4,7 @@
#=0D
# Copyright (C) Microsoft Corporation. All rights reserved.=0D
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights =
reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
##=0D
@@ -22,7 +23,7 @@
#=0D
# The following information is for reference only and not required by the =
build tools.=0D
#=0D
-# VALID_ARCHITECTURES =3D IA32 X64 ARM AARCH64 RISCV64=0D
+# VALID_ARCHITECTURES =3D IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64=0D
#=0D
=0D
[Packages]=0D
diff --git a/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/PeiCryptLib.inf b/=
CryptoPkg/Library/BaseCryptLibOnProtocolPpi/PeiCryptLib.inf
index 038ca71890..e7d153db0b 100644
--- a/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/PeiCryptLib.inf
+++ b/CryptoPkg/Library/BaseCryptLibOnProtocolPpi/PeiCryptLib.inf
@@ -4,6 +4,7 @@
#=0D
# Copyright (C) Microsoft Corporation. All rights reserved.=0D
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights =
reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
##=0D
@@ -21,7 +22,7 @@
#=0D
# The following information is for reference only and not required by the =
build tools.=0D
#=0D
-# VALID_ARCHITECTURES =3D IA32 X64 ARM AARCH64 RISCV64=0D
+# VALID_ARCHITECTURES =3D IA32 X64 ARM AARCH64 RISCV64 LOONGARCH64=0D
#=0D
=0D
[Packages]=0D
diff --git a/CryptoPkg/Library/Include/CrtLibSupport.h b/CryptoPkg/Library/=
Include/CrtLibSupport.h
index e49060124f..5072c343da 100644
--- a/CryptoPkg/Library/Include/CrtLibSupport.h
+++ b/CryptoPkg/Library/Include/CrtLibSupport.h
@@ -4,6 +4,7 @@
=0D
Copyright (c) 2010 - 2022, Intel Corporation. All rights reserved.<BR>=0D
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights =
reserved.<BR>=0D
+Copyright (c) 2022, Loongson Technology Corporation Limited. All rights re=
served.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
**/=0D
@@ -46,7 +47,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define CONFIG_HEADER_BN_H=0D
=0D
#if !defined (SIXTY_FOUR_BIT) && !defined (THIRTY_TWO_BIT)=0D
- #if defined (MDE_CPU_X64) || defined (MDE_CPU_AARCH64) || defined (MDE_C=
PU_IA64) || defined (MDE_CPU_RISCV64)=0D
+ #if defined (MDE_CPU_X64) || defined (MDE_CPU_AARCH64) || defined (MDE_C=
PU_IA64) || defined (MDE_CPU_RISCV64) || defined (MDE_CPU_LOONGARCH64)=0D
//=0D
// With GCC we would normally use SIXTY_FOUR_BIT_LONG, but MSVC needs=0D
// SIXTY_FOUR_BIT, because 'long' is 32-bit and only 'long long' is=0D
diff --git a/CryptoPkg/Library/OpensslLib/OpensslLib.inf b/CryptoPkg/Librar=
y/OpensslLib/OpensslLib.inf
index c899b811b1..f0ca72eeed 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLib.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLib.inf
@@ -3,6 +3,7 @@
#=0D
# Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.<BR>=
=0D
# (C) Copyright 2020 Hewlett Packard Enterprise Development LP<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights=
reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
##=0D
@@ -675,6 +676,7 @@
GCC:*_*_ARM_CC_FLAGS =3D $(OPENSSL_FLAGS) -Wno-error=3Dmaybe-uniniti=
alized -Wno-error=3Dunused-but-set-variable=0D
GCC:*_*_AARCH64_CC_FLAGS =3D $(OPENSSL_FLAGS) -Wno-error=3Dmaybe-uniniti=
alized -Wno-format -Wno-error=3Dunused-but-set-variable=0D
GCC:*_*_RISCV64_CC_FLAGS =3D $(OPENSSL_FLAGS) -Wno-error=3Dmaybe-uniniti=
alized -Wno-format -Wno-error=3Dunused-but-set-variable=0D
+ GCC:*_*_LOONGARCH64_CC_FLAGS =3D $(OPENSSL_FLAGS) -Wno-error=3Dmaybe-uni=
nitialized -Wno-format -Wno-error=3Dunused-but-set-variable=0D
GCC:*_CLANG35_*_CC_FLAGS =3D -std=3Dc99 -Wno-error=3Duninitialized=0D
GCC:*_CLANG38_*_CC_FLAGS =3D -std=3Dc99 -Wno-error=3Duninitialized=0D
GCC:*_CLANGPDB_*_CC_FLAGS =3D -std=3Dc99 -Wno-error=3Duninitialized -Wno=
-error=3Dincompatible-pointer-types -Wno-error=3Dpointer-sign -Wno-error=3D=
implicit-function-declaration -Wno-error=3Dignored-pragma-optimize=0D
diff --git a/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf b/CryptoPkg/=
Library/OpensslLib/OpensslLibCrypto.inf
index 0ec3724541..195016fd3d 100644
--- a/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
+++ b/CryptoPkg/Library/OpensslLib/OpensslLibCrypto.inf
@@ -3,6 +3,7 @@
#=0D
# Copyright (c) 2010 - 2020, Intel Corporation. All rights reserved.<BR>=
=0D
# (C) Copyright 2020 Hewlett Packard Enterprise Development LP<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights=
reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
##=0D
@@ -624,6 +625,7 @@
GCC:*_*_ARM_CC_FLAGS =3D $(OPENSSL_FLAGS) -Wno-error=3Dmaybe-uniniti=
alized -Wno-error=3Dunused-but-set-variable=0D
GCC:*_*_AARCH64_CC_FLAGS =3D $(OPENSSL_FLAGS) -Wno-error=3Dmaybe-uniniti=
alized -Wno-format -Wno-error=3Dunused-but-set-variable=0D
GCC:*_*_RISCV64_CC_FLAGS =3D $(OPENSSL_FLAGS) -Wno-error=3Dmaybe-uniniti=
alized -Wno-format -Wno-error=3Dunused-but-set-variable=0D
+ GCC:*_*_LOONGARCH64_CC_FLAGS =3D $(OPENSSL_FLAGS) -Wno-error=3Dmaybe-uni=
nitialized -Wno-format -Wno-error=3Dunused-but-set-variable=0D
GCC:*_CLANG35_*_CC_FLAGS =3D -std=3Dc99 -Wno-error=3Duninitialized=0D
GCC:*_CLANG38_*_CC_FLAGS =3D -std=3Dc99 -Wno-error=3Duninitialized=0D
GCC:*_CLANGPDB_*_CC_FLAGS =3D -std=3Dc99 -Wno-error=3Duninitialized -Wno=
-error=3Dincompatible-pointer-types -Wno-error=3Dpointer-sign -Wno-error=3D=
implicit-function-declaration -Wno-error=3Dignored-pragma-optimize=0D
diff --git a/CryptoPkg/Library/TlsLib/TlsLib.inf b/CryptoPkg/Library/TlsLib=
/TlsLib.inf
index bc61cda745..20b0ea6832 100644
--- a/CryptoPkg/Library/TlsLib/TlsLib.inf
+++ b/CryptoPkg/Library/TlsLib/TlsLib.inf
@@ -3,6 +3,7 @@
#=0D
# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>=
=0D
# (C) Copyright 2016-2020 Hewlett Packard Enterprise Development LP<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights=
reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
##=0D
@@ -19,7 +20,7 @@
#=0D
# The following information is for reference only and not required by the =
build tools.=0D
#=0D
-# VALID_ARCHITECTURES =3D IA32 X64 ARM AARCH64 RISCV64=0D
+# VALID_ARCHITECTURES =3D IA32 X64 ARM AARCH64 RISCV64 LOONGARC=
H64=0D
#=0D
=0D
[Sources]=0D
diff --git a/CryptoPkg/Library/TlsLibNull/TlsLibNull.inf b/CryptoPkg/Librar=
y/TlsLibNull/TlsLibNull.inf
index b2920ddacf..12d7cc764a 100644
--- a/CryptoPkg/Library/TlsLibNull/TlsLibNull.inf
+++ b/CryptoPkg/Library/TlsLibNull/TlsLibNull.inf
@@ -3,6 +3,7 @@
#=0D
# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>=
=0D
# (C) Copyright 2016-2020 Hewlett Packard Enterprise Development LP<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights=
reserved.<BR>=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
##=0D
@@ -19,7 +20,7 @@
#=0D
# The following information is for reference only and not required by the =
build tools.=0D
#=0D
-# VALID_ARCHITECTURES =3D IA32 X64 ARM AARCH64 RISCV64=0D
+# VALID_ARCHITECTURES =3D IA32 X64 ARM AARCH64 RISCV64 LOONGARC=
H64=0D
#=0D
=0D
[Sources]=0D
--=20
2.27.0


[PATCH v2 08/34] MdePkg/Include: Add LOONGARCH related definitions EDK2 CI.

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

HTTP/PXE boot LOONGARCH64 related definitions for EDK2 CI.

For the LOONGARCH values, please seeing following URL section
"Processor Architecture Types":
https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>

Signed-off-by: Chao Li <lichao@...>
---
MdePkg/Include/IndustryStandard/Dhcp.h | 45 ++++++++++++++------------
1 file changed, 25 insertions(+), 20 deletions(-)

diff --git a/MdePkg/Include/IndustryStandard/Dhcp.h b/MdePkg/Include/Indust=
ryStandard/Dhcp.h
index f209f1b2eb..46ab4f8e75 100644
--- a/MdePkg/Include/IndustryStandard/Dhcp.h
+++ b/MdePkg/Include/IndustryStandard/Dhcp.h
@@ -4,6 +4,7 @@
=0D
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>=0D
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+ Copyright (c) 2022, Loongson Technology Corporation Limited. All rights =
reserved.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
**/=0D
=0D
@@ -256,27 +257,31 @@ typedef enum {
=0D
///=0D
/// Processor Architecture Types=0D
-/// These identifiers are defined by IETF:=0D
-/// http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xm=
l=0D
+/// These identifiers are defined by IANA:=0D
+/// https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.x=
html=0D
///=0D
-#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE=0D
-#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE=0D
-#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE=0D
-#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE=0D
-#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE=0D
-#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for PXE=
=0D
-#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for PXE=
=0D
-#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 for =
PXE=0D
-#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 for =
PXE=0D
-#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 for=
PXE=0D
+#define PXE_CLIENT_ARCH_X86_BIOS 0x0000 /// x86 BIOS for PXE=
=0D
+#define PXE_CLIENT_ARCH_IPF 0x0002 /// Itanium for PXE=0D
+#define PXE_CLIENT_ARCH_IA32 0x0006 /// x86 uefi for PXE=
=0D
+#define PXE_CLIENT_ARCH_X64 0x0007 /// x64 uefi for PXE=
=0D
+#define PXE_CLIENT_ARCH_EBC 0x0009 /// EBC for PXE=0D
+#define PXE_CLIENT_ARCH_ARM 0x000A /// Arm uefi 32 for P=
XE=0D
+#define PXE_CLIENT_ARCH_AARCH64 0x000B /// Arm uefi 64 for P=
XE=0D
+#define PXE_CLIENT_ARCH_RISCV32 0x0019 /// RISC-V uefi 32 fo=
r PXE=0D
+#define PXE_CLIENT_ARCH_RISCV64 0x001B /// RISC-V uefi 64 fo=
r PXE=0D
+#define PXE_CLIENT_ARCH_RISCV128 0x001D /// RISC-V uefi 128 f=
or PXE=0D
+#define PXE_CLIENT_ARCH_LOONGARCH32 0x0025 /// LoongArch uefi 32=
for PXE=0D
+#define PXE_CLIENT_ARCH_LOONGARCH64 0x0027 /// LoongArch uefi 64=
for PXE=0D
=0D
-#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot from =
http=0D
-#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot from =
http=0D
-#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from http=
=0D
-#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot fr=
om http=0D
-#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot fr=
om http=0D
-#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 boot=
from http=0D
-#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 boot=
from http=0D
-#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 boo=
t from http=0D
+#define HTTP_CLIENT_ARCH_IA32 0x000F /// x86 uefi boot fr=
om http=0D
+#define HTTP_CLIENT_ARCH_X64 0x0010 /// x64 uefi boot fr=
om http=0D
+#define HTTP_CLIENT_ARCH_EBC 0x0011 /// EBC boot from ht=
tp=0D
+#define HTTP_CLIENT_ARCH_ARM 0x0012 /// Arm uefi 32 boot=
from http=0D
+#define HTTP_CLIENT_ARCH_AARCH64 0x0013 /// Arm uefi 64 boot=
from http=0D
+#define HTTP_CLIENT_ARCH_RISCV32 0x001A /// RISC-V uefi 32 b=
oot from http=0D
+#define HTTP_CLIENT_ARCH_RISCV64 0x001C /// RISC-V uefi 64 b=
oot from http=0D
+#define HTTP_CLIENT_ARCH_RISCV128 0x001E /// RISC-V uefi 128 =
boot from http=0D
+#define HTTP_CLIENT_ARCH_LOONGARCH32 0x0026 /// LoongArch uefi 3=
2 boot from http=0D
+#define HTTP_CLIENT_ARCH_LOONGARCH64 0x0028 /// LoongArch uefi 6=
4 boot from http=0D
=0D
#endif=0D
--=20
2.27.0


[PATCH v2 01/34] MdePkg: Added file of DebugSupport.h to MdePkg.ci.yaml

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

DebugSupport.h is all defined by UEFI Spec, most of the code
doesn't fit EDKII coding style, add it to IgnoreFiles field to
make CI ECC check pass.

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>

Signed-off-by: Chao Li <lichao@...>
---
MdePkg/MdePkg.ci.yaml | 1 +
1 file changed, 1 insertion(+)

diff --git a/MdePkg/MdePkg.ci.yaml b/MdePkg/MdePkg.ci.yaml
index 054233ebc7..9d141aa3cb 100644
--- a/MdePkg/MdePkg.ci.yaml
+++ b/MdePkg/MdePkg.ci.yaml
@@ -52,6 +52,7 @@
"Include/IndustryStandard/UefiTcgPlatform.h",=0D
"Include/Library/PcdLib.h",=0D
"Include/Library/SafeIntLib.h",=0D
+ "Include/Protocol/DebugSupport.h",=0D
"Test/UnitTest/Library/BaseSafeIntLib/TestBaseSafeIntLib.c"=0D
]=0D
},=0D
--=20
2.27.0


[PATCH v2 06/34] NetworkPkg/HttpBootDxe: Add LOONGARCH64 architecture for EDK2 CI.

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

Add LOONGARCH architecture for EDK2 CI testing.

Cc: Maciej Rabeda <maciej.rabeda@...>
Cc: Jiaxin Wu <jiaxin.wu@...>
Cc: Siyuan Fu <siyuan.fu@...>

Signed-off-by: Chao Li <lichao@...>
---
NetworkPkg/HttpBootDxe/HttpBootDhcp4.h | 3 +++
1 file changed, 3 insertions(+)

diff --git a/NetworkPkg/HttpBootDxe/HttpBootDhcp4.h b/NetworkPkg/HttpBootDx=
e/HttpBootDhcp4.h
index d76f0e84d6..f00fabead2 100644
--- a/NetworkPkg/HttpBootDxe/HttpBootDhcp4.h
+++ b/NetworkPkg/HttpBootDxe/HttpBootDhcp4.h
@@ -3,6 +3,7 @@
=0D
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>=0D
Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights =
reserved.<BR>=0D
+Copyright (c) 2022, Loongson Technology Corporation Limited. All rights re=
served.<BR>=0D
SPDX-License-Identifier: BSD-2-Clause-Patent=0D
=0D
**/=0D
@@ -40,6 +41,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#define EFI_HTTP_BOOT_CLIENT_SYSTEM_ARCHITECTURE HTTP_CLIENT_ARCH_RISCV64=
=0D
#elif defined (MDE_CPU_EBC)=0D
#define EFI_HTTP_BOOT_CLIENT_SYSTEM_ARCHITECTURE HTTP_CLIENT_ARCH_EBC=0D
+#elif defined (MDE_CPU_LOONGARCH64)=0D
+#define EFI_HTTP_BOOT_CLIENT_SYSTEM_ARCHITECTURE HTTP_CLIENT_ARCH_LOONGAR=
CH64=0D
#endif=0D
=0D
/// DHCP offer types among HTTP boot.=0D
--=20
2.27.0


[PATCH v2 04/34] FmpDevicePkg: Add LOONGARCH64 architecture for EDK2 CI.

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

Add LOONGARCH64 architecture for EDK2 CI testing.

Cc: Liming Gao <gaoliming@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Guomin Jiang <guomin.jiang@...>
Cc: Wei6 Xu <wei6.xu@...>

Signed-off-by: Chao Li <lichao@...>
---
FmpDevicePkg/FmpDevicePkg.dsc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/FmpDevicePkg/FmpDevicePkg.dsc b/FmpDevicePkg/FmpDevicePkg.dsc
index 7b1af285dd..f9f26c54bb 100644
--- a/FmpDevicePkg/FmpDevicePkg.dsc
+++ b/FmpDevicePkg/FmpDevicePkg.dsc
@@ -9,6 +9,7 @@
# Copyright (c) Microsoft Corporation.<BR>=0D
# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>=0D
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right=
s reserved.<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights =
reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -20,7 +21,7 @@
PLATFORM_VERSION =3D 0.1=0D
DSC_SPECIFICATION =3D 0x00010005=0D
OUTPUT_DIRECTORY =3D Build/FmpDevicePkg=0D
- SUPPORTED_ARCHITECTURES =3D IA32|X64|ARM|AARCH64|RISCV64=0D
+ SUPPORTED_ARCHITECTURES =3D IA32|X64|ARM|AARCH64|RISCV64|LOONGARC=
H64=0D
BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT=0D
SKUID_IDENTIFIER =3D DEFAULT=0D
=0D
--=20
2.27.0


[PATCH v2 00/34] Add a new architecture called LoongArch in EDK II

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

UEFI Spec V2.10 already supports LoongArch and all changes of this
commit passwed Azure CI testing, so let's enable it in EDK2. This commit
contains 35 patchs, with patch 0 is the cover and the rest being the
LoongArch base code.

Changes from v1 to v2:
1. For patch 0008, added IANA website link in the commit message and
Dhcp.h.
2. Added IANA, Microsft and UEFI specification links in every patch
commit message that uses them.
3. For patch 0023, LoongArch64 supports unaligned access operations, so
use the unaligned read/write generic implementation. Added Barrier.S
file to provide barrier operations for LoongArch.
4. For patch 0024, convert inline assembly code to ASM code.
5. Added the BZ link in every patch commit message.

Please refer to this URL for the code repo of LoongArch64:
https://github.com/loongson/edk2/tree/LoongArch

Fore more documents of LoongArch please refer to following URL:
https://loongson.github.io/LoongArch-Documentation/README-EN.html

Modified modules: FatPkg, FmpDevicePkg, NetworkPkg,
NetworkPkg/HttpBootDxe, CryptoPkg, MdePkg/Include, SecurityPkg,
ShellPkg, UnitTestFrameworkPkg, MdePkg/DxeServicesLib, MdeModulePkg,
.python/SpellCheck, BaseTools, .azurepipelines, .pytool, MdePkg,
MdeModulePkg and MdePkg/MdePkg.ci.yaml.

Cc: Ray Ni <ray.ni@...>
Cc: Liming Gao <gaoliming@...>
Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Guomin Jiang <guomin.jiang@...>
Cc: Wei6 Xu <wei6.xu@...>
Cc: Maciej Rabeda <maciej.rabeda@...>
Cc: Jiaxin Wu <jiaxin.wu@...>
Cc: Siyuan Fu <siyuan.fu@...>
Cc: Jiewen Yao <jiewen.yao@...>
Cc: Jian J Wang <jian.j.wang@...>
Cc: Xiaoyu Lu <xiaoyu1.lu@...>
Cc: Zhiguang Liu <zhiguang.liu@...>
Cc: Zhichao Gao <zhichao.gao@...>
Cc: Bob Feng <bob.c.feng@...>
Cc: Yuwei Chen <yuwei.chen@...>

Chao Li (34):
MdePkg: Added file of DebugSupport.h to MdePkg.ci.yaml
MdePkg: Added LoongArch jump buffer register definition to
MdePkg.ci.yaml
FatPkg: Add LOONGARCH64 architecture for EDK2 CI.
FmpDevicePkg: Add LOONGARCH64 architecture for EDK2 CI.
NetworkPkg: Add LOONGARCH64 architecture for EDK2 CI.
NetworkPkg/HttpBootDxe: Add LOONGARCH64 architecture for EDK2 CI.
CryptoPkg: Add LOONGARCH64 architecture for EDK2 CI.
MdePkg/Include: Add LOONGARCH related definitions EDK2 CI.
SecurityPkg: Add LOONGARCH64 architecture for EDK2 CI.
ShellPkg: Add LOONGARCH64 architecture for EDK2 CI.
UnitTestFrameworkPkg: Add LOONGARCH64 architecture for EDK2 CI.
MdePkg/DxeServicesLib: Add LOONGARCH64 architecture
MdeModulePkg: Use LockBoxNullLib for LOONGARCH64
.python/SpellCheck: Add "Loongson" and "LOONGARCH" to "words" section
BaseTools: BaseTools changes for LoongArch platform.
BaseTools: BaseTools changes for LoongArch platform.
BaseTools: BaseTools changes for LoongArch platform.
BaseTools: Enable LoongArch64 architecture for LoongArch64 EDK2 CI.
.azurepipelines: Add LoongArch64 architecture on LoongArch64 EDK2 CI.
.pytool: Add LoongArch64 architecture on LoongArch64 EDK2 CI.
MdePkg: Add LoongArch LOONGARCH64 binding
MdePkg/Include: LoongArch definitions.
MdePkg/BaseLib: BaseLib for LOONGARCH64 architecture.
MdePkg/BaseCacheMaintenanceLib: LoongArch cache maintenance
implementation.
MdePkg/BaseIoLibIntrinsic: IoLibNoIo for LoongArch architecture.
MdePkg/BasePeCoff: Add LoongArch PE/Coff related code.
MdePkg/BaseCpuLib: LoongArch Base CPU library implementation.
MdePkg/BaseSynchronizationLib: LoongArch cache related code.
MdePkg/BaseSafeIntLib: Add LoongArch64 architecture for
BaseSafeIntLib.
MdeModulePkg/Logo: Add LoongArch64 architecture.
MdeModulePkg/CapsuleRuntimeDxe: Add LoongArch64 architecture.
MdeModulePkg/DxeIplPeim : LoongArch DxeIPL implementation.
NetworkPkg: Add LoongArch64 architecture.
BaseTools: Add LoongArch64 binding.

.azurepipelines/Ubuntu-GCC5.yml | 3 +-
.pytool/CISettings.py | 5 +-
.pytool/Plugin/SpellCheck/cspell.base.yaml | 4 +-
...gcc_loongarch64_unknown_linux_ext_dep.yaml | 22 ++
BaseTools/Conf/tools_def.template | 54 +++-
.../LinuxGcc5ToolChain/LinuxGcc5ToolChain.py | 31 ++
BaseTools/Source/C/Common/BasePeCoff.c | 15 +-
BaseTools/Source/C/Common/PeCoffLoaderEx.c | 79 +++++
BaseTools/Source/C/GNUmakefile | 3 +
BaseTools/Source/C/GenFv/GenFvInternalLib.c | 125 +++++++-
BaseTools/Source/C/GenFw/Elf64Convert.c | 293 +++++++++++++++++-
BaseTools/Source/C/GenFw/elf_common.h | 94 ++++++
.../C/Include/IndustryStandard/PeImage.h | 57 ++--
.../C/Include/LoongArch64/ProcessorBind.h | 80 +++++
BaseTools/Source/C/Makefiles/header.makefile | 6 +
BaseTools/Source/Python/Common/DataType.py | 21 +-
.../Source/Python/UPT/Library/DataType.py | 24 +-
BaseTools/Source/Python/build/buildoptions.py | 3 +-
CryptoPkg/CryptoPkg.dsc | 3 +-
.../Library/BaseCryptLib/BaseCryptLib.inf | 6 +-
.../Library/BaseCryptLib/RuntimeCryptLib.inf | 4 +
.../BaseCryptLibNull/BaseCryptLibNull.inf | 3 +-
.../BaseCryptLibOnProtocolPpi/DxeCryptLib.inf | 3 +-
.../BaseCryptLibOnProtocolPpi/PeiCryptLib.inf | 3 +-
CryptoPkg/Library/Include/CrtLibSupport.h | 3 +-
CryptoPkg/Library/OpensslLib/OpensslLib.inf | 2 +
.../Library/OpensslLib/OpensslLibCrypto.inf | 2 +
CryptoPkg/Library/TlsLib/TlsLib.inf | 3 +-
CryptoPkg/Library/TlsLibNull/TlsLibNull.inf | 3 +-
FatPkg/FatPkg.dsc | 3 +-
FmpDevicePkg/FmpDevicePkg.dsc | 3 +-
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 6 +-
.../Core/DxeIplPeim/LoongArch64/DxeLoadFunc.c | 63 ++++
MdeModulePkg/Logo/Logo.inf | 3 +-
MdeModulePkg/MdeModulePkg.dsc | 4 +-
.../CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +-
MdePkg/Include/IndustryStandard/Dhcp.h | 45 +--
MdePkg/Include/IndustryStandard/PeImage.h | 9 +
MdePkg/Include/Library/BaseLib.h | 24 ++
MdePkg/Include/LoongArch64/ProcessorBind.h | 120 +++++++
MdePkg/Include/Protocol/DebugSupport.h | 107 ++++++-
MdePkg/Include/Protocol/PxeBaseCode.h | 3 +
MdePkg/Include/Uefi/UefiBaseType.h | 14 +
MdePkg/Include/Uefi/UefiSpec.h | 16 +-
.../BaseCacheMaintenanceLib.inf | 6 +-
.../BaseCacheMaintenanceLib/LoongArchCache.c | 254 +++++++++++++++
MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 7 +-
MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +-
.../BaseCpuLib/LoongArch/CpuFlushTlb.S | 15 +
.../Library/BaseCpuLib/LoongArch/CpuSleep.S | 15 +
.../BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 10 +-
MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c | 3 +-
MdePkg/Library/BaseLib/BaseLib.inf | 16 +-
MdePkg/Library/BaseLib/LoongArch64/Barrier.S | 28 ++
.../BaseLib/LoongArch64/CpuBreakpoint.S | 24 ++
MdePkg/Library/BaseLib/LoongArch64/CpuPause.S | 31 ++
.../BaseLib/LoongArch64/DisableInterrupts.S | 21 ++
.../BaseLib/LoongArch64/EnableInterrupts.S | 21 ++
.../BaseLib/LoongArch64/GetInterruptState.S | 35 +++
.../BaseLib/LoongArch64/InternalSwitchStack.c | 58 ++++
.../Library/BaseLib/LoongArch64/MemoryFence.S | 18 ++
.../BaseLib/LoongArch64/SetJumpLongJump.S | 49 +++
.../Library/BaseLib/LoongArch64/SwitchStack.S | 39 +++
MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +-
.../Library/BasePeCoffLib/BasePeCoffLib.inf | 5 +
.../Library/BasePeCoffLib/BasePeCoffLib.uni | 2 +
.../BasePeCoffLib/LoongArch/PeCoffLoaderEx.c | 137 ++++++++
.../Library/BaseSafeIntLib/BaseSafeIntLib.inf | 9 +-
.../BaseSynchronizationLib.inf | 5 +
.../LoongArch64/Synchronization.c | 246 +++++++++++++++
.../Library/DxeServicesLib/DxeServicesLib.inf | 4 +-
MdePkg/MdePkg.ci.yaml | 13 +
MdePkg/MdePkg.dec | 4 +
MdePkg/MdePkg.dsc | 3 +-
NetworkPkg/HttpBootDxe/HttpBootDhcp4.h | 3 +
NetworkPkg/Network.dsc.inc | 3 +-
NetworkPkg/NetworkPkg.dsc | 3 +-
SecurityPkg/SecurityPkg.dsc | 3 +-
ShellPkg/ShellPkg.dsc | 3 +-
UnitTestFrameworkPkg/UnitTestFrameworkPkg.dsc | 3 +-
80 files changed, 2368 insertions(+), 119 deletions(-)
create mode 100644 BaseTools/Bin/gcc_loongarch64_unknown_linux_ext_dep.yaml
create mode 100644 BaseTools/Source/C/Include/LoongArch64/ProcessorBind.h
create mode 100644 MdeModulePkg/Core/DxeIplPeim/LoongArch64/DxeLoadFunc.c
create mode 100644 MdePkg/Include/LoongArch64/ProcessorBind.h
create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c
create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/CpuFlushTlb.S
create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Barrier.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/CpuPause.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/MemoryFence.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S
create mode 100644 MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S
create mode 100644 MdePkg/Library/BasePeCoffLib/LoongArch/PeCoffLoaderEx.c
create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c

--
2.27.0


[PATCH v2 03/34] FatPkg: Add LOONGARCH64 architecture for EDK2 CI.

Chao Li
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053

Add LOONGARCH64 architecture for EDK2 CI testing.

Cc: Ray Ni <ray.ni@...>

Signed-off-by: Chao Li <lichao@...>
---
FatPkg/FatPkg.dsc | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/FatPkg/FatPkg.dsc b/FatPkg/FatPkg.dsc
index 6fa439e440..076b577972 100644
--- a/FatPkg/FatPkg.dsc
+++ b/FatPkg/FatPkg.dsc
@@ -5,6 +5,7 @@
# for EDK II Prime release.=0D
# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>=
=0D
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ=
ts reserved.<BR>=0D
+# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights=
reserved.<BR>=0D
#=0D
# SPDX-License-Identifier: BSD-2-Clause-Patent=0D
#=0D
@@ -15,7 +16,7 @@
PLATFORM_GUID =3D 25b55dbc-9d0b-4a32-80da-46e1273d622c=
=0D
PLATFORM_VERSION =3D 0.3=0D
DSC_SPECIFICATION =3D 0x00010005=0D
- SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64|RISCV64=0D
+ SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64|RISCV64|LOON=
GARCH64=0D
OUTPUT_DIRECTORY =3D Build/Fat=0D
BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT=0D
SKUID_IDENTIFIER =3D DEFAULT=0D
--=20
2.27.0