Date   

[PATCH v3 3/7] ShellPkg: Update Acpiview PPTT parser to ACPI 6.4

Chris Jones
 

Bugzilla: 3697 (https://bugzilla.tianocore.org/show_bug.cgi?id=3697)

Update the Acpiview PPTT parser to use Acpi64.h. As part of the changes,
remove support for parsing PPTT type 2 ID structure.

Mantis ID for removing PPTT type 2 structure:
2072 (https://mantis.uefi.org/mantis/view.php?id=2072)

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
---
ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c | 61 ++++----------------
ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.c | 2 +-
2 files changed, 12 insertions(+), 51 deletions(-)

diff --git a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c
index f47b92f8c55ba5a479571a0bea378c75dfde13ed..7be249819e70dee9547c3fecc0763f473aa9ce92 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c
@@ -1,11 +1,11 @@
/** @file
PPTT table parser

- Copyright (c) 2019 - 2020, ARM Limited. All rights reserved.
+ Copyright (c) 2019 - 2021, ARM Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

@par Reference(s):
- - ACPI 6.3 Specification - January 2019
+ - ACPI 6.4 Specification - January 2021
- ARM Architecture Reference Manual ARMv8 (D.a)
**/

@@ -161,8 +161,8 @@ ValidateCacheAttributes (
)
{
// Reference: Advanced Configuration and Power Interface (ACPI) Specification
- // Version 6.2 Errata A, September 2017
- // Table 5-153: Cache Type Structure
+ // Version 6.4, January 2021
+ // Table 5-140: Cache Type Structure
UINT8 Attributes;

Attributes = *(UINT8 *)Ptr;
@@ -227,22 +227,6 @@ STATIC CONST ACPI_PARSER CacheTypeStructureParser[] = {
{ L"Line size", 2, 22, L"%d", NULL, NULL, ValidateCacheLineSize, NULL }
};

-/**
- An ACPI_PARSER array describing the ID Type Structure - Type 2.
-**/
-STATIC CONST ACPI_PARSER IdStructureParser[] = {
- { L"Type", 1, 0, L"0x%x", NULL, NULL, NULL, NULL },
- { L"Length", 1, 1, L"%d", NULL, NULL, NULL, NULL },
- { L"Reserved", 2, 2, L"0x%x", NULL, NULL, NULL, NULL },
-
- { L"VENDOR_ID", 4, 4, NULL, Dump4Chars, NULL, NULL, NULL },
- { L"LEVEL_1_ID", 8, 8, L"0x%x", NULL, NULL, NULL, NULL },
- { L"LEVEL_2_ID", 8, 16, L"0x%x", NULL, NULL, NULL, NULL },
- { L"MAJOR_REV", 2, 24, L"0x%x", NULL, NULL, NULL, NULL },
- { L"MINOR_REV", 2, 26, L"0x%x", NULL, NULL, NULL, NULL },
- { L"SPIN_REV", 2, 28, L"0x%x", NULL, NULL, NULL, NULL },
-};
-
/**
This function parses the Processor Hierarchy Node Structure (Type 0).

@@ -340,29 +324,6 @@ DumpCacheTypeStructure (
);
}

-/**
- This function parses the ID Structure (Type 2).
-
- @param [in] Ptr Pointer to the start of the ID Structure data.
- @param [in] Length Length of the ID Structure.
-**/
-STATIC
-VOID
-DumpIDStructure (
- IN UINT8 *Ptr,
- IN UINT8 Length
- )
-{
- ParseAcpi (
- TRUE,
- 2,
- "ID Structure",
- Ptr,
- Length,
- PARSER_PARAMS (IdStructureParser)
- );
-}
-
/**
This function parses the ACPI PPTT table.
When trace is enabled this function parses the PPTT table and
@@ -371,7 +332,6 @@ DumpIDStructure (
This function parses the following processor topology structures:
- Processor hierarchy node structure (Type 0)
- Cache Type Structure (Type 1)
- - ID structure (Type 2)

This function also performs validation of the ACPI table fields.

@@ -451,22 +411,23 @@ ParseAcpiPptt (
Print (L"0x%x\n", Offset);

switch (*ProcessorTopologyStructureType) {
- case EFI_ACPI_6_2_PPTT_TYPE_PROCESSOR:
+ case EFI_ACPI_6_4_PPTT_TYPE_PROCESSOR:
DumpProcessorHierarchyNodeStructure (
ProcessorTopologyStructurePtr,
*ProcessorTopologyStructureLength
);
break;
- case EFI_ACPI_6_2_PPTT_TYPE_CACHE:
+ case EFI_ACPI_6_4_PPTT_TYPE_CACHE:
DumpCacheTypeStructure (
ProcessorTopologyStructurePtr,
*ProcessorTopologyStructureLength
);
break;
- case EFI_ACPI_6_2_PPTT_TYPE_ID:
- DumpIDStructure (
- ProcessorTopologyStructurePtr,
- *ProcessorTopologyStructureLength
+ case EFI_ACPI_6_3_PPTT_TYPE_ID:
+ IncrementErrorCount ();
+ Print (
+ L"ERROR: PPTT Type 2 - Processor ID has been removed and must not be"
+ L"used.\n"
);
break;
default:
diff --git a/ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.c b/ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.c
index 0ad7bf4c845f3c065764680c01eaa27796b09226..09bdddb56e5bd70dec44bdbdcba88373f93daa66 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/UefiShellAcpiViewCommandLib.c
@@ -62,7 +62,7 @@ ACPI_TABLE_PARSER ParserList[] = {
ParseAcpiMcfg },
{ EFI_ACPI_6_4_PLATFORM_COMMUNICATIONS_CHANNEL_TABLE_SIGNATURE,
ParseAcpiPcct },
- { EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ { EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
ParseAcpiPptt },
{ RSDP_TABLE_INFO, ParseAcpiRsdp },
{ EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE, ParseAcpiSlit },
--
Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")


[PATCH v3 6/7] DynamicTablesPkg: Update PPTT generator to ACPI 6.4

Chris Jones
 

Bugzilla: 3697 (https://bugzilla.tianocore.org/show_bug.cgi?id=3697)

Update the PPTT generator to use Acpi64.h.

Signed-off-by: Chris Jones <christopher.jones@arm.com>
---
DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c | 44 ++++++++++----------
1 file changed, 22 insertions(+), 22 deletions(-)

diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c
index 58ad338d339f7f2cf506df961f016edb160f0edc..3d416ca78ec16a1929ede87abbe4f8f4464ef0cf 100644
--- a/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c
@@ -1,11 +1,11 @@
/** @file
PPTT Table Generator

- Copyright (c) 2019, ARM Limited. All rights reserved.
+ Copyright (c) 2021, ARM Limited. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent

@par Reference(s):
- - ACPI 6.3 Specification, January 2019
+ - ACPI 6.4 Specification, January 2021

@par Glossary:
- Cm or CM - Configuration Manager
@@ -96,7 +96,7 @@ GetProcHierarchyNodeSize (
ASSERT (Node != NULL);

// <size of Processor Hierarchy Node> + <size of Private Resources array>
- return sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR) +
+ return sizeof (EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR) +
(Node->NoOfPrivateResources * sizeof (UINT32));
}

@@ -116,7 +116,7 @@ GET_SIZE_OF_PPTT_STRUCTS (
*/
GET_SIZE_OF_PPTT_STRUCTS (
CacheTypeStructs,
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE),
+ sizeof (EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE),
CM_ARM_CACHE_INFO
);

@@ -468,12 +468,12 @@ EFI_STATUS
AddProcHierarchyNodes (
IN CONST ACPI_PPTT_GENERATOR *CONST Generator,
IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST CfgMgrProtocol,
- IN CONST EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER *Pptt,
+ IN CONST EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER *Pptt,
IN CONST UINT32 NodesStartOffset
)
{
EFI_STATUS Status;
- EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *ProcStruct;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR *ProcStruct;
UINT32 *PrivateResources;
BOOLEAN IsGicCTokenDuplicated;

@@ -494,7 +494,7 @@ AddProcHierarchyNodes (
(Pptt != NULL)
);

- ProcStruct = (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)Pptt +
+ ProcStruct = (EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)Pptt +
NodesStartOffset);

ProcNodeIterator = Generator->ProcHierarchyNodeIndexedList;
@@ -538,7 +538,7 @@ AddProcHierarchyNodes (
}

// Populate the node header
- ProcStruct->Type = EFI_ACPI_6_3_PPTT_TYPE_PROCESSOR;
+ ProcStruct->Type = EFI_ACPI_6_4_PPTT_TYPE_PROCESSOR;
ProcStruct->Length = (UINT8)Length;
ProcStruct->Reserved[0] = EFI_ACPI_RESERVED_BYTE;
ProcStruct->Reserved[1] = EFI_ACPI_RESERVED_BYTE;
@@ -661,7 +661,7 @@ AddProcHierarchyNodes (

ProcStruct->NumberOfPrivateResources = ProcInfoNode->NoOfPrivateResources;
PrivateResources = (UINT32 *)((UINT8 *)ProcStruct +
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR));
+ sizeof (EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR));

if (ProcStruct->NumberOfPrivateResources != 0) {
// Populate the private resources array
@@ -684,7 +684,7 @@ AddProcHierarchyNodes (
}

// Next Processor Hierarchy Node
- ProcStruct = (EFI_ACPI_6_3_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)ProcStruct +
+ ProcStruct = (EFI_ACPI_6_4_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)ProcStruct +
ProcStruct->Length);
ProcNodeIterator++;
} // Processor Hierarchy Node
@@ -748,12 +748,12 @@ EFI_STATUS
AddCacheTypeStructures (
IN CONST ACPI_PPTT_GENERATOR *CONST Generator,
IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST CfgMgrProtocol,
- IN CONST EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER *Pptt,
+ IN CONST EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER *Pptt,
IN CONST UINT32 NodesStartOffset
)
{
EFI_STATUS Status;
- EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *CacheStruct;
+ EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE *CacheStruct;
PPTT_NODE_INDEXER *PpttNodeFound;
CM_ARM_CACHE_INFO *CacheInfoNode;
PPTT_NODE_INDEXER *CacheNodeIterator;
@@ -765,7 +765,7 @@ AddCacheTypeStructures (
(Pptt != NULL)
);

- CacheStruct = (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)((UINT8 *)Pptt +
+ CacheStruct = (EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE *)((UINT8 *)Pptt +
NodesStartOffset);

CacheNodeIterator = Generator->CacheStructIndexedList;
@@ -775,13 +775,13 @@ AddCacheTypeStructures (
CacheInfoNode = (CM_ARM_CACHE_INFO *)CacheNodeIterator->Object;

// Populate the node header
- CacheStruct->Type = EFI_ACPI_6_3_PPTT_TYPE_CACHE;
- CacheStruct->Length = sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE);
+ CacheStruct->Type = EFI_ACPI_6_4_PPTT_TYPE_CACHE;
+ CacheStruct->Length = sizeof (EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE);
CacheStruct->Reserved[0] = EFI_ACPI_RESERVED_BYTE;
CacheStruct->Reserved[1] = EFI_ACPI_RESERVED_BYTE;

// "On Arm-based systems, all cache properties must be provided in the
- // table." (ACPI 6.3, Section 5.2.29.2)
+ // table." (ACPI 6.4, Section 5.2.29.2)
CacheStruct->Flags.SizePropertyValid = 1;
CacheStruct->Flags.NumberOfSetsValid = 1;
CacheStruct->Flags.AssociativityValid = 1;
@@ -941,7 +941,7 @@ AddCacheTypeStructures (
CacheStruct->LineSize = CacheInfoNode->LineSize;

// Next Cache Type Structure
- CacheStruct = (EFI_ACPI_6_3_PPTT_STRUCTURE_CACHE *)((UINT8 *)CacheStruct +
+ CacheStruct = (EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE *)((UINT8 *)CacheStruct +
CacheStruct->Length);
CacheNodeIterator++;
} // Cache Type Structure
@@ -999,7 +999,7 @@ BuildPpttTable (
// Pointer to the Node Indexer array
PPTT_NODE_INDEXER *NodeIndexer;

- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER *Pptt;
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER *Pptt;

ASSERT (
(This != NULL) &&
@@ -1087,7 +1087,7 @@ BuildPpttTable (
Generator->NodeIndexer = NodeIndexer;

// Calculate the size of the PPTT table
- TableSize = sizeof (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER);
+ TableSize = sizeof (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER);

// Include the size of Processor Hierarchy Nodes and index them
if (Generator->ProcHierarchyNodeCount != 0) {
@@ -1155,7 +1155,7 @@ BuildPpttTable (
goto error_handler;
}

- Pptt = (EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER *)*Table;
+ Pptt = (EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER *)*Table;

DEBUG ((
DEBUG_INFO,
@@ -1312,9 +1312,9 @@ ACPI_PPTT_GENERATOR PpttGenerator = {
// Generator Description
L"ACPI.STD.PPTT.GENERATOR",
// ACPI Table Signature
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
// ACPI Table Revision supported by this Generator
- EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION,
+ EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION,
// Minimum supported ACPI Table Revision
EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION,
// Creator ID
--
Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")


[PATCH v3 0/7] Support ACPI 6.4 PPTT changes

Chris Jones
 

Bugzilla: 3697 (https://bugzilla.tianocore.org/show_bug.cgi?id=3697)

This patch series updates the Acpiview PPTT parser and DynamicTablesPkg
PPTT generator to support ACPI 6.4. This consists of two main changes:
- The addition of the 'Cache ID' field.
- The removal of the PPTT ID (type 2) structure.

In addition add two 'Cache ID' defines and remove the type 2 PPTT
structure from Acpi64.h as these changes were missing when Acpi64.h was
introduced.

Changes since v2:
1. Added mantis ID for PPTT type 2 structure removal on relevant commit
messages. No change to code.
2. Applied uncrustify to all patches. No other changes to code.

Changes since v1:
1. Patch 3/7 ShellPkg:
- Changed PPTT ID error message to say "removed" instead of "deprecated".
2. Patch 4/7 ShellPkg:
- Fixed a bug where 'CacheFlags' and 'CacheId' were only set after the
validation function had finished. Instead set them inside the
validation function using the first 'Ptr' parameter.
3. Patch 7/7 DynamicTablesPkg:
- Make IsCacheIdUnique() return BOOLEAN instead of EFI_STATUS.
- Added a missing space to the definition of 'IsCacheIdUnique'.

The changes can be seen at: https://github.com/chris-jones-arm/edk2/tree/1632_64_acpi_cache_id_v3


Chris Jones (7):
MdePkg: Add missing Cache ID (in)valid define
MdePkg: Remove PPTT ID type structure
ShellPkg: Update Acpiview PPTT parser to ACPI 6.4
ShellPkg: Add Cache ID to PPTT parser
DynamicTablesPkg: Remove PPTT ID structure from ACPI 6.4 generator
DynamicTablesPkg: Update PPTT generator to ACPI 6.4
DynamicTablesPkg: Add CacheId to PPTT generator

.../Include/ArmNameSpaceObjects.h | 27 +-
.../Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c | 296 +++++++-----------
.../Acpi/Arm/AcpiPpttLibArm/PpttGenerator.h | 4 -
MdePkg/Include/IndustryStandard/Acpi64.h | 18 +-
.../Parsers/Pptt/PpttParser.c | 214 +++++++++----
.../UefiShellAcpiViewCommandLib.c | 2 +-
6 files changed, 272 insertions(+), 289 deletions(-)

--
Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")


[PATCH v3 7/7] DynamicTablesPkg: Add CacheId to PPTT generator

Chris Jones
 

Bugzilla: 3697 (https://bugzilla.tianocore.org/show_bug.cgi?id=3697)

Update the PPTT generator with the CacheId field as defined in table
5.140 of the ACPI 6.4 specification.

Also add validations to ensure that the cache id generated is unique.

Signed-off-by: Chris Jones <christopher.jones@arm.com>
---
DynamicTablesPkg/Include/ArmNameSpaceObjects.h | 4 +-
DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c | 102 ++++++++++++++++++--
2 files changed, 96 insertions(+), 10 deletions(-)

diff --git a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h b/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
index 3246e8884723ac85340bf880a3859800726be3c1..6ea03fca487b96577b8fd8105bc3d22047ff5697 100644
--- a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
+++ b/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
@@ -741,10 +741,12 @@ typedef struct CmArmCacheInfo {
/// PPTT_ARM_CCIDX_CACHE_ASSOCIATIVITY_MAX. Therfore this field
/// is 32-bit wide.
UINT32 Associativity;
- /// Cache attributes (ACPI 6.3 - January 2019, PPTT, Table 5-156)
+ /// Cache attributes (ACPI 6.4 - January 2021, PPTT, Table 5.140)
UINT8 Attributes;
/// Line size in bytes
UINT16 LineSize;
+ /// Unique ID for the cache
+ UINT32 CacheId;
} CM_ARM_CACHE_INFO;

/** A structure that describes a reference to another Configuration Manager
diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c
index 3d416ca78ec16a1929ede87abbe4f8f4464ef0cf..6b74572ea2dd8478f14d013e6cb7394216e45d8d 100644
--- a/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c
@@ -726,6 +726,35 @@ AddProcHierarchyNodes (
return Status;
}

+/**
+ Test whether CacheId is unique among the CacheIdList.
+
+ @param [in] CacheId Cache ID to check.
+ @param [in] CacheIdList List of already existing cache IDs.
+ @param [in] CacheIdListSize Size of CacheIdList.
+
+ @retval TRUE CacheId does not exist in CacheIdList.
+ @retval FALSE CacheId already exists in CacheIdList.
+**/
+STATIC
+BOOLEAN
+IsCacheIdUnique (
+ IN CONST UINT32 CacheId,
+ IN CONST UINT32 *CacheIdList,
+ IN CONST UINT32 CacheIdListSize
+ )
+{
+ UINT32 Index;
+
+ for (Index = 0; Index < CacheIdListSize; Index++) {
+ if (CacheIdList[Index] == CacheId) {
+ return FALSE;
+ }
+ }
+
+ return TRUE;
+}
+
/**
Update the Cache Type Structure (Type 1) information.

@@ -738,10 +767,12 @@ AddProcHierarchyNodes (
@param [in] Pptt Pointer to PPTT table structure.
@param [in] NodesStartOffset Offset from the start of PPTT table to the
start of Cache Type Structures.
+ @param [in] Revision Revision of the PPTT table being requested.

@retval EFI_SUCCESS Structures updated successfully.
@retval EFI_INVALID_PARAMETER A parameter is invalid.
@retval EFI_NOT_FOUND A required object was not found.
+ @retval EFI_OUT_OF_RESOURCES Out of resources.
**/
STATIC
EFI_STATUS
@@ -749,7 +780,8 @@ AddCacheTypeStructures (
IN CONST ACPI_PPTT_GENERATOR *CONST Generator,
IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST CfgMgrProtocol,
IN CONST EFI_ACPI_6_4_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER *Pptt,
- IN CONST UINT32 NodesStartOffset
+ IN CONST UINT32 NodesStartOffset,
+ IN CONST UINT32 Revision
)
{
EFI_STATUS Status;
@@ -758,6 +790,9 @@ AddCacheTypeStructures (
CM_ARM_CACHE_INFO *CacheInfoNode;
PPTT_NODE_INDEXER *CacheNodeIterator;
UINT32 NodeCount;
+ BOOLEAN CacheIdUnique;
+ UINT32 TotalNodeCount;
+ UINT32 *FoundCacheIds;

ASSERT (
(Generator != NULL) &&
@@ -770,6 +805,13 @@ AddCacheTypeStructures (

CacheNodeIterator = Generator->CacheStructIndexedList;
NodeCount = Generator->CacheStructCount;
+ TotalNodeCount = NodeCount;
+
+ FoundCacheIds = AllocateZeroPool (TotalNodeCount * sizeof (*FoundCacheIds));
+ if (FoundCacheIds == NULL) {
+ DEBUG ((DEBUG_ERROR, "ERROR: PPTT: Failed to allocate resources.\n"));
+ return EFI_OUT_OF_RESOURCES;
+ }

while (NodeCount-- != 0) {
CacheInfoNode = (CM_ARM_CACHE_INFO *)CacheNodeIterator->Object;
@@ -789,6 +831,7 @@ AddCacheTypeStructures (
CacheStruct->Flags.CacheTypeValid = 1;
CacheStruct->Flags.WritePolicyValid = 1;
CacheStruct->Flags.LineSizeValid = 1;
+ CacheStruct->Flags.CacheIdValid = 1;
CacheStruct->Flags.Reserved = 0;

// Populate the reference to the next level of cache
@@ -811,7 +854,7 @@ AddCacheTypeStructures (
CacheInfoNode->Token,
Status
));
- return Status;
+ goto cleanup;
}

// Update Cache Structure with the offset for the next level of cache
@@ -835,7 +878,7 @@ AddCacheTypeStructures (
CacheInfoNode->NumberOfSets,
Status
));
- return Status;
+ goto cleanup;
}

if (CacheInfoNode->NumberOfSets > PPTT_ARM_CACHE_NUMBER_OF_SETS_MAX) {
@@ -862,7 +905,7 @@ AddCacheTypeStructures (
CacheInfoNode->Associativity,
Status
));
- return Status;
+ goto cleanup;
}

// Validate the Associativity field based on the architecture specification
@@ -881,7 +924,7 @@ AddCacheTypeStructures (
CacheInfoNode->Associativity,
Status
));
- return Status;
+ goto cleanup;
}

if (CacheInfoNode->Associativity > PPTT_ARM_CACHE_ASSOCIATIVITY_MAX) {
@@ -923,7 +966,7 @@ AddCacheTypeStructures (
CacheInfoNode->LineSize,
Status
));
- return Status;
+ goto cleanup;
}

if ((CacheInfoNode->LineSize & (CacheInfoNode->LineSize - 1)) != 0) {
@@ -935,18 +978,58 @@ AddCacheTypeStructures (
CacheInfoNode->LineSize,
Status
));
- return Status;
+ goto cleanup;
}

CacheStruct->LineSize = CacheInfoNode->LineSize;

+ if (Revision >= 3) {
+ // Validate and populate cache id
+ if (CacheInfoNode->CacheId == 0) {
+ Status = EFI_INVALID_PARAMETER;
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: PPTT: The cache id cannot be zero. Status = %r\n",
+ Status
+ ));
+ goto cleanup;
+ }
+
+ CacheIdUnique = IsCacheIdUnique (
+ CacheInfoNode->CacheId,
+ FoundCacheIds,
+ TotalNodeCount
+ );
+ if (!CacheIdUnique) {
+ Status = EFI_INVALID_PARAMETER;
+ DEBUG ((
+ DEBUG_ERROR,
+ "ERROR: PPTT: The cache id is not unique. " \
+ "CacheId = %d. Status = %r\n",
+ CacheInfoNode->CacheId,
+ Status
+ ));
+ goto cleanup;
+ }
+
+ // Store the cache id so we can check future cache ids for uniqueness
+ FoundCacheIds[NodeCount] = CacheInfoNode->CacheId;
+
+ CacheStruct->CacheId = CacheInfoNode->CacheId;
+ }
+
// Next Cache Type Structure
CacheStruct = (EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE *)((UINT8 *)CacheStruct +
CacheStruct->Length);
CacheNodeIterator++;
} // Cache Type Structure

- return EFI_SUCCESS;
+ Status = EFI_SUCCESS;
+
+cleanup:
+ FreePool (FoundCacheIds);
+
+ return Status;
}

/**
@@ -1205,7 +1288,8 @@ BuildPpttTable (
Generator,
CfgMgrProtocol,
Pptt,
- CacheStructOffset
+ CacheStructOffset,
+ AcpiTableInfo->AcpiTableRevision
);
if (EFI_ERROR (Status)) {
DEBUG ((
--
Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")


[PATCH v3 5/7] DynamicTablesPkg: Remove PPTT ID structure from ACPI 6.4 generator

Chris Jones
 

Bugzilla: 3697 (https://bugzilla.tianocore.org/show_bug.cgi?id=3697)

ACPI 6.3A deprecated PPTT ID (type 2) structure which was subsequently
removed in ACPI 6.4. Therefore remove support for generating PPTT ID
structures.

Mantis ID for removing PPTT type 2 structure:
2072 (https://mantis.uefi.org/mantis/view.php?id=2072)

Signed-off-by: Chris Jones <christopher.jones@arm.com>
---
DynamicTablesPkg/Include/ArmNameSpaceObjects.h | 23 +--
DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c | 154 +-------------------
DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.h | 4 -
3 files changed, 3 insertions(+), 178 deletions(-)

diff --git a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h b/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
index 22b37edfabd1f6a1d1a3015f4a0249c28489367c..3246e8884723ac85340bf880a3859800726be3c1 100644
--- a/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
+++ b/DynamicTablesPkg/Include/ArmNameSpaceObjects.h
@@ -50,7 +50,7 @@ typedef enum ArmObjectID {
EArmObjSmmuInterruptArray, ///< 26 - SMMU Interrupt Array
EArmObjProcHierarchyInfo, ///< 27 - Processor Hierarchy Info
EArmObjCacheInfo, ///< 28 - Cache Info
- EArmObjProcNodeIdInfo, ///< 29 - Processor Node ID Info
+ EArmObjReserved29, ///< 29 - Reserved
EArmObjCmRef, ///< 30 - CM Object Reference
EArmObjMemoryAffinityInfo, ///< 31 - Memory Affinity Info
EArmObjDeviceHandleAcpi, ///< 32 - Device Handle Acpi
@@ -747,27 +747,6 @@ typedef struct CmArmCacheInfo {
UINT16 LineSize;
} CM_ARM_CACHE_INFO;

-/** A structure that describes the ID Structure (Type 2) in PPTT
-
- ID: EArmObjProcNodeIdInfo
-*/
-typedef struct CmArmProcNodeIdInfo {
- /// A unique token used to identify this object
- CM_OBJECT_TOKEN Token;
- // Vendor ID (as described in ACPI ID registry)
- UINT32 VendorId;
- /// First level unique node ID
- UINT64 Level1Id;
- /// Second level unique node ID
- UINT64 Level2Id;
- /// Major revision of the node
- UINT16 MajorRev;
- /// Minor revision of the node
- UINT16 MinorRev;
- /// Spin revision of the node
- UINT16 SpinRev;
-} CM_ARM_PROC_NODE_ID_INFO;
-
/** A structure that describes a reference to another Configuration Manager
object.

diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c
index f78bbed7c1beee4211752bba94ce531a84e84f10..58ad338d339f7f2cf506df961f016edb160f0edc 100644
--- a/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.c
@@ -34,7 +34,6 @@
The following Configuration Manager Object(s) are used by this Generator:
- EArmObjProcHierarchyInfo (REQUIRED)
- EArmObjCacheInfo
- - EArmObjProcNodeIdInfo
- EArmObjCmRef
- EArmObjGicCInfo (REQUIRED)
*/
@@ -59,16 +58,6 @@ GET_OBJECT_LIST (
CM_ARM_CACHE_INFO
);

-/**
- This macro expands to a function that retrieves the ID information for
- Processor Hierarchy Nodes from the Configuration Manager.
-*/
-GET_OBJECT_LIST (
- EObjNameSpaceArm,
- EArmObjProcNodeIdInfo,
- CM_ARM_PROC_NODE_ID_INFO
- );
-
/**
This macro expands to a function that retrieves the cross-CM-object-
reference information from the Configuration Manager.
@@ -131,15 +120,6 @@ GET_SIZE_OF_PPTT_STRUCTS (
CM_ARM_CACHE_INFO
);

-/** This macro expands to a function that retrieves the amount of memory
- required to store the ID Structures (Type 2) and updates the Node Indexer.
-*/
-GET_SIZE_OF_PPTT_STRUCTS (
- IdStructs,
- sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_ID),
- CM_ARM_PROC_NODE_ID_INFO
- );
-
/**
Search the Node Indexer and return the indexed PPTT node with the given
Token.
@@ -373,8 +353,8 @@ AddPrivateResources (
}

// The Node indexer has the Processor hierarchy nodes at the begining
- // followed by the cache structs and Id structs. Therefore we can
- // skip the Processor hierarchy nodes in the node indexer search.
+ // followed by the cache structs. Therefore we can skip the Processor
+ // hierarchy nodes in the node indexer search.
Status = GetPpttNodeReferencedByToken (
Generator->CacheStructIndexedList,
(Generator->ProcTopologyStructCount -
@@ -969,71 +949,6 @@ AddCacheTypeStructures (
return EFI_SUCCESS;
}

-/**
- Update the ID Type Structure (Type 2) information.
-
- This function populates the ID Type Structures with information from
- the Configuration Manager and and adds this information to the PPTT table.
-
- @param [in] Generator Pointer to the PPTT Generator.
- @param [in] CfgMgrProtocol Pointer to the Configuration Manager
- Protocol Interface.
- @param [in] Pptt Pointer to PPTT table structure.
- @param [in] NodesStartOffset Offset from the start of PPTT table to the
- start of ID Type Structures.
-
- @retval EFI_SUCCESS Structures updated successfully.
- @retval EFI_INVALID_PARAMETER A parameter is invalid.
- @retval EFI_NOT_FOUND A required object was not found.
-**/
-STATIC
-EFI_STATUS
-AddIdTypeStructures (
- IN CONST ACPI_PPTT_GENERATOR *CONST Generator,
- IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST CfgMgrProtocol,
- IN CONST EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_HEADER *Pptt,
- IN CONST UINT32 NodesStartOffset
- )
-{
- EFI_ACPI_6_3_PPTT_STRUCTURE_ID *IdStruct;
- CM_ARM_PROC_NODE_ID_INFO *ProcIdInfoNode;
- PPTT_NODE_INDEXER *IdStructIterator;
- UINT32 NodeCount;
-
- ASSERT (
- (Generator != NULL) &&
- (CfgMgrProtocol != NULL) &&
- (Pptt != NULL)
- );
-
- IdStruct = (EFI_ACPI_6_3_PPTT_STRUCTURE_ID *)((UINT8 *)Pptt + NodesStartOffset);
-
- IdStructIterator = Generator->IdStructIndexedList;
- NodeCount = Generator->IdStructCount;
- while (NodeCount-- != 0) {
- ProcIdInfoNode = (CM_ARM_PROC_NODE_ID_INFO *)IdStructIterator->Object;
-
- // Populate the node
- IdStruct->Type = EFI_ACPI_6_3_PPTT_TYPE_ID;
- IdStruct->Length = sizeof (EFI_ACPI_6_3_PPTT_STRUCTURE_ID);
- IdStruct->Reserved[0] = EFI_ACPI_RESERVED_BYTE;
- IdStruct->Reserved[1] = EFI_ACPI_RESERVED_BYTE;
- IdStruct->VendorId = ProcIdInfoNode->VendorId;
- IdStruct->Level1Id = ProcIdInfoNode->Level1Id;
- IdStruct->Level2Id = ProcIdInfoNode->Level2Id;
- IdStruct->MajorRev = ProcIdInfoNode->MajorRev;
- IdStruct->MinorRev = ProcIdInfoNode->MinorRev;
- IdStruct->SpinRev = ProcIdInfoNode->SpinRev;
-
- // Next ID Type Structure
- IdStruct = (EFI_ACPI_6_3_PPTT_STRUCTURE_ID *)((UINT8 *)IdStruct +
- IdStruct->Length);
- IdStructIterator++;
- } // ID Type Structure
-
- return EFI_SUCCESS;
-}
-
/**
Construct the PPTT ACPI table.

@@ -1072,15 +987,12 @@ BuildPpttTable (
UINT32 ProcTopologyStructCount;
UINT32 ProcHierarchyNodeCount;
UINT32 CacheStructCount;
- UINT32 IdStructCount;

UINT32 ProcHierarchyNodeOffset;
UINT32 CacheStructOffset;
- UINT32 IdStructOffset;

CM_ARM_PROC_HIERARCHY_INFO *ProcHierarchyNodeList;
CM_ARM_CACHE_INFO *CacheStructList;
- CM_ARM_PROC_NODE_ID_INFO *IdStructList;

ACPI_PPTT_GENERATOR *Generator;

@@ -1155,27 +1067,6 @@ BuildPpttTable (
ProcTopologyStructCount += CacheStructCount;
Generator->CacheStructCount = CacheStructCount;

- // Get the processor hierarchy node ID info and update the processor topology
- // structure count with ID Structures (Type 2)
- Status = GetEArmObjProcNodeIdInfo (
- CfgMgrProtocol,
- CM_NULL_TOKEN,
- &IdStructList,
- &IdStructCount
- );
- if (EFI_ERROR (Status) && (Status != EFI_NOT_FOUND)) {
- DEBUG ((
- DEBUG_ERROR,
- "ERROR: PPTT: Failed to get processor hierarchy node ID info. " \
- "Status = %r\n",
- Status
- ));
- goto error_handler;
- }
-
- ProcTopologyStructCount += IdStructCount;
- Generator->IdStructCount = IdStructCount;
-
// Allocate Node Indexer array
NodeIndexer = (PPTT_NODE_INDEXER *)AllocateZeroPool (
sizeof (PPTT_NODE_INDEXER) *
@@ -1241,27 +1132,6 @@ BuildPpttTable (
));
}

- // Include the size of ID Type Structures and index them
- if (Generator->IdStructCount != 0) {
- IdStructOffset = TableSize;
- Generator->IdStructIndexedList = NodeIndexer;
- TableSize += GetSizeofIdStructs (
- IdStructOffset,
- IdStructList,
- Generator->IdStructCount,
- &NodeIndexer
- );
- DEBUG ((
- DEBUG_INFO,
- " IdStructCount = %d\n" \
- " IdStructOffset = 0x%x\n" \
- " IdStructIndexedList = 0x%p\n",
- Generator->IdStructCount,
- IdStructOffset,
- Generator->IdStructIndexedList
- ));
- }
-
DEBUG ((
DEBUG_INFO,
"INFO: PPTT:\n" \
@@ -1347,24 +1217,6 @@ BuildPpttTable (
}
}

- // Add ID Type Structures (Type 2) to the generated table
- if (Generator->IdStructCount != 0) {
- Status = AddIdTypeStructures (
- Generator,
- CfgMgrProtocol,
- Pptt,
- IdStructOffset
- );
- if (EFI_ERROR (Status)) {
- DEBUG ((
- DEBUG_ERROR,
- "ERROR: PPTT: Failed to add ID Type Structures. Status = %r\n",
- Status
- ));
- goto error_handler;
- }
- }
-
// Validate CM object cross-references in PPTT
Status = DetectCyclesInTopology (Generator);
if (EFI_ERROR (Status)) {
@@ -1488,8 +1340,6 @@ ACPI_PPTT_GENERATOR PpttGenerator = {
0,
// Count of Cache Structures
0,
- // Count of Id Structures
- 0,
// Pointer to PPTT Node Indexer
NULL
};
diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.h b/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.h
index f587e67e9f8bf51511c6187ba0384e1cb60661d5..15b0a9871c3d555a62b79595c317e6597f6ead05 100644
--- a/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.h
+++ b/DynamicTablesPkg/Library/Acpi/Arm/AcpiPpttLibArm/PpttGenerator.h
@@ -171,8 +171,6 @@ typedef struct AcpiPpttGenerator {
UINT32 ProcHierarchyNodeCount;
/// Count of Cache Structures
UINT32 CacheStructCount;
- /// Count of Id Structures
- UINT32 IdStructCount;
/// List of indexed CM objects for PPTT generation
PPTT_NODE_INDEXER *NodeIndexer;
/// Pointer to the start of Processor Hierarchy nodes in
@@ -180,8 +178,6 @@ typedef struct AcpiPpttGenerator {
PPTT_NODE_INDEXER *ProcHierarchyNodeIndexedList;
/// Pointer to the start of Cache Structures in the Node Indexer array
PPTT_NODE_INDEXER *CacheStructIndexedList;
- /// Pointer to the start of Id Structures in the Node Indexer array
- PPTT_NODE_INDEXER *IdStructIndexedList;
} ACPI_PPTT_GENERATOR;

#pragma pack()
--
Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")


[PATCH v3 4/7] ShellPkg: Add Cache ID to PPTT parser

Chris Jones
 

Bugzilla: 3697 (https://bugzilla.tianocore.org/show_bug.cgi?id=3697)

Update the Acpiview PPTT parser with the Cache ID field and relevant
validations as defined in tables 5.140 and 5.141 of the ACPI 6.4
specification.

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
---
ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c | 153 ++++++++++++++++++--
1 file changed, 139 insertions(+), 14 deletions(-)

diff --git a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c
index 7be249819e70dee9547c3fecc0763f473aa9ce92..8b12809f8a155b0ee0a4ad5c63d620b48d97f4b0 100644
--- a/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c
+++ b/ShellPkg/Library/UefiShellAcpiViewCommandLib/Parsers/Pptt/PpttParser.c
@@ -17,10 +17,94 @@
#include "PpttParser.h"

// Local variables
-STATIC CONST UINT8 *ProcessorTopologyStructureType;
-STATIC CONST UINT8 *ProcessorTopologyStructureLength;
-STATIC CONST UINT32 *NumberOfPrivateResources;
-STATIC ACPI_DESCRIPTION_HEADER_INFO AcpiHdrInfo;
+STATIC CONST UINT8 *ProcessorTopologyStructureType;
+STATIC CONST UINT8 *ProcessorTopologyStructureLength;
+STATIC CONST UINT32 *NumberOfPrivateResources;
+STATIC CONST EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS *CacheFlags;
+STATIC ACPI_DESCRIPTION_HEADER_INFO AcpiHdrInfo;
+
+/**
+ Increment the error count and print an error that a required flag is missing.
+
+ @param [in] FlagName Name of the missing flag.
+**/
+STATIC
+VOID
+EFIAPI
+LogCacheFlagError (
+ IN CONST CHAR16 *FlagName
+ )
+{
+ IncrementErrorCount ();
+ Print (
+ L"\nERROR: On Arm based systems, all cache properties must be"
+ L"provided in the cache type structure."
+ L"Missing '%s' flag.",
+ *FlagName
+ );
+}
+
+/**
+ This function validates the Cache Type Structure (Type 1) Cache Flags field.
+
+ @param [in] Ptr Pointer to the start of the field data.
+ @param [in] Context Pointer to context specific information e.g. this
+ could be a pointer to the ACPI table header.
+**/
+STATIC
+VOID
+EFIAPI
+ValidateCacheFlags (
+ IN UINT8 *Ptr,
+ IN VOID *Context
+ )
+{
+ #if defined (MDE_CPU_ARM) || defined (MDE_CPU_AARCH64)
+ CacheFlags = (EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS *)Ptr;
+
+ if (CacheFlags == NULL) {
+ IncrementErrorCount ();
+ Print (L"\nERROR: Cache Structure Flags were not successfully read.");
+ return;
+ }
+
+ if (CacheFlags->SizePropertyValid == EFI_ACPI_6_4_PPTT_CACHE_SIZE_INVALID) {
+ LogCacheFlagError (L"Size Property Valid");
+ }
+
+ if (CacheFlags->NumberOfSetsValid == EFI_ACPI_6_4_PPTT_NUMBER_OF_SETS_INVALID) {
+ LogCacheFlagError (L"Number Of Sets Valid");
+ }
+
+ if (CacheFlags->AssociativityValid == EFI_ACPI_6_4_PPTT_ASSOCIATIVITY_INVALID) {
+ LogCacheFlagError (L"Associativity Valid");
+ }
+
+ if (CacheFlags->AllocationTypeValid == EFI_ACPI_6_4_PPTT_ALLOCATION_TYPE_INVALID) {
+ LogCacheFlagError (L"Allocation Type Valid");
+ }
+
+ if (CacheFlags->CacheTypeValid == EFI_ACPI_6_4_PPTT_CACHE_TYPE_INVALID) {
+ LogCacheFlagError (L"Cache Type Valid");
+ }
+
+ if (CacheFlags->WritePolicyValid == EFI_ACPI_6_4_PPTT_WRITE_POLICY_INVALID) {
+ LogCacheFlagError (L"Write Policy Valid");
+ }
+
+ if (CacheFlags->LineSizeValid == EFI_ACPI_6_4_PPTT_LINE_SIZE_INVALID) {
+ LogCacheFlagError (L"Line Size Valid");
+ }
+
+ // Cache ID was only introduced in revision 3
+ if (*(AcpiHdrInfo.Revision) >= 3) {
+ if (CacheFlags->CacheIdValid == EFI_ACPI_6_4_PPTT_CACHE_ID_INVALID) {
+ LogCacheFlagError (L"Cache Id Valid");
+ }
+ }
+
+ #endif
+}

/**
This function validates the Cache Type Structure (Type 1) 'Number of sets'
@@ -145,6 +229,45 @@ ValidateCacheLineSize (
#endif
}

+/**
+ This function validates the Cache Type Structure (Type 1) Cache ID field.
+
+ @param [in] Ptr Pointer to the start of the field data.
+ @param [in] Context Pointer to context specific information e.g. this
+ could be a pointer to the ACPI table header.
+**/
+STATIC
+VOID
+EFIAPI
+ValidateCacheId (
+ IN UINT8 *Ptr,
+ IN VOID *Context
+ )
+{
+ UINT32 CacheId;
+
+ CacheId = *(UINT32 *)Ptr;
+
+ // Cache ID was only introduced in revision 3
+ if (*(AcpiHdrInfo.Revision) < 3) {
+ return;
+ }
+
+ if (CacheFlags == NULL) {
+ IncrementErrorCount ();
+ Print (L"\nERROR: Cache Structure Flags were not successfully read.");
+ return;
+ }
+
+ if (CacheFlags->CacheIdValid == EFI_ACPI_6_4_PPTT_CACHE_ID_VALID) {
+ if (CacheId == 0) {
+ IncrementErrorCount ();
+ Print (L"\nERROR: 0 is not a valid Cache ID.");
+ return;
+ }
+ }
+}
+
/**
This function validates the Cache Type Structure (Type 1) Attributes field.

@@ -214,17 +337,19 @@ STATIC CONST ACPI_PARSER ProcessorHierarchyNodeStructureParser[] = {
An ACPI_PARSER array describing the Cache Type Structure - Type 1.
**/
STATIC CONST ACPI_PARSER CacheTypeStructureParser[] = {
- { L"Type", 1, 0, L"0x%x", NULL, NULL, NULL, NULL },
- { L"Length", 1, 1, L"%d", NULL, NULL, NULL, NULL },
- { L"Reserved", 2, 2, L"0x%x", NULL, NULL, NULL, NULL },
+ { L"Type", 1, 0, L"0x%x", NULL, NULL, NULL, NULL },
+ { L"Length", 1, 1, L"%d", NULL, NULL, NULL, NULL },
+ { L"Reserved", 2, 2, L"0x%x", NULL, NULL, NULL, NULL },

- { L"Flags", 4, 4, L"0x%x", NULL, NULL, NULL, NULL },
- { L"Next Level of Cache", 4, 8, L"0x%x", NULL, NULL, NULL, NULL },
- { L"Size", 4, 12, L"0x%x", NULL, NULL, NULL, NULL },
- { L"Number of sets", 4, 16, L"%d", NULL, NULL, ValidateCacheNumberOfSets, NULL },
- { L"Associativity", 1, 20, L"%d", NULL, NULL, ValidateCacheAssociativity, NULL },
- { L"Attributes", 1, 21, L"0x%x", NULL, NULL, ValidateCacheAttributes, NULL },
- { L"Line size", 2, 22, L"%d", NULL, NULL, ValidateCacheLineSize, NULL }
+ { L"Flags", 4, 4, L"0x%x", NULL, (VOID **)&CacheFlags, ValidateCacheFlags,
+ NULL },
+ { L"Next Level of Cache", 4, 8, L"0x%x", NULL, NULL, NULL, NULL },
+ { L"Size", 4, 12, L"0x%x", NULL, NULL, NULL, NULL },
+ { L"Number of sets", 4, 16, L"%d", NULL, NULL, ValidateCacheNumberOfSets, NULL },
+ { L"Associativity", 1, 20, L"%d", NULL, NULL, ValidateCacheAssociativity, NULL },
+ { L"Attributes", 1, 21, L"0x%x", NULL, NULL, ValidateCacheAttributes, NULL },
+ { L"Line size", 2, 22, L"%d", NULL, NULL, ValidateCacheLineSize, NULL },
+ { L"Cache ID", 4, 24, L"%d", NULL, NULL, ValidateCacheId, NULL }
};

/**
--
Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")


[PATCH v3 1/7] MdePkg: Add missing Cache ID (in)valid define

Chris Jones
 

Bugzilla: 3697 (https://bugzilla.tianocore.org/show_bug.cgi?id=3697)

Add Cache ID valid/invalid defines to Acpi64.h which were not initially
added when the CacheIdValid field was added to
EFI_ACPI_6_4_PPTT_STRUCTURE_CACHE_FLAGS.

Signed-off-by: Chris Jones <christopher.jones@arm.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
Reviewed-by: Zhichao Gao <zhichao.gao@intel.com>
---
MdePkg/Include/IndustryStandard/Acpi64.h | 2 ++
1 file changed, 2 insertions(+)

diff --git a/MdePkg/Include/IndustryStandard/Acpi64.h b/MdePkg/Include/IndustryStandard/Acpi64.h
index 9cdd35b563fa8a181084f4f1b243793ae467ad6a..ff3cb441c215550f7cc635ced0f58e00d6510163 100644
--- a/MdePkg/Include/IndustryStandard/Acpi64.h
+++ b/MdePkg/Include/IndustryStandard/Acpi64.h
@@ -2680,6 +2680,8 @@ typedef struct {
#define EFI_ACPI_6_4_PPTT_WRITE_POLICY_VALID 0x1
#define EFI_ACPI_6_4_PPTT_LINE_SIZE_INVALID 0x0
#define EFI_ACPI_6_4_PPTT_LINE_SIZE_VALID 0x1
+#define EFI_ACPI_6_4_PPTT_CACHE_ID_INVALID 0x0
+#define EFI_ACPI_6_4_PPTT_CACHE_ID_VALID 0x1

///
/// Cache Type Structure flags
--
Guid("CE165669-3EF3-493F-B85D-6190EE5B9759")


Re: Looking for latest edk2 dev tools for win32

Pedro Falcato
 

Hi,

When I set up my Windows dev environment a month or two ago, I followed the following guide: https://github.com/tianocore/tianocore.github.io/wiki/Windows-systems#compile-tools

This should probably still work.

Best regards,
Pedro 

On Wed, Dec 8, 2021 at 3:07 PM Rao G <grao.v80@...> wrote:
Hi All,

The below tools does not seem to be latest
https://github.com/tianocore/edk2-BaseTools-win32

Older Genffs.exe does not understand -oi option

GenFfs -t EFI_FV_FILETYPE_PEIM -g AAC33064-9ED0-4b89-A5AD-3EA767960B22 -o c:\edk2\Build\EmulatorIA32\DEBUG_VS2012x86\FV\Ffs\AAC33064-9ED0-4b89-A5AD-3EA767960B22FaultTolerantWritePei\AAC33064-9ED0-4b89-A5AD-3EA767960B22.ffs -oi c:\edk2\Build\EmulatorIA32\DEBUG_VS2012x86\FV\Ffs\AAC33064-9ED0-4b89-A5AD-3EA767960B22FaultTolerantWritePei\AAC33064-9ED0-4b89-A5AD-3EA767960B22SEC1.1.dpx -oi c:\edk2\Build\EmulatorIA32\DEBUG_VS2012x86\FV\Ffs\AAC33064-9ED0-4b89-A5AD-3EA767960B22FaultTolerantWritePei\AAC33064-9ED0-4b89-A5AD-3EA767960B22SEC2.1.pe32 -n 0 -oi c:\edk2\Build\EmulatorIA32\DEBUG_VS2012x86\FV\Ffs\AAC33064-9ED0-4b89-A5AD-3EA767960B22FaultTolerantWritePei\AAC33064-9ED0-4b89-A5AD-3EA767960B22SEC3.ui -oi c:\edk2\Build\EmulatorIA32\DEBUG_VS2012x86\FV\Ffs\AAC33064-9ED0-4b89-A5AD-3EA767960B22FaultTolerantWritePei\AAC33064-9ED0-4b89-A5AD-3EA767960B22SEC4.ver

GenFfs: ERROR 1000: Unknown option 


Tried building for windows from given link below, could not find Genffs.c file

Please share info on how to build the latest ekd2-basetools for windows.

Best Regards
Ranga



--
Pedro Falcato


Looking for latest edk2 dev tools for win32

Rao G
 

Hi All,

The below tools does not seem to be latest
https://github.com/tianocore/edk2-BaseTools-win32

Older Genffs.exe does not understand -oi option

GenFfs -t EFI_FV_FILETYPE_PEIM -g AAC33064-9ED0-4b89-A5AD-3EA767960B22 -o c:\edk2\Build\EmulatorIA32\DEBUG_VS2012x86\FV\Ffs\AAC33064-9ED0-4b89-A5AD-3EA767960B22FaultTolerantWritePei\AAC33064-9ED0-4b89-A5AD-3EA767960B22.ffs -oi c:\edk2\Build\EmulatorIA32\DEBUG_VS2012x86\FV\Ffs\AAC33064-9ED0-4b89-A5AD-3EA767960B22FaultTolerantWritePei\AAC33064-9ED0-4b89-A5AD-3EA767960B22SEC1.1.dpx -oi c:\edk2\Build\EmulatorIA32\DEBUG_VS2012x86\FV\Ffs\AAC33064-9ED0-4b89-A5AD-3EA767960B22FaultTolerantWritePei\AAC33064-9ED0-4b89-A5AD-3EA767960B22SEC2.1.pe32 -n 0 -oi c:\edk2\Build\EmulatorIA32\DEBUG_VS2012x86\FV\Ffs\AAC33064-9ED0-4b89-A5AD-3EA767960B22FaultTolerantWritePei\AAC33064-9ED0-4b89-A5AD-3EA767960B22SEC3.ui -oi c:\edk2\Build\EmulatorIA32\DEBUG_VS2012x86\FV\Ffs\AAC33064-9ED0-4b89-A5AD-3EA767960B22FaultTolerantWritePei\AAC33064-9ED0-4b89-A5AD-3EA767960B22SEC4.ver

GenFfs: ERROR 1000: Unknown option 


Tried building for windows from given link below, could not find Genffs.c file

Please share info on how to build the latest ekd2-basetools for windows.

Best Regards
Ranga


Re: [PATCH] SecurityPkg: Debug trace package integration to enable debug message capture on all targets.

Yao, Jiewen
 

Hey
First, please include Bugzilla link, so that we can have background.

Second, it is weird to me that you change the INF only.
I don't understand. Is that a complete patch?

-----Original Message-----
From: Reji, RencyX <rencyx.reji@intel.com>
Sent: Wednesday, December 8, 2021 8:22 PM
To: devel@edk2.groups.io
Cc: Reji, RencyX <rencyx.reji@intel.com>; Zhang, Qi1 <qi1.zhang@intel.com>;
Kumar, Rahul1 <rahul1.kumar@intel.com>; Yao, Jiewen
<jiewen.yao@intel.com>; Wang, Jian J <jian.j.wang@intel.com>
Subject: [PATCH] SecurityPkg: Debug trace package integration to enable debug
message capture on all targets.

We are introducing a new feature where we will be using a device to collect
debug messages
to extend capability of debug beyond current scope. We are required to extend
capability of
debug library by changing debug macro expression and collect debug messages
for all target
such as Debug, Release and Silent.

Cc: Qi Zhang <qi1.zhang@intel.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Signed-off-by: Rency Reji <RencyX.Reji@intel.com>
---
SecurityPkg/SecurityPkg.dsc | 1 +
SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf | 1 +
SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf | 1 +
SecurityPkg/Tcg/TcgPei/TcgPei.inf | 1 +
4 files changed, 4 insertions(+)

diff --git a/SecurityPkg/SecurityPkg.dsc b/SecurityPkg/SecurityPkg.dsc
index 73a93c2285..0f1b3d62e9 100644
--- a/SecurityPkg/SecurityPkg.dsc
+++ b/SecurityPkg/SecurityPkg.dsc
@@ -72,6 +72,7 @@

MmUnblockMemoryLib|MdePkg/Library/MmUnblockMemoryLib/MmUnblockM
emoryLibNull.inf

SecureBootVariableLib|SecurityPkg/Library/SecureBootVariableLib/SecureBoot
VariableLib.inf

SecureBootVariableProvisionLib|SecurityPkg/Library/SecureBootVariableProvisi
onLib/SecureBootVariableProvisionLib.inf
+ ExtDebugLib|MdePkg/Library/BaseExtDebugLib/BaseExtDebugLib.inf

[LibraryClasses.ARM, LibraryClasses.AARCH64]
#
diff --git a/SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf
b/SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf
index 653dc1f64f..0b8c6af3b0 100644
--- a/SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf
+++ b/SecurityPkg/Tcg/PhysicalPresencePei/PhysicalPresencePei.inf
@@ -38,6 +38,7 @@
[LibraryClasses]
PeimEntryPoint
PeiServicesLib
+ ExtDebugLib

[Ppis]
gPeiLockPhysicalPresencePpiGuid ## PRODUCES
diff --git a/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf
b/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf
index 06c26a2904..a11cf661ab 100644
--- a/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf
+++ b/SecurityPkg/Tcg/Tcg2Pei/Tcg2Pei.inf
@@ -55,6 +55,7 @@
ReportStatusCodeLib
ResetSystemLib
PrintLib
+ ExtDebugLib

[Guids]
gTcgEventEntryHobGuid ## PRODUCES ##
HOB
diff --git a/SecurityPkg/Tcg/TcgPei/TcgPei.inf
b/SecurityPkg/Tcg/TcgPei/TcgPei.inf
index 2e3e7e0575..90d55e7256 100644
--- a/SecurityPkg/Tcg/TcgPei/TcgPei.inf
+++ b/SecurityPkg/Tcg/TcgPei/TcgPei.inf
@@ -52,6 +52,7 @@
ReportStatusCodeLib
Tpm12CommandLib
PerformanceLib
+ ExtDebugLib

[Guids]
gTcgEventEntryHobGuid ## PRODUCES ##
HOB
--
2.34.1.windows.1


Re: EDK2 CI build error "Uncrustify Coding Standard"

Brijesh Singh
 

Hi Mike,

On 12/7/21 3:02 PM, Kinney, Michael D wrote:
Hi Brijesh,
Yes. Your branch can be rebased on top of edk2/master after uncrustify changes.
You have added new c/h files, so those files need to be run through uncrustify locally and
your patch updated with those formatting changes.
The following command updates every c/h file except BaseTools locally.
git ls-files *.c *.h :!BaseTools/* | .pytool\Plugin\UncrustifyCheck\mu-uncrustify-release_extdep\Windows-x86\uncrustify.exe -c .pytool\Plugin\UncrustifyCheck\uncrustify.cfg -F - --replace --no-backup --if-changed
If you know the package you are working on, the following one will work faster.
git ls-files <PackageName>*.c <PackageName>*.h :!BaseTools/* | .pytool\Plugin\UncrustifyCheck\mu-uncrustify-release_extdep\Windows-x86\uncrustify.exe -c .pytool\Plugin\UncrustifyCheck\uncrustify.cfg -F - --replace --no-backup --if-changed
OvmfPkg Example:
git ls-files OvmfPkg/*.c OvmfPkg/*.h :!BaseTools/* | .pytool\Plugin\UncrustifyCheck\mu-uncrustify-release_extdep\Windows-x86\uncrustify.exe -c .pytool\Plugin\UncrustifyCheck\uncrustify.cfg -F - --replace --no-backup --if-changed
Thanks for the detail, I just did a pull and now I see the uncrustify cfg files. I followed your above command on my Ubuntu desktop and getting the below unknown symbol, is this a known issue ?


brijesh@sbrijesh-desktop:~/workdir/snp-edk2$ git ls-files OvmfPkg/Sec/AmdSev.c | uncrustify -c .pytool/Plugin/UncrustifyCheck/uncrustify.cfg -F - --replace --no-backup --if-changed
.pytool/Plugin/UncrustifyCheck/uncrustify.cfg:73: unknown symbol 'nl_func_call_args_multi_line_ignore_closures'
.pytool/Plugin/UncrustifyCheck/uncrustify.cfg:79: unknown symbol 'indent_func_call_edk2_style'
.pytool/Plugin/UncrustifyCheck/uncrustify.cfg:120: unknown symbol 'sp_do_brace_open'
.pytool/Plugin/UncrustifyCheck/uncrustify.cfg:134: unknown symbol 'sp_before_vardef_square'
.pytool/Plugin/UncrustifyCheck/uncrustify.cfg:178: unknown symbol 'sp_brace_close_while'
.pytool/Plugin/UncrustifyCheck/uncrustify.cfg:184: unknown symbol 'sp_before_square_asm_block'
.pytool/Plugin/UncrustifyCheck/uncrustify.cfg:205: unknown symbol 'sp_while_paren_open'
.pytool/Plugin/UncrustifyCheck/uncrustify.cfg:229: unknown symbol 'indent_func_def_param_paren_pos_threshold'
.pytool/Plugin/UncrustifyCheck/uncrustify.cfg:270: unknown symbol 'align_edk2_style'
.pytool/Plugin/UncrustifyCheck/uncrustify.cfg:323: unknown symbol 'cmt_align_doxygen_javadoc_tags'
.pytool/Plugin/UncrustifyCheck/uncrustify.cfg:406: unknown symbol 'nl_before_whole_file_ifdef'
Parsing: OvmfPkg/Sec/AmdSev.c as language C
brijesh@sbrijesh-desktop:~/workdir/snp-edk2$
brijesh@sbrijesh-desktop:~/workdir/snp-edk2$ uncrustify --version
Uncrustify-0.69.0_f

I did submitted PR after above uncurstify run but the CI still didn't like it. Do we need to have specific version of uncrustify ?

-Brijesh

You do have to use the .pytool stuart commands to setup your environment so uncrustify tool is installed automatically.
This also allows you to run all the EDK II CI tests locally if you want to check and fix issues before
submitting a PR.
https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Ftianocore%2Fedk2%2Fblob%2Fmaster%2F.pytool%2FReadme.md%23running-ci-locally&;data=04%7C01%7Cbrijesh.singh%40amd.com%7Cb303a189de3446c5c52108d9b9c4e760%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637745077634999978%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&amp;sdata=OnGmCqMIEwmrZmn48M6MwErLyB60ORfN7CUceS%2BhPmI%3D&amp;reserved=0
You can also use git filter-branch to uncrustify a more complex patch series. That is in the email thread
and will be included in the Wiki.
Best regards,
Mike

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of Michael Kubacki
Sent: Tuesday, December 7, 2021 12:50 PM
To: devel@edk2.groups.io; brijesh.singh@amd.com
Subject: Re: [edk2-devel] EDK2 CI build error "Uncrustify Coding Standard"

Hi Brijesh,

A Tianocore wiki article is being prepared but the background and
instructions for what to do were sent in this mail regarding the hard
freeze being lifted - https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fedk2.groups.io%2Fg%2Fdevel%2Fmessage%2F84458&;data=04%7C01%7Cbrijesh.singh%40amd.com%7Cb303a189de3446c5c52108d9b9c4e760%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637745077635009974%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&amp;sdata=LRtAPIFef6zlz6x0YNqpM9Hn5WIjFP1C0moMZFO9TWA%3D&amp;reserved=0.

Do you have questions after reading through that?

Thanks,
Michael

On 12/7/2021 2:52 PM, Brijesh Singh via groups.io wrote:
Hi All,

I am rebasing the SNP series and encountering the error like below from
the CI. I am not sure what I am missing. For testing purpose, I just
tried one commit and CI Windows build complains about this. This is the
same patch which passed all the CI. Any idea what I maybe missing ?


WARNING - A file header template is not specified in the config file.
WARNING - A function header template is not specified in the config file.
ERROR - /home/vsts/work/1/s/OvmfPkg/Sec/AmdSev.c
ERROR - /home/vsts/work/1/s/OvmfPkg/Sec/AmdSev.h
ERROR - --->Test Failed: Uncrustify Coding Standard Test NO-TARGET
returned 2


My patch does add the two files and they are listed in .inf.

-Brijesh





Re: [EXTERNAL] RE: [edk2-devel] [edk2-platforms] [PATCH V1] PurleyOpenBoardPkg : Linux Boot Improvements

manickavasakam karpagavinayagam
 

Thank you again Isaac for reviewing the code changes. We don't have any concerns.

-Manic

-----Original Message-----
From: Oram, Isaac W <isaac.w.oram@intel.com>
Sent: Tuesday, December 7, 2021 8:07 PM
To: devel@edk2.groups.io; Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Harikrishna Doppalapudi <Harikrishnad@ami.com>; Manish Jha <manishj@ami.com>; Zachary Bobroff <zacharyb@ami.com>
Subject: [EXTERNAL] RE: [edk2-devel] [edk2-platforms] [PATCH V1] PurleyOpenBoardPkg : Linux Boot Improvements


**CAUTION: The e-mail below is from an external source. Please exercise caution before opening attachments, clicking links, or following guidance.**

Reviewed-by: Isaac Oram <isaac.w.oram@intel.com>

There are a few small whitespace and comment things I plan to cleanup before submission:

Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c
- Seems to have some Unicode garbage at end of file.
- Missing newline at end of file

Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.
- Some trailing whitespace at end of lines

Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.fdf
- Sizes and offsets were updated, but comments were not. I find that these often get out of date, so I believe it is better to delete the comments than have incorrect comments.

Platform/Intel/PurleyOpenBoardPkg/Features/LinuxBoot/Readme.md
- "linux.efi is a dummy files." Files should now be file.

Please let me know if that is a concern.

Regards,
Isaac

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of manickavasakam karpagavinayagam via groups.io
Sent: Monday, December 6, 2021 12:53 PM
To: devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Oram, Isaac W <isaac.w.oram@intel.com>; DOPPALAPUDI, HARIKRISHNA <harikrishnad@ami.com>; Jha, Manish <manishj@ami.com>; Bobroff, Zachary <zacharyb@ami.com>; KARPAGAVINAYAGAM, MANICKAVASAKAM <manickavasakamk@ami.com>
Subject: [edk2-devel] [edk2-platforms] [PATCH V1] PurleyOpenBoardPkg : Linux Boot Improvements

Linux Boot : Remove separate initrd file. Linux Binaries build with an Integrated Initrd
Synced edk2-platforms\Platform\Intel\PurleyOpenBoardPkg\Override\Platform\Intel\MinPlatformPkg\Bds
with the latest edk2-platforms\Platform\Intel\MinPlatformPkg\Bds
Applied and moved earlier overrides done in DxePlatformBootManagerLib to BoardBdsHookLib

Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <isaac.w.oram@intel.com>
Cc: Harikrishna Doppalapudi <harikrishnad@ami.com>
Cc: Manish Jha <manishj@ami.com>
Cc: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
Cc: Zachary Bobroff <zacharyb@ami.com>

Signed-off-by: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
---
Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c | 1 +
Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreDxeInclude.dsc | 5 +-
Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreUefiBootInclude.fdf | 5 +-
Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.dsc | 6 +-
Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.fdf | 17 +-
Platform/Intel/PurleyOpenBoardPkg/Features/LinuxBoot/LinuxBinaries/initrd.cpio.xz | Bin 16 -> 0 bytes
Platform/Intel/PurleyOpenBoardPkg/Features/LinuxBoot/LinuxBoot.c | 63 -
Platform/Intel/PurleyOpenBoardPkg/Features/LinuxBoot/Readme.md | 11 +-
Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHook.h | 211 +++
Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c | 1400 ++++++++++++++++++++
Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf | 99 ++
Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/{MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/PlatformBootOption.c => BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c} | 1146 ++++++++--------
Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/{MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/MemoryTest.c => BoardModulePkg/Library/BoardBdsHookLib/BoardMemoryTest.c} | 171 +--
Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.c | 1281 ++----------------
Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.h | 181 +--
Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf | 60 +-
16 files changed, 2526 insertions(+), 2131 deletions(-)

diff --git a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c
index 4fdc9ac94e..97c4548fd6 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c
+++ b/Platform/Intel/PurleyOpenBoardPkg/Acpi/BoardAcpiDxe/AmlOffsetTable.c
@@ -289,3 +289,4 @@ AML_OFFSET_TABLE_ENTRY DSDT_PLATWFP__OffsetTable[] =
{NULL,0,0,0,0,0} /* Table terminator */

};



+
\ No newline at end of file
diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreDxeInclude.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreDxeInclude.dsc
index e653287d05..6ddd3734dc 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreDxeInclude.dsc
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreDxeInclude.dsc
@@ -101,6 +101,8 @@
!endif

#MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf

MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf

+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

+ MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf



!if gPlatformTokenSpaceGuid.PcdLinuxBootEnable == FALSE

MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf

@@ -108,9 +110,6 @@


MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf



- MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf

-

- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf



MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf

diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreUefiBootInclude.fdf b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreUefiBootInclude.fdf
index 78f0a31a4d..dc6e9e8bc6 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreUefiBootInclude.fdf
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/CoreUefiBootInclude.fdf
@@ -67,6 +67,9 @@ INF FatPkg/EnhancedFatDxe/Fat.inf


#INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf

INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf

+INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

+INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf

+



!if gPlatformTokenSpaceGuid.PcdLinuxBootEnable == FALSE

INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf

@@ -74,9 +77,7 @@ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf


INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf



-INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf



-INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf

INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf

INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf



diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.dsc b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.dsc
index 3bac6d394e..8fe4cb7e97 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.dsc
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.dsc
@@ -89,7 +89,7 @@
[Components.$(DXE_ARCH)]

#TiogaPass Override START : Added Board Specific changes in core drivers

#!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc

-!include CoreDxeInclude.dsc

+!include CoreDxeInclude.dsc

#TiogaPass Override END



#######################################

@@ -155,7 +155,11 @@
!endif

TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointLib.inf

BoardBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/BoardBootManagerLibNull/BoardBootManagerLibNull.inf

+!if gPlatformTokenSpaceGuid.PcdFastBoot == FALSE

BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf

+!else

+ BoardBdsHookLib|$(PLATFORM_BOARD_PACKAGE)/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf

+!endif

!if gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable == TRUE

IpmiBaseLib|OutOfBandManagement/IpmiFeaturePkg/Library/IpmiBaseLib/IpmiBaseLib.inf

!endif

diff --git a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.fdf b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.fdf
index b162483c44..b49c7c0a34 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.fdf
+++ b/Platform/Intel/PurleyOpenBoardPkg/BoardTiogaPass/OpenBoardPkg.fdf
@@ -22,15 +22,15 @@
!if gPlatformTokenSpaceGuid.PcdLinuxBootEnable == TRUE



SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00000000 # Flash addr (0xFF840000)

-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00300000 #

-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x00300000 # Flash addr (0xFF8A0000)

-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00100000 #

-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x00400000 # Flash addr (0xFF910000)

+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = 0x00200000 #

+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = 0x00200000 # Flash addr (0xFF8A0000)

+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x000F0000 #

+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = 0x002F0000 # Flash addr (0xFF910000)

SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00100000 #

-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUOffset = 0x00500000 # Flash addr (0xFFE00000)

+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUOffset = 0x003F0000 # Flash addr (0xFFE00000)

SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspUSize = 0x00100000 #

-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x00600000 # Flash addr (0xFF9A0000)

-SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x00600000 #

+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = 0x004F0000 # Flash addr (0xFF9A0000)

+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x00710000 #

SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = 0x00C00000 # Flash addr (0xFF800000)

SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0007C000 #



@@ -345,9 +345,6 @@ FILE DRIVER = 81339b04-fa8c-4be0-9ca7-916fc5319eb5 {
SECTION PE32 = $(PLATFORM_BOARD_PACKAGE)/Features/LinuxBoot/LinuxBinaries/linux.efi

}



-FILE FREEFORM = 16b60e5d-f1c5-42f0-9b34-08C81C430473 {

- SECTION RAW = $(PLATFORM_BOARD_PACKAGE)/Features/LinuxBoot/LinuxBinaries/initrd.cpio.xz

-}



!endif



diff --git a/Platform/Intel/PurleyOpenBoardPkg/Features/LinuxBoot/LinuxBinaries/initrd.cpio.xz b/Platform/Intel/PurleyOpenBoardPkg/Features/LinuxBoot/LinuxBinaries/initrd.cpio.xz
deleted file mode 100644
index 01d633b27e8ea9b17084fc911d0c8cc43a4170a9..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

literal 16
KcmZQzKm`B*5C8!H

diff --git a/Platform/Intel/PurleyOpenBoardPkg/Features/LinuxBoot/LinuxBoot.c b/Platform/Intel/PurleyOpenBoardPkg/Features/LinuxBoot/LinuxBoot.c
index 366d97c125..b30559772d 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/Features/LinuxBoot/LinuxBoot.c
+++ b/Platform/Intel/PurleyOpenBoardPkg/Features/LinuxBoot/LinuxBoot.c
@@ -26,12 +26,6 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#include <Library/DxeServicesLib.h>

#include "LinuxBoot.h"



-//16b60e5d-f1c5-42f0-9b34-08C81C430473

-#define LINUX_BOOT_INITRD_GUID \

- { \

- 0x16b60e5d, 0xf1c5, 0x42f0, {0x9b, 0x34, 0x08, 0xc8, 0x1c, 0x43, 0x04, 0x73} \

- }

-

#define LINUX_BOOT_KERNEL_GUID \

{ \

0x81339b04, 0xfa8c, 0x4be0, {0x9c, 0xa7, 0x91, 0x6f, 0xc5, 0x31, 0x9e, 0xb5} \

@@ -78,15 +72,6 @@ LoadLinux (
IN OUT VOID *KernelSetup

);



-VOID*

-EFIAPI

-LoadLinuxAllocateInitrdPages (

- IN VOID *KernelSetup,

- IN UINTN Pages

- );

-

-EFI_GUID gLinuxBootInitrdFileGuid = LINUX_BOOT_INITRD_GUID;

-

EFI_GUID gLinuxBootKernelFileGuid = LINUX_BOOT_KERNEL_GUID;



//---------------------------------------------------------------------------

@@ -189,9 +174,6 @@ LoadAndLaunchKernel (
VOID *KernelBuffer = NULL;

VOID *KernelFfsBuffer = NULL;

UINTN KernelFfsSize = 0;

- VOID *InitrdData = NULL;

- VOID *InitrdBuffer = NULL;

- UINTN InitrdSize = 0;

struct BootParams *BootParams = NULL;

struct BootParams *HandoverParams = NULL;

UINT32 StartOffset = 0;

@@ -301,49 +283,6 @@ LoadAndLaunchKernel (


DEBUG((DEBUG_INFO, "Kernel loaded.\n"));



- //

- // Initrd load and preparation

- //

- DEBUG((DEBUG_INFO, "Preparing the initrd...\n"));

-

- // Retrieve the initrd from the firmware volume

- Status = GetSectionFromAnyFv(

- &gLinuxBootInitrdFileGuid,

- EFI_SECTION_RAW,

- 0,

- &InitrdBuffer,

- &InitrdSize

- );

-

- if (EFI_ERROR(Status)) {

- DEBUG((DEBUG_ERROR, "Could not retrieve initrd; %r.\n", Status));

- goto FatalError;

- }

-

- DEBUG((DEBUG_INFO, "Loaded initrd to buffer at 0x%p with size 0x%X.\n", InitrdBuffer, InitrdSize));

- DEBUG((DEBUG_INFO, "Printing first 0x%X bytes:\n", MIN(0x100, InitrdSize)));

- DumpHex(2, 0, MIN(0x100, InitrdSize), InitrdBuffer);

-

- // Allocate the initrd for the kernel and copy it in

- InitrdData = LoadLinuxAllocateInitrdPages(HandoverParams, EFI_SIZE_TO_PAGES(InitrdSize));

- if (InitrdData == NULL) {

- DEBUG((DEBUG_ERROR, "Unable to allocate memory for initrd.\n"));

- goto FatalError;

- }

-

- gBS->CopyMem(InitrdData, InitrdBuffer, InitrdSize);

-

- HandoverParams->Hdr.RamDiskStart = (UINT32)(UINTN) InitrdData;

- HandoverParams->Hdr.RamDiskLen = (UINT32) InitrdSize;

-

- DEBUG((DEBUG_INFO, "Initrd loaded.\n"));

- DEBUG((DEBUG_INFO, "Printing first 0x%X bytes of initrd buffer:\n", MIN(0x100, InitrdSize)));

- DumpHex(2, 0, MIN(0x100, InitrdSize), InitrdData);

-

- // General cleanup before launching the kernel

- gBS->FreePool(InitrdBuffer);

- InitrdBuffer = NULL;

-

gBS->UnloadImage(KernelHandle);

gBS->FreePool(KernelFfsBuffer);

KernelFfsBuffer = NULL;

@@ -367,10 +306,8 @@ LoadAndLaunchKernel (


FatalError:

// Free everything

- if (InitrdData != NULL) gBS->FreePages((EFI_PHYSICAL_ADDRESS) InitrdData, EFI_SIZE_TO_PAGES(InitrdSize));

if (KernelBuffer != NULL) gBS->FreePages((EFI_PHYSICAL_ADDRESS) KernelBuffer, EFI_SIZE_TO_PAGES(HandoverParams->Hdr.InitSize));

if (HandoverParams != NULL) gBS->FreePages((EFI_PHYSICAL_ADDRESS) HandoverParams, EFI_SIZE_TO_PAGES(KERNEL_SETUP_SIZE));

- if (InitrdBuffer != NULL) gBS->FreePool(InitrdBuffer);

if (KernelHandle != NULL) gBS->UnloadImage(KernelHandle);

if (KernelFfsBuffer != NULL) gBS->FreePool(KernelFfsBuffer);



diff --git a/Platform/Intel/PurleyOpenBoardPkg/Features/LinuxBoot/Readme.md b/Platform/Intel/PurleyOpenBoardPkg/Features/LinuxBoot/Readme.md
index 04bf550104..8d8c67b659 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/Features/LinuxBoot/Readme.md
+++ b/Platform/Intel/PurleyOpenBoardPkg/Features/LinuxBoot/Readme.md
@@ -1,9 +1,8 @@


-linux.efi/initrd.cpio.xz are dummy files.

-These dummy files needs to be replaced by building the Linux Kernel.

+linux.efi is a dummy files.

+These dummy files needs to be replaced by building the Linux Kernel with an Integrated Initrd.



-1. Follow directions on https://nam12.safelinks.protection.outlook.com/?url=http%3A%2F%2Fosresearch.net%2FBuilding%2F&;data=04%7C01%7Cmanickavasakamk%40ami.com%7C019a0d0750c34fd2b62d08d9b9e6fda5%7C27e97857e15f486cb58e86c2b3040f93%7C1%7C0%7C637745224037767019%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&amp;sdata=TXdPgaEebaqVrwppOpIGGS%2F5lnrAtu1GA4mH49zpigI%3D&amp;reserved=0 to compile the heads kernel and initrd for qemu-system_x86_64

-2. Copy the following built files

-(1) initrd.cpio.xz to LinuxBoot/LinuxBinaries/initrd.cpio.xz

-(2) bzimage to LinuxBoot/LinuxBinaries/linux.efi

+1. Follow u-root https://nam12.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgithub.com%2Fu-root%2Fu-root%23readme&;data=04%7C01%7Cmanickavasakamk%40ami.com%7C019a0d0750c34fd2b62d08d9b9e6fda5%7C27e97857e15f486cb58e86c2b3040f93%7C1%7C0%7C637745224037767019%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&amp;sdata=QBOElw5IXcEWVtJhQiWvJXM1mUFtfHWK8L75%2FIGRFBg%3D&amp;reserved=0 to compile an initrd

+2. Follow directions on https://nam12.safelinks.protection.outlook.com/?url=http%3A%2F%2Fosresearch.net%2FBuilding%2F&;data=04%7C01%7Cmanickavasakamk%40ami.com%7C019a0d0750c34fd2b62d08d9b9e6fda5%7C27e97857e15f486cb58e86c2b3040f93%7C1%7C0%7C637745224037767019%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&amp;sdata=TXdPgaEebaqVrwppOpIGGS%2F5lnrAtu1GA4mH49zpigI%3D&amp;reserved=0 to integrate initrd and compile the heads kernel

+3. Copy bzimage with integrated initrd to LinuxBoot/LinuxBinaries/linux.efi



diff --git a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHook.h b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHook.h
new file mode 100644
index 0000000000..5f41fd49c7
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHook.h
@@ -0,0 +1,211 @@
+/** @file
+ Header file for BDS Hook Library
+
+Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#ifndef _BOARD_BDS_HOOK_H_
+#define _BOARD_BDS_HOOK_H_
+
+#include <PiDxe.h>
+#include <Protocol/DevicePath.h>
+#include <Protocol/SimpleNetwork.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <Protocol/LoadFile.h>
+#include <Protocol/PciIo.h>
+#include <Protocol/CpuIo2.h>
+#include <Protocol/LoadedImage.h>
+#include <Protocol/DiskInfo.h>
+#include <Protocol/GraphicsOutput.h>
+#include <Protocol/UgaDraw.h>
+#include <Protocol/GenericMemoryTest.h>
+#include <Protocol/DevicePathToText.h>
+#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/SimpleFileSystem.h>
+
+#include <Guid/CapsuleVendor.h>
+#include <Guid/MemoryTypeInformation.h>
+#include <Guid/GlobalVariable.h>
+#include <Guid/MemoryOverwriteControl.h>
+#include <Guid/FileInfo.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/UefiRuntimeServicesTableLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PlatformBootManagerLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/UefiLib.h>
+#include <Library/HobLib.h>
+#include <Library/DxeServicesLib.h>
+#include <Library/DxeServicesTableLib.h>
+#include <Library/PrintLib.h>
+#include <Library/HiiLib.h>
+#include <Library/CapsuleLib.h>
+#include <Library/PerformanceLib.h>
+
+#include <IndustryStandard/Pci30.h>
+#include <IndustryStandard/PciCodeId.h>
+#include <Protocol/PciEnumerationComplete.h>
+
+///
+/// ConnectType
+///
+#define CONSOLE_OUT 0x00000001
+#define STD_ERROR 0x00000002
+#define CONSOLE_IN 0x00000004
+#define CONSOLE_ALL (CONSOLE_OUT | CONSOLE_IN | STD_ERROR)
+
+extern EFI_GUID gUefiShellFileGuid;
+extern EFI_BOOT_MODE gBootMode;
+
+#define gPciRootBridge \
+ { \
+ { \
+ ACPI_DEVICE_PATH, \
+ ACPI_DP, \
+ { \
+ (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \
+ (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \
+ }, \
+ }, \
+ EISA_PNP_ID (0x0A03), \
+ 0 \
+ }
+
+#define gEndEntire \
+ { \
+ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { END_DEVICE_PATH_LENGTH, 0 } \
+ }
+
+typedef struct {
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ UINTN ConnectType;
+} BDS_CONSOLE_CONNECT_ENTRY;
+
+//
+// Platform Root Bridge
+//
+typedef struct {
+ ACPI_HID_DEVICE_PATH PciRootBridge;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_ROOT_BRIDGE_DEVICE_PATH;
+
+//
+// Below is the platform console device path
+//
+typedef struct {
+ ACPI_HID_DEVICE_PATH PciRootBridge;
+ PCI_DEVICE_PATH IsaBridge;
+ ACPI_HID_DEVICE_PATH Keyboard;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_KEYBOARD_DEVICE_PATH;
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH PciRootBridge;
+ PCI_DEVICE_PATH PciDevice;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_ONBOARD_CONTROLLER_DEVICE_PATH;
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH PciRootBridge;
+ PCI_DEVICE_PATH Pci0Device;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_PEG_ROOT_CONTROLLER_DEVICE_PATH;
+
+typedef struct {
+ ACPI_HID_DEVICE_PATH PciRootBridge;
+ PCI_DEVICE_PATH PciBridge;
+ PCI_DEVICE_PATH PciDevice;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} PLATFORM_PCI_CONTROLLER_DEVICE_PATH;
+
+//
+// Below is the boot option device path
+//
+
+#define CLASS_HID 3
+#define SUBCLASS_BOOT 1
+#define PROTOCOL_KEYBOARD 1
+
+typedef struct {
+ USB_CLASS_DEVICE_PATH UsbClass;
+ EFI_DEVICE_PATH_PROTOCOL End;
+} USB_CLASS_FORMAT_DEVICE_PATH;
+
+extern USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath;
+
+//
+// Platform BDS Functions
+//
+
+
+/**
+ Perform the memory test base on the memory test intensive level,
+ and update the memory resource.
+
+ @param Level The memory test intensive level.
+
+ @retval EFI_STATUS Success test all the system memory and update
+ the memory resource
+
+**/
+EFI_STATUS
+MemoryTest (
+ IN EXTENDMEM_COVERAGE_LEVEL Level
+ );
+
+/**
+ Connect with predeined platform connect sequence,
+ the OEM/IBV can customize with their own connect sequence.
+
+ @param[in] BootMode Boot mode of this boot.
+**/
+VOID
+ConnectSequence (
+ IN EFI_BOOT_MODE BootMode
+ );
+
+
+/**
+ Compares boot priorities of two boot options
+
+ @param Left The left boot option
+ @param Right The right boot option
+
+ @return The difference between the Left and Right
+ boot options
+ **/
+INTN
+EFIAPI
+CompareBootOption (
+ CONST VOID *Left,
+ CONST VOID *Right
+ );
+
+/**
+ This function is called after all the boot options are enumerated and ordered properly.
+**/
+VOID
+RegisterStaticHotkey (
+ VOID
+ );
+
+
+/**
+ Registers/Unregisters boot option hotkey
+
+ @param OptionNumber The boot option number for the key option.
+ @param Key The the key input
+ @param Add Flag to indicate to add or remove a key
+**/
+VOID
+RegisterDefaultBootOption (
+ VOID
+ );
+
+#endif
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c
new file mode 100644
index 0000000000..f19720f814
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.c
@@ -0,0 +1,1400 @@
+/** @file
+ This library registers Bds callbacks. It is a default library
+ implementation instance of the BDS hook library
+
+ Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+ Copyright (c) 2021, American Megatrends International LLC.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Guid/EventGroup.h>
+
+#include <Library/IoLib.h>
+#include <Library/PciLib.h>
+#include <Library/UefiBootManagerLib.h>
+#include <Library/Tcg2PhysicalPresenceLib.h>
+
+#include <Protocol/BlockIo.h>
+#include <Protocol/UsbIo.h>
+#include <Protocol/PciEnumerationComplete.h>
+
+#include "BoardBdsHook.h"
+
+#define IS_FIRST_BOOT_VAR_NAME L"IsFirstBoot"
+
+GLOBAL_REMOVE_IF_UNREFERENCED EFI_BOOT_MODE gBootMode;
+BOOLEAN gPPRequireUIConfirm;
+extern UINTN mBootMenuOptionNumber;
+
+
+GLOBAL_REMOVE_IF_UNREFERENCED USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = {
+ {
+ {
+ MESSAGING_DEVICE_PATH,
+ MSG_USB_CLASS_DP,
+ {
+ (UINT8) (sizeof (USB_CLASS_DEVICE_PATH)),
+ (UINT8) ((sizeof (USB_CLASS_DEVICE_PATH)) >> 8)
+ }
+ },
+ 0xffff, // VendorId
+ 0xffff, // ProductId
+ CLASS_HID, // DeviceClass
+ SUBCLASS_BOOT, // DeviceSubClass
+ PROTOCOL_KEYBOARD // DeviceProtocol
+ },
+ gEndEntire
+};
+
+
+//
+// BDS Platform Functions
+//
+BOOLEAN
+IsMorBitSet (
+ VOID
+ )
+{
+ UINTN MorControl;
+ EFI_STATUS Status;
+ UINTN DataSize;
+
+ //
+ // Check if the MOR bit is set.
+ //
+ DataSize = sizeof (MorControl);
+ Status = gRT->GetVariable (
+ MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME,
+ &gEfiMemoryOverwriteControlDataGuid,
+ NULL,
+ &DataSize,
+ &MorControl
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((DEBUG_INFO, " gEfiMemoryOverwriteControlDataGuid doesn't exist!!***\n"));
+ MorControl = 0;
+ } else {
+ DEBUG ((DEBUG_INFO, " Get the gEfiMemoryOverwriteControlDataGuid = %x!!***\n", MorControl));
+ }
+
+ return (BOOLEAN) (MorControl & 0x01);
+}
+
+
+/**
+ Prints device paths.
+ @param Name The device name.
+ @param DevicePath The device path to be printed
+**/
+VOID
+EFIAPI
+DumpDevicePath (
+ IN CHAR16 *Name,
+ IN EFI_DEVICE_PATH *DevicePath
+ )
+{
+ CHAR16 *Str;
+ Str = ConvertDevicePathToText (DevicePath, TRUE, TRUE);
+ DEBUG ((DEBUG_INFO, "%s: %s\n", Name, Str));
+ if (Str != NULL) {
+ FreePool (Str);
+ }
+}
+
+/**
+ Return whether the device is trusted console.
+
+ @param Device The device to be tested.
+
+ @retval TRUE The device can be trusted.
+ @retval FALSE The device cannot be trusted.
+**/
+BOOLEAN
+IsTrustedConsole (
+ IN CONSOLE_TYPE ConsoleType,
+ IN EFI_DEVICE_PATH_PROTOCOL *Device
+ )
+{
+ VOID *TrustedConsoleDevicepath;
+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *Instance;
+ UINTN Size;
+ EFI_DEVICE_PATH_PROTOCOL *ConsoleDevice;
+
+ if (Device == NULL) {
+ return FALSE;
+ }
+
+ ConsoleDevice = DuplicateDevicePath (Device);
+
+ TrustedConsoleDevicepath = NULL;
+
+ switch (ConsoleType) {
+ case ConIn:
+ TrustedConsoleDevicepath = PcdGetPtr (PcdTrustedConsoleInputDevicePath);
+ break;
+ case ConOut:
+ //
+ // Check GOP and remove last node
+ //
+ TempDevicePath = ConsoleDevice;
+ while (!IsDevicePathEndType (TempDevicePath)) {
+ if (DevicePathType (TempDevicePath) == ACPI_DEVICE_PATH &&
+ DevicePathSubType (TempDevicePath) == ACPI_ADR_DP) {
+ SetDevicePathEndNode (TempDevicePath);
+ break;
+ }
+ TempDevicePath = NextDevicePathNode (TempDevicePath);
+ }
+
+ TrustedConsoleDevicepath = PcdGetPtr (PcdTrustedConsoleOutputDevicePath);
+ break;
+ default:
+ ASSERT (FALSE);
+ break;
+ }
+
+ TempDevicePath = TrustedConsoleDevicepath;
+ do {
+ Instance = GetNextDevicePathInstance (&TempDevicePath, &Size);
+ if (Instance == NULL) {
+ break;
+ }
+
+ if (CompareMem (ConsoleDevice, Instance, Size - END_DEVICE_PATH_LENGTH) == 0) {
+ FreePool (Instance);
+ FreePool (ConsoleDevice);
+ return TRUE;
+ }
+
+ FreePool (Instance);
+ } while (TempDevicePath != NULL);
+
+ FreePool (ConsoleDevice);
+
+ return FALSE;
+}
+
+
+/**
+ Return whether the USB device path is in a short form.
+
+ @param DevicePath The device path to be tested.
+
+ @retval TRUE The device path is in short form.
+ @retval FALSE The device path is not in short form.
+**/
+BOOLEAN
+IsUsbShortForm (
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
+ )
+{
+ if ((DevicePathType (DevicePath) == MESSAGING_DEVICE_PATH) &&
+ ((DevicePathSubType (DevicePath) == MSG_USB_CLASS_DP) ||
+ (DevicePathSubType (DevicePath) == MSG_USB_WWID_DP)) ) {
+ return TRUE;
+ }
+
+ return FALSE;
+}
+
+/**
+ Connect the USB short form device path.
+
+ @param DevicePath USB short form device path
+
+ @retval EFI_SUCCESS Successfully connected the USB device
+ @retval EFI_NOT_FOUND Cannot connect the USB device
+ @retval EFI_INVALID_PARAMETER The device path is invalid.
+**/
+EFI_STATUS
+ConnectUsbShortFormDevicePath (
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
+ )
+{
+ EFI_STATUS Status;
+ EFI_HANDLE *Handles;
+ UINTN HandleCount;
+ UINTN Index;
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ UINT8 Class[3];
+ BOOLEAN AtLeastOneConnected;
+
+ //
+ // Check the passed in parameters
+ //
+ if (DevicePath == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ if (!IsUsbShortForm (DevicePath)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Find the usb host controller firstly, then connect with the remaining device path
+ //
+ AtLeastOneConnected = FALSE;
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiPciIoProtocolGuid,
+ NULL,
+ &HandleCount,
+ &Handles
+ );
+ for (Index = 0; Index < HandleCount; Index++) {
+ Status = gBS->HandleProtocol (
+ Handles[Index],
+ &gEfiPciIoProtocolGuid,
+ (VOID **) &PciIo
+ );
+ if (!EFI_ERROR (Status)) {
+ //
+ // Check whether the Pci device is the wanted usb host controller
+ //
+ Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x09, 3, &Class);
+ if (!EFI_ERROR (Status) &&
+ ((PCI_CLASS_SERIAL == Class[2]) && (PCI_CLASS_SERIAL_USB == Class[1]))) {
+ Status = gBS->ConnectController (
+ Handles[Index],
+ NULL,
+ DevicePath,
+ FALSE
+ );
+ if (!EFI_ERROR(Status)) {
+ AtLeastOneConnected = TRUE;
+ }
+ }
+ }
+ }
+
+ return AtLeastOneConnected ? EFI_SUCCESS : EFI_NOT_FOUND;
+}
+
+
+/**
+ Return whether the Handle is a vga handle.
+
+ @param Handle The handle to be tested.
+
+ @retval TRUE The handle is a vga handle.
+ @retval FALSE The handle is not a vga handle..
+**/
+BOOLEAN
+IsVgaHandle (
+ IN EFI_HANDLE Handle
+ )
+{
+ EFI_PCI_IO_PROTOCOL *PciIo;
+ PCI_TYPE00 Pci;
+ EFI_STATUS Status;
+
+ Status = gBS->HandleProtocol (
+ Handle,
+ &gEfiPciIoProtocolGuid,
+ (VOID **)&PciIo
+ );
+ if (!EFI_ERROR (Status)) {
+ Status = PciIo->Pci.Read (
+ PciIo,
+ EfiPciIoWidthUint32,
+ 0,
+ sizeof (Pci) / sizeof (UINT32),
+ &Pci
+ );
+ if (!EFI_ERROR (Status)) {
+ if (IS_PCI_VGA (&Pci) || IS_PCI_OLD_VGA (&Pci)) {
+ return TRUE;
+ }
+ }
+ }
+ return FALSE;
+}
+
+
+/**
+ Return whether the device path points to a video controller.
+
+ @param DevicePath The device path to be tested.
+
+ @retval TRUE The device path points to a video controller.
+ @retval FALSE The device path does not point to a video controller.
+**/
+EFI_HANDLE
+IsVideoController (
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
+ )
+{
+ EFI_DEVICE_PATH_PROTOCOL *DupDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
+ EFI_STATUS Status;
+ EFI_HANDLE DeviceHandle;
+
+ DupDevicePath = DuplicateDevicePath (DevicePath);
+ ASSERT (DupDevicePath != NULL);
+ if (DupDevicePath == NULL) {
+ return NULL;
+ }
+
+ TempDevicePath = DupDevicePath;
+ Status = gBS->LocateDevicePath (
+ &gEfiDevicePathProtocolGuid,
+ &TempDevicePath,
+ &DeviceHandle
+ );
+ FreePool (DupDevicePath);
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
+
+ if (IsVgaHandle (DeviceHandle)) {
+ return DeviceHandle;
+ } else {
+ return NULL;
+ }
+}
+
+
+/**
+ Return whether the device path is a GOP device path.
+
+ @param DevicePath The device path to be tested.
+
+ @retval TRUE The device path is a GOP device path.
+ @retval FALSE The device on the device path is not a GOP device path.
+**/
+BOOLEAN
+IsGopDevicePath (
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
+ )
+{
+ while (!IsDevicePathEndType (DevicePath)) {
+ if (DevicePathType (DevicePath) == ACPI_DEVICE_PATH &&
+ DevicePathSubType (DevicePath) == ACPI_ADR_DP) {
+ return TRUE;
+ }
+ DevicePath = NextDevicePathNode (DevicePath);
+ }
+ return FALSE;
+}
+
+
+/**
+ Remove all GOP device path instance from DevicePath and add the Gop to the DevicePath.
+
+ @param DevicePath The device path to be removed
+ @param Gop The device path to be added.
+
+ @retval Return The updated device path.
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+UpdateGopDevicePath (
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath,
+ EFI_DEVICE_PATH_PROTOCOL *Gop
+ )
+{
+ UINTN Size;
+ UINTN GopSize;
+ EFI_DEVICE_PATH_PROTOCOL *Temp;
+ EFI_DEVICE_PATH_PROTOCOL *Return;
+ EFI_DEVICE_PATH_PROTOCOL *Instance;
+ BOOLEAN Exist;
+
+ Exist = FALSE;
+ Return = NULL;
+ GopSize = GetDevicePathSize (Gop);
+ do {
+ Instance = GetNextDevicePathInstance (&DevicePath, &Size);
+ if (Instance == NULL) {
+ break;
+ }
+ if (!IsGopDevicePath (Instance) ||
+ (Size == GopSize && CompareMem (Instance, Gop, GopSize) == 0)
+ ) {
+ if (Size == GopSize && CompareMem (Instance, Gop, GopSize) == 0) {
+ Exist = TRUE;
+ }
+ Temp = Return;
+ Return = AppendDevicePathInstance (Return, Instance);
+ if (Temp != NULL) {
+ FreePool (Temp);
+ }
+ }
+ FreePool (Instance);
+ } while (DevicePath != NULL);
+
+ if (!Exist) {
+ Temp = Return;
+ Return = AppendDevicePathInstance (Return, Gop);
+ if (Temp != NULL) {
+ FreePool (Temp);
+ }
+ }
+ return Return;
+}
+
+
+/**
+ Get Graphics Controller Handle.
+
+ @param NeedTrustedConsole The flag to determine if trusted console
+ or non trusted console should be returned
+
+ @retval NULL Console not found
+ @retval PciHandles Successfully located
+**/
+EFI_HANDLE
+EFIAPI
+GetGraphicsController (
+ IN BOOLEAN NeedTrustedConsole
+ )
+{
+ EFI_STATUS Status;
+ UINTN Index;
+ EFI_HANDLE *PciHandles;
+ UINTN PciHandlesSize;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiPciIoProtocolGuid,
+ NULL,
+ &PciHandlesSize,
+ &PciHandles
+ );
+ if (EFI_ERROR (Status)) {
+ return NULL;
+ }
+
+ for (Index = 0; Index < PciHandlesSize; Index++) {
+ Status = gBS->HandleProtocol (
+ PciHandles[Index],
+ &gEfiDevicePathProtocolGuid,
+ (VOID **) &DevicePath
+ );
+ if (EFI_ERROR(Status)) {
+ continue;
+ }
+ if (!IsVgaHandle (PciHandles[Index])) {
+ continue;
+ }
+ if ((NeedTrustedConsole && IsTrustedConsole (ConOut, DevicePath)) ||
+ ((!NeedTrustedConsole) && (!IsTrustedConsole (ConOut, DevicePath)))) {
+ return PciHandles[Index];
+ }
+ }
+
+ return NULL;
+}
+
+
+/**
+ Updates Graphic ConOut variable.
+
+ @param NeedTrustedConsole The flag that determines if trusted console
+ or non trusted console should be returned
+**/
+VOID
+UpdateGraphicConOut (
+ IN BOOLEAN NeedTrustedConsole
+ )
+{
+ EFI_HANDLE GraphicsControllerHandle;
+ EFI_DEVICE_PATH_PROTOCOL *GopDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *ConOutDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *UpdatedConOutDevicePath;
+
+ //
+ // Update ConOut variable
+ //
+ GraphicsControllerHandle = GetGraphicsController (NeedTrustedConsole);
+ if (GraphicsControllerHandle != NULL) {
+ //
+ // Connect the GOP driver
+ //
+ gBS->ConnectController (GraphicsControllerHandle, NULL, NULL, TRUE);
+
+ //
+ // Get the GOP device path
+ // NOTE: We may get a device path that contains Controller node in it.
+ //
+ GopDevicePath = EfiBootManagerGetGopDevicePath (GraphicsControllerHandle);
+ if (GopDevicePath != NULL) {
+ GetEfiGlobalVariable2 (L"ConOut", (VOID **)&ConOutDevicePath, NULL);
+ UpdatedConOutDevicePath = UpdateGopDevicePath (ConOutDevicePath, GopDevicePath);
+ if (ConOutDevicePath != NULL) {
+ FreePool (ConOutDevicePath);
+ }
+ FreePool (GopDevicePath);
+ gRT->SetVariable (
+ L"ConOut",
+ &gEfiGlobalVariableGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_BOOTSERVICE_ACCESS,
+ GetDevicePathSize (UpdatedConOutDevicePath),
+ UpdatedConOutDevicePath
+ );
+ }
+ }
+}
+
+
+/**
+ The function connects the trusted consoles.
+**/
+VOID
+ConnectTrustedConsole (
+ VOID
+ )
+{
+ EFI_DEVICE_PATH_PROTOCOL *Consoles;
+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *Instance;
+ EFI_DEVICE_PATH_PROTOCOL *Next;
+ UINTN Size;
+ UINTN Index;
+ EFI_HANDLE Handle;
+ EFI_STATUS Status;
+ CHAR16 *ConsoleVar[] = {L"ConIn", L"ConOut"};
+ VOID *TrustedConsoleDevicepath;
+
+ TrustedConsoleDevicepath = PcdGetPtr (PcdTrustedConsoleInputDevicePath);
+ DumpDevicePath (L"TrustedConsoleIn", TrustedConsoleDevicepath);
+ TrustedConsoleDevicepath = PcdGetPtr (PcdTrustedConsoleOutputDevicePath);
+ DumpDevicePath (L"TrustedConsoleOut", TrustedConsoleDevicepath);
+
+ for (Index = 0; Index < sizeof (ConsoleVar) / sizeof (ConsoleVar[0]); Index++) {
+
+ GetEfiGlobalVariable2 (ConsoleVar[Index], (VOID **)&Consoles, NULL);
+
+ TempDevicePath = Consoles;
+ do {
+ Instance = GetNextDevicePathInstance (&TempDevicePath, &Size);
+ if (Instance == NULL) {
+ break;
+ }
+ if (IsTrustedConsole (Index, Instance)) {
+ if (IsUsbShortForm (Instance)) {
+ ConnectUsbShortFormDevicePath (Instance);
+ } else {
+ for (Next = Instance; !IsDevicePathEnd (Next); Next = NextDevicePathNode (Next)) {
+ if (DevicePathType (Next) == ACPI_DEVICE_PATH && DevicePathSubType (Next) == ACPI_ADR_DP) {
+ break;
+ } else if (DevicePathType (Next) == HARDWARE_DEVICE_PATH &&
+ DevicePathSubType (Next) == HW_CONTROLLER_DP &&
+ DevicePathType (NextDevicePathNode (Next)) == ACPI_DEVICE_PATH &&
+ DevicePathSubType (NextDevicePathNode (Next)) == ACPI_ADR_DP
+ ) {
+ break;
+ }
+ }
+ if (!IsDevicePathEnd (Next)) {
+ SetDevicePathEndNode (Next);
+ Status = EfiBootManagerConnectDevicePath (Instance, &Handle);
+ if (!EFI_ERROR (Status)) {
+ gBS->ConnectController (Handle, NULL, NULL, TRUE);
+ }
+ } else {
+ EfiBootManagerConnectDevicePath (Instance, NULL);
+ }
+ }
+ }
+ FreePool (Instance);
+ } while (TempDevicePath != NULL);
+
+ if (Consoles != NULL) {
+ FreePool (Consoles);
+ }
+ }
+}
+
+
+/**
+ The function connects the trusted Storages.
+**/
+VOID
+ConnectTrustedStorage (
+ VOID
+ )
+{
+ VOID *TrustedStorageDevicepath;
+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *Instance;
+ UINTN Size;
+ EFI_DEVICE_PATH_PROTOCOL *TempStorageDevicePath;
+ EFI_STATUS Status;
+ EFI_HANDLE DeviceHandle;
+
+ TrustedStorageDevicepath = PcdGetPtr (PcdTrustedStorageDevicePath);
+ DumpDevicePath (L"TrustedStorage", TrustedStorageDevicepath);
+
+ TempDevicePath = TrustedStorageDevicepath;
+ do {
+ Instance = GetNextDevicePathInstance (&TempDevicePath, &Size);
+ if (Instance == NULL) {
+ break;
+ }
+
+ EfiBootManagerConnectDevicePath (Instance, NULL);
+
+ TempStorageDevicePath = Instance;
+
+ Status = gBS->LocateDevicePath (
+ &gEfiDevicePathProtocolGuid,
+ &TempStorageDevicePath,
+ &DeviceHandle
+ );
+ if (!EFI_ERROR (Status)) {
+ gBS->ConnectController (DeviceHandle, NULL, NULL, FALSE);
+ }
+
+ FreePool (Instance);
+ } while (TempDevicePath != NULL);
+}
+
+
+/**
+ Check if current BootCurrent variable is internal shell boot option.
+
+ @retval TRUE BootCurrent is internal shell.
+ @retval FALSE BootCurrent is not internal shell.
+**/
+BOOLEAN
+BootCurrentIsInternalShell (
+ VOID
+ )
+{
+ UINTN VarSize;
+ UINT16 BootCurrent;
+ CHAR16 BootOptionName[16];
+ UINT8 *BootOption;
+ UINT8 *Ptr;
+ BOOLEAN Result;
+ EFI_STATUS Status;
+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;
+ EFI_DEVICE_PATH_PROTOCOL *LastDeviceNode;
+ EFI_GUID *GuidPoint;
+
+ BootOption = NULL;
+ Result = FALSE;
+
+ //
+ // Get BootCurrent variable
+ //
+ VarSize = sizeof (UINT16);
+ Status = gRT->GetVariable (
+ L"BootCurrent",
+ &gEfiGlobalVariableGuid,
+ NULL,
+ &VarSize,
+ &BootCurrent
+ );
+ if (EFI_ERROR (Status)) {
+ return FALSE;
+ }
+
+ //
+ // Create boot option Bootxxxx from BootCurrent
+ //
+ UnicodeSPrint (BootOptionName, sizeof(BootOptionName), L"Boot%04X", BootCurrent);
+
+ GetEfiGlobalVariable2 (BootOptionName, (VOID **) &BootOption, &VarSize);
+ if (BootOption == NULL || VarSize == 0) {
+ return FALSE;
+ }
+
+ Ptr = BootOption;
+ Ptr += sizeof (UINT32);
+ Ptr += sizeof (UINT16);
+ Ptr += StrSize ((CHAR16 *) Ptr);
+ TempDevicePath = (EFI_DEVICE_PATH_PROTOCOL *) Ptr;
+ LastDeviceNode = TempDevicePath;
+ while (!IsDevicePathEnd (TempDevicePath)) {
+ LastDeviceNode = TempDevicePath;
+ TempDevicePath = NextDevicePathNode (TempDevicePath);
+ }
+ GuidPoint = EfiGetNameGuidFromFwVolDevicePathNode (
+ (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *) LastDeviceNode
+ );
+ if ((GuidPoint != NULL) &&
+ ((CompareGuid (GuidPoint, &gUefiShellFileGuid)))) {
+ //
+ // if this option is internal shell, return TRUE
+ //
+ Result = TRUE;
+ }
+
+ if (BootOption != NULL) {
+ FreePool (BootOption);
+ BootOption = NULL;
+ }
+
+ return Result;
+}
+
+/**
+ This function will change video resolution and text mode
+ for internl shell when internal shell is launched.
+
+ @param None.
+
+ @retval EFI_SUCCESS Mode is changed successfully.
+ @retval Others Mode failed to changed.
+**/
+EFI_STATUS
+EFIAPI
+ChangeModeForInternalShell (
+ VOID
+ )
+{
+ EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput;
+ EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *SimpleTextOut;
+ UINTN SizeOfInfo;
+ EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info;
+ UINT32 MaxGopMode;
+ UINT32 MaxTextMode;
+ UINT32 ModeNumber;
+ UINTN HandleCount;
+ EFI_HANDLE *HandleBuffer;
+ EFI_STATUS Status;
+ UINTN Index;
+ UINTN CurrentColumn;
+ UINTN CurrentRow;
+
+ //
+ // Internal shell mode
+ //
+ UINT32 mShellModeColumn;
+ UINT32 mShellModeRow;
+ UINT32 mShellHorizontalResolution;
+ UINT32 mShellVerticalResolution;
+
+
+ //
+ // Get user defined text mode for internal shell only once.
+ //
+ mShellHorizontalResolution = PcdGet32 (PcdSetupVideoHorizontalResolution);
+ mShellVerticalResolution = PcdGet32 (PcdSetupVideoVerticalResolution);
+ mShellModeColumn = PcdGet32 (PcdSetupConOutColumn);
+ mShellModeRow = PcdGet32 (PcdSetupConOutRow);
+
+
+ Status = gBS->HandleProtocol (
+ gST->ConsoleOutHandle,
+ &gEfiGraphicsOutputProtocolGuid,
+ (VOID**)&GraphicsOutput
+ );
+ if (EFI_ERROR (Status)) {
+ GraphicsOutput = NULL;
+ }
+
+ Status = gBS->HandleProtocol (
+ gST->ConsoleOutHandle,
+ &gEfiSimpleTextOutProtocolGuid,
+ (VOID**)&SimpleTextOut
+ );
+ if (EFI_ERROR (Status)) {
+ SimpleTextOut = NULL;
+ }
+
+ if ((GraphicsOutput == NULL) || (SimpleTextOut == NULL)) {
+ return EFI_UNSUPPORTED;
+ }
+
+ MaxGopMode = GraphicsOutput->Mode->MaxMode;
+ MaxTextMode = SimpleTextOut->Mode->MaxMode;
+
+ //
+ // 1. If current video resolution is same with new video resolution,
+ // video resolution need not be changed.
+ // 1.1. If current text mode is same with new text mode, text mode need not be change.
+ // 1.2. If current text mode is different with new text mode, text mode need be change to new text mode.
+ // 2. If current video resolution is different with new video resolution, we need restart whole console drivers.
+ //
+ for (ModeNumber = 0; ModeNumber < MaxGopMode; ModeNumber++) {
+ Status = GraphicsOutput->QueryMode (
+ GraphicsOutput,
+ ModeNumber,
+ &SizeOfInfo,
+ &Info
+ );
+ if (!EFI_ERROR (Status)) {
+ if ((Info->HorizontalResolution == mShellHorizontalResolution) &&
+ (Info->VerticalResolution == mShellVerticalResolution)) {
+ if ((GraphicsOutput->Mode->Info->HorizontalResolution == mShellHorizontalResolution) &&
+ (GraphicsOutput->Mode->Info->VerticalResolution == mShellVerticalResolution)) {
+ //
+ // If current video resolution is same with new resolution,
+ // then check if current text mode is same with new text mode.
+ //
+ Status = SimpleTextOut->QueryMode (SimpleTextOut, SimpleTextOut->Mode->Mode, &CurrentColumn, &CurrentRow);
+ ASSERT_EFI_ERROR (Status);
+ if (CurrentColumn == mShellModeColumn && CurrentRow == mShellModeRow) {
+ //
+ // Current text mode is same with new text mode, text mode need not be change.
+ //
+ FreePool (Info);
+ return EFI_SUCCESS;
+ } else {
+ //
+ // Current text mode is different with new text mode, text mode need be change to new text mode.
+ //
+ for (Index = 0; Index < MaxTextMode; Index++) {
+ Status = SimpleTextOut->QueryMode (SimpleTextOut, Index, &CurrentColumn, &CurrentRow);
+ if (!EFI_ERROR(Status)) {
+ if ((CurrentColumn == mShellModeColumn) && (CurrentRow == mShellModeRow)) {
+ //
+ // New text mode is supported, set it.
+ //
+ Status = SimpleTextOut->SetMode (SimpleTextOut, Index);
+ ASSERT_EFI_ERROR (Status);
+ //
+ // Update text mode PCD.
+ //
+ Status = PcdSet32S (PcdConOutColumn, mShellModeColumn);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet32S (PcdConOutRow, mShellModeRow);
+ ASSERT_EFI_ERROR (Status);
+
+ FreePool (Info);
+ return EFI_SUCCESS;
+ }
+ }
+ }
+ if (Index == MaxTextMode) {
+ //
+ // If new text mode is not supported, return error.
+ //
+ FreePool (Info);
+ return EFI_UNSUPPORTED;
+ }
+ }
+ } else {
+ FreePool (Info);
+ //
+ // If current video resolution is not same with the new one, set new video resolution.
+ // In this case, the driver which produces simple text out need be restarted.
+ //
+ Status = GraphicsOutput->SetMode (GraphicsOutput, ModeNumber);
+ if (!EFI_ERROR (Status)) {
+ //
+ // Set PCD to restart GraphicsConsole and Consplitter to change video resolution
+ // and produce new text mode based on new resolution.
+ //
+ Status = PcdSet32S (PcdVideoHorizontalResolution, mShellHorizontalResolution);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet32S (PcdVideoVerticalResolution, mShellVerticalResolution);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet32S (PcdConOutColumn, mShellModeColumn);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = PcdSet32S (PcdConOutRow, mShellModeRow);
+ ASSERT_EFI_ERROR (Status);
+
+ Status = gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiSimpleTextOutProtocolGuid,
+ NULL,
+ &HandleCount,
+ &HandleBuffer
+ );
+ if (!EFI_ERROR (Status)) {
+ for (Index = 0; Index < HandleCount; Index++) {
+ gBS->DisconnectController (HandleBuffer[Index], NULL, NULL);
+ }
+ for (Index = 0; Index < HandleCount; Index++) {
+ gBS->ConnectController (HandleBuffer[Index], NULL, NULL, TRUE);
+ }
+ if (HandleBuffer != NULL) {
+ FreePool (HandleBuffer);
+ }
+ break;
+ }
+ }
+ }
+ }
+ FreePool (Info);
+ }
+ }
+
+ if (ModeNumber == MaxGopMode) {
+ //
+ // If the new resolution is not supported, return error.
+ //
+ return EFI_UNSUPPORTED;
+ }
+
+ return EFI_SUCCESS;
+}
+
+
+/**
+ The function connects the trusted consoles and then call the PP processing library interface.
+**/
+VOID
+ProcessTcgPp (
+ VOID
+ )
+{
+ gPPRequireUIConfirm |= Tcg2PhysicalPresenceLibNeedUserConfirm();
+
+ if (gPPRequireUIConfirm) {
+ ConnectTrustedConsole ();
+ }
+
+ Tcg2PhysicalPresenceLibProcessRequest (NULL);
+}
+
+
+/**
+ The function connects the trusted storage to perform TPerReset.
+**/
+VOID
+ProcessTcgMor (
+ VOID
+ )
+{
+ if (IsMorBitSet ()) {
+ ConnectTrustedConsole();
+ ConnectTrustedStorage();
+ }
+}
+
+
+/**
+ Update the ConIn variable with USB Keyboard device path,if its not already exists in ConIn
+**/
+VOID
+EnumUsbKeyboard (
+ VOID
+ )
+{
+ DEBUG ((DEBUG_INFO, "[EnumUsbKeyboard]\n"));
+ EfiBootManagerUpdateConsoleVariable (ConIn, (EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath, NULL);
+ //
+ // Append Usb Keyboard short form DevicePath into "ConInDev"
+ //
+ EfiBootManagerUpdateConsoleVariable (ConInDev, (EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath, NULL);
+}
+
+
+/**
+ Connect with predeined platform connect sequence,
+ the OEM/IBV can customize with their own connect sequence.
+
+ @param[in] BootMode Boot mode of this boot.
+**/
+VOID
+ConnectSequence (
+ IN EFI_BOOT_MODE BootMode
+ )
+{
+ EfiBootManagerConnectAll ();
+}
+
+/**
+ Connects Root Bridge
+ **/
+VOID
+ConnectRootBridge (
+ BOOLEAN Recursive
+ )
+{
+ UINTN RootBridgeHandleCount;
+ EFI_HANDLE *RootBridgeHandleBuffer;
+ UINTN RootBridgeIndex;
+
+ RootBridgeHandleCount = 0;
+ gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiPciRootBridgeIoProtocolGuid,
+ NULL,
+ &RootBridgeHandleCount,
+ &RootBridgeHandleBuffer
+ );
+ for (RootBridgeIndex = 0; RootBridgeIndex < RootBridgeHandleCount; RootBridgeIndex++) {
+ gBS->ConnectController (RootBridgeHandleBuffer[RootBridgeIndex], NULL, NULL, Recursive);
+ }
+}
+
+VOID
+AddConsoleVariable (
+ IN CONSOLE_TYPE ConsoleType,
+ IN EFI_DEVICE_PATH *ConsoleDevicePath
+ )
+{
+ EFI_DEVICE_PATH *TempDevicePath;
+ EFI_DEVICE_PATH *Instance;
+ UINTN Size;
+ EFI_HANDLE GraphicsControllerHandle;
+ EFI_DEVICE_PATH *GopDevicePath;
+
+ TempDevicePath = ConsoleDevicePath;
+ do {
+ Instance = GetNextDevicePathInstance (&TempDevicePath, &Size);
+ if (Instance == NULL) {
+ break;
+ }
+
+ switch (ConsoleType) {
+ case ConIn:
+ if (IsUsbShortForm (Instance)) {
+ //
+ // Append Usb Keyboard short form DevicePath into "ConInDev"
+ //
+ EfiBootManagerUpdateConsoleVariable (ConInDev, Instance, NULL);
+ }
+ EfiBootManagerUpdateConsoleVariable (ConsoleType, Instance, NULL);
+ break;
+ case ConOut:
+ GraphicsControllerHandle = IsVideoController (Instance);
+ if (GraphicsControllerHandle == NULL) {
+ EfiBootManagerUpdateConsoleVariable (ConsoleType, Instance, NULL);
+ } else {
+ //
+ // Connect the GOP driver
+ //
+ gBS->ConnectController (GraphicsControllerHandle, NULL, NULL, TRUE);
+ //
+ // Get the GOP device path
+ // NOTE: We may get a device path that contains Controller node in it.
+ //
+ GopDevicePath = EfiBootManagerGetGopDevicePath (GraphicsControllerHandle);
+ if (GopDevicePath != NULL) {
+ EfiBootManagerUpdateConsoleVariable (ConsoleType, GopDevicePath, NULL);
+ }
+ }
+ break;
+ default:
+ ASSERT(FALSE);
+ break;
+ }
+
+ FreePool (Instance);
+ } while (TempDevicePath != NULL);
+}
+
+
+/**
+ This is the callback function for PCI ENUMERATION COMPLETE.
+
+ @param[in] Event The Event this notify function registered to.
+ @param[in] Context Pointer to the context data registered to the Event.
+**/
+VOID
+EFIAPI
+BdsPciEnumCompleteCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_STATUS Status;
+ VOID *ProtocolPointer;
+ EFI_DEVICE_PATH_PROTOCOL *VarConOut;
+ EFI_DEVICE_PATH_PROTOCOL *VarConIn;
+
+ Status = EFI_SUCCESS;
+
+ //
+ // Check if this is first time called by EfiCreateProtocolNotifyEvent() or not,
+ // if it is, we will skip it until real event is triggered
+ //
+ Status = gBS->LocateProtocol (&gEfiPciEnumerationCompleteProtocolGuid, NULL, (VOID **) &ProtocolPointer);
+ if (EFI_SUCCESS != Status) {
+ return;
+ }
+ //gBS->CloseEvent (Event);
+
+ if (PcdGetBool (PcdUpdateConsoleInBds) == TRUE) {
+
+ DEBUG ((DEBUG_INFO, "Event BdsPciEnumCompleteCallback callback starts\n"));
+
+ gBootMode = GetBootModeHob ();
+
+ //
+ // Fill ConIn/ConOut in Full Configuration boot mode
+ //
+ DEBUG ((DEBUG_INFO, "PlatformBootManagerInit - %x\n", gBootMode));
+
+
+ if (gBootMode == BOOT_WITH_FULL_CONFIGURATION ||
+ gBootMode == BOOT_WITH_DEFAULT_SETTINGS ||
+ gBootMode == BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS ||
+ gBootMode == BOOT_IN_RECOVERY_MODE) {
+
+ GetEfiGlobalVariable2 (L"ConOut", (VOID **)&VarConOut, NULL);
+ if (VarConOut != NULL) {
+ FreePool (VarConOut);
+ }
+
+ GetEfiGlobalVariable2 (L"ConIn", (VOID **)&VarConIn, NULL);
+ if (VarConIn != NULL) {
+ FreePool (VarConIn);
+ }
+
+ //
+ // Only fill ConIn/ConOut when ConIn/ConOut is empty because we may drop to Full Configuration boot mode in non-first boot
+ //
+ if (VarConOut == NULL || VarConIn == NULL) {
+ if (PcdGetSize (PcdTrustedConsoleOutputDevicePath) >= sizeof(EFI_DEVICE_PATH_PROTOCOL)) {
+ AddConsoleVariable (ConOut, PcdGetPtr (PcdTrustedConsoleOutputDevicePath));
+ }
+ if (PcdGetSize (PcdTrustedConsoleInputDevicePath) >= sizeof(EFI_DEVICE_PATH_PROTOCOL)) {
+ AddConsoleVariable (ConIn, PcdGetPtr (PcdTrustedConsoleInputDevicePath));
+ }
+ }
+ }
+
+ //
+ // Enumerate USB keyboard
+ //
+ EnumUsbKeyboard ();
+
+ //
+ // For trusted console it must be handled here.
+ //
+ UpdateGraphicConOut (TRUE);
+
+ //
+ // Register Boot Options
+ //
+ RegisterDefaultBootOption ();
+
+ //
+ // Register Static Hot keys
+ //
+ RegisterStaticHotkey ();
+ }
+
+ //
+ // Process Physical Preo
+ //
+ PERF_START_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7010);
+ if (PcdGetBool (PcdTpm2Enable)) {
+ ProcessTcgPp ();
+ ProcessTcgMor ();
+ }
+ PERF_END_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7011);
+
+ //
+ // Perform memory test
+ // We should make all UEFI memory and GCD information populated before ExitPmAuth.
+ // SMM may consume these information.
+ //
+ MemoryTest((EXTENDMEM_COVERAGE_LEVEL) PcdGet32 (PcdPlatformMemoryCheckLevel));
+}
+
+/**
+ This is the callback function for Smm Ready To Lock.
+
+ @param[in] Event The Event this notify function registered to.
+ @param[in] Context Pointer to the context data registered to the Event.
+**/
+VOID
+EFIAPI
+BdsSmmReadyToLockCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ VOID *ProtocolPointer;
+ EFI_STATUS Status;
+ //
+ // Check if this is first time called by EfiCreateProtocolNotifyEvent() or not,
+ // if it is, we will skip it until real event is triggered
+ //
+ Status = gBS->LocateProtocol (&gEfiDxeSmmReadyToLockProtocolGuid, NULL, (VOID **) &ProtocolPointer);
+ if (EFI_SUCCESS != Status) {
+ return;
+ }
+
+ DEBUG ((DEBUG_INFO, "Event gEfiDxeSmmReadyToLockProtocolGuid callback starts\n"));
+
+ //
+ // Dispatch the deferred 3rd party images.
+ //
+ EfiBootManagerDispatchDeferredImages ();
+
+ if (PcdGetBool (PcdUpdateConsoleInBds) == TRUE) {
+ //
+ // For non-trusted console it must be handled here.
+ //
+ UpdateGraphicConOut (FALSE);
+ }
+}
+
+/**
+ ReadyToBoot callback to set video and text mode for internal shell boot.
+ That will not connect USB controller while CSM and FastBoot are disabled, we need to connect them
+ before booting to Shell for showing USB devices in Shell.
+
+ When FastBoot is enabled and Windows Console is the chosen Console behavior, input devices will not be connected
+ by default. Hence, when booting to EFI shell, connecting input consoles are required.
+
+ @param Event Pointer to this event
+ @param Context Event hanlder private data
+
+ @retval None.
+**/
+VOID
+EFIAPI
+BdsReadyToBootCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ DEBUG ((DEBUG_INFO, "BdsReadyToBootCallback\n"));
+
+ if (BootCurrentIsInternalShell ()) {
+
+ ChangeModeForInternalShell ();
+ EfiBootManagerConnectAllDefaultConsoles ();
+ gDS->Dispatch ();
+ }
+}
+
+
+/**
+ Before console after trusted console event callback
+
+ @param[in] Event The Event this notify function registered to.
+ @param[in] Context Pointer to the context data registered to the Event.
+**/
+VOID
+BdsBeforeConsoleAfterTrustedConsoleCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ DEBUG ((DEBUG_INFO, "Event gBdsEventBeforeConsoleBeforeEndOfDxeGuid callback starts\n"));
+
+ //
+ // Connect Root Bridge to make PCI BAR resource allocated and all PciIo created
+ //
+ ConnectRootBridge (FALSE);
+}
+
+
+/**
+ Before console before end of DXE event callback
+
+ @param[in] Event The Event this notify function registered to.
+ @param[in] Context Pointer to the context data registered to the Event.
+**/
+VOID
+BdsBeforeConsoleBeforeEndOfDxeGuidCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ DEBUG ((DEBUG_INFO, "Event gBdsBeforeConsoleBeforeEndOfDxeGuid callback starts\n"));
+
+}
+
+
+/**
+ After console ready before boot option event callback
+
+ @param[in] Event The Event this notify function registered to.
+ @param[in] Context Pointer to the context data registered to the Event.
+**/
+VOID
+BdsAfterConsoleReadyBeforeBootOptionCallback (
+ IN EFI_EVENT Event,
+ IN VOID *Context
+ )
+{
+ EFI_BOOT_MODE LocalBootMode;
+ EFI_STATUS Status;
+ BOOLEAN IsFirstBoot;
+ UINTN DataSize;
+
+ DEBUG ((DEBUG_INFO, "Event gBdsAfterConsoleReadyBeforeBootOptionEvent callback starts\n"));
+ //
+ // Get current Boot Mode
+ //
+ LocalBootMode = gBootMode;
+ DEBUG ((DEBUG_INFO, "Current local bootmode - %x\n", LocalBootMode));
+
+ //
+ // Go the different platform policy with different boot mode
+ // Notes: this part code can be change with the table policy
+ //
+ switch (LocalBootMode) {
+ case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:
+ case BOOT_WITH_MINIMAL_CONFIGURATION:
+ case BOOT_ON_S4_RESUME:
+ //
+ // Perform some platform specific connect sequence
+ //
+ if (PcdGetBool (PcdFastBoot) == FALSE) {
+ PERF_START_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7050);
+ ConnectSequence (LocalBootMode);
+ PERF_END_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7051);
+ }
+
+ break;
+
+ case BOOT_WITH_FULL_CONFIGURATION:
+ case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS:
+ case BOOT_WITH_DEFAULT_SETTINGS:
+ default:
+ //
+ // Perform some platform specific connect sequence
+ //
+ ConnectSequence (LocalBootMode);
+
+ //
+ // Only in Full Configuration boot mode we do the enumeration of boot device
+ //
+ //
+ // Dispatch all but Storage Oprom explicitly, because we assume Int13Thunk driver is there.
+ //
+
+ //
+ // PXE boot option may appear after boot option enumeration
+ //
+
+ EfiBootManagerRefreshAllBootOption ();
+ DataSize = sizeof (BOOLEAN);
+ Status = gRT->GetVariable (
+ IS_FIRST_BOOT_VAR_NAME,
+ &gEfiCallerIdGuid,
+ NULL,
+ &DataSize,
+ &IsFirstBoot
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // If can't find the variable, see it as the first boot
+ //
+ IsFirstBoot = TRUE;
+ }
+
+ if (IsFirstBoot) {
+ //
+ // In the first boot, sort the boot option
+ //
+ EfiBootManagerSortLoadOptionVariable (LoadOptionTypeBoot, CompareBootOption);
+ IsFirstBoot = FALSE;
+ Status = gRT->SetVariable (
+ IS_FIRST_BOOT_VAR_NAME,
+ &gEfiCallerIdGuid,
+ EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
+ sizeof (BOOLEAN),
+ &IsFirstBoot
+ );
+ }
+
+ break;
+ }
+
+ if (PcdGetBool (PcdFastBoot) == FALSE) {
+ Print (L"Press F2 for Setup, or F7 for BootMenu!\n");
+ }
+
+
+}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf
new file mode 100644
index 0000000000..a664380c39
--- /dev/null
+++ b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf
@@ -0,0 +1,99 @@
+### @file
+# Module Information file for the Bds Hook Library.
+#
+# Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, American Megatrends International LLC.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+###
+
+[Defines]
+ INF_VERSION = 0x00010017
+ BASE_NAME = BoardBdsHookLib
+ FILE_GUID = 649A7502-7301-4E3A-A99B-EA91AD6DD7A8
+ VERSION_STRING = 1.0
+ MODULE_TYPE = DXE_DRIVER
+ LIBRARY_CLASS = BoardBdsHookLib|DXE_DRIVER
+
+[LibraryClasses]
+ BaseLib
+ MemoryAllocationLib
+ UefiBootServicesTableLib
+ UefiRuntimeServicesTableLib
+ BaseMemoryLib
+ DebugLib
+ PcdLib
+ PrintLib
+ DevicePathLib
+ UefiLib
+ HobLib
+ DxeServicesLib
+ DxeServicesTableLib
+ HiiLib
+ UefiBootManagerLib
+ PerformanceLib
+ TimerLib
+ Tcg2PhysicalPresenceLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ SecurityPkg/SecurityPkg.dec
+ MinPlatformPkg/MinPlatformPkg.dec
+ BoardModulePkg/BoardModulePkg.dec
+ PurleyOpenBoardPkg/OpenBoardPkg.dec
+
+[Pcd]
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable ## CONSUMES
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn ## PRODUCES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution ## CONSUMES
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand ## PRODUCES
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformMemoryCheckLevel ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath ## CONSUMES
+ gMinPlatformPkgTokenSpaceGuid.PcdTrustedStorageDevicePath ## CONSUMES
+ gPlatformTokenSpaceGuid.PcdUpdateConsoleInBds ## CONSUMES
+ gPlatformTokenSpaceGuid.PcdFastBoot ## CONSUMES
+
+[Sources]
+ BoardBdsHook.h
+ BoardBdsHookLib.c
+ BoardMemoryTest.c
+ BoardBootOption.c
+
+[Protocols]
+ gEfiPciRootBridgeIoProtocolGuid ## CONSUMES
+ gEfiPciIoProtocolGuid ## CONSUMES
+ gEfiCpuIo2ProtocolGuid ## CONSUMES
+ gEfiDxeSmmReadyToLockProtocolGuid ## PRODUCES
+ gEfiGenericMemTestProtocolGuid ## CONSUMES
+ gEfiDiskInfoProtocolGuid ## CONSUMES
+ gEfiDevicePathToTextProtocolGuid ## CONSUMES
+ gEfiSimpleTextInputExProtocolGuid ## CONSUMES
+ gEfiFirmwareVolume2ProtocolGuid ## CONSUMES
+ gEfiFormBrowser2ProtocolGuid ## CONSUMES
+ gEfiGenericMemTestProtocolGuid ## CONSUMES
+ gEfiDxeSmmReadyToLockProtocolGuid
+
+[Guids]
+ gEfiGlobalVariableGuid ## PRODUCES
+ gEfiMemoryOverwriteControlDataGuid ## PRODUCES
+ gEfiEndOfDxeEventGroupGuid ## CONSUMES
+ gBdsEventBeforeConsoleAfterTrustedConsoleGuid
+ gBdsEventBeforeConsoleBeforeEndOfDxeGuid
+ gBdsEventAfterConsoleReadyBeforeBootOptionGuid
+
+[Depex.common.DXE_DRIVER]
+ gEfiVariableArchProtocolGuid
+
+[Depex]
+ TRUE
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/PlatformBootOption.c b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
similarity index 87%
rename from Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/PlatformBootOption.c
rename to Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
index 84aa097d58..cb461ae041 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/PlatformBootOption.c
+++ b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardBootOption.c
@@ -1,559 +1,587 @@
-/** @file

- Driver for Platform Boot Options support.

-

-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>

-SPDX-License-Identifier: BSD-2-Clause-Patent

-

-**/

-

-#include "BdsPlatform.h"

-

-#include <Library/PcdLib.h>

-

-BOOLEAN mContinueBoot = FALSE;

-BOOLEAN mBootMenuBoot = FALSE;

-BOOLEAN mPxeBoot = FALSE;

-BOOLEAN mHotKeypressed = FALSE;

-EFI_EVENT HotKeyEvent = NULL;

-

-UINTN mBootMenuOptionNumber;

-

-EFI_DEVICE_PATH_PROTOCOL *

-BdsCreateShellDevicePath (

- VOID

- )

-/*++

-

-Routine Description:

-

- This function will create a SHELL BootOption to boot.

-

-Arguments:

-

- None.

-

-Returns:

-

- Shell Device path for booting.

-

---*/

-{

- UINTN FvHandleCount;

- EFI_HANDLE *FvHandleBuffer;

- UINTN Index;

- EFI_STATUS Status;

- EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;

- UINTN Size;

- UINT32 AuthenticationStatus;

- EFI_DEVICE_PATH_PROTOCOL *DevicePath;

- VOID *Buffer;

-

- DevicePath = NULL;

- Status = EFI_SUCCESS;

-

- DEBUG ((DEBUG_INFO, "BdsCreateShellDevicePath\n"));

- gBS->LocateHandleBuffer (

- ByProtocol,

- &gEfiFirmwareVolume2ProtocolGuid,

- NULL,

- &FvHandleCount,

- &FvHandleBuffer

- );

-

- for (Index = 0; Index < FvHandleCount; Index++) {

- gBS->HandleProtocol (

- FvHandleBuffer[Index],

- &gEfiFirmwareVolume2ProtocolGuid,

- (VOID **) &Fv

- );

-

- Buffer = NULL;

- Size = 0;

- Status = Fv->ReadSection (

- Fv,

- &gUefiShellFileGuid,

- EFI_SECTION_PE32,

- 0,

- &Buffer,

- &Size,

- &AuthenticationStatus

- );

- if (EFI_ERROR (Status)) {

- //

- // Skip if no shell file in the FV

- //

- continue;

- } else {

- //

- // Found the shell

- //

- break;

- }

- }

-

- if (EFI_ERROR (Status)) {

- //

- // No shell present

- //

- if (FvHandleCount) {

- FreePool (FvHandleBuffer);

- }

- return NULL;

- }

- //

- // Build the shell boot option

- //

- DevicePath = DevicePathFromHandle (FvHandleBuffer[Index]);

-

- if (FvHandleCount) {

- FreePool (FvHandleBuffer);

- }

-

- return DevicePath;

-}

-

-

-EFI_STATUS

-CreateFvBootOption (

- EFI_GUID *FileGuid,

- CHAR16 *Description,

- EFI_BOOT_MANAGER_LOAD_OPTION *BootOption,

- UINT32 Attributes,

- UINT8 *OptionalData, OPTIONAL

- UINT32 OptionalDataSize

- )

-{

- EFI_STATUS Status;

- EFI_DEVICE_PATH_PROTOCOL *DevicePath;

- EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;

- MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;

- EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;

- UINT32 AuthenticationStatus;

- VOID *Buffer;

- UINTN Size;

-

- if ((BootOption == NULL) || (FileGuid == NULL) || (Description == NULL)) {

- return EFI_INVALID_PARAMETER;

- }

-

- EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);

-

- if (!CompareGuid (&gUefiShellFileGuid, FileGuid)) {

- Status = gBS->HandleProtocol (

- gImageHandle,

- &gEfiLoadedImageProtocolGuid,

- (VOID **) &LoadedImage

- );

- if (!EFI_ERROR (Status)) {

- Status = gBS->HandleProtocol (

- LoadedImage->DeviceHandle,

- &gEfiFirmwareVolume2ProtocolGuid,

- (VOID **) &Fv

- );

- if (!EFI_ERROR (Status)) {

- Buffer = NULL;

- Size = 0;

- Status = Fv->ReadSection (

- Fv,

- FileGuid,

- EFI_SECTION_PE32,

- 0,

- &Buffer,

- &Size,

- &AuthenticationStatus

- );

- if (Buffer != NULL) {

- FreePool (Buffer);

- }

- }

- }

- if (EFI_ERROR (Status)) {

- return EFI_NOT_FOUND;

- }

-

- DevicePath = AppendDevicePathNode (

- DevicePathFromHandle (LoadedImage->DeviceHandle),

- (EFI_DEVICE_PATH_PROTOCOL *) &FileNode

- );

- } else {

- DevicePath = AppendDevicePathNode (

- BdsCreateShellDevicePath (),

- (EFI_DEVICE_PATH_PROTOCOL *) &FileNode

- );

- }

-

- Status = EfiBootManagerInitializeLoadOption (

- BootOption,

- LoadOptionNumberUnassigned,

- LoadOptionTypeBoot,

- Attributes,

- Description,

- DevicePath,

- OptionalData,

- OptionalDataSize

- );

- FreePool (DevicePath);

- return Status;

-}

-

-EFI_GUID mUiFile = {

- 0x462CAA21, 0x7614, 0x4503, { 0x83, 0x6E, 0x8A, 0xB6, 0xF4, 0x66, 0x23, 0x31 }

-};

-EFI_GUID mBootMenuFile = {

- 0xEEC25BDC, 0x67F2, 0x4D95, { 0xB1, 0xD5, 0xF8, 0x1B, 0x20, 0x39, 0xD1, 0x1D }

-};

-

-

-/**

- Return the index of the load option in the load option array.

-

- The function consider two load options are equal when the

- OptionType, Attributes, Description, FilePath and OptionalData are equal.

-

- @param Key Pointer to the load option to be found.

- @param Array Pointer to the array of load options to be found.

- @param Count Number of entries in the Array.

-

- @retval -1 Key wasn't found in the Array.

- @retval 0 ~ Count-1 The index of the Key in the Array.

-**/

-INTN

-PlatformFindLoadOption (

- IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key,

- IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array,

- IN UINTN Count

- )

-{

- UINTN Index;

-

- for (Index = 0; Index < Count; Index++) {

- if ((Key->OptionType == Array[Index].OptionType) &&

- (Key->Attributes == Array[Index].Attributes) &&

- (StrCmp (Key->Description, Array[Index].Description) == 0) &&

- (CompareMem (Key->FilePath, Array[Index].FilePath, GetDevicePathSize (Key->FilePath)) == 0) &&

- (Key->OptionalDataSize == Array[Index].OptionalDataSize) &&

- (CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->OptionalDataSize) == 0)) {

- return (INTN) Index;

- }

- }

-

- return -1;

-}

-

-UINTN

-RegisterFvBootOption (

- EFI_GUID *FileGuid,

- CHAR16 *Description,

- UINTN Position,

- UINT32 Attributes,

- UINT8 *OptionalData, OPTIONAL

- UINT32 OptionalDataSize

- )

-{

- EFI_STATUS Status;

- UINTN OptionIndex;

- EFI_BOOT_MANAGER_LOAD_OPTION NewOption;

- EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;

- UINTN BootOptionCount;

-

- NewOption.OptionNumber = LoadOptionNumberUnassigned;

- Status = CreateFvBootOption (FileGuid, Description, &NewOption, Attributes, OptionalData, OptionalDataSize);

- if (!EFI_ERROR (Status)) {

- BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOptionTypeBoot);

-

- OptionIndex = PlatformFindLoadOption (&NewOption, BootOptions, BootOptionCount);

-

- if (OptionIndex == -1) {

- Status = EfiBootManagerAddLoadOptionVariable (&NewOption, Position);

- ASSERT_EFI_ERROR (Status);

- } else {

- NewOption.OptionNumber = BootOptions[OptionIndex].OptionNumber;

- }

- EfiBootManagerFreeLoadOption (&NewOption);

- EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);

- }

-

- return NewOption.OptionNumber;

-}

-

-

-

-VOID

-EFIAPI

-PlatformBootManagerWaitCallback (

- UINT16 TimeoutRemain

- )

-{

- EFI_STATUS Status;

- EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *TxtInEx;

- EFI_KEY_DATA KeyData;

- BOOLEAN PausePressed;

-

- //

- // Pause on PAUSE key

- //

- Status = gBS->HandleProtocol (gST->ConsoleInHandle, &gEfiSimpleTextInputExProtocolGuid, (VOID **) &TxtInEx);

- ASSERT_EFI_ERROR (Status);

-

- PausePressed = FALSE;

-

- while (TRUE) {

- Status = TxtInEx->ReadKeyStrokeEx (TxtInEx, &KeyData);

- if (EFI_ERROR (Status)) {

- break;

- }

-

- if (KeyData.Key.ScanCode == SCAN_PAUSE) {

- PausePressed = TRUE;

- break;

- }

- }

-

- //

- // Loop until non-PAUSE key pressed

- //

- while (PausePressed) {

- Status = TxtInEx->ReadKeyStrokeEx (TxtInEx, &KeyData);

- if (!EFI_ERROR (Status)) {

- DEBUG ((

- DEBUG_INFO, "[PauseCallback] %x/%x %x/%x\n",

- KeyData.Key.ScanCode, KeyData.Key.UnicodeChar,

- KeyData.KeyState.KeyShiftState, KeyData.KeyState.KeyToggleState

- ));

- PausePressed = (BOOLEAN) (KeyData.Key.ScanCode == SCAN_PAUSE);

- }

- }

-}

-

-

-EFI_GUID gUefiShellFileGuid = { 0x7C04A583, 0x9E3E, 0x4f1c, { 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } };

-

-#define INTERNAL_UEFI_SHELL_NAME L"Internal UEFI Shell 2.0"

-#define UEFI_HARD_DRIVE_NAME L"UEFI Hard Drive"

-

-VOID

-RegisterDefaultBootOption (

- VOID

- )

-{

-#if 0

- EFI_DEVICE_PATH_PROTOCOL *DevicePath;

- EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;

- MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;

-#endif

- UINT16 *ShellData;

- UINT32 ShellDataSize;

-

- ShellData = NULL;

- ShellDataSize = 0;

- RegisterFvBootOption (&gUefiShellFileGuid, INTERNAL_UEFI_SHELL_NAME, (UINTN) -1, LOAD_OPTION_ACTIVE, (UINT8 *)ShellData, ShellDataSize);

-

- //

- // Boot Menu

- //

- mBootMenuOptionNumber = RegisterFvBootOption (&mBootMenuFile, L"Boot Device List", (UINTN) -1, LOAD_OPTION_CATEGORY_APP | LOAD_OPTION_ACTIVE | LOAD_OPTION_HIDDEN, NULL, 0);

-

- if (mBootMenuOptionNumber == LoadOptionNumberUnassigned) {

- DEBUG ((DEBUG_INFO, "BootMenuOptionNumber (%d) should not be same to LoadOptionNumberUnassigned(%d).\n", mBootMenuOptionNumber, LoadOptionNumberUnassigned));

- }

-#if 0

- //

- // Boot Manager Menu

- //

- EfiInitializeFwVolDevicepathNode (&FileNode, &mUiFile);

-

- gBS->HandleProtocol (

- gImageHandle,

- &gEfiLoadedImageProtocolGuid,

- (VOID **) &LoadedImage

- );

- DevicePath = AppendDevicePathNode (DevicePathFromHandle (LoadedImage->DeviceHandle), (EFI_DEVICE_PATH_PROTOCOL *) &FileNode);

-#endif

-

-}

-

-VOID

-RegisterBootOptionHotkey (

- UINT16 OptionNumber,

- EFI_INPUT_KEY *Key,

- BOOLEAN Add

- )

-{

- EFI_STATUS Status;

-

- if (!Add) {

- //

- // No enter hotkey when force to setup or there is no boot option

- //

- Status = EfiBootManagerDeleteKeyOptionVariable (NULL, 0, Key, NULL);

- ASSERT (Status == EFI_SUCCESS || Status == EFI_NOT_FOUND);

- } else {

- //

- // Register enter hotkey for the first boot option

- //

- Status = EfiBootManagerAddKeyOptionVariable (NULL, OptionNumber, 0, Key,NULL);

- ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);

- }

-}

-

-EFI_STATUS

-EFIAPI

-DetectKeypressCallback (

- IN EFI_KEY_DATA *KeyData

-)

-{

- mHotKeypressed = TRUE;

-

- if (HotKeyEvent != NULL) {

- gBS->SignalEvent(HotKeyEvent);

- }

-

- return EFI_SUCCESS;

-}

-

-/**

- This function is called after all the boot options are enumerated and ordered properly.

-**/

-VOID

-RegisterStaticHotkey (

- VOID

- )

-{

-

- EFI_INPUT_KEY Enter;

- EFI_KEY_DATA F2;

- EFI_KEY_DATA F7;

- BOOLEAN EnterSetup;

- EFI_STATUS Status;

- EFI_BOOT_MANAGER_LOAD_OPTION BootOption;

-

- EnterSetup = FALSE;

-

- //

- // [Enter]

- //

- mContinueBoot = !EnterSetup;

- if (mContinueBoot) {

- Enter.ScanCode = SCAN_NULL;

- Enter.UnicodeChar = CHAR_CARRIAGE_RETURN;

- EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);

- }

-

-

- //

- // [F2]/[F7]

- //

- F2.Key.ScanCode = SCAN_F2;

- F2.Key.UnicodeChar = CHAR_NULL;

- F2.KeyState.KeyShiftState = EFI_SHIFT_STATE_VALID;

- F2.KeyState.KeyToggleState = 0;

- Status = EfiBootManagerGetBootManagerMenu (&BootOption);

- ASSERT_EFI_ERROR (Status);

- RegisterBootOptionHotkey ((UINT16) BootOption.OptionNumber, &F2.Key, TRUE);

- EfiBootManagerFreeLoadOption (&BootOption);

-

- F7.Key.ScanCode = SCAN_F7;

- F7.Key.UnicodeChar = CHAR_NULL;

- F7.KeyState.KeyShiftState = EFI_SHIFT_STATE_VALID;

- F7.KeyState.KeyToggleState = 0;

- mBootMenuBoot = !EnterSetup;

- RegisterBootOptionHotkey ((UINT16) mBootMenuOptionNumber, &F7.Key, mBootMenuBoot);

-

-}

-

-UINT8

-BootOptionType (

- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath

- )

-{

- EFI_DEVICE_PATH_PROTOCOL *Node;

- EFI_DEVICE_PATH_PROTOCOL *NextNode;

-

- for (Node = DevicePath; !IsDevicePathEndType (Node); Node = NextDevicePathNode (Node)) {

- if (DevicePathType (Node) == MESSAGING_DEVICE_PATH) {

- //

- // Make sure the device path points to the driver device.

- //

- NextNode = NextDevicePathNode (Node);

- if (DevicePathSubType(NextNode) == MSG_DEVICE_LOGICAL_UNIT_DP) {

- //

- // if the next node type is Device Logical Unit, which specify the Logical Unit Number (LUN),

- // skip it

- //

- NextNode = NextDevicePathNode (NextNode);

- }

- if (IsDevicePathEndType (NextNode)) {

- if ((DevicePathType (Node) == MESSAGING_DEVICE_PATH)) {

- return DevicePathSubType (Node);

- } else {

- return MSG_SATA_DP;

- }

- }

- }

- }

-

- return (UINT8) -1;

-}

-

-/**

- Returns the priority number.

- OptionType EFI

- ------------------------------------

- PXE 2

- DVD 4

- USB 6

- NVME 7

- HDD 8

- EFI Shell 9

- Others 100

-

- @param BootOption

-**/

-UINTN

-BootOptionPriority (

- CONST EFI_BOOT_MANAGER_LOAD_OPTION *BootOption

- )

-{

- //

- // EFI boot options

- //

- switch (BootOptionType (BootOption->FilePath)) {

- case MSG_MAC_ADDR_DP:

- case MSG_VLAN_DP:

- case MSG_IPv4_DP:

- case MSG_IPv6_DP:

- return 2;

-

- case MSG_SATA_DP:

- case MSG_ATAPI_DP:

- case MSG_UFS_DP:

- case MSG_NVME_NAMESPACE_DP:

- return 4;

-

- case MSG_USB_DP:

- return 6;

-

- }

- if (StrCmp (BootOption->Description, INTERNAL_UEFI_SHELL_NAME) == 0) {

- if (PcdGetBool (PcdBootToShellOnly)) {

- return 0;

- }

- return 9;

- }

- if (StrCmp (BootOption->Description, UEFI_HARD_DRIVE_NAME) == 0) {

- return 8;

- }

- return 100;

-}

-

-INTN

-EFIAPI

-CompareBootOption (

- CONST VOID *Left,

- CONST VOID *Right

- )

-{

- return BootOptionPriority ((EFI_BOOT_MANAGER_LOAD_OPTION *) Left) -

- BootOptionPriority ((EFI_BOOT_MANAGER_LOAD_OPTION *) Right);

-}

-

+/** @file
+ Driver for Platform Boot Options support.
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BoardBdsHook.h"
+
+BOOLEAN mContinueBoot = FALSE;
+BOOLEAN mBootMenuBoot = FALSE;
+BOOLEAN mPxeBoot = FALSE;
+BOOLEAN mHotKeypressed = FALSE;
+EFI_EVENT HotKeyEvent = NULL;
+
+UINTN mBootMenuOptionNumber;
+UINTN mSetupOptionNumber;
+
+
+/**
+ This function will create a SHELL BootOption to boot.
+
+ @return Shell Device path for booting.
+**/
+EFI_DEVICE_PATH_PROTOCOL *
+BdsCreateShellDevicePath (
+ VOID
+ )
+{
+ UINTN FvHandleCount;
+ EFI_HANDLE *FvHandleBuffer;
+ UINTN Index;
+ EFI_STATUS Status;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
+ UINTN Size;
+ UINT32 AuthenticationStatus;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ VOID *Buffer;
+
+ DevicePath = NULL;
+ Status = EFI_SUCCESS;
+
+ DEBUG ((DEBUG_INFO, "BdsCreateShellDevicePath\n"));
+ gBS->LocateHandleBuffer (
+ ByProtocol,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ NULL,
+ &FvHandleCount,
+ &FvHandleBuffer
+ );
+
+ for (Index = 0; Index < FvHandleCount; Index++) {
+ gBS->HandleProtocol (
+ FvHandleBuffer[Index],
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **) &Fv
+ );
+
+ Buffer = NULL;
+ Size = 0;
+ Status = Fv->ReadSection (
+ Fv,
+ &gUefiShellFileGuid,
+ EFI_SECTION_PE32,
+ 0,
+ &Buffer,
+ &Size,
+ &AuthenticationStatus
+ );
+ if (EFI_ERROR (Status)) {
+ //
+ // Skip if no shell file in the FV
+ //
+ continue;
+ } else {
+ //
+ // Found the shell
+ //
+ break;
+ }
+ }
+
+ if (EFI_ERROR (Status)) {
+ //
+ // No shell present
+ //
+ if (FvHandleCount) {
+ FreePool (FvHandleBuffer);
+ }
+ return NULL;
+ }
+ //
+ // Build the shell boot option
+ //
+ DevicePath = DevicePathFromHandle (FvHandleBuffer[Index]);
+
+ if (FvHandleCount) {
+ FreePool (FvHandleBuffer);
+ }
+
+ return DevicePath;
+}
+
+
+EFI_STATUS
+CreateFvBootOption (
+ EFI_GUID *FileGuid,
+ CHAR16 *Description,
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOption,
+ UINT32 Attributes,
+ UINT8 *OptionalData, OPTIONAL
+ UINT32 OptionalDataSize
+ )
+{
+ EFI_STATUS Status;
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;
+ EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
+ MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
+ EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;
+ UINT32 AuthenticationStatus;
+ VOID *Buffer;
+ UINTN Size;
+
+ if ((BootOption == NULL) || (FileGuid == NULL) || (Description == NULL)) {
+ return EFI_INVALID_PARAMETER;
+ }
+
+ EfiInitializeFwVolDevicepathNode (&FileNode, FileGuid);
+
+ if (!CompareGuid (&gUefiShellFileGuid, FileGuid)) {
+ Status = gBS->HandleProtocol (
+ gImageHandle,
+ &gEfiLoadedImageProtocolGuid,
+ (VOID **) &LoadedImage
+ );
+ if (!EFI_ERROR (Status)) {
+ Status = gBS->HandleProtocol (
+ LoadedImage->DeviceHandle,
+ &gEfiFirmwareVolume2ProtocolGuid,
+ (VOID **) &Fv
+ );
+ if (!EFI_ERROR (Status)) {
+ Buffer = NULL;
+ Size = 0;
+ Status = Fv->ReadSection (
+ Fv,
+ FileGuid,
+ EFI_SECTION_PE32,
+ 0,
+ &Buffer,
+ &Size,
+ &AuthenticationStatus
+ );
+ if (Buffer != NULL) {
+ FreePool (Buffer);
+ }
+ }
+ }
+ if (EFI_ERROR (Status)) {
+ return EFI_NOT_FOUND;
+ }
+
+ DevicePath = AppendDevicePathNode (
+ DevicePathFromHandle (LoadedImage->DeviceHandle),
+ (EFI_DEVICE_PATH_PROTOCOL *) &FileNode
+ );
+ } else {
+ DevicePath = AppendDevicePathNode (
+ BdsCreateShellDevicePath (),
+ (EFI_DEVICE_PATH_PROTOCOL *) &FileNode
+ );
+ }
+
+ Status = EfiBootManagerInitializeLoadOption (
+ BootOption,
+ LoadOptionNumberUnassigned,
+ LoadOptionTypeBoot,
+ Attributes,
+ Description,
+ DevicePath,
+ OptionalData,
+ OptionalDataSize
+ );
+ FreePool (DevicePath);
+ return Status;
+}
+
+EFI_GUID mUiFile = {
+ 0x462CAA21, 0x7614, 0x4503, { 0x83, 0x6E, 0x8A, 0xB6, 0xF4, 0x66, 0x23, 0x31 }
+};
+EFI_GUID mBootMenuFile = {
+ 0xEEC25BDC, 0x67F2, 0x4D95, { 0xB1, 0xD5, 0xF8, 0x1B, 0x20, 0x39, 0xD1, 0x1D }
+};
+
+
+/**
+ Return the index of the load option in the load option array.
+
+ The function consider two load options are equal when the
+ OptionType, Attributes, Description, FilePath and OptionalData are equal.
+
+ @param Key Pointer to the load option to be found.
+ @param Array Pointer to the array of load options to be found.
+ @param Count Number of entries in the Array.
+
+ @retval -1 Key wasn't found in the Array.
+ @retval 0 ~ Count-1 The index of the Key in the Array.
+**/
+INTN
+PlatformFindLoadOption (
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Key,
+ IN CONST EFI_BOOT_MANAGER_LOAD_OPTION *Array,
+ IN UINTN Count
+ )
+{
+ UINTN Index;
+
+ for (Index = 0; Index < Count; Index++) {
+ if ((Key->OptionType == Array[Index].OptionType) &&
+ (Key->Attributes == Array[Index].Attributes) &&
+ (StrCmp (Key->Description, Array[Index].Description) == 0) &&
+ (CompareMem (Key->FilePath, Array[Index].FilePath, GetDevicePathSize (Key->FilePath)) == 0) &&
+ (Key->OptionalDataSize == Array[Index].OptionalDataSize) &&
+ (CompareMem (Key->OptionalData, Array[Index].OptionalData, Key->OptionalDataSize) == 0)) {
+ return (INTN) Index;
+ }
+ }
+
+ return -1;
+}
+
+
+/**
+ Registers a boot option
+
+ @param FileGuid Boot file GUID
+ @param Description Boot option discription
+ @param Position Position of the new load option to put in the ****Order variable.
+ @param Attributes Boot option attributes
+ @param OptionalData Optional data of the boot option.
+ @param OptionalDataSize Size of the optional data of the boot option
+
+ @return boot option number
+**/
+UINTN
+RegisterFvBootOption (
+ EFI_GUID *FileGuid,
+ CHAR16 *Description,
+ UINTN Position,
+ UINT32 Attributes,
+ UINT8 *OptionalData, OPTIONAL
+ UINT32 OptionalDataSize
+ )
+{
+ EFI_STATUS Status;
+ UINTN OptionIndex;
+ EFI_BOOT_MANAGER_LOAD_OPTION NewOption;
+ EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;
+ UINTN BootOptionCount;
+
+ NewOption.OptionNumber = LoadOptionNumberUnassigned;
+ Status = CreateFvBootOption (FileGuid, Description, &NewOption, Attributes, OptionalData, OptionalDataSize);
+ if (!EFI_ERROR (Status)) {
+ BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOptionTypeBoot);
+
+ OptionIndex = PlatformFindLoadOption (&NewOption, BootOptions, BootOptionCount);
+
+ if (OptionIndex == -1) {
+ Status = EfiBootManagerAddLoadOptionVariable (&NewOption, Position);
+ ASSERT_EFI_ERROR (Status);
+ } else {
+ NewOption.OptionNumber = BootOptions[OptionIndex].OptionNumber;
+ }
+ EfiBootManagerFreeLoadOption (&NewOption);
+ EfiBootManagerFreeLoadOptions (BootOptions, BootOptionCount);
+ }
+
+ return NewOption.OptionNumber;
+}
+
+
+/**
+ Boot manager wait callback
+
+ @param TimeoutRemain The remaingin timeout period
+**/
+VOID
+EFIAPI
+PlatformBootManagerWaitCallback (
+ UINT16 TimeoutRemain
+ )
+{
+ EFI_STATUS Status;
+ EFI_SIMPLE_TEXT_INPUT_EX_PROTOCOL *TxtInEx;
+ EFI_KEY_DATA KeyData;
+ BOOLEAN PausePressed;
+
+ //
+ // Pause on PAUSE key
+ //
+ Status = gBS->HandleProtocol (gST->ConsoleInHandle, &gEfiSimpleTextInputExProtocolGuid, (VOID **) &TxtInEx);
+ ASSERT_EFI_ERROR (Status);
+
+ PausePressed = FALSE;
+
+ while (TRUE) {
+ Status = TxtInEx->ReadKeyStrokeEx (TxtInEx, &KeyData);
+ if (EFI_ERROR (Status)) {
+ break;
+ }
+
+ if (KeyData.Key.ScanCode == SCAN_PAUSE) {
+ PausePressed = TRUE;
+ break;
+ }
+ }
+
+ //
+ // Loop until non-PAUSE key pressed
+ //
+ while (PausePressed) {
+ Status = TxtInEx->ReadKeyStrokeEx (TxtInEx, &KeyData);
+ if (!EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_INFO, "[PauseCallback] %x/%x %x/%x\n",
+ KeyData.Key.ScanCode, KeyData.Key.UnicodeChar,
+ KeyData.KeyState.KeyShiftState, KeyData.KeyState.KeyToggleState
+ ));
+ PausePressed = (BOOLEAN) (KeyData.Key.ScanCode == SCAN_PAUSE);
+ }
+ }
+}
+
+
+EFI_GUID gUefiShellFileGuid = { 0x7C04A583, 0x9E3E, 0x4f1c, { 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 } };
+
+#define INTERNAL_UEFI_SHELL_NAME L"Internal UEFI Shell 2.0"
+#define UEFI_HARD_DRIVE_NAME L"UEFI Hard Drive"
+
+/**
+ Registers default boot option
+**/
+
+VOID
+RegisterDefaultBootOption (
+ VOID
+ )
+{
+ UINT16 *ShellData;
+ UINT32 ShellDataSize;
+
+ ShellData = NULL;
+ ShellDataSize = 0;
+ RegisterFvBootOption (&gUefiShellFileGuid, INTERNAL_UEFI_SHELL_NAME, (UINTN) -1, LOAD_OPTION_ACTIVE, (UINT8 *)ShellData, ShellDataSize);
+
+ //
+ // Boot Menu
+ //
+ mBootMenuOptionNumber = RegisterFvBootOption (&mBootMenuFile, L"Boot Device List", (UINTN) -1, LOAD_OPTION_CATEGORY_APP | LOAD_OPTION_ACTIVE | LOAD_OPTION_HIDDEN, NULL, 0);
+
+ if (mBootMenuOptionNumber == LoadOptionNumberUnassigned) {
+ DEBUG ((DEBUG_INFO, "BootMenuOptionNumber (%d) should not be same to LoadOptionNumberUnassigned(%d).\n", mBootMenuOptionNumber, LoadOptionNumberUnassigned));
+ }
+
+ //
+ // Boot Manager Menu
+ //
+ mSetupOptionNumber = RegisterFvBootOption (&mUiFile, L"Enter Setup", (UINTN) -1, LOAD_OPTION_CATEGORY_APP | LOAD_OPTION_ACTIVE | LOAD_OPTION_HIDDEN, NULL, 0);
+}
+
+/**
+ Registers/Unregisters boot option hotkey
+
+ @param OptionNumber The boot option number for the key option.
+ @param Key The the key input
+ @param Add Flag to indicate to add or remove a key
+**/
+VOID
+RegisterBootOptionHotkey (
+ UINT16 OptionNumber,
+ EFI_INPUT_KEY *Key,
+ BOOLEAN Add
+ )
+{
+ EFI_STATUS Status;
+
+ if (!Add) {
+ //
+ // No enter hotkey when force to setup or there is no boot option
+ //
+ Status = EfiBootManagerDeleteKeyOptionVariable (NULL, 0, Key, NULL);
+ ASSERT (Status == EFI_SUCCESS || Status == EFI_NOT_FOUND);
+ } else {
+ //
+ // Register enter hotkey for the first boot option
+ //
+ Status = EfiBootManagerAddKeyOptionVariable (NULL, OptionNumber, 0, Key,NULL);
+ ASSERT (Status == EFI_SUCCESS || Status == EFI_ALREADY_STARTED);
+ }
+}
+
+
+/**
+ Detect key press callback
+
+ @param The key data
+
+ @retval EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+DetectKeypressCallback (
+ IN EFI_KEY_DATA *KeyData
+)
+{
+ mHotKeypressed = TRUE;
+
+ if (HotKeyEvent != NULL) {
+ gBS->SignalEvent(HotKeyEvent);
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ This function is called after all the boot options are enumerated and ordered properly.
+**/
+VOID
+RegisterStaticHotkey (
+ VOID
+ )
+{
+
+ EFI_INPUT_KEY Enter;
+ EFI_KEY_DATA F2;
+ EFI_KEY_DATA F7;
+ BOOLEAN EnterSetup;
+
+ EnterSetup = FALSE;
+
+ //
+ // [Enter]
+ //
+ mContinueBoot = !EnterSetup;
+ if (mContinueBoot) {
+ Enter.ScanCode = SCAN_NULL;
+ Enter.UnicodeChar = CHAR_CARRIAGE_RETURN;
+ EfiBootManagerRegisterContinueKeyOption (0, &Enter, NULL);
+ }
+
+
+ //
+ // [F2]/[F7]
+ //
+ if (mSetupOptionNumber != LoadOptionNumberUnassigned) {
+ F2.Key.ScanCode = SCAN_F2;
+ F2.Key.UnicodeChar = CHAR_NULL;
+ F2.KeyState.KeyShiftState = EFI_SHIFT_STATE_VALID;
+ F2.KeyState.KeyToggleState = 0;
+ RegisterBootOptionHotkey ((UINT16) mSetupOptionNumber, &F2.Key, TRUE);
+ }
+
+ F7.Key.ScanCode = SCAN_F7;
+ F7.Key.UnicodeChar = CHAR_NULL;
+ F7.KeyState.KeyShiftState = EFI_SHIFT_STATE_VALID;
+ F7.KeyState.KeyToggleState = 0;
+ mBootMenuBoot = !EnterSetup;
+ RegisterBootOptionHotkey ((UINT16) mBootMenuOptionNumber, &F7.Key, mBootMenuBoot);
+
+}
+
+
+
+/**
+ Returns the boot option type of a device
+
+ @param DevicePath The path of device whose boot option type
+ to be returned
+ @retval -1 Device type not found
+ @retval > -1 Device type found
+**/
+UINT8
+BootOptionType (
+ IN EFI_DEVICE_PATH_PROTOCOL *DevicePath
+ )
+{
+ EFI_DEVICE_PATH_PROTOCOL *Node;
+ EFI_DEVICE_PATH_PROTOCOL *NextNode;
+
+ for (Node = DevicePath; !IsDevicePathEndType (Node); Node = NextDevicePathNode (Node)) {
+ if (DevicePathType (Node) == MESSAGING_DEVICE_PATH) {
+ //
+ // Make sure the device path points to the driver device.
+ //
+ NextNode = NextDevicePathNode (Node);
+ if (DevicePathSubType(NextNode) == MSG_DEVICE_LOGICAL_UNIT_DP) {
+ //
+ // if the next node type is Device Logical Unit, which specify the Logical Unit Number (LUN),
+ // skip it
+ //
+ NextNode = NextDevicePathNode (NextNode);
+ }
+ if (IsDevicePathEndType (NextNode)) {
+ if ((DevicePathType (Node) == MESSAGING_DEVICE_PATH)) {
+ return DevicePathSubType (Node);
+ } else {
+ return MSG_SATA_DP;
+ }
+ }
+ }
+ }
+
+ return (UINT8) -1;
+}
+
+/**
+ Returns the priority number.
+ OptionType EFI
+ ------------------------------------
+ PXE 2
+ DVD 4
+ USB 6
+ NVME 7
+ HDD 8
+ EFI Shell 9
+ Others 100
+
+ @param BootOption
+**/
+UINTN
+BootOptionPriority (
+ CONST EFI_BOOT_MANAGER_LOAD_OPTION *BootOption
+ )
+{
+ //
+ // EFI boot options
+ //
+ switch (BootOptionType (BootOption->FilePath)) {
+ case MSG_MAC_ADDR_DP:
+ case MSG_VLAN_DP:
+ case MSG_IPv4_DP:
+ case MSG_IPv6_DP:
+ return 2;
+
+ case MSG_SATA_DP:
+ case MSG_ATAPI_DP:
+ case MSG_UFS_DP:
+ case MSG_NVME_NAMESPACE_DP:
+ return 4;
+
+ case MSG_USB_DP:
+ return 6;
+
+ }
+ if (StrCmp (BootOption->Description, INTERNAL_UEFI_SHELL_NAME) == 0) {
+ if (PcdGetBool (PcdBootToShellOnly)) {
+ return 0;
+ }
+ return 9;
+ }
+ if (StrCmp (BootOption->Description, UEFI_HARD_DRIVE_NAME) == 0) {
+ return 8;
+ }
+ return 100;
+}
+
+/**
+ Compares boot priorities of two boot options
+
+ @param Left The left boot option
+ @param Right The right boot option
+
+ @return The difference between the Left and Right
+ boot options
+ **/
+INTN
+EFIAPI
+CompareBootOption (
+ CONST VOID *Left,
+ CONST VOID *Right
+ )
+{
+ return BootOptionPriority ((EFI_BOOT_MANAGER_LOAD_OPTION *) Left) -
+ BootOptionPriority ((EFI_BOOT_MANAGER_LOAD_OPTION *) Right);
+}
+
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/MemoryTest.c b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardMemoryTest.c
similarity index 93%
rename from Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/MemoryTest.c
rename to Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardMemoryTest.c
index e6445fecf8..4f93e9e142 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/MemoryTest.c
+++ b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/BoardModulePkg/Library/BoardBdsHookLib/BoardMemoryTest.c
@@ -1,85 +1,86 @@
-/** @file

- Perform the platform memory test

-

-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>

-SPDX-License-Identifier: BSD-2-Clause-Patent

-

-**/

-

-#include "BdsPlatform.h"

-#include <Protocol/GenericMemoryTest.h>

-

-/**

- Perform the memory test base on the memory test intensive level,

- and update the memory resource.

-

- @param Level The memory test intensive level.

-

- @retval EFI_STATUS Success test all the system memory and update

- the memory resource

-

-**/

-EFI_STATUS

-MemoryTest (

- IN EXTENDMEM_COVERAGE_LEVEL Level

- )

-{

- EFI_STATUS Status;

- BOOLEAN RequireSoftECCInit;

- EFI_GENERIC_MEMORY_TEST_PROTOCOL *GenMemoryTest;

- UINT64 TestedMemorySize;

- UINT64 TotalMemorySize;

- BOOLEAN ErrorOut;

- BOOLEAN TestAbort;

-

- TestedMemorySize = 0;

- TotalMemorySize = 0;

- ErrorOut = FALSE;

- TestAbort = FALSE;

-

- RequireSoftECCInit = FALSE;

-

- Status = gBS->LocateProtocol (

- &gEfiGenericMemTestProtocolGuid,

- NULL,

- (VOID **) &GenMemoryTest

- );

- if (EFI_ERROR (Status)) {

- return EFI_SUCCESS;

- }

-

- Status = GenMemoryTest->MemoryTestInit (

- GenMemoryTest,

- Level,

- &RequireSoftECCInit

- );

- if (Status == EFI_NO_MEDIA) {

- //

- // The PEI codes also have the relevant memory test code to check the memory,

- // it can select to test some range of the memory or all of them. If PEI code

- // checks all the memory, this BDS memory test will has no not-test memory to

- // do the test, and then the status of EFI_NO_MEDIA will be returned by

- // "MemoryTestInit". So it does not need to test memory again, just return.

- //

- return EFI_SUCCESS;

- }

-

- if (PcdGetBool (PcdFastBoot) == FALSE) {

- do {

- Status = GenMemoryTest->PerformMemoryTest (

- GenMemoryTest,

- &TestedMemorySize,

- &TotalMemorySize,

- &ErrorOut,

- TestAbort

- );

- if (ErrorOut && (Status == EFI_DEVICE_ERROR)) {

- ASSERT (0);

- }

- } while (Status != EFI_NOT_FOUND);

- }

-

- Status = GenMemoryTest->Finished (GenMemoryTest);

-

- return EFI_SUCCESS;

-}

+/** @file
+ Perform the platform memory test
+
+Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2021, American Megatrends International LLC.<BR>
+SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "BoardBdsHook.h"
+#include <Protocol/GenericMemoryTest.h>
+
+/**
+ Perform the memory test base on the memory test intensive level,
+ and update the memory resource.
+
+ @param Level The memory test intensive level.
+
+ @retval EFI_STATUS Success test all the system memory and update
+ the memory resource
+
+**/
+EFI_STATUS
+MemoryTest (
+ IN EXTENDMEM_COVERAGE_LEVEL Level
+ )
+{
+ EFI_STATUS Status;
+ BOOLEAN RequireSoftECCInit;
+ EFI_GENERIC_MEMORY_TEST_PROTOCOL *GenMemoryTest;
+ UINT64 TestedMemorySize;
+ UINT64 TotalMemorySize;
+ BOOLEAN ErrorOut;
+ BOOLEAN TestAbort;
+
+ TestedMemorySize = 0;
+ TotalMemorySize = 0;
+ ErrorOut = FALSE;
+ TestAbort = FALSE;
+
+ RequireSoftECCInit = FALSE;
+
+ Status = gBS->LocateProtocol (
+ &gEfiGenericMemTestProtocolGuid,
+ NULL,
+ (VOID **) &GenMemoryTest
+ );
+ if (EFI_ERROR (Status)) {
+ return EFI_SUCCESS;
+ }
+
+ Status = GenMemoryTest->MemoryTestInit (
+ GenMemoryTest,
+ Level,
+ &RequireSoftECCInit
+ );
+ if (Status == EFI_NO_MEDIA) {
+ //
+ // The PEI codes also have the relevant memory test code to check the memory,
+ // it can select to test some range of the memory or all of them. If PEI code
+ // checks all the memory, this BDS memory test will has no not-test memory to
+ // do the test, and then the status of EFI_NO_MEDIA will be returned by
+ // "MemoryTestInit". So it does not need to test memory again, just return.
+ //
+ return EFI_SUCCESS;
+ }
+
+ if (PcdGetBool (PcdFastBoot) == FALSE) {
+ do {
+ Status = GenMemoryTest->PerformMemoryTest (
+ GenMemoryTest,
+ &TestedMemorySize,
+ &TotalMemorySize,
+ &ErrorOut,
+ TestAbort
+ );
+ if (ErrorOut && (Status == EFI_DEVICE_ERROR)) {
+ ASSERT (0);
+ }
+ } while (Status != EFI_NOT_FOUND);
+ }
+
+ Status = GenMemoryTest->Finished (GenMemoryTest);
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.c b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.c
index bd0509ab10..a7e5c78469 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.c
+++ b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.c
@@ -1,138 +1,21 @@
/** @file

This file include all platform action which can be customized by IBV/OEM.



-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>

+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>

Copyright (c) 2021, American Megatrends International LLC.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent



**/



#include "BdsPlatform.h"

-#include <Guid/EventGroup.h>

-#include <Protocol/DxeSmmReadyToLock.h>

-#include <Protocol/FirmwareVolume2.h>

-#include <Protocol/PciRootBridgeIo.h>



-#include <Protocol/BlockIo.h>

-#include <Protocol/PciIo.h>

-#include <Library/IoLib.h>

-#include <Library/PciLib.h>

-#include <Guid/EventGroup.h>

-

-#include <Library/Tcg2PhysicalPresenceLib.h>

-

-#include <Library/HobLib.h>

-#include <Protocol/UsbIo.h>

-

-#include <Library/UefiBootManagerLib.h>

-

-GLOBAL_REMOVE_IF_UNREFERENCED EFI_BOOT_MODE gBootMode;

-

-BOOLEAN gPPRequireUIConfirm;

-

-extern UINTN mBootMenuOptionNumber;

+extern UINTN mBootMenuOptionNumber;



EFI_STATUS

LinuxBootStart (

VOID

);



-

-GLOBAL_REMOVE_IF_UNREFERENCED USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = {

- {

- {

- MESSAGING_DEVICE_PATH,

- MSG_USB_CLASS_DP,

- {

- (UINT8) (sizeof (USB_CLASS_DEVICE_PATH)),

- (UINT8) ((sizeof (USB_CLASS_DEVICE_PATH)) >> 8)

- }

- },

- 0xffff, // VendorId

- 0xffff, // ProductId

- CLASS_HID, // DeviceClass

- SUBCLASS_BOOT, // DeviceSubClass

- PROTOCOL_KEYBOARD // DeviceProtocol

- },

- gEndEntire

-};

-

-//

-// Internal shell mode

-//

-GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mShellModeColumn;

-GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mShellModeRow;

-GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mShellHorizontalResolution;

-GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mShellVerticalResolution;

-//

-// BDS Platform Functions

-//

-

-BOOLEAN

-IsMorBitSet (

- VOID

- )

-{

- UINTN MorControl;

- EFI_STATUS Status;

- UINTN DataSize;

-

- //

- // Check if the MOR bit is set.

- //

- DataSize = sizeof (MorControl);

- Status = gRT->GetVariable (

- MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME,

- &gEfiMemoryOverwriteControlDataGuid,

- NULL,

- &DataSize,

- &MorControl

- );

- if (EFI_ERROR (Status)) {

- DEBUG ((DEBUG_INFO, " PlatformBootMangerLib: gEfiMemoryOverwriteControlDataGuid doesn't exist!!***\n"));

- MorControl = 0;

- } else {

- DEBUG ((DEBUG_INFO, " PlatformBootMangerLib: Get the gEfiMemoryOverwriteControlDataGuid = %x!!***\n", MorControl));

- }

-

- return (BOOLEAN) (MorControl & 0x01);

-}

-

-VOID

-DumpDevicePath (

- IN CHAR16 *Name,

- IN EFI_DEVICE_PATH *DevicePath

- )

-{

- CHAR16 *Str;

-

- Str = ConvertDevicePathToText(DevicePath, TRUE, TRUE);

- DEBUG ((DEBUG_INFO, "%s: %s\n", Name, Str));

- if (Str != NULL) {

- FreePool (Str);

- }

-}

-

-/**

- An empty function to pass error checking of CreateEventEx ().

-

- This empty function ensures that EVT_NOTIFY_SIGNAL_ALL is error

- checked correctly since it is now mapped into CreateEventEx() in UEFI 2.0.

-

- @param Event Event whose notification function is being invoked.

- @param Context The pointer to the notification function's context,

- which is implementation-dependent.

-**/

-VOID

-EFIAPI

-InternalBdsEmptyCallbackFuntion (

- IN EFI_EVENT Event,

- IN VOID *Context

- )

-{

- return;

-}

-

VOID

ExitPmAuth (

VOID

@@ -152,7 +35,7 @@ ExitPmAuth (
Status = gBS->CreateEventEx (

EVT_NOTIFY_SIGNAL,

TPL_CALLBACK,

- InternalBdsEmptyCallbackFuntion,

+ EfiEventEmptyFunction,

NULL,

&gEfiEndOfDxeEventGroupGuid,

&EndOfDxeEvent

@@ -179,918 +62,134 @@ ExitPmAuth (
DEBUG((DEBUG_INFO,"ExitPmAuth ()- End\n"));

}



-VOID

-ConnectRootBridge (

- BOOLEAN Recursive

- )

-{

- UINTN RootBridgeHandleCount;

- EFI_HANDLE *RootBridgeHandleBuffer;

- UINTN RootBridgeIndex;

-

- RootBridgeHandleCount = 0;

- gBS->LocateHandleBuffer (

- ByProtocol,

- &gEfiPciRootBridgeIoProtocolGuid,

- NULL,

- &RootBridgeHandleCount,

- &RootBridgeHandleBuffer

- );

- for (RootBridgeIndex = 0; RootBridgeIndex < RootBridgeHandleCount; RootBridgeIndex++) {

- gBS->ConnectController (RootBridgeHandleBuffer[RootBridgeIndex], NULL, NULL, Recursive);

- }

-}

-



/**

- Return whether the device is trusted console.

-

- @param Device The device to be tested.

-

- @retval TRUE The device can be trusted.

- @retval FALSE The device cannot be trusted.

-**/

-BOOLEAN

-IsTrustedConsole (

- IN CONSOLE_TYPE ConsoleType,

- IN EFI_DEVICE_PATH_PROTOCOL *Device

- )

-{

- VOID *TrustedConsoleDevicepath;

- EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;

- EFI_DEVICE_PATH_PROTOCOL *Instance;

- UINTN Size;

- EFI_DEVICE_PATH_PROTOCOL *ConsoleDevice;

+ Creates an EFI event in the BDS Event Group.



- if (Device == NULL) {

- return FALSE;

- }

-

- ConsoleDevice = DuplicateDevicePath(Device);

-

- TrustedConsoleDevicepath = NULL;

-

- switch (ConsoleType) {

- case ConIn:

- TrustedConsoleDevicepath = PcdGetPtr (PcdTrustedConsoleInputDevicePath);

- break;

- case ConOut:

- //

- // Check GOP and remove last node

- //

- TempDevicePath = ConsoleDevice;

- while (!IsDevicePathEndType (TempDevicePath)) {

- if (DevicePathType (TempDevicePath) == ACPI_DEVICE_PATH &&

- DevicePathSubType (TempDevicePath) == ACPI_ADR_DP) {

- SetDevicePathEndNode (TempDevicePath);

- break;

- }

- TempDevicePath = NextDevicePathNode (TempDevicePath);

- }

-

- TrustedConsoleDevicepath = PcdGetPtr (PcdTrustedConsoleOutputDevicePath);

- break;

- default:

- ASSERT(FALSE);

- break;

- }

-

- TempDevicePath = TrustedConsoleDevicepath;

- do {

- Instance = GetNextDevicePathInstance (&TempDevicePath, &Size);

- if (Instance == NULL) {

- break;

- }

-

- if (CompareMem (ConsoleDevice, Instance, Size - END_DEVICE_PATH_LENGTH) == 0) {

- FreePool (Instance);

- FreePool (ConsoleDevice);

- return TRUE;

- }

+ @param NotifyTpl The task priority level of the event.

+ @param gEfiEventGuid The GUID of the event group to signal.

+ @param BdsConsoleEvent Returns the EFI event returned from gBS->CreateEvent(Ex).



- FreePool (Instance);

- } while (TempDevicePath != NULL);

+ @retval EFI_SUCCESS Event was created.

+ @retval Other Event was not created.



- FreePool (ConsoleDevice);

-

- return FALSE;

-}

-

-BOOLEAN

-IsUsbShortForm (

- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath

- )

-{

- if ((DevicePathType (DevicePath) == MESSAGING_DEVICE_PATH) &&

- ((DevicePathSubType (DevicePath) == MSG_USB_CLASS_DP) || (DevicePathSubType (DevicePath) == MSG_USB_WWID_DP)) ) {

- return TRUE;

- }

-

- return FALSE;

-}

-

-/**

- Connect the USB short form device path.

-

- @param DevicePath USB short form device path

-

- @retval EFI_SUCCESS Successfully connected the USB device

- @retval EFI_NOT_FOUND Cannot connect the USB device

- @retval EFI_INVALID_PARAMETER The device path is invalid.

**/

EFI_STATUS

-ConnectUsbShortFormDevicePath (

- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath

+EFIAPI

+CreateBdsEvent (

+ IN EFI_TPL NotifyTpl,

+ IN EFI_GUID *gEfiEventGuid,

+ OUT EFI_EVENT *BdsConsoleEvent

)

{

- EFI_STATUS Status;

- EFI_HANDLE *Handles;

- UINTN HandleCount;

- UINTN Index;

- EFI_PCI_IO_PROTOCOL *PciIo;

- UINT8 Class[3];

- BOOLEAN AtLeastOneConnected;

+ EFI_STATUS Status;



- //

- // Check the passed in parameters

- //

- if (DevicePath == NULL) {

- return EFI_INVALID_PARAMETER;

- }

+ ASSERT (BdsConsoleEvent != NULL);



- if (!IsUsbShortForm (DevicePath)) {

- return EFI_INVALID_PARAMETER;

- }

-

- //

- // Find the usb host controller firstly, then connect with the remaining device path

- //

- AtLeastOneConnected = FALSE;

- Status = gBS->LocateHandleBuffer (

- ByProtocol,

- &gEfiPciIoProtocolGuid,

+ Status = gBS->CreateEventEx (

+ EVT_NOTIFY_SIGNAL,

+ NotifyTpl,

+ EfiEventEmptyFunction,

NULL,

- &HandleCount,

- &Handles

- );

- for (Index = 0; Index < HandleCount; Index++) {

- Status = gBS->HandleProtocol (

- Handles[Index],

- &gEfiPciIoProtocolGuid,

- (VOID **) &PciIo

- );

- if (!EFI_ERROR (Status)) {

- //

- // Check whether the Pci device is the wanted usb host controller

- //

- Status = PciIo->Pci.Read (PciIo, EfiPciIoWidthUint8, 0x09, 3, &Class);

- if (!EFI_ERROR (Status) &&

- ((PCI_CLASS_SERIAL == Class[2]) && (PCI_CLASS_SERIAL_USB == Class[1]))

- ) {

- Status = gBS->ConnectController (

- Handles[Index],

- NULL,

- DevicePath,

- FALSE

- );

- if (!EFI_ERROR(Status)) {

- AtLeastOneConnected = TRUE;

- }

- }

- }

- }

-

- return AtLeastOneConnected ? EFI_SUCCESS : EFI_NOT_FOUND;

-}

-

-/**

- Update the ConIn variable with USB Keyboard device path,if its not already exists in ConIn

-**/

-VOID

-EnumUsbKeyboard (

- VOID

- )

-{

- DEBUG ((DEBUG_INFO, "[EnumUsbKeyboard]\n"));

- EfiBootManagerUpdateConsoleVariable (ConIn, (EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath, NULL);

-

- //

- // Append Usb Keyboard short form DevicePath into "ConInDev"

- //

- EfiBootManagerUpdateConsoleVariable (ConInDev, (EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath, NULL);

-}

-

-BOOLEAN

-IsVgaHandle (

- IN EFI_HANDLE Handle

- )

-{

- EFI_PCI_IO_PROTOCOL *PciIo;

- PCI_TYPE00 Pci;

- EFI_STATUS Status;

-

- Status = gBS->HandleProtocol (

- Handle,

- &gEfiPciIoProtocolGuid,

- (VOID **)&PciIo

+ gEfiEventGuid,

+ BdsConsoleEvent

);

- if (!EFI_ERROR (Status)) {

- Status = PciIo->Pci.Read (

- PciIo,

- EfiPciIoWidthUint32,

- 0,

- sizeof (Pci) / sizeof (UINT32),

- &Pci

- );

- if (!EFI_ERROR (Status)) {

- if (IS_PCI_VGA (&Pci) || IS_PCI_OLD_VGA (&Pci)) {

- return TRUE;

- }

- }

- }

- return FALSE;

-}

-

-EFI_HANDLE

-IsVideoController (

- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath

- )

-{

- EFI_DEVICE_PATH_PROTOCOL *DupDevicePath;

- EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;

- EFI_STATUS Status;

- EFI_HANDLE DeviceHandle;

-

- DupDevicePath = DuplicateDevicePath (DevicePath);

- ASSERT (DupDevicePath != NULL);

- if (DupDevicePath == NULL) {

- return NULL;

- }

-

- TempDevicePath = DupDevicePath;

- Status = gBS->LocateDevicePath (

- &gEfiDevicePathProtocolGuid,

- &TempDevicePath,

- &DeviceHandle

- );

- FreePool (DupDevicePath);

- if (EFI_ERROR (Status)) {

- return NULL;

- }

-

- if (IsVgaHandle (DeviceHandle)) {

- return DeviceHandle;

- } else {

- return NULL;

- }

-}

-

-BOOLEAN

-IsGopDevicePath (

- IN EFI_DEVICE_PATH_PROTOCOL *DevicePath

- )

-{

- while (!IsDevicePathEndType (DevicePath)) {

- if (DevicePathType (DevicePath) == ACPI_DEVICE_PATH &&

- DevicePathSubType (DevicePath) == ACPI_ADR_DP) {

- return TRUE;

- }

- DevicePath = NextDevicePathNode (DevicePath);

- }

- return FALSE;

-}



-/**

- Remove all GOP device path instance from DevicePath and add the Gop to the DevicePath.

-**/

-EFI_DEVICE_PATH_PROTOCOL *

-UpdateGopDevicePath (

- EFI_DEVICE_PATH_PROTOCOL *DevicePath,

- EFI_DEVICE_PATH_PROTOCOL *Gop

- )

-{

- UINTN Size;

- UINTN GopSize;

- EFI_DEVICE_PATH_PROTOCOL *Temp;

- EFI_DEVICE_PATH_PROTOCOL *Return;

- EFI_DEVICE_PATH_PROTOCOL *Instance;

- BOOLEAN Exist;

-

- Exist = FALSE;

- Return = NULL;

- GopSize = GetDevicePathSize (Gop);

- do {

- Instance = GetNextDevicePathInstance (&DevicePath, &Size);

- if (Instance == NULL) {

- break;

- }

- if (!IsGopDevicePath (Instance) ||

- (Size == GopSize && CompareMem (Instance, Gop, GopSize) == 0)

- ) {

- if (Size == GopSize && CompareMem (Instance, Gop, GopSize) == 0) {

- Exist = TRUE;

- }

- Temp = Return;

- Return = AppendDevicePathInstance (Return, Instance);

- if (Temp != NULL) {

- FreePool (Temp);

- }

- }

- FreePool (Instance);

- } while (DevicePath != NULL);

-

- if (!Exist) {

- Temp = Return;

- Return = AppendDevicePathInstance (Return, Gop);

- if (Temp != NULL) {

- FreePool (Temp);

- }

- }

- return Return;

+ return Status;

}



/**

- Get Graphics Controller Handle.

+ Create, Signal, and Close the Bds Event Before Console After

+ Trusted Console event using CreateBdsEvent().



- @retval GraphicsController Successfully located

- @retval NULL Failed to locate

**/

-EFI_HANDLE

-EFIAPI

-GetGraphicsController (

- IN BOOLEAN NeedTrustedConsole

- )

-{

- EFI_STATUS Status;

- UINTN Index;

- EFI_HANDLE *PciHandles;

- UINTN PciHandlesSize;

- EFI_DEVICE_PATH_PROTOCOL *DevicePath;

-

- Status = gBS->LocateHandleBuffer (

- ByProtocol,

- &gEfiPciIoProtocolGuid,

- NULL,

- &PciHandlesSize,

- &PciHandles

- );

- if (EFI_ERROR (Status)) {

- return NULL;

- }

-

- for (Index = 0; Index < PciHandlesSize; Index++) {

- Status = gBS->HandleProtocol (

- PciHandles[Index],

- &gEfiDevicePathProtocolGuid,

- (VOID **) &DevicePath

- );

- if (EFI_ERROR(Status)) {

- continue;

- }

- if (!IsVgaHandle (PciHandles[Index])) {

- continue;

- }

- if ((NeedTrustedConsole && IsTrustedConsole (ConOut, DevicePath)) ||

- ((!NeedTrustedConsole) && (!IsTrustedConsole (ConOut, DevicePath)))) {

- return PciHandles[Index];

- }

- }

-

- return NULL;

-}

-

VOID

-UpdateGraphicConOut (

- IN BOOLEAN NeedTrustedConsole

- )

-{

- EFI_HANDLE GraphicsControllerHandle;

- EFI_DEVICE_PATH_PROTOCOL *GopDevicePath;

- EFI_DEVICE_PATH_PROTOCOL *ConOutDevicePath;

- EFI_DEVICE_PATH_PROTOCOL *UpdatedConOutDevicePath;

-

- //

- // Update ConOut variable

- //

- GraphicsControllerHandle = GetGraphicsController (NeedTrustedConsole);

- if (GraphicsControllerHandle != NULL) {

- //

- // Connect the GOP driver

- //

- gBS->ConnectController (GraphicsControllerHandle, NULL, NULL, TRUE);

-

- //

- // Get the GOP device path

- // NOTE: We may get a device path that contains Controller node in it.

- //

- GopDevicePath = EfiBootManagerGetGopDevicePath (GraphicsControllerHandle);

- if (GopDevicePath != NULL) {

- GetEfiGlobalVariable2 (L"ConOut", (VOID **)&ConOutDevicePath, NULL);

- UpdatedConOutDevicePath = UpdateGopDevicePath (ConOutDevicePath, GopDevicePath);

- if (ConOutDevicePath != NULL) {

- FreePool (ConOutDevicePath);

- }

- FreePool (GopDevicePath);

- gRT->SetVariable (

- L"ConOut",

- &gEfiGlobalVariableGuid,

- EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_BOOTSERVICE_ACCESS,

- GetDevicePathSize (UpdatedConOutDevicePath),

- UpdatedConOutDevicePath

- );

- }

- }

-}

-

-VOID

-AddConsoleVariable (

- IN CONSOLE_TYPE ConsoleType,

- IN EFI_DEVICE_PATH *ConsoleDevicePath

- )

-{

- EFI_DEVICE_PATH *TempDevicePath;

- EFI_DEVICE_PATH *Instance;

- UINTN Size;

- EFI_HANDLE GraphicsControllerHandle;

- EFI_DEVICE_PATH *GopDevicePath;

-

- TempDevicePath = ConsoleDevicePath;

- do {

- Instance = GetNextDevicePathInstance (&TempDevicePath, &Size);

- if (Instance == NULL) {

- break;

- }

-

- switch (ConsoleType) {

- case ConIn:

- if (IsUsbShortForm (Instance)) {

- //

- // Append Usb Keyboard short form DevicePath into "ConInDev"

- //

- EfiBootManagerUpdateConsoleVariable (ConInDev, Instance, NULL);

- }

- EfiBootManagerUpdateConsoleVariable (ConsoleType, Instance, NULL);

- break;

- case ConOut:

- GraphicsControllerHandle = IsVideoController (Instance);

- if (GraphicsControllerHandle == NULL) {

- EfiBootManagerUpdateConsoleVariable (ConsoleType, Instance, NULL);

- } else {

- //

- // Connect the GOP driver

- //

- gBS->ConnectController (GraphicsControllerHandle, NULL, NULL, TRUE);

- //

- // Get the GOP device path

- // NOTE: We may get a device path that contains Controller node in it.

- //

- GopDevicePath = EfiBootManagerGetGopDevicePath (GraphicsControllerHandle);

- if (GopDevicePath != NULL) {

- EfiBootManagerUpdateConsoleVariable (ConsoleType, GopDevicePath, NULL);

- }

- }

- break;

- default:

- ASSERT(FALSE);

- break;

- }

-

- FreePool (Instance);

- } while (TempDevicePath != NULL);

-}

-

-/**

- The function connects the trusted consoles.

-**/

-VOID

-ConnectTrustedConsole (

+EFIAPI

+BdsSignalEventBeforeConsoleAfterTrustedConsole (

VOID

)

{

- EFI_DEVICE_PATH_PROTOCOL *Consoles;

- EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;

- EFI_DEVICE_PATH_PROTOCOL *Instance;

- EFI_DEVICE_PATH_PROTOCOL *Next;

- UINTN Size;

- UINTN Index;

- EFI_HANDLE Handle;

- EFI_STATUS Status;

- CHAR16 *ConsoleVar[] = {L"ConIn", L"ConOut"};

- VOID *TrustedConsoleDevicepath;

+ EFI_STATUS Status;

+ EFI_EVENT BdsConsoleEvent;



- TrustedConsoleDevicepath = PcdGetPtr (PcdTrustedConsoleInputDevicePath);

- DumpDevicePath (L"TrustedConsoleIn", TrustedConsoleDevicepath);

- TrustedConsoleDevicepath = PcdGetPtr (PcdTrustedConsoleOutputDevicePath);

- DumpDevicePath (L"TrustedConsoleOut", TrustedConsoleDevicepath);

+ DEBUG ((DEBUG_INFO, "%a \n", __FUNCTION__));



- for (Index = 0; Index < sizeof (ConsoleVar) / sizeof (ConsoleVar[0]); Index++) {

+ Status = CreateBdsEvent (

+ TPL_CALLBACK,

+ &gBdsEventBeforeConsoleAfterTrustedConsoleGuid,

+ &BdsConsoleEvent

+ );



- GetEfiGlobalVariable2 (ConsoleVar[Index], (VOID **)&Consoles, NULL);

-

- TempDevicePath = Consoles;

- do {

- Instance = GetNextDevicePathInstance (&TempDevicePath, &Size);

- if (Instance == NULL) {

- break;

- }

- if (IsTrustedConsole (Index, Instance)) {

- if (IsUsbShortForm (Instance)) {

- ConnectUsbShortFormDevicePath (Instance);

- } else {

- for (Next = Instance; !IsDevicePathEnd (Next); Next = NextDevicePathNode (Next)) {

- if (DevicePathType (Next) == ACPI_DEVICE_PATH && DevicePathSubType (Next) == ACPI_ADR_DP) {

- break;

- } else if (DevicePathType (Next) == HARDWARE_DEVICE_PATH &&

- DevicePathSubType (Next) == HW_CONTROLLER_DP &&

- DevicePathType (NextDevicePathNode (Next)) == ACPI_DEVICE_PATH &&

- DevicePathSubType (NextDevicePathNode (Next)) == ACPI_ADR_DP

- ) {

- break;

- }

- }

- if (!IsDevicePathEnd (Next)) {

- SetDevicePathEndNode (Next);

- Status = EfiBootManagerConnectDevicePath (Instance, &Handle);

- if (!EFI_ERROR (Status)) {

- gBS->ConnectController (Handle, NULL, NULL, TRUE);

- }

- } else {

- EfiBootManagerConnectDevicePath (Instance, NULL);

- }

- }

- }

- FreePool (Instance);

- } while (TempDevicePath != NULL);

+ ASSERT_EFI_ERROR (Status);



- if (Consoles != NULL) {

- FreePool (Consoles);

- }

+ if (!EFI_ERROR (Status)) {

+ gBS->SignalEvent (BdsConsoleEvent);

+ gBS->CloseEvent (BdsConsoleEvent);

+ DEBUG ((DEBUG_INFO,"All EventBeforeConsoleAfterTrustedConsole callbacks have returned successfully\n"));

}

}



-/**

- The function connects the trusted Storages.

-**/

-VOID

-ConnectTrustedStorage (

- VOID

- )

-{

- VOID *TrustedStorageDevicepath;

- EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;

- EFI_DEVICE_PATH_PROTOCOL *Instance;

- UINTN Size;

- EFI_DEVICE_PATH_PROTOCOL *TempStorageDevicePath;

- EFI_STATUS Status;

- EFI_HANDLE DeviceHandle;

-

- TrustedStorageDevicepath = PcdGetPtr (PcdTrustedStorageDevicePath);

- DumpDevicePath (L"TrustedStorage", TrustedStorageDevicepath);

-

- TempDevicePath = TrustedStorageDevicepath;

- do {

- Instance = GetNextDevicePathInstance (&TempDevicePath, &Size);

- if (Instance == NULL) {

- break;

- }

-

- EfiBootManagerConnectDevicePath (Instance, NULL);

-

- TempStorageDevicePath = Instance;

-

- Status = gBS->LocateDevicePath (

- &gEfiDevicePathProtocolGuid,

- &TempStorageDevicePath,

- &DeviceHandle

- );

- if (!EFI_ERROR (Status)) {

- gBS->ConnectController (DeviceHandle, NULL, NULL, FALSE);

- }

-

- FreePool (Instance);

- } while (TempDevicePath != NULL);

-}

-

-/**

- The function connects the trusted consoles and then call the PP processing library interface.

-**/

-VOID

-ProcessTcgPp (

- VOID

- )

-{

- gPPRequireUIConfirm |= Tcg2PhysicalPresenceLibNeedUserConfirm();

-

- if (gPPRequireUIConfirm) {

- ConnectTrustedConsole ();

- }

-

- Tcg2PhysicalPresenceLibProcessRequest (NULL);

-}



/**

- The function connects the trusted storage to perform TPerReset.

+ Create, Signal, and Close the Bds Before Console Before End Of Dxe

+ event using CreateBdsEvent().

**/

VOID

-ProcessTcgMor (

+EFIAPI

+BdsSignalEventBeforeConsoleBeforeEndOfDxe (

VOID

)

{

- if (IsMorBitSet ()) {

- ConnectTrustedConsole();

- ConnectTrustedStorage();

- }

-}

+ EFI_STATUS Status;

+ EFI_EVENT BdsConsoleEvent;



-/**

- Check if current BootCurrent variable is internal shell boot option.

+ DEBUG ((DEBUG_INFO, "%a \n", __FUNCTION__));



- @retval TRUE BootCurrent is internal shell.

- @retval FALSE BootCurrent is not internal shell.

-**/

-BOOLEAN

-BootCurrentIsInternalShell (

- VOID

- )

-{

- UINTN VarSize;

- UINT16 BootCurrent;

- CHAR16 BootOptionName[16];

- UINT8 *BootOption;

- UINT8 *Ptr;

- BOOLEAN Result;

- EFI_STATUS Status;

- EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;

- EFI_DEVICE_PATH_PROTOCOL *LastDeviceNode;

- EFI_GUID *GuidPoint;

+ Status = CreateBdsEvent (

+ TPL_CALLBACK,

+ &gBdsEventBeforeConsoleBeforeEndOfDxeGuid,

+ &BdsConsoleEvent

+ );



- BootOption = NULL;

- Result = FALSE;

+ ASSERT_EFI_ERROR (Status);



- //

- // Get BootCurrent variable

- //

- VarSize = sizeof (UINT16);

- Status = gRT->GetVariable (

- L"BootCurrent",

- &gEfiGlobalVariableGuid,

- NULL,

- &VarSize,

- &BootCurrent

- );

- if (EFI_ERROR (Status)) {

- return FALSE;

- }

-

- //

- // Create boot option Bootxxxx from BootCurrent

- //

- UnicodeSPrint (BootOptionName, sizeof(BootOptionName), L"Boot%04X", BootCurrent);

-

- GetEfiGlobalVariable2 (BootOptionName, (VOID **) &BootOption, &VarSize);

- if (BootOption == NULL || VarSize == 0) {

- return FALSE;

- }

-

- Ptr = BootOption;

- Ptr += sizeof (UINT32);

- Ptr += sizeof (UINT16);

- Ptr += StrSize ((CHAR16 *) Ptr);

- TempDevicePath = (EFI_DEVICE_PATH_PROTOCOL *) Ptr;

- LastDeviceNode = TempDevicePath;

- while (!IsDevicePathEnd (TempDevicePath)) {

- LastDeviceNode = TempDevicePath;

- TempDevicePath = NextDevicePathNode (TempDevicePath);

- }

- GuidPoint = EfiGetNameGuidFromFwVolDevicePathNode (

- (MEDIA_FW_VOL_FILEPATH_DEVICE_PATH *) LastDeviceNode

- );

- if ((GuidPoint != NULL) &&

- ((CompareGuid (GuidPoint, &gUefiShellFileGuid)))

- ) {

- //

- // if this option is internal shell, return TRUE

- //

- Result = TRUE;

- }

-

- if (BootOption != NULL) {

- FreePool (BootOption);

- BootOption = NULL;

+ if (!EFI_ERROR (Status)) {

+ gBS->SignalEvent (BdsConsoleEvent);

+ gBS->CloseEvent (BdsConsoleEvent);

+ DEBUG ((DEBUG_INFO,"All BeforeConsoleBeforeEndOfDxe callbacks have returned successfully\n"));

}

-

- return Result;

}



/**

- This function will change video resolution and text mode

- for internl shell when internal shell is launched.

-

- @param None.

-

- @retval EFI_SUCCESS Mode is changed successfully.

- @retval Others Mode failed to changed.

+ Create, Signal, and Close the Bds After Console Ready Before Boot Option

+ using CreateBdsEvent().

**/

-EFI_STATUS

+VOID

EFIAPI

-ChangeModeForInternalShell (

+BdsSignalEventAfterConsoleReadyBeforeBootOption (

VOID

)

{

- EFI_GRAPHICS_OUTPUT_PROTOCOL *GraphicsOutput;

- EFI_SIMPLE_TEXT_OUTPUT_PROTOCOL *SimpleTextOut;

- UINTN SizeOfInfo;

- EFI_GRAPHICS_OUTPUT_MODE_INFORMATION *Info;

- UINT32 MaxGopMode;

- UINT32 MaxTextMode;

- UINT32 ModeNumber;

- UINTN HandleCount;

- EFI_HANDLE *HandleBuffer;

- EFI_STATUS Status;

- UINTN Index;

- UINTN CurrentColumn;

- UINTN CurrentRow;

+ EFI_STATUS Status;

+ EFI_EVENT BdsConsoleEvent;



- Status = gBS->HandleProtocol (

- gST->ConsoleOutHandle,

- &gEfiGraphicsOutputProtocolGuid,

- (VOID**)&GraphicsOutput

- );

- if (EFI_ERROR (Status)) {

- GraphicsOutput = NULL;

- }

+ DEBUG ((DEBUG_INFO, "%a \n", __FUNCTION__));



- Status = gBS->HandleProtocol (

- gST->ConsoleOutHandle,

- &gEfiSimpleTextOutProtocolGuid,

- (VOID**)&SimpleTextOut

- );

- if (EFI_ERROR (Status)) {

- SimpleTextOut = NULL;

- }

+ Status = CreateBdsEvent (

+ TPL_CALLBACK,

+ &gBdsEventAfterConsoleReadyBeforeBootOptionGuid,

+ &BdsConsoleEvent

+ );



- if ((GraphicsOutput == NULL) || (SimpleTextOut == NULL)) {

- return EFI_UNSUPPORTED;

- }

-

- MaxGopMode = GraphicsOutput->Mode->MaxMode;

- MaxTextMode = SimpleTextOut->Mode->MaxMode;

-

- //

- // 1. If current video resolution is same with new video resolution,

- // video resolution need not be changed.

- // 1.1. If current text mode is same with new text mode, text mode need not be change.

- // 1.2. If current text mode is different with new text mode, text mode need be change to new text mode.

- // 2. If current video resolution is different with new video resolution, we need restart whole console drivers.

- //

- for (ModeNumber = 0; ModeNumber < MaxGopMode; ModeNumber++) {

- Status = GraphicsOutput->QueryMode (

- GraphicsOutput,

- ModeNumber,

- &SizeOfInfo,

- &Info

- );

- if (!EFI_ERROR (Status)) {

- if ((Info->HorizontalResolution == mShellHorizontalResolution) &&

- (Info->VerticalResolution == mShellVerticalResolution)) {

- if ((GraphicsOutput->Mode->Info->HorizontalResolution == mShellHorizontalResolution) &&

- (GraphicsOutput->Mode->Info->VerticalResolution == mShellVerticalResolution)) {

- //

- // If current video resolution is same with new resolution,

- // then check if current text mode is same with new text mode.

- //

- Status = SimpleTextOut->QueryMode (SimpleTextOut, SimpleTextOut->Mode->Mode, &CurrentColumn, &CurrentRow);

- ASSERT_EFI_ERROR (Status);

- if (CurrentColumn == mShellModeColumn && CurrentRow == mShellModeRow) {

- //

- // Current text mode is same with new text mode, text mode need not be change.

- //

- FreePool (Info);

- return EFI_SUCCESS;

- } else {

- //

- // Current text mode is different with new text mode, text mode need be change to new text mode.

- //

- for (Index = 0; Index < MaxTextMode; Index++) {

- Status = SimpleTextOut->QueryMode (SimpleTextOut, Index, &CurrentColumn, &CurrentRow);

- if (!EFI_ERROR(Status)) {

- if ((CurrentColumn == mShellModeColumn) && (CurrentRow == mShellModeRow)) {

- //

- // New text mode is supported, set it.

- //

- Status = SimpleTextOut->SetMode (SimpleTextOut, Index);

- ASSERT_EFI_ERROR (Status);

- //

- // Update text mode PCD.

- //

- Status = PcdSet32S (PcdConOutColumn, mShellModeColumn);

- ASSERT_EFI_ERROR (Status);

-

- Status = PcdSet32S (PcdConOutRow, mShellModeRow);

- ASSERT_EFI_ERROR (Status);

-

- FreePool (Info);

- return EFI_SUCCESS;

- }

- }

- }

- if (Index == MaxTextMode) {

- //

- // If new text mode is not supported, return error.

- //

- FreePool (Info);

- return EFI_UNSUPPORTED;

- }

- }

- } else {

- FreePool (Info);

- //

- // If current video resolution is not same with the new one, set new video resolution.

- // In this case, the driver which produces simple text out need be restarted.

- //

- Status = GraphicsOutput->SetMode (GraphicsOutput, ModeNumber);

- if (!EFI_ERROR (Status)) {

- //

- // Set PCD to restart GraphicsConsole and Consplitter to change video resolution

- // and produce new text mode based on new resolution.

- //

- Status = PcdSet32S (PcdVideoHorizontalResolution, mShellHorizontalResolution);

- ASSERT_EFI_ERROR (Status);

-

- Status = PcdSet32S (PcdVideoVerticalResolution, mShellVerticalResolution);

- ASSERT_EFI_ERROR (Status);

-

- Status = PcdSet32S (PcdConOutColumn, mShellModeColumn);

- ASSERT_EFI_ERROR (Status);

-

- Status = PcdSet32S (PcdConOutRow, mShellModeRow);

- ASSERT_EFI_ERROR (Status);

-

- Status = gBS->LocateHandleBuffer (

- ByProtocol,

- &gEfiSimpleTextOutProtocolGuid,

- NULL,

- &HandleCount,

- &HandleBuffer

- );

- if (!EFI_ERROR (Status)) {

- for (Index = 0; Index < HandleCount; Index++) {

- gBS->DisconnectController (HandleBuffer[Index], NULL, NULL);

- }

- for (Index = 0; Index < HandleCount; Index++) {

- gBS->ConnectController (HandleBuffer[Index], NULL, NULL, TRUE);

- }

- if (HandleBuffer != NULL) {

- FreePool (HandleBuffer);

- }

- break;

- }

- }

- }

- }

- FreePool (Info);

- }

- }

+ ASSERT_EFI_ERROR (Status);



- if (ModeNumber == MaxGopMode) {

- //

- // If the new resolution is not supported, return error.

- //

- return EFI_UNSUPPORTED;

+ if (!EFI_ERROR (Status)) {

+ gBS->SignalEvent (BdsConsoleEvent);

+ gBS->CloseEvent (BdsConsoleEvent);

+ DEBUG ((DEBUG_INFO,"All AfterConsoleReadyBeforeBootOption callbacks have returned successfully\n"));

}

-

- return EFI_SUCCESS;

}



-/**

- ReadyToBoot callback to set video and text mode for internal shell boot.

- That will not connect USB controller while CSM and FastBoot are disabled, we need to connect them

- before booting to Shell for showing USB devices in Shell.

-

- When FastBoot is enabled and Windows Console is the chosen Console behavior, input devices will not be connected

- by default. Hence, when booting to EFI shell, connecting input consoles are required.

-

- @param Event Pointer to this event

- @param Context Event hanlder private data

-

- @retval None.

-**/

-VOID

-EFIAPI

-OnReadyToBootCallBack (

- IN EFI_EVENT Event,

- IN VOID *Context

- )

-{

- DEBUG ((EFI_D_INFO, "OnReadyToBootCallBack\n"));

-

- if (BootCurrentIsInternalShell ()) {

-

- ChangeModeForInternalShell ();

- EfiBootManagerConnectAllDefaultConsoles();

- gDS->Dispatch ();

- }

-}



/**

Platform Bds init. Incude the platform firmware vendor, revision

@@ -1102,153 +201,37 @@ PlatformBootManagerBeforeConsole (
VOID

)

{

- EFI_STATUS Status;

- EFI_DEVICE_PATH_PROTOCOL *VarConOut;

- EFI_DEVICE_PATH_PROTOCOL *VarConIn;

- EFI_EVENT Event;



DEBUG ((EFI_D_INFO, "PlatformBootManagerBeforeConsole\n"));



- Status = EFI_SUCCESS;

-

//

- // Get user defined text mode for internal shell only once.

+ // Trusted console can be added in a PciEnumComplete callback

//

- mShellHorizontalResolution = PcdGet32 (PcdSetupVideoHorizontalResolution);

- mShellVerticalResolution = PcdGet32 (PcdSetupVideoVerticalResolution);

- mShellModeColumn = PcdGet32 (PcdSetupConOutColumn);

- mShellModeRow = PcdGet32 (PcdSetupConOutRow);

-

- if (PcdGetBool (PcdUpdateConsoleInBds) == TRUE) {

- //

- // Create event to set proper video resolution and text mode for internal shell.

- //

- Status = EfiCreateEventReadyToBootEx (

- TPL_CALLBACK,

- OnReadyToBootCallBack,

- NULL,

- &Event

- );

- ASSERT_EFI_ERROR (Status);

-

- //

- // Connect Root Bridge to make PCI BAR resource allocated and all PciIo created

- //

- ConnectRootBridge (FALSE);

-

- //

- // Fill ConIn/ConOut in Full Configuration boot mode

- //

- DEBUG ((DEBUG_INFO, "PlatformBootManagerInit - %x\n", gBootMode));

-

- if (gBootMode == BOOT_WITH_FULL_CONFIGURATION ||

- gBootMode == BOOT_WITH_DEFAULT_SETTINGS ||

- gBootMode == BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS ||

- gBootMode == BOOT_IN_RECOVERY_MODE) {

-

- GetEfiGlobalVariable2 (L"ConOut", (VOID **)&VarConOut, NULL); if (VarConOut != NULL) { FreePool (VarConOut); }

- GetEfiGlobalVariable2 (L"ConIn", (VOID **)&VarConIn, NULL); if (VarConIn != NULL) { FreePool (VarConIn); }

-

- //

- // Only fill ConIn/ConOut when ConIn/ConOut is empty because we may drop to Full Configuration boot mode in non-first boot

- //

- if (VarConOut == NULL || VarConIn == NULL) {

- if (PcdGetSize (PcdTrustedConsoleOutputDevicePath) >= sizeof(EFI_DEVICE_PATH_PROTOCOL)) {

- AddConsoleVariable (ConOut, PcdGetPtr (PcdTrustedConsoleOutputDevicePath));

- }

- if (PcdGetSize (PcdTrustedConsoleInputDevicePath) >= sizeof(EFI_DEVICE_PATH_PROTOCOL)) {

- AddConsoleVariable (ConIn, PcdGetPtr (PcdTrustedConsoleInputDevicePath));

- }

- }

- }

-

- EnumUsbKeyboard ();

- //

- // For trusted console it must be handled here.

- //

- UpdateGraphicConOut (TRUE);

-

- //

- // Dynamically register hot key: F2/F7/Enter

- //

- RegisterDefaultBootOption ();

- RegisterStaticHotkey ();

- }

-

- PERF_START_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7010);

- if (PcdGetBool (PcdTpm2Enable)) {

- ProcessTcgPp ();

- ProcessTcgMor ();

- }

- PERF_END_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7011);



//

- // We should make all UEFI memory and GCD information populated before ExitPmAuth.

- // SMM may consume these information.

+ // Signal Before Console, after Trusted console Event

//

- MemoryTest((EXTENDMEM_COVERAGE_LEVEL) PcdGet32 (PcdPlatformMemoryCheckLevel));

-

- PERF_START_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7020);

- ExitPmAuth ();

- PERF_END_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7021);

+ BdsSignalEventBeforeConsoleAfterTrustedConsole ();



//

- // Dispatch the deferred 3rd party images.

+ // Signal Before Console, before End of Dxe

//

- EfiBootManagerDispatchDeferredImages ();

+ BdsSignalEventBeforeConsoleBeforeEndOfDxe ();



//

- // For non-trusted console it must be handled here.

+ // Signal End Of Dxe Event

//

- if (PcdGetBool (PcdUpdateConsoleInBds) == TRUE) {

- UpdateGraphicConOut (FALSE);

- }

-}

-

-

-/**

- Connect with predeined platform connect sequence,

- the OEM/IBV can customize with their own connect sequence.

-

- @param[in] BootMode Boot mode of this boot.

-**/

-VOID

-ConnectSequence (

- IN EFI_BOOT_MODE BootMode

- )

-{

- EfiBootManagerConnectAll ();

-}

-

-/**

- The function is to consider the boot order which is not in our expectation.

- In the case that we need to re-sort the boot option.

-

- @retval TRUE Need to sort Boot Option.

- @retval FALSE Don't need to sort Boot Option.

-**/

-BOOLEAN

-IsNeedSortBootOption (

- VOID

- )

-{

- EFI_BOOT_MANAGER_LOAD_OPTION *BootOptions;

- UINTN BootOptionCount;

-

- BootOptions = EfiBootManagerGetLoadOptions (&BootOptionCount, LoadOptionTypeBoot);

+ PERF_START_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7020);

+ ExitPmAuth ();

+ PERF_END_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7021);



//

- // If setup is the first priority in boot option, we need to sort boot option.

+ // Deferred 3rd party images can be dispatched in

+ // an SmmReadyToLock callback

//

- if ((BootOptionCount > 1) &&

- (((StrnCmp (BootOptions->Description, L"Enter Setup", StrLen (L"Enter Setup"))) == 0) ||

- ((StrnCmp (BootOptions->Description, L"BootManagerMenuApp", StrLen (L"BootManagerMenuApp"))) == 0))) {

- return TRUE;

- }

-

- return FALSE;

}



+

/**

The function will excute with as the platform policy, current policy

is driven by boot mode. IBV/OEM can customize this code for their specific

@@ -1265,71 +248,11 @@ PlatformBootManagerAfterConsole (
VOID

)

{

- EFI_BOOT_MODE LocalBootMode;

-

DEBUG ((EFI_D_INFO, "PlatformBootManagerAfterConsole\n"));

-

- //

- // Get current Boot Mode

- //

- LocalBootMode = gBootMode;

- DEBUG ((DEBUG_INFO, "Current local bootmode - %x\n", LocalBootMode));

-

- LinuxBootStart();



- //

- // Go the different platform policy with different boot mode

- // Notes: this part code can be change with the table policy

- //

- switch (LocalBootMode) {

-

- case BOOT_ASSUMING_NO_CONFIGURATION_CHANGES:

- case BOOT_WITH_MINIMAL_CONFIGURATION:

- case BOOT_ON_S4_RESUME:

- //

- // Perform some platform specific connect sequence

- //

- if (PcdGetBool (PcdFastBoot) == FALSE) {

- PERF_START_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7050);

- ConnectSequence (LocalBootMode);

- PERF_END_EX(NULL,"EventRec", NULL, AsmReadTsc(), 0x7051);

- }

-

- break;

-

- case BOOT_WITH_FULL_CONFIGURATION:

- case BOOT_WITH_FULL_CONFIGURATION_PLUS_DIAGNOSTICS:

- case BOOT_WITH_DEFAULT_SETTINGS:

- default:

- //

- // Perform some platform specific connect sequence

- //

- ConnectSequence (LocalBootMode);

-

- //

- // Only in Full Configuration boot mode we do the enumeration of boot device

- //

- //

- // Dispatch all but Storage Oprom explicitly, because we assume Int13Thunk driver is there.

- //

- EfiBootManagerRefreshAllBootOption ();

-

- if (IsNeedSortBootOption()) {

- EfiBootManagerSortLoadOptionVariable (LoadOptionTypeBoot, CompareBootOption);

- }

- //

- // PXE boot option may appear after boot option enumeration

- //

-

- break;

- }

-

- if (PcdGetBool (PcdFastBoot) == FALSE) {

- Print (L"Press F7 for BootMenu!\n");

+ LinuxBootStart();



- EfiBootManagerRefreshAllBootOption ();

- EfiBootManagerSortLoadOptionVariable (LoadOptionTypeBoot, CompareBootOption);

- }

+ BdsSignalEventAfterConsoleReadyBeforeBootOption ();

}



/**

@@ -1345,19 +268,19 @@ PlatformBootManagerUnableToBoot (
VOID

)

{

- EFI_STATUS Status;

- EFI_BOOT_MANAGER_LOAD_OPTION BootDeviceList;

- CHAR16 OptionName[sizeof ("Boot####")];

+ BoardBootManagerUnableToBoot ();

+}



- if (mBootMenuOptionNumber == LoadOptionNumberUnassigned) {

- return;

- }

- UnicodeSPrint (OptionName, sizeof (OptionName), L"Boot%04x", mBootMenuOptionNumber);

- Status = EfiBootManagerVariableToLoadOption (OptionName, &BootDeviceList);

- if (EFI_ERROR (Status)) {

- return;

- }

- for (;;) {

- EfiBootManagerBoot (&BootDeviceList);

- }

+/**

+ This function is called each second during the boot manager waits the timeout.

+

+ @param TimeoutRemain The remaining timeout.

+**/

+VOID

+EFIAPI

+PlatformBootManagerWaitCallback (

+ UINT16 TimeoutRemain

+ )

+{

+ BoardBootManagerWaitCallback (TimeoutRemain);

}

diff --git a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.h b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.h
index 360a00d7d7..031676cdc3 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.h
+++ b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/BdsPlatform.h
@@ -1,7 +1,7 @@
/** @file

Header file for BDS Platform specific code



-Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>

+Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent



**/

@@ -9,176 +9,13 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _BDS_PLATFORM_H

#define _BDS_PLATFORM_H



-#include <PiDxe.h>

-#include <Protocol/DevicePath.h>

-#include <Protocol/SimpleNetwork.h>

-#include <Protocol/PciRootBridgeIo.h>

-#include <Protocol/LoadFile.h>

-#include <Protocol/PciIo.h>

-#include <Protocol/CpuIo2.h>

-#include <Protocol/LoadedImage.h>

-#include <Protocol/DiskInfo.h>

-#include <Protocol/GraphicsOutput.h>

-#include <Protocol/UgaDraw.h>

-#include <Protocol/GenericMemoryTest.h>

-#include <Protocol/DevicePathToText.h>

-#include <Protocol/FirmwareVolume2.h>

-#include <Protocol/SimpleFileSystem.h>

-

-#include <Guid/CapsuleVendor.h>

-#include <Guid/MemoryTypeInformation.h>

-#include <Guid/GlobalVariable.h>

-#include <Guid/MemoryOverwriteControl.h>

-#include <Guid/FileInfo.h>

-#include <Library/DebugLib.h>

-#include <Library/BaseMemoryLib.h>

-#include <Library/UefiBootServicesTableLib.h>

-#include <Library/UefiRuntimeServicesTableLib.h>

-#include <Library/MemoryAllocationLib.h>

-#include <Library/BaseLib.h>

-#include <Library/PcdLib.h>

-#include <Library/PlatformBootManagerLib.h>

-#include <Library/DevicePathLib.h>

-#include <Library/UefiLib.h>

-#include <Library/HobLib.h>

-#include <Library/DxeServicesLib.h>

-#include <Library/DxeServicesTableLib.h>

-#include <Library/PrintLib.h>

-#include <Library/HiiLib.h>

-#include <Library/CapsuleLib.h>

-#include <Library/PerformanceLib.h>

-

-#include <IndustryStandard/Pci30.h>

-#include <IndustryStandard/PciCodeId.h>

-

-///

-/// ConnectType

-///

-#define CONSOLE_OUT 0x00000001

-#define STD_ERROR 0x00000002

-#define CONSOLE_IN 0x00000004

-#define CONSOLE_ALL (CONSOLE_OUT | CONSOLE_IN | STD_ERROR)

-

-extern EFI_GUID gUefiShellFileGuid;

-extern EFI_BOOT_MODE gBootMode;

-

-#define gPciRootBridge \

- { \

- { \

- ACPI_DEVICE_PATH, \

- ACPI_DP, \

- { \

- (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \

- (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8) \

- }, \

- }, \

- EISA_PNP_ID (0x0A03), \

- 0 \

- }

-

-#define gEndEntire \

- { \

- END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { END_DEVICE_PATH_LENGTH, 0 } \

- }

-

-typedef struct {

- EFI_DEVICE_PATH_PROTOCOL *DevicePath;

- UINTN ConnectType;

-} BDS_CONSOLE_CONNECT_ENTRY;

-

-//

-// Platform Root Bridge

-//

-typedef struct {

- ACPI_HID_DEVICE_PATH PciRootBridge;

- EFI_DEVICE_PATH_PROTOCOL End;

-} PLATFORM_ROOT_BRIDGE_DEVICE_PATH;

-

-//

-// Below is the platform console device path

-//

-typedef struct {

- ACPI_HID_DEVICE_PATH PciRootBridge;

- PCI_DEVICE_PATH IsaBridge;

- ACPI_HID_DEVICE_PATH Keyboard;

- EFI_DEVICE_PATH_PROTOCOL End;

-} PLATFORM_KEYBOARD_DEVICE_PATH;

-

-typedef struct {

- ACPI_HID_DEVICE_PATH PciRootBridge;

- PCI_DEVICE_PATH PciDevice;

- EFI_DEVICE_PATH_PROTOCOL End;

-} PLATFORM_ONBOARD_CONTROLLER_DEVICE_PATH;

-

-typedef struct {

- ACPI_HID_DEVICE_PATH PciRootBridge;

- PCI_DEVICE_PATH Pci0Device;

- EFI_DEVICE_PATH_PROTOCOL End;

-} PLATFORM_PEG_ROOT_CONTROLLER_DEVICE_PATH;

-

-typedef struct {

- ACPI_HID_DEVICE_PATH PciRootBridge;

- PCI_DEVICE_PATH PciBridge;

- PCI_DEVICE_PATH PciDevice;

- EFI_DEVICE_PATH_PROTOCOL End;

-} PLATFORM_PCI_CONTROLLER_DEVICE_PATH;

-

-//

-// Below is the boot option device path

-//

-

-#define CLASS_HID 3

-#define SUBCLASS_BOOT 1

-#define PROTOCOL_KEYBOARD 1

-

-typedef struct {

- USB_CLASS_DEVICE_PATH UsbClass;

- EFI_DEVICE_PATH_PROTOCOL End;

-} USB_CLASS_FORMAT_DEVICE_PATH;

-

-extern USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath;

-

-//

-// Platform BDS Functions

-//

-

-

-/**

- Perform the memory test base on the memory test intensive level,

- and update the memory resource.

-

- @param Level The memory test intensive level.

-

- @retval EFI_STATUS Success test all the system memory and update

- the memory resource

-

-**/

-EFI_STATUS

-MemoryTest (

- IN EXTENDMEM_COVERAGE_LEVEL Level

- );

-

-VOID

-ConnectSequence (

- IN EFI_BOOT_MODE BootMode

- );

-

-

-INTN

-EFIAPI

-CompareBootOption (

- CONST VOID *Left,

- CONST VOID *Right

- );

-

-

-VOID

-RegisterStaticHotkey (

- VOID

- );

-VOID

-RegisterDefaultBootOption (

- VOID

- );

+ #include <Library/DebugLib.h>

+ #include <Library/UefiBootServicesTableLib.h>

+ #include <Library/PlatformBootManagerLib.h>

+ #include <Library/UefiLib.h>

+ #include <Library/HobLib.h>

+ #include <Library/PrintLib.h>

+ #include <Library/PerformanceLib.h>

+ #include <Library/BoardBootManagerLib.h>



#endif

diff --git a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf
index 21ac65257c..c795418c02 100644
--- a/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf
+++ b/Platform/Intel/PurleyOpenBoardPkg/Override/Platform/Intel/MinPlatformPkg/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf
@@ -1,12 +1,12 @@
-## @file

+### @file

# Component name for module DxePlatformBootManagerLib

#

-# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>

+# Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>

# Copyright (c) 2021, American Megatrends International LLC.<BR>

#

# SPDX-License-Identifier: BSD-2-Clause-Patent

#

-##

+###



[Defines]

INF_VERSION = 0x00010017

@@ -24,23 +24,13 @@


[LibraryClasses]

BaseLib

- MemoryAllocationLib

UefiBootServicesTableLib

- UefiRuntimeServicesTableLib

- BaseMemoryLib

DebugLib

- PcdLib

- PrintLib

- DevicePathLib

UefiLib

HobLib

- DxeServicesLib

- DxeServicesTableLib

- HiiLib

UefiBootManagerLib

PerformanceLib

- TimerLib

- Tcg2PhysicalPresenceLib

+ BoardBootManagerLib

LinuxBootLib



[Packages]

@@ -48,51 +38,19 @@
MdeModulePkg/MdeModulePkg.dec

SecurityPkg/SecurityPkg.dec

MinPlatformPkg/MinPlatformPkg.dec

- PurleyOpenBoardPkg/OpenBoardPkg.dec

-

-[Pcd]

- gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable ## CONSUMES

- gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut ## PRODUCES

- gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution ## PRODUCES

- gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution ## PRODUCES

- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow ## PRODUCES

- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn ## PRODUCES

- gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutColumn ## CONSUMES

- gEfiMdeModulePkgTokenSpaceGuid.PcdSetupConOutRow ## CONSUMES

- gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoHorizontalResolution ## CONSUMES

- gEfiMdeModulePkgTokenSpaceGuid.PcdSetupVideoVerticalResolution ## CONSUMES

- gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand ## PRODUCES

- gMinPlatformPkgTokenSpaceGuid.PcdPlatformMemoryCheckLevel ## CONSUMES

- gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly ## CONSUMES

- gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath ## CONSUMES

- gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath ## CONSUMES

- gMinPlatformPkgTokenSpaceGuid.PcdTrustedStorageDevicePath ## CONSUMES

- gPlatformTokenSpaceGuid.PcdUpdateConsoleInBds ## CONSUMES

- gPlatformTokenSpaceGuid.PcdFastBoot ## CONSUMES



[Sources]

BdsPlatform.c

BdsPlatform.h

- PlatformBootOption.c

- MemoryTest.c



[Protocols]

- gEfiPciRootBridgeIoProtocolGuid ## CONSUMES

- gEfiPciIoProtocolGuid ## CONSUMES

- gEfiCpuIo2ProtocolGuid ## CONSUMES

- gEfiDxeSmmReadyToLockProtocolGuid ## PRODUCES

- gEfiGenericMemTestProtocolGuid ## CONSUMES

- gEfiDiskInfoProtocolGuid ## CONSUMES

- gEfiDevicePathToTextProtocolGuid ## CONSUMES

- gEfiSimpleTextInputExProtocolGuid ## CONSUMES

- gEfiFirmwareVolume2ProtocolGuid ## CONSUMES

- gEfiFormBrowser2ProtocolGuid ## CONSUMES

- gEfiGenericMemTestProtocolGuid ## CONSUMES

+ gEfiDxeSmmReadyToLockProtocolGuid ## PRODUCES



[Guids]

- gEfiGlobalVariableGuid ## PRODUCES

- gEfiMemoryOverwriteControlDataGuid ## PRODUCES

- gEfiEndOfDxeEventGroupGuid ## CONSUMES

+ gEfiEndOfDxeEventGroupGuid ## CONSUMES

+ gBdsEventBeforeConsoleAfterTrustedConsoleGuid

+ gBdsEventBeforeConsoleBeforeEndOfDxeGuid

+ gBdsEventAfterConsoleReadyBeforeBootOptionGuid



[Depex.common.DXE_DRIVER]

gEfiVariableArchProtocolGuid

--
2.25.0.windows.1


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Re: [EXTERNAL] RE: [edk2-platforms] [PATCH V1] WhitleyOpenBoardPkg : Support for Junction City Platform.

manickavasakam karpagavinayagam
 

Isaac :

OK. We will try to move the Junction UBA into JunctionCity folder.

Thank you

-Manic

-----Original Message-----
From: Oram, Isaac W <isaac.w.oram@intel.com>
Sent: Tuesday, December 7, 2021 2:33 PM
To: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Harikrishna Doppalapudi <Harikrishnad@ami.com>; Manish Jha <manishj@ami.com>; Zachary Bobroff <zacharyb@ami.com>
Subject: RE: [EXTERNAL] RE: [edk2-platforms] [PATCH V1] WhitleyOpenBoardPkg : Support for Junction City Platform.

Manic,

Please move UBA Junction City specific content into JunctionCity folder. We should do the same for the different RVP boards as well. The MinPlatform design goal is to have the shared code across the family of platforms in the *OpenBoardPkg and the individual board libraries, build files, etc in a board subdirectory. That will also make it easier to deprecate support for boards in the future. I will work to address that in future platforms.

Regards,
Isaac

-----Original Message-----
From: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
Sent: Tuesday, December 7, 2021 9:02 AM
To: Oram, Isaac W <isaac.w.oram@intel.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; DOPPALAPUDI, HARIKRISHNA <harikrishnad@ami.com>; Jha, Manish <manishj@ami.com>; Bobroff, Zachary <zacharyb@ami.com>
Subject: RE: [EXTERNAL] RE: [edk2-platforms] [PATCH V1] WhitleyOpenBoardPkg : Support for Junction City Platform.

Isaac :

Thank you for your review comments. Please see the inline response and provide your comments if there is any.

-----Original Message-----
From: Oram, Isaac W <isaac.w.oram@intel.com>
Sent: Monday, December 6, 2021 7:43 PM
To: Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>; devel@edk2.groups.io
Cc: Desimone, Nathaniel L <nathaniel.l.desimone@intel.com>; Harikrishna Doppalapudi <Harikrishnad@ami.com>; Manish Jha <manishj@ami.com>; Zachary Bobroff <zacharyb@ami.com>; Manickavasakam Karpagavinayagam <manickavasakamk@ami.com>
Subject: [EXTERNAL] RE: [edk2-platforms] [PATCH V1] WhitleyOpenBoardPkg : Support for Junction City Platform.


**CAUTION: The e-mail below is from an external source. Please exercise caution before opening attachments, clicking links, or following guidance.**

Manic,

Please run python \edk2\BaseTools\Scripts\PatchCheck.py -1 to verify your commit passes recommendations and fix the issues that this script highlights. This is documented somewhere in edk2 development process.

edk2-platforms\Platform\Intel\WhitleyOpenBoardPkg\JunctionCity\Library\IpmiPlatformHookLib\IpmiPlatformHookLib.c: Coding style issues:
- Line 22: Missing space before ( in "PlatformIpmiIoRangeSet("
- Line 47: Missing space after ,
Function comment block doesn't match current coding standards/style. Block is after prototype and not using doxygen identifiers.

[Manic] : We will correct it.

edk2-platforms\Platform\Intel\WhitleyOpenBoardPkg\JunctionCity\Library\PeiPlatformHookLib\PeiPlatformHooklib.c: Coding style
- Line 23: Missing line containing VOID, ) not indented
- Line 26 and 40: Missing space before (
- Line 37: Missing line containing VOID
- Line 25: Status not used for anything. I believe that this can cause compiler errors for some static analysis checks.

[Manic] : We will correct it.

edk2-platforms/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo: Design suggestion.
- This is optional for you to implement. The underlying design is not very extensible. It might be nicer for all future derivative boards if there is an option to force it at build via a board ID FixedAtBuild PCD. Maybe a UINT8 with default 0x00. Then modify board detection to only get GPIO if it is zero, otherwise use the build value and skip detection. Then you don't have to maintain your own copy of this PEIM.

[Manic] : We will modify edk2-platforms\Platform\Intel\WhitleyOpenBoardPkg\Platform\Pei\PlatformInfo\PlatformInfo.c GetPlatformInfo() to check build time boardId PCD. If it is zero, regular code flow will be executed.
If not, we will use the build time boardID Pcd and return from the start of the function.

edk2-platforms/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.h
- I am not a lawyer, but I don't believe it is correct to add copyright to something that has not been changed from the original.

[Manic] : Will remove the copyright if the file content is not changed.

edk2-platforms\Platform\Intel\WhitleyOpenBoardPkg\JunctionCity\build_board.py
- typo JuctioCity
[Manic] : We will correct the typo

- It might be nicer to add this to the build_board.py that is used to build all the other Platform\Intel boards to be consistent. That would be good to discuss with Nate who knows this code better.
[Manic] : build_board.py is maintained separately for WilsonCityRvp/CooperCityRvp in the respective folders edk2-platforms\Platform\Intel\WhitleyOpenBoardPkg\WilsonCityRvp or CooperCityRvp. We followed the same and I believe this is a good approach.


edk2-platforms/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
edk2-platforms/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
- We don't want to make these ever expanding. The problem is that if each board includes these, they get a large number of unnecessary components. I think that you want to either make custom copies in JunctionCity/Include/Dsc and /Fdf, or just put into your PlatformPkg.dsc and .fdf directly.

[Manic] : We will remove and move the changes from UbaRpBoards.dsc/ UbaDxeRpBoards.fdf to JunctionCity PlatformPkg.dsc and .fdf.
But TypeJunctionCity UBA folder will be present in the same location edk2-platforms\Platform\Intel\WhitleyOpenBoardPkg\Uba\UbaMain as like others TypeCooperCityRP, TypeWilsonCityRP and TypeWilsonCitySMT.

edk2-platforms/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
- Typo: TypeJunctioCity

[Manic] : We will remove TypeJunctioCity.

edk2-platforms/Platform/Intel/Readme.md
- Line 63 is not needed. Line 62 identifies the family of boards, Junction City is just a board within the family. Please remove this line.

[Manic] : We will remove the line

edk2-platforms/Readme.md
- Line 251 is not needed, please do not add.

[Manic] : We will remove the line

The current implementation of PlatformPkg.dsc is ok. This feedback is optional for you to implement. However, you can include the WhitleyOpenBoardPkg\PlatformPkg.dsc and avoid a lot of duplicate code. I attached a patch with a sample of what that would look like. I did not get it fully building with IPMI and network advanced features. That should just take a little time to debug. Some issues with one or both of those advanced features interacting with other DSC content. Anyway, you can see that this is much simpler and shows only the differences from the parent reference board. It is not as easy to do the same thing with FDF, so we plan to break that content up in the future to make it sensible to modify reasonably.

[Manic] : Agreed. We will include WhitleyOpenBoardPkg\PlatformPkg.dsc in our JunctionCity\PlatformPkg.dsc and leave the FDF file as it is.

Regards,
Isaac

-----Original Message-----
From: manickavasakam karpagavinayagam <mailto:manickavasakamk@ami.com>
Sent: Monday, November 29, 2021 3:15 PM
To: mailto:devel@edk2.groups.io
Cc: Desimone, Nathaniel L <mailto:nathaniel.l.desimone@intel.com>; Oram, Isaac W <mailto:isaac.w.oram@intel.com>; DOPPALAPUDI, HARIKRISHNA <mailto:harikrishnad@ami.com>; Jha, Manish <mailto:manishj@ami.com>; Bobroff, Zachary <mailto:zacharyb@ami.com>; KARPAGAVINAYAGAM, MANICKAVASAKAM <mailto:manickavasakamk@ami.com>
Subject: [edk2-platforms] [PATCH V1] WhitleyOpenBoardPkg : Support for Junction City Platform.

Support for JunctionCity Platform
- Add JunctionCity UBA's (Except GpioTable.c, IioBifurInit.c), all
other files in UBA folder are just name replacement (replaced TypeWilsonCity with TypeJunctionCity)
- Disabled Intel ME IDE-R devices, KT devices to avoid BIOS POST time
- JunctionCity has different SKU's. Apart from reading the GPIO's always forcing
board id to JunctionCity in GetPlatformInfo()

Cc: Nate DeSimone <mailto:nathaniel.l.desimone@intel.com>
Cc: Isaac Oram <mailto:isaac.w.oram@intel.com>
Cc: Harikrishna Doppalapudi <mailto:harikrishnad@ami.com>
Cc: Manish Jha <mailto:manishj@ami.com>
Cc: Manickavasakam Karpagavinayagam <mailto:manickavasakamk@ami.com>
Cc: Zachary Bobroff <mailto:zacharyb@ami.com>

Signed-off-by: Manickavasakam Karpagavinayagam <mailto:manickavasakamk@ami.com>
---
Platform/Intel/Readme.md | 12 +
Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc | 2 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c | 60 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf | 32 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.c | 92 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf | 35 +
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.c | 741 +++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.h | 90 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.inf | 64 ++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc | 996 ++++++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf | 821 ++++++++++++++++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py | 127 +++
Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg | 37 +
Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec | 1 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c | 11 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf | 2 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf | 8 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c | 100 ++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h | 119 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf | 48 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c | 116 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h | 58 ++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf | 48 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c | 128 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h | 27 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf | 45 +
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/AcpiTablePcds.c | 54 ++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/GpioTable.c | 296 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/IioBifurInit.c | 242 +++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/KtiEparam.c | 69 ++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PcdData.c | 275 ++++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PchEarlyUpdate.c | 93 ++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInit.h | 78 ++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.c | 157 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.inf | 167 ++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SlotTable.c | 172 ++++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SoftStrapFixup.c | 121 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/UsbOC.c | 127 +++
Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc | 9 +
Platform/Intel/build.cfg | 1 +
Readme.md | 1 +
Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h | 2 +
42 files changed, 5684 insertions(+)

diff --git a/Platform/Intel/Readme.md b/Platform/Intel/Readme.md
index 965009ce21..dd02d1526d 100644
--- a/Platform/Intel/Readme.md
+++ b/Platform/Intel/Readme.md
@@ -60,6 +60,7 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol
* The `CometlakeOpenBoardPkg` contains board implementations for CometLake systems.

* The `TigerlakeOpenBoardPkg` contains board implementations for TigerLake systems.

* The `WhitleyOpenBoardPkg` contains board implementations for Ice Lake-SP and Cooper Lake systems.

+* The `WhitleyOpenBoardPkg` contains board implementations for JunctionCity systems.



### **Supported Hardware**



@@ -89,6 +90,7 @@ A UEFI firmware implementation using MinPlatformPkg is constructed using the fol
| TGL-U DDR4 RVP | TigerLake | TigerlakeOpenBoardPkg | TigerlakeURvp |

| Wilson City RVP | IceLake-SP (Xeon Scalable) | WhitleyOpenBoardPkg | WilsonCityRvp |

| Cooper City RVP | Copper Lake | WhitleyOpenBoardPkg | CooperCityRvp |

+| JunctionCity | IceLake-SP (Xeon Scalable) | WhitleyOpenBoardPkg | JunctionCity |



*Note: RVP = Reference and Validation Platform*



@@ -392,6 +394,16 @@ For PurleyOpenBoardPkg (TiogaPass)
**WhitleyOpenBoardPkg**

1. This firmware project has been tested booting to UEFI shell with headless serial console



+**JunctionCity**

+1. This firmware project has been tested booting to UEFI shell

+2. Booted to RHEL 8.2, Ubuntu 18.04 using U2 NVME Disk

+3. Booted to Windows 2019 using M2 SSD Disk

+4. Connected PCIE Network card and made sure PCIE card detected in POST and in OS

+5. Verified TPM offboard chip detection

+

+### **Known limitations**

+1. System boots very slow when booting to RHEL 8.2 OS using SATA drive

+

### **Package Builds**



In some cases, such as BoardModulePkg, a package may provide a set of functionality that is included in other

diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
index 99ab0961ca..05d140898f 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
@@ -2,6 +2,7 @@
# Platform description.

#

# Copyright (c) 2017 - 2021, Intel Corporation. All rights reserved.<BR>

+# Copyright (c) 2021, American Megatrends International LLC. <BR>

#

# SPDX-License-Identifier: BSD-2-Clause-Patent

#

@@ -133,5 +134,6 @@
}

SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf

SecurityPkg/Tcg/Tcg2Config/Tcg2ConfigDxe.inf

+ SecurityPkg/Tcg/Tcg2Acpi/Tcg2Acpi.inf

!endif



diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c
new file mode 100644
index 0000000000..680b0ac6b7
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.c
@@ -0,0 +1,60 @@
+/** @file
+ This file implements the IPMI Platform hook functions
+
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include <Uefi.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/DebugLib.h>
+#define KCS_BASE_ADDRESS_MASK 0xFFF0
+#define NUMBER_OF_BYTES_TO_DECODE 0x10
+
+//
+// Prototype definitions for IPMI Platform Update Library
+//
+
+EFI_STATUS
+EFIAPI
+PlatformIpmiIoRangeSet(
+ UINT16 IpmiIoBase
+)
+/*++
+
+ Routine Description:
+
+ This function sets IPMI Io range
+
+ Arguments:
+
+ IpmiIoBase
+
+ Returns:
+
+ Status
+
+--*/
+{
+
+ EFI_STATUS Status;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi;
+
+ DynamicSiLibraryPpi = NULL;
+
+ DEBUG ((EFI_D_INFO, "PlatformIpmiIoRangeSet IpmiIoBase %x\n",IpmiIoBase));
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "PeiServicesLocatePpi for gDynamicSiLibraryPpiGuid failed. Status %r\n", Status));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ DynamicSiLibraryPpi->PchLpcGenIoRangeSet ((IpmiIoBase & KCS_BASE_ADDRESS_MASK), NUMBER_OF_BYTES_TO_DECODE);
+
+ return EFI_SUCCESS;
+
+}
\ No newline at end of file
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf
new file mode 100644
index 0000000000..699d89b24a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf
@@ -0,0 +1,32 @@
+## @file
+# Component description file for IPMI platform hook Library.
+#
+# Copyright (c) 2018 - 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, American Megatrends International LLC.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IpmiPlatformHookLib
+ FILE_GUID = A770BDB8-331A-4110-8B60-81FC17480B36
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = IpmiPlatformHookLib
+
+[sources]
+ IpmiPlatformHookLib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+
+[LibraryClasses]
+ DebugLib
+
+[Ppis]
+ gDynamicSiLibraryPpiGuid ## CONSUMES
+
+[Depex]
+ gDynamicSiLibraryPpiGuid
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.c
new file mode 100644
index 0000000000..d2ccfebc43
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.c
@@ -0,0 +1,92 @@
+/** @file
+ PEI Library Functions. Initialize GPIOs
+
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Uefi.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/DebugLib.h>
+#include <Library/UbaGpioInitLib.h>
+#include <Library/PeiPlatformHooklib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+/**
+ Configure GPIO
+
+ @param[in] PlatformInfo
+**/
+VOID
+GpioInit (
+)
+{
+ EFI_STATUS Status;
+ Status = PlatformInitGpios();
+}
+
+/**
+ Disables ME PCI devices like IDE-R , KT
+
+ @param[in] None
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+DisableMEDevices (
+)
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi;
+
+ DynamicSiLibraryPpi = NULL;
+
+ DEBUG ((DEBUG_INFO, "DisableMEDevices\n"));
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ //
+ //Disable IDE-R
+ //
+ DynamicSiLibraryPpi->PchPcrAndThenOr32 (
+ PID_PSF1,
+ (R_PCH_H_PCR_PSF1_T0_SHDW_IDER_REG_BASE + R_PCH_PSFX_PCR_T0_SHDW_PCIEN),
+ (UINT32)~0,
+ B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS
+ );
+
+ //
+ //Disable KT
+ //
+ DynamicSiLibraryPpi->PchPcrAndThenOr32 (
+ PID_PSF1,
+ (R_PCH_H_PCR_PSF1_T0_SHDW_KT_REG_BASE + R_PCH_PSFX_PCR_T0_SHDW_PCIEN),
+ (UINT32)~0,
+ B_PCH_PSFX_PCR_T0_SHDW_PCIEN_FUNDIS
+ );
+ return EFI_SUCCESS;
+
+}
+
+/**
+ Configure GPIO and SIO
+
+ @retval EFI_SUCCESS Operation success.
+**/
+EFI_STATUS
+BoardInit (
+ )
+{
+
+ GpioInit();
+ DisableMEDevices ();
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
new file mode 100644
index 0000000000..fb3985c4e0
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
@@ -0,0 +1,35 @@
+## @file
+#
+# @copyright
+# Copyright 1999 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PeiPlatformHookLib
+ FILE_GUID = 6E9351C3-A17A-4ADF-8602-55B07962718F
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PeiPlatformHookLib|PEIM PEI_CORE SEC
+
+[Sources]
+ PeiPlatformHooklib.c
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+
+[LibraryClasses]
+ DebugLib
+ UbaGpioInitLib
+
+[Pcd]
+
+[Ppis]
+
+[Guids]
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.c b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.c
new file mode 100644
index 0000000000..acc9605df2
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.c
@@ -0,0 +1,741 @@
+/** @file
+ Platform Info PEIM.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PlatformInfo.h"
+#include <GpioPinsSklH.h>
+#include <Library/GpioLib.h>
+#include <Library/PchInfoLib.h>
+
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+#include <Library/UbaGpioPlatformConfig.h>
+#include <UncoreCommonIncludes.h>
+#include <PlatformInfoTypes.h>
+
+#include <Library/PeiServicesLib.h>
+
+#define TEMP_BUS_NUMBER (0x3F)
+
+
+STATIC EFI_PEI_PPI_DESCRIPTOR mPlatformInfoPpi = {
+ EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST,
+ &gEfiPlatformInfoGuid,
+ NULL
+ };
+
+#define BOARD_ID_GPIO_PADS_NUMBER 6
+#define BOARD_REV_ID_GPIO_PADS_NUMBER 3
+
+//
+// These pads shall not be board specific as these are used for Board ID and Rev ID detection
+// Therefore can not be moved to UBA and are common for all Purley boards
+//
+GPIO_PAD mBoardId [BOARD_ID_GPIO_PADS_NUMBER] = {
+ // BoardId pads - PADCFG register for GPIO G12
+ // WARNING: The pad number must be obtained from board schematics
+ GPIO_SKL_H_GPP_G12,
+ GPIO_SKL_H_GPP_G13,
+ GPIO_SKL_H_GPP_G14,
+ GPIO_SKL_H_GPP_G15,
+ GPIO_SKL_H_GPP_G16,
+ GPIO_SKL_H_GPP_B19
+};
+
+GPIO_PAD mBoardRevId [BOARD_REV_ID_GPIO_PADS_NUMBER] = {
+ // Board RevId pads - Start from pad C12
+ // WARNING: This should be obtained from board schematics
+ GPIO_SKL_H_GPP_C12,
+ GPIO_SKL_H_GPP_C13,
+ GPIO_SKL_H_GPP_B9
+};
+
+GPIO_CONFIG mBoardAndRevIdConfig = {
+ // Board and Revision ID pads configuration required for proper reading the values
+ GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutDefault, GpioIntDefault,
+ GpioPlatformReset, GpioTermDefault, GpioLockDefault, GpioRxRaw1Default
+};
+
+
+VOID
+GpioConfigForBoardId (
+ VOID
+ )
+{
+ UINT8 i;
+ EFI_STATUS Status;
+ GPIO_CONFIG PadConfig;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ PadConfig.PadMode = mBoardAndRevIdConfig.PadMode;
+ PadConfig.HostSoftPadOwn = mBoardAndRevIdConfig.HostSoftPadOwn;
+ PadConfig.Direction = mBoardAndRevIdConfig.Direction;
+ PadConfig.OutputState = mBoardAndRevIdConfig.OutputState;
+ PadConfig.InterruptConfig = mBoardAndRevIdConfig.InterruptConfig;
+ PadConfig.PowerConfig = mBoardAndRevIdConfig.PowerConfig;
+ PadConfig.ElectricalConfig = mBoardAndRevIdConfig.ElectricalConfig;
+ PadConfig.LockConfig = mBoardAndRevIdConfig.LockConfig;
+ PadConfig.OtherSettings = mBoardAndRevIdConfig.OtherSettings;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return;
+ }
+
+ for (i = 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) {
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (mBoardId[i], &PadConfig);
+ ASSERT_EFI_ERROR (Status);
+ }
+}
+
+
+VOID
+GpioConfigForBoardRevId (
+ VOID
+ )
+{
+ UINT8 i;
+ EFI_STATUS Status;
+ GPIO_CONFIG PadConfig;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ PadConfig.PadMode = mBoardAndRevIdConfig.PadMode;
+ PadConfig.HostSoftPadOwn = mBoardAndRevIdConfig.HostSoftPadOwn;
+ PadConfig.Direction = mBoardAndRevIdConfig.Direction;
+ PadConfig.OutputState = mBoardAndRevIdConfig.OutputState;
+ PadConfig.InterruptConfig = mBoardAndRevIdConfig.InterruptConfig;
+ PadConfig.PowerConfig = mBoardAndRevIdConfig.PowerConfig;
+ PadConfig.ElectricalConfig = mBoardAndRevIdConfig.ElectricalConfig;
+ PadConfig.LockConfig = mBoardAndRevIdConfig.LockConfig;
+ PadConfig.OtherSettings = mBoardAndRevIdConfig.OtherSettings;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return;
+ }
+
+ for (i = 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++) {
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (mBoardRevId[i], &PadConfig);
+ ASSERT_EFI_ERROR (Status);
+ }
+}
+
+/**
+
+ Reads GPIO pins to get Board ID value
+
+ @retval Status - Success if GPIO's are read properly
+
+**/
+EFI_STATUS
+GpioGetBoardId (
+ OUT UINT32 *BoardId
+ )
+{
+ EFI_STATUS Status = EFI_DEVICE_ERROR;
+ UINT32 Data32;
+ UINT8 i;
+ UINT32 BdId;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ if (BoardId == NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ BdId = 0;
+
+ GpioConfigForBoardId ();
+
+ for (i = 0; i < BOARD_ID_GPIO_PADS_NUMBER; i++) {
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (mBoardId[i], &Data32);
+ if (EFI_ERROR(Status)) {
+ break;
+ }
+ if (Data32) {
+ BdId = BdId | (1 << i);
+ }
+ }
+ if (Status != EFI_SUCCESS) {
+ return Status;
+ }
+ *BoardId = BdId;
+ return EFI_SUCCESS;
+}
+
+/**
+
+ Reads GPIO pins to get Board Revision ID value
+
+ @retval Status - Success if GPIO's are read properly
+
+**/
+EFI_STATUS
+GpioGetBoardRevId (
+ OUT UINT32 *BoardRevId
+ )
+{
+ EFI_STATUS Status = EFI_DEVICE_ERROR;
+ UINT32 Data32;
+ UINT8 i;
+ UINT32 RevId;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ if (BoardRevId == NULL) {
+ return EFI_UNSUPPORTED;
+ }
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ RevId = 0;
+
+ GpioConfigForBoardRevId ();
+
+ for (i = 0; i < BOARD_REV_ID_GPIO_PADS_NUMBER; i++){
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (mBoardRevId[i], &Data32);
+ if (EFI_ERROR(Status)) {
+ break;
+ }
+ if (Data32) {
+ RevId = RevId | (1 << i);
+ }
+ }
+ if (Status != EFI_SUCCESS) {
+ return Status;
+ }
+ *BoardRevId = RevId;
+ return EFI_SUCCESS;
+
+}
+
+/**
+
+ Returns the Model ID of the CPU.
+ Model ID = EAX[7:4]
+
+**/
+VOID
+GetCpuInfo (
+ UINT32 *CpuType,
+ UINT8 *CpuStepping
+ )
+
+{
+ UINT32 RegEax=0;
+
+ AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);
+
+ *CpuStepping = (UINT8) (RegEax & 0x0F);
+ *CpuType = (UINT32) (RegEax >> 4);
+}
+
+
+/**
+
+ GC_TODO: add routine description
+
+ @param BAR - GC_TODO: add arg description
+ @param PeiServices - GC_TODO: add arg description
+
+ @retval None
+
+**/
+VOID
+InitGSX(
+ UINT32 *BAR,
+ IN EFI_PEI_SERVICES **PeiServices
+)
+{
+}
+
+/**
+
+ GC_TODO: add routine description
+
+ @param Data - GC_TODO: add arg description
+ @param PeiServices - GC_TODO: add arg description
+
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+ @retval EFI_UNSUPPORTED - GC_TODO: add retval description
+
+**/
+EFI_STATUS
+GsxRead(
+ UINT32 *Data,
+ IN EFI_PEI_SERVICES **PeiServices
+)
+{
+ return EFI_UNSUPPORTED;
+}
+
+/**
+
+ GC_TODO: add routine description
+
+ @param Data - GC_TODO: add arg description
+ @param PeiServices - GC_TODO: add arg description
+
+ @retval None
+
+**/
+VOID
+GetGsxBoardID(
+ BOARD_ID *Data,
+ IN EFI_PEI_SERVICES **PeiServices
+)
+{
+
+ EFI_STATUS Status;
+ UINT32 GSXIN[2];
+ UINT32 RetryCount;
+
+ RetryCount = 0;
+ GSXIN[0] = 0;
+ GSXIN[1] = 0;
+
+ do {
+ Status = GsxRead(GSXIN, PeiServices);
+
+ if(Status){
+ // if EFI_SUCCESS != Success then retry one more time
+ RetryCount ++;
+ }else{
+ // if EFI_SUCCESS read Board ID and exit
+ RetryCount = 0xFFFFFFFF;
+ }
+
+ if (GSXIN[0] & BIT0) {
+ Data->BoardID.BoardID0 = 1;
+ }
+
+ if (GSXIN[0] & BIT1) {
+ Data->BoardID.BoardID1 = 1;
+ }
+
+ if (GSXIN[0] & BIT2) {
+ Data->BoardID.BoardID2 = 1;
+ }
+
+ if (GSXIN[0] & BIT3) {
+ Data->BoardID.BoardID3 = 1;
+ }
+
+ if (GSXIN[0] & BIT4) {
+ Data->BoardID.BoardID4 = 1;
+ }
+
+ if (GSXIN[0] & BIT5) {
+ Data->BoardID.BoardRev0 = 1;
+ }
+
+ if (GSXIN[0] & BIT6) {
+ Data->BoardID.BoardRev1 = 1;
+ }
+
+ } while(RetryCount < 1);
+
+ if(Status){
+ //
+ // Unhable to read GSX HW error Hang the system
+ //
+ DEBUG ((EFI_D_ERROR, "ERROR: GSX HW is unavailable, SYSTEM HANG\n"));
+ CpuDeadLoop ();
+ }
+}
+
+/**
+ Get Platform Type by read Platform Data Region in SPI flash.
+ SPI Descriptor Mode Routines for Accessing Platform Info from Platform Data Region (PDR)
+
+ @param PeiServices - General purpose services available to every PEIM.
+ @param PlatformInfoHob - Platform Type is returned in PlatformInfoHob->BoardId
+
+ @retval Status EFI_SUCCESS - PDR read success
+ @retval Status EFI_INCOMPATIBLE_VERSION - PDR read but it is not valid Platform Type
+
+**/
+EFI_STATUS
+PdrGetPlatformInfo (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+{
+ EFI_STATUS Status;
+ PCH_SPI_PROTOCOL *SpiPpi;
+ UINTN Size;
+
+ //
+ // Locate the SPI PPI Interface
+ //
+ Status = (*PeiServices)->LocatePpi (
+ PeiServices,
+ &gPchSpiPpiGuid,
+ 0,
+ NULL,
+ &SpiPpi
+ );
+
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ //
+ // Read the PIT (Platform Info Table) from the SPI Flash Platform Data Region
+ //
+ Size = sizeof (EFI_PLATFORM_INFO);
+ Status = SpiPpi->FlashRead (
+ SpiPpi,
+ FlashRegionPlatformData,
+ PDR_REGION_START_OFFSET,
+ (UINT32) Size,
+ (UINT8 *) PlatformInfoHob
+ );
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ if ((PlatformInfoHob->BoardId >= TypePlatformMin) && (PlatformInfoHob->BoardId <= TypePlatformMax)) {
+ //
+ // Valid Platform Identified
+ //
+ DEBUG ((DEBUG_INFO, "Platform Info from PDR: Type = %x\n",PlatformInfoHob->BoardId));
+ } else {
+ //
+ // Reading PIT from SPI PDR Failed or a unknown platform identified
+ //
+ DEBUG ((EFI_D_ERROR, "PIT from SPI PDR reports Platform ID as %x. This is unknown ID. Assuming Greencity Platform!\n", PlatformInfoHob->BoardId));
+ PlatformInfoHob->BoardId = TypePlatformUnknown;
+ Status = EFI_INCOMPATIBLE_VERSION;
+ }
+ return Status;
+}
+
+VOID
+GatherQATInfo(OUT EFI_PLATFORM_INFO *PlatformInfoHob)
+/**
+
+ GC_TODO: add routine description
+
+ @param None
+
+ @ret None
+**/
+{
+ EFI_STATUS Status;
+ GPIO_CONFIG PadConfig;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ // Gpio programming to QAT board detection
+ PadConfig.PadMode = GpioPadModeGpio;
+ PadConfig.HostSoftPadOwn = GpioHostOwnDefault;
+ PadConfig.Direction = GpioDirIn;
+ PadConfig.OutputState = GpioOutLow;
+ PadConfig.InterruptConfig = GpioIntDis;
+ PadConfig.PowerConfig = GpioResetPwrGood;
+ PadConfig.ElectricalConfig = GpioTermNone;
+ PadConfig.LockConfig = GpioPadConfigLock;
+ PadConfig.OtherSettings = 00;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return;
+ }
+
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B3, &PadConfig);
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B3, &PlatformInfoHob->QATDis);
+ Status = DynamicSiLibraryPpi->GpioSetPadConfig (GPIO_SKL_H_GPP_B4, &PadConfig);
+ Status = DynamicSiLibraryPpi->GpioGetInputValue (GPIO_SKL_H_GPP_B4, &PlatformInfoHob->QATSel);
+}
+
+EFI_STATUS
+GetPlatformInfo (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+/**
+
+ GC_TODO: add routine description
+
+ @param PeiServices - GC_TODO: add arg description
+ @param PlatformInfoHob - GC_TODO: add arg description
+
+ @retval EFI_UNSUPPORTED - GC_TODO: add retval description
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+
+**/
+{
+
+
+ UINT32 BoardId;
+ UINT32 BoardRev;
+ EFI_PEI_PCI_CFG2_PPI *PciCfgPpi;
+ EFI_STATUS Status;
+
+ PciCfgPpi = (**PeiServices).PciCfg;
+ ASSERT (PciCfgPpi != NULL);
+
+ PlatformInfoHob->BoardId = TypeNeonCityEPRP;
+ DEBUG ((DEBUG_INFO, "Use GPIO to read Board ID\n"));
+
+ Status = GpioGetBoardId (&BoardId);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n"));
+ return Status;
+ }
+ Status = GpioGetBoardRevId (&BoardRev);
+ if (EFI_ERROR(Status)) {
+ DEBUG ((EFI_D_ERROR, "Error: Can't read GPIO to get Board ID!\n"));
+ return Status;
+ }
+ PlatformInfoHob->TypeRevisionId = BoardRev;
+
+ //
+ //Forcing the Board id to JunctionCity
+ //
+ PlatformInfoHob->BoardId = TypeJunctionCity;
+ DEBUG ((DEBUG_INFO, "Board ID = TypeJunctionCity\n"));
+
+ GatherQATInfo(PlatformInfoHob);
+
+ DEBUG ((DEBUG_INFO, "Board Rev.: %d\n", BoardRev));
+ return EFI_SUCCESS;
+}
+
+/**
+
+ This function initializes the board related flag to indicates if
+ PCH and Lan-On-Motherboard (LOM) devices is supported.
+
+**/
+VOID
+GetPchLanSupportInfo(
+ IN EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+{
+ PlatformInfoHob->PchData.LomLanSupported = 0;
+}
+
+/**
+
+ GC_TODO: add routine description
+
+ @param PeiVariable - GC_TODO: add arg description
+ @param PlatformInfoHob - GC_TODO: add arg description
+
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+
+**/
+EFI_STATUS
+EFIAPI
+GetIioCommonRcPlatformSetupPolicy(
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+ {
+ UINT8 IsocEn;
+
+ CopyMem (&IsocEn, (UINT8 *)PcdGetPtr(PcdSocketCommonRcConfig) + OFFSET_OF(SOCKET_COMMONRC_CONFIGURATION, IsocEn), sizeof(UINT8));
+
+ PlatformInfoHob->SysData.IsocEn = IsocEn; // ISOC enabled
+
+ return EFI_SUCCESS;
+}
+/**
+
+ GC_TODO: add routine description
+
+ @param PeiVariable - GC_TODO: add arg description
+ @param PlatformInfoHob - GC_TODO: add arg description
+
+ @retval EFI_SUCCESS - GC_TODO: add retval description
+
+**/
+EFI_STATUS
+EFIAPI
+GetIioPlatformSetupPolicy(
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ )
+{
+ return EFI_SUCCESS;
+}
+
+
+/**
+ Platform Type detection. Because the PEI globle variable
+ is in the flash, it could not change directly.So use
+ 2 PPIs to distinguish the platform type.
+
+ @param FfsHeader - Pointer to Firmware File System file header.
+ @param PeiServices - General purpose services available to every PEIM.
+
+ @retval EFI_SUCCESS - Memory initialization completed successfully.
+ @retval Others - All other error conditions encountered result in an ASSERT.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformInfoInit (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status;
+ EFI_PEI_PCI_CFG2_PPI *PciCfgPpi;
+ EFI_PEI_READ_ONLY_VARIABLE2_PPI *PeiVariable;
+ EFI_PLATFORM_INFO PlatformInfoHob;
+ EFI_PLATFORM_INFO tempPlatformInfoHob;
+ UINT8 ChipId;
+ UINT32 Delay;
+ UINT32 CpuType;
+ UINT8 CpuStepping;
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+
+ PciCfgPpi = (**PeiServices).PciCfg;
+ if (PciCfgPpi == NULL) {
+ DEBUG ((EFI_D_ERROR, "\nError! PlatformInfoInit() - PeiServices is a NULL Pointer!!!\n"));
+ ASSERT_EFI_ERROR (EFI_INVALID_PARAMETER);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ //
+ // Locate Variable PPI
+ //
+ Status = PeiServicesLocatePpi (&gEfiPeiReadOnlyVariable2PpiGuid, 0, NULL, &PeiVariable);
+
+ (*PeiServices)->SetMem (&PlatformInfoHob, sizeof (PlatformInfoHob), 0);
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ //
+ // --------------------------------------------------
+ //
+ // Detect the iBMC SIO for CV/CRB Platforms
+ // 0x2E/0x2F decoding has been enabled in MonoStatusCode PEIM.
+ //
+ IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_UNLOCK);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+ IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_CHIP_ID_REG);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+ ChipId = IoRead8 (PILOTIV_SIO_DATA_PORT);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+ IoWrite8 (PILOTIV_SIO_INDEX_PORT, PILOTIV_SIO_LOCK);
+ for (Delay = 0; Delay < 40; Delay++) IoRead8 (0x61);
+
+ if (EFI_ERROR (Status))
+ {
+ DEBUG((EFI_D_ERROR, "LocatePpi Error in PlatformInfo.c !\n"));
+ }
+
+ Status = GetIioPlatformSetupPolicy (&PlatformInfoHob);
+ ASSERT_EFI_ERROR (Status);
+ Status = GetIioCommonRcPlatformSetupPolicy (&PlatformInfoHob);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Update PCH Type
+ //
+ PlatformInfoHob.PchType = DynamicSiLibraryPpi->GetPchSeries ();
+ PlatformInfoHob.PchSku = DynamicSiLibraryPpi->GetPchLpcDeviceId ();
+ PlatformInfoHob.PchRevision = (UINT8) DynamicSiLibraryPpi->PchStepping ();
+ PlatformInfoHob.MaxNumOfPchs = 1;
+ Status = EFI_SUCCESS;
+
+ if(!EFI_ERROR(Status)) {
+ Status = GetPlatformInfo (PeiServices, &PlatformInfoHob);
+ if(EFI_ERROR (Status)) {
+ Status = PdrGetPlatformInfo (PeiServices, &tempPlatformInfoHob);
+ PlatformInfoHob.BoardId = tempPlatformInfoHob.BoardId;
+ PlatformInfoHob.TypeRevisionId = tempPlatformInfoHob.TypeRevisionId;
+ if (EFI_ERROR(Status)) {
+ PlatformInfoHob.BoardId = TypePlatformUnknown;
+ }
+ }
+ } else {
+ PlatformInfoHob.BoardId = TypePlatformUnknown;
+ }
+
+ //
+ // Update IIO Type
+ //
+ PlatformInfoHob.IioRevision = 0;
+
+
+ //
+ // Get Subtractive decode enable bit from descriptor
+ //
+
+ if (DynamicSiLibraryPpi->PchIsGbeRegionValid () == FALSE) {
+ PlatformInfoHob.PchData.GbeRegionInvalid = 1;
+ } else {
+ PlatformInfoHob.PchData.GbeRegionInvalid = 0;
+ }
+ GetPchLanSupportInfo (&PlatformInfoHob);
+ PlatformInfoHob.PchData.GbePciePortNum = 0xFF;
+ PlatformInfoHob.PchData.GbePciePortNum = (UINT8) DynamicSiLibraryPpi->PchGetGbePortNumber ();
+ PlatformInfoHob.PchData.GbeEnabled = DynamicSiLibraryPpi->PchIsGbePresent ();
+ PlatformInfoHob.PchData.PchStepping = (UINT8) DynamicSiLibraryPpi->PchStepping ();
+
+ PlatformInfoHob.SysData.SysSioExist = (UINT8)IsSioExist();
+
+ GetCpuInfo (&CpuType, &CpuStepping);
+ PlatformInfoHob.CpuType = CpuType;
+ PlatformInfoHob.CpuStepping = CpuStepping;
+
+ //
+ // Set default memory topology to DaisyChainTopology. This should be modified in UBA board
+ // specific file.
+ //
+ (*PeiServices)->SetMem (&PlatformInfoHob.MemoryTopology, sizeof (PlatformInfoHob.MemoryTopology), DaisyChainTopology);
+
+ //
+ // Set default memory type connector to DimmConnectorPth. This should be modified in UBA board
+ // specific file.
+ //
+ (*PeiServices)->SetMem (&PlatformInfoHob.MemoryConnectorType, sizeof (PlatformInfoHob.MemoryConnectorType), DimmConnectorPth);
+
+ //
+ // Build HOB for setup memory information
+ //
+ BuildGuidDataHob (
+ &gEfiPlatformInfoGuid,
+ &(PlatformInfoHob),
+ sizeof (EFI_PLATFORM_INFO)
+ );
+
+ Status = (**PeiServices).InstallPpi (PeiServices, &mPlatformInfoPpi);
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Save PlatformInfoHob.BoardId in CMOS
+ //
+ IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_LO);
+ IoWrite8 (R_IOPORT_CMOS_UPPER_DATA, (UINT8)PlatformInfoHob.BoardId);
+
+ IoWrite8 (R_IOPORT_CMOS_UPPER_INDEX, CMOS_PLATFORM_ID_HI);
+ IoWrite8 (R_IOPORT_CMOS_UPPER_DATA, (UINT8)((PlatformInfoHob.PcieRiser2Type << 4) + (PlatformInfoHob.PcieRiser1Type)));
+
+ return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.h b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.h
new file mode 100644
index 0000000000..bb00b2cc75
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.h
@@ -0,0 +1,90 @@
+/** @file
+ Platform Info Driver.
+
+ @copyright
+ Copyright 1999 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PLATFORM_INFO_INTERNAL_H_
+#define _PLATFORM_INFO_INTERNAL_H_
+
+#include <PiPei.h>
+#include <Ppi/CpuIo.h>
+#include <Ppi/Spi.h>
+#include <Ppi/ReadOnlyVariable2.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HobLib.h>
+#include <Library/PlatformHooksLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Guid/SocketVariable.h>
+#include <Guid/SetupVariable.h>
+#include <Guid/PlatformInfo.h>
+#include <IndustryStandard/Pci22.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioLib.h>
+#include <Platform.h>
+#include "SioRegs.h"
+#include <Register/PchRegsSpi.h>
+#include <PchAccess.h>
+#include <Register/PchRegsLpc.h>
+#include <Library/ReportStatusCodeLib.h>
+#include <Register/Cpuid.h>
+
+#define EFI_PLATFORMINFO_DRIVER_PRIVATE_SIGNATURE SIGNATURE_32 ('P', 'I', 'N', 'F')
+
+//
+// CPU Model
+//
+#define INVALID_MODEL 0x0
+
+#define R_SB_SPI_FDOC 0xB0
+#define R_SB_SPI_FDOD 0xB4
+#define SPI_OPCODE_READ_INDEX 4
+#define PDR_REGION_START_OFFSET 0x0
+
+typedef union BOARD_ID
+{
+ struct{
+ UINT8 BoardID0 :1;
+ UINT8 BoardID1 :1;
+ UINT8 BoardID2 :1;
+ UINT8 BoardID3 :1;
+ UINT8 BoardID4 :1;
+ UINT8 BoardRev0 :1;
+ UINT8 BoardRev1 :1;
+ UINT8 Rsvd :1;
+ }BoardID;
+}BOARD_ID;
+
+typedef union RISER_ID
+{
+ struct{
+ UINT8 RiserID0 :1;
+ UINT8 RiserID1 :1;
+ UINT8 RiserID2 :1;
+ UINT8 RiserID3 :1;
+ UINT8 Rsvd :4;
+ }RiserID;
+}RISER_ID;
+
+
+
+EFI_STATUS
+PdrGetPlatformInfo (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+ );
+
+EFI_STATUS
+GPIOGetPlatformInfo (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ OUT EFI_PLATFORM_INFO *PlatformInfoHob
+);
+
+#endif
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.inf b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.inf
new file mode 100644
index 0000000000..41c072e29e
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/Platform/Pei/PlatformInfo/PlatformInfo.inf
@@ -0,0 +1,64 @@
+## @file
+# PlatformInfo PEIM
+#
+# @copyright
+# Copyright 2009 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = PlatformInfo
+ FILE_GUID = 0CEBAC0F-9349-44EC-A2DC-E07F34D412B3
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ ENTRY_POINT = PlatformInfoInit
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32
+#
+
+[Sources]
+ PlatformInfo.c
+ PlatformInfo.h
+
+[Packages]
+ MdePkg/MdePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ UefiCpuPkg/UefiCpuPkg.dec
+
+[LibraryClasses]
+ PeimEntryPoint
+ PcdLib
+ DebugLib
+ HobLib
+ IoLib
+ PlatformHooksLib
+ PeiServicesLib
+
+[Pcd]
+ gStructPcdTokenSpaceGuid.PcdSocketCommonRcConfig
+
+[Guids]
+ gEfiPlatformInfoGuid
+ gEfiSetupVariableGuid
+
+[Ppis]
+ gPchSpiPpiGuid
+ gEfiPeiReadOnlyVariable2PpiGuid
+ gDynamicSiLibraryPpiGuid ## CONSUMES
+
+[Depex]
+ gPchSpiPpiGuid AND
+ gEfiPeiReadOnlyVariable2PpiGuid AND
+ gDynamicSiLibraryPpiGuid
+
+
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc
new file mode 100644
index 0000000000..62d4ea68b0
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc
@@ -0,0 +1,996 @@
+## @file
+# X64 Platform with 64-bit DXE.
+#
+# @copyright
+# Copyright 2008 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+ BOARD_NAME = JunctionCity
+ PLATFORM_NAME = $(BOARD_NAME)
+ PLATFORM_GUID = F5798629-30B2-42EC-A1CA-825FEAA8A22A
+ PLATFORM_VERSION = 0.1
+ DSC_SPECIFICATION = 0x00010005
+ OUTPUT_DIRECTORY = Build/$(RP_PKG)
+ SUPPORTED_ARCHITECTURES = IA32|X64
+ BUILD_TARGETS = DEBUG|RELEASE
+ SKUID_IDENTIFIER = DEFAULT
+ VPD_TOOL_GUID = 8C3D856A-9BE6-468E-850A-24F7A8D38E08
+ FLASH_DEFINITION = $(RP_PKG)/$(BOARD_NAME)/PlatformPkg.fdf
+ PLATFORM_SI_PACKAGE = ClientOneSiliconPkg
+ DEFINE PLATFORM_SI_BIN_PACKAGE = WhitleySiliconBinPkg
+ PEI_ARCH = IA32
+ DXE_ARCH = X64
+
+!if $(CPUTARGET) == "CPX"
+ DEFINE FSP_BIN_PKG = CedarIslandFspBinPkg
+ DEFINE IIO_INSTANCE = Skx
+!elseif $(CPUTARGET) == "ICX"
+ DEFINE FSP_BIN_PKG = WhitleyFspBinPkg
+ DEFINE IIO_INSTANCE = Icx
+!else
+ DEFINE IIO_INSTANCE = UnknownCpu
+!endif
+
+ #
+ # Platform On/Off features are defined here
+ #
+ !include $(RP_PKG)/PlatformPkgConfig.dsc
+
+ #
+ # MRC common configuration options defined here
+ #
+ !include $(SILICON_PKG)/MrcCommonConfig.dsc
+
+[Packages]
+ IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec
+
+ !include $(FSP_BIN_PKG)/DynamicExPcd.dsc
+ !include $(FSP_BIN_PKG)/DynamicExPcdFvLateSilicon.dsc
+ !include $(RP_PKG)/DynamicExPcd.dsc
+
+ !include $(RP_PKG)/Uba/UbaCommon.dsc
+ !include $(RP_PKG)/Uba/UbaRpBoards.dsc
+
+ !include $(RP_PKG)/Include/Dsc/EnablePerformanceMonitoringInfrastructure.dsc
+
+ !include AdvancedFeaturePkg/Include/AdvancedFeaturesPcd.dsc
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this
+# Platform.
+#
+################################################################################
+[SkuIds]
+ 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.
+
+[DefaultStores]
+ 0|STANDARD
+ 1|MANUFACTURING
+
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+[PcdsFeatureFlag]
+ #
+ # MinPlatform control flags
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable |FALSE
+
+ # don't degrade 64bit MMIO space to 32-bit
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDegradeResourceForOptionRom|FALSE
+
+ # Server doesn't support capsule update on Reset.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|FALSE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|TRUE
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuHotPlugSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE
+
+ gEfiCpRcPkgTokenSpaceGuid.Reserved15|TRUE
+
+!if ($(CPUTARGET) == "ICX")
+ gEfiCpRcPkgTokenSpaceGuid.PcdMemBootHealthFeatureSupported|FALSE
+!endif # $(CPUTARGET) == "ICX"
+
+ gCpuPkgTokenSpaceGuid.PcdCpuSkylakeFamilyFlag|TRUE
+ gCpuPkgTokenSpaceGuid.PcdCpuIcelakeFamilyFlag|TRUE
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmDebug|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSelectLfpAsBspFlag|TRUE
+
+ ## Uncomment for better boot performance
+# gPerfOptTokenSpaceGuid.PcdPreUefiLegacyEnable|FALSE
+# gPerfOptTokenSpaceGuid.PcdLocalVideoEnable|FALSE
+
+ gPlatformTokenSpaceGuid.PcdSupportUnsignedCapsuleImage|TRUE
+
+ ## This PCD specified whether ACPI SDT protocol is installed.
+ gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE
+
+ ## This PCD specifies whether FPGA routine will be active
+ gSocketPkgFpgaGuid.PcdSktFpgaActive|TRUE
+
+!if $(CPU_SKX_ONLY_SUPPORT) == TRUE
+ gEfiCpRcPkgTokenSpaceGuid.PerBitMargin|FALSE
+ gEfiCpRcPkgTokenSpaceGuid.PcdSeparateCwlAdj|TRUE
+!endif
+
+ ## This PCD specifies whether or not to enable the High Speed UART
+ gPlatformModuleTokenSpaceGuid.PcdEnableHighSpeedUart|FALSE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
+
+[PcdsFixedAtBuild]
+ gEfiCpRcPkgTokenSpaceGuid.PcdRankSwitchFixOption|2
+
+ ## MinPlatform Boot Stage Selector
+ # Stage 1 - enable debug (system deadloop after debug init)
+ # Stage 2 - mem init (system deadloop after mem init)
+ # Stage 3 - boot to shell only
+ # Stage 4 - boot to OS
+ # Stage 5 - boot to OS with security boot enabled
+ # Stage 6 - boot with advanced features enabled
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdBootStage|6
+
+!if $(TARGET) == "RELEASE"
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x03
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE
+!else
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F # Enable asserts, prints, code, clear memory, and deadloops on asserts.
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07
+ gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdFixedDebugPrintErrorLevel|0x80200047 # Built in messages: Error, MTRR, info, load, warn, init
+ gEfiSourceLevelDebugPkgTokenSpaceGuid.PcdDebugLoadImageMethod|0x2 # This is set to INT3 (0x2) for Simics source level debugging
+!endif
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdShadowPeimOnS3Boot|TRUE
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x0
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|100000000
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x4449204C45544E49 # "INTEL ID"
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x100000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxSizeNonPopulateCapsule|0x2100000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0302
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140
+
+ gCpuPkgTokenSpaceGuid.PcdCpuIEDRamSize|0x400000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|512
+ gCpuPkgTokenSpaceGuid.PcdPlatformType|2
+ gCpuPkgTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|4000
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x10000
+
+ #PcdCpuMicrocodePatchRegionSize = PcdFlashNvStorageMicrocodeSize - (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER))
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0x1FFF70
+
+ #
+ # This controls the NEM code region cached during SEC
+ # It usually isn't necessary to match exactly the FV layout in the FDF file.
+ # It is a performance optimization to have it match the flash region exactly
+ # as then no extra reads are done to load unused flash into cache.
+ #
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionBase|0xFFC00000
+ gCpuUncoreTokenSpaceGuid.PcdFlashSecCacheRegionSize|0x00400000
+
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0x00FE800000
+ gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x0000200000
+
+ #
+ # Mode | FSP_MODE | PcdFspModeSelection
+ # ------------------|----------|--------------------
+ # FSP Dispatch Mode | 1 | 0
+ # FSP API Mode | 0 | 1
+ #
+!if ($(FSP_MODE) == 0)
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|1
+ gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00070000
+!else
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0
+!endif
+ gUefiCpuPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x20000
+
+ #
+ # These will be initialized during build
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|0x00000000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|0x00000000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|0x00000000
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase|0x00000000
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize|0x00000000
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase|0x00000000
+
+ ## Specifies delay value in microseconds after sending out an INIT IPI.
+ # @Prompt Configure delay value after send an INIT IPI
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuInitIpiDelayInMicroSeconds|10
+ ## Specifies max supported number of Logical Processors.
+ # @Prompt Configure max supported number of Logical Processorss
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize|0x1000
+
+ gPlatformTokenSpaceGuid.PcdPerfPkgPchPmBaseFunctionNumber|0x2
+
+ gPlatformTokenSpaceGuid.PcdUboDev|0x08
+ gPlatformTokenSpaceGuid.PcdUboFunc|0x02
+ gPlatformTokenSpaceGuid.PcdUboCpuBusNo0|0xCC
+
+ gCpuPkgTokenSpaceGuid.PcdCpuIEDEnabled|TRUE
+ gPlatformTokenSpaceGuid.PcdSupportLegacyStack|FALSE
+
+ ## Defines the ACPI register set base address.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Timer IO Port Address
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress | 0x0500
+
+ ## Defines the PCI Bus Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
+ # @Prompt ACPI Hardware PCI Bus Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber | 0x00
+
+ ## Defines the PCI Device Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
+ # The invalid 0xFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Device Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber | 0x1F
+
+ ## Defines the PCI Function Number of the PCI device that contains the BAR and Enable for ACPI hardware registers.
+ # The invalid 0xFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Function Number
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber | 0x02
+
+ ## Defines the PCI Register Offset of the PCI device that contains the Enable for ACPI hardware registers.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Register Offset
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset |0x0044
+
+ ## Defines the bit mask that must be set to enable the APIC hardware register BAR.
+ # @Prompt ACPI Hardware PCI Bar Enable BitMask
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask | 0x80
+
+ ## Defines the PCI Register Offset of the PCI device that contains the BAR for ACPI hardware registers.
+ # The invalid 0xFFFF is as its default value. It must be configured to the real value.
+ # @Prompt ACPI Hardware PCI Bar Register Offset
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset |0x0040
+
+ ## Defines the offset to the 32-bit Timer Value register that resides within the ACPI BAR.
+ # @Prompt Offset to 32-bit Timer register in ACPI BAR
+ gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset |0x0008
+
+!if $(CPUTARGET) == "ICX"
+ #
+ # ACPI PCD custom override
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x4C544E49
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013
+!endif
+
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|28
+ gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|$(MAX_SOCKET)
+ gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07
+
+ # Enable DDRT scheduler debug features for power on
+ gEfiCpRcPkgTokenSpaceGuid.PcdDdrtSchedulerDebugDefault|TRUE
+
+ # Disable Fast Warm Boot for Whitley Openboard Package
+ gEfiCpRcPkgTokenSpaceGuid.PcdMrcFastBootDefault|FALSE
+
+!if $(CPU_SKX_ONLY_SUPPORT) == FALSE
+ gCpuUncoreTokenSpaceGuid.PcdWaSerializationEn|FALSE
+ gEfiCpRcPkgTokenSpaceGuid.PcdMrcCmdVrefCenteringTrainingEnable|FALSE
+!endif
+
+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcIndexRegister|0x74
+ gPcAtChipsetPkgTokenSpaceGuid.PcdRtcTargetRegister|0x75
+
+ #
+ # PlatformInitPreMem
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0x100
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0xA30
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x100
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x100
+ gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0x100
+
+ gEfiCpRcPkgTokenSpaceGuid.PcdReserved15|0
+
+ !include $(SILICON_PKG)/Product/Whitley/SiliconPkg10nmPcds.dsc
+
+[PcdsFixedAtBuild.IA32]
+ #
+ # FSP Base address PCD will be updated in FDF basing on flash map.
+ #
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0
+
+!if ($(FSP_MODE) == 0)
+ gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE
+ gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x4000000
+ gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType|0
+!endif
+
+[PcdsFixedAtBuild.X64]
+ # Change PcdBootManagerMenuFile to UiApp
+ ##
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
+
+ gPlatformModuleTokenSpaceGuid.PcdS3AcpiReservedMemorySize|0xC00000
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable |TRUE
+
+ #
+ # AcpiPlatform
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiEnableSwSmi|0xA0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiDisableSwSmi|0xA1
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicCount|32
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicIdBase|0x09
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicAddressBase|0xFEC01000
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicInterruptBase|24
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtPreferredPmProfile|0x04
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtIaPcBootArch|0x0000
+ gMinPlatformPkgTokenSpaceGuid.PcdFadtFlags|0x000004A5
+ gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress|0xFEE00000
+ gMinPlatformPkgTokenSpaceGuid.PcdIoApicAddress|0xFEC00000
+ gMinPlatformPkgTokenSpaceGuid.PcdIoApicId|0x08
+
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AEventBlockAddress|0x500
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BEventBlockAddress|0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1AControlBlockAddress|0x504
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm1BControlBlockAddress|0
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPm2ControlBlockAddress|0x550
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiPmTimerBlockAddress|0x508
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe0BlockAddress|0x580
+ gMinPlatformPkgTokenSpaceGuid.PcdAcpiGpe1BlockAddress|0
+
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|FALSE
+
+ gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleInputDevicePath|{ 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, 0x04, 0x00, 0x03, 0x0F, 0x0B, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x01, 0x01, 0x7F, 0xFF, 0x04, 0x00}
+ gMinPlatformPkgTokenSpaceGuid.PcdTrustedConsoleOutputDevicePath|{ 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x1F, 0x02, 0x01, 0x0C, 0x00, 0xD0, 0x41, 0x01, 0x05, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0e, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x01, 0x01, 0x03, 0x0a, 0x14, 0x00, 0x53, 0x47, 0xC1, 0xe0, 0xbe, 0xf9, 0xd2, 0x11, 0x9a, 0x0c, 0x00, 0x90, 0x27, 0x3f, 0xc1, 0x4d, 0x7F, 0x01, 0x04, 0x00, 0x02, 0x01, 0x0C, 0x00, 0xd0, 0x41, 0x03, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x06, 0x00, 0x00, 0x02, 0x7F, 0xFF, 0x04, 0x00}
+ gBoardModulePkgTokenSpaceGuid.PcdSuperIoPciIsaBridgeDevice|{0x0, 0x0, 0x1F, 0x0}
+ gBoardModulePkgTokenSpaceGuid.PcdUart1Enable|0x01
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMinimalValidYear|1900
+ gPcAtChipsetPkgTokenSpaceGuid.PcdMaximalValidYear|9999
+
+[PcdsPatchableInModule]
+ #
+ # These debug options are patcheable so that they can be manipulated during debug (if memory is updateable)
+ #
+
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07 # Enable status codes for debug, progress, and errors
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000042 # Displayed messages: Error, Info, warn
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x80000000
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0
+
+!if $(PREMEM_PAGE_ALLOC_SUPPORT) == FALSE
+ gEfiCpRcPkgTokenSpaceGuid.PcdPeiTemporaryRamRcHeapSize|0x130000
+!endif
+
+[PcdsDynamicExDefault.IA32]
+!if ($(FSP_MODE) == 0)
+ gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x00000000
+!endif
+
+
+[PcdsDynamicExHii]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable|L"1GPageTable"|gEfiGenericVariableGuid|0x0|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5 # Variable: L"Timeout"
+ gPlatformTokenSpaceGuid.PcdPlatformMemoryCheck|L"MemoryCheck"|gPlatformTokenSpaceGuid|0x0|0
+ gCpPlatTokenSpaceGuid.PcdUefiOptimizedBoot|L"UefiOptimizedBoot"|gCpPlatTokenSpaceGuid|0x0|TRUE
+ gPlatformModuleTokenSpaceGuid.PcdBootState|L"BootState"|gEfiGenericVariableGuid|0x0|TRUE
+ gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"
+ gPlatformTokenSpaceGuid.PcdBootDeviceScratchPad5Changed|L"BootDeviceScratchPad"|gEfiGenericVariableGuid|0x0|FALSE
+
+[PcdsDynamicExDefault]
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|200000
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmPhysicalPresence|TRUE
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmAutoDetection|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+ gPlatformModuleTokenSpaceGuid.PcdLtConfigLockEnable|TRUE
+ gPlatformModuleTokenSpaceGuid.PcdProcessorLtsxEnable|FALSE
+
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmMsrSaveStateEnable|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmRuntimeCtlHooks|FALSE
+
+ gSiPkgTokenSpaceGuid.PcdWakeOnRTCS5|FALSE
+ gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeHour|0
+ gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeMinute|0
+ gSiPkgTokenSpaceGuid.PcdRtcWakeupTimeSecond|0
+
+ #Platform should change it to by code
+ gSiPkgTokenSpaceGuid.PcdPchSataInitReg78Data|0xAAAA0000
+ gSiPkgTokenSpaceGuid.PcdPchSataInitReg88Data|0xAA33AA22
+
+ gEfiSecurityPkgTokenSpaceGuid.PcdUserPhysicalPresence|TRUE
+
+ #
+ # CPU features related PCDs.
+ #
+ gCpuPkgTokenSpaceGuid.PcdCpuEnergyPolicy
+ gUefiCpuPkgTokenSpaceGuid.PcdCpuClockModulationDutyCycle
+ gUefiCpuPkgTokenSpaceGuid.PcdIsPowerOnReset
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|TRUE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMrIovSupport|FALSE
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSystemPageSize|0x01
+
+ ## Put fTPM guid here: e.g. { 0xf9c6a62f, 0xc60f, 0x4b44, { 0xa6, 0x29, 0xed, 0x3d, 0x40, 0xae, 0xfa, 0x5f } }
+ ## TPM1.2 { 0x8b01e5b6, 0x4f19, 0x46e8, { 0xab, 0x93, 0x1c, 0x53, 0x67, 0x1b, 0x90, 0xcc } }
+ ## TPM2.0Dtpm { 0x286bf25a, 0xc2c3, 0x408c, { 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17 } }
+
+ #TPM2.0#
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid|{0x5a, 0xf2, 0x6b, 0x28, 0xc3, 0xc2, 0x8c, 0x40, 0xb3, 0xb4, 0x25, 0xe6, 0x75, 0x8b, 0x73, 0x17}
+
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpmInitializationPolicy|0
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2InitializationPolicy|1
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2SelfTestPolicy|0
+
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmUseDelayIndication|FALSE
+ gCpuPkgTokenSpaceGuid.PcdCpuSmmUseBlockIndication|FALSE
+
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId|0x102b
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId|0x0522
+
+ gPlatformTokenSpaceGuid.PcdSetupMenuScanCode|0x000C
+ gPlatformTokenSpaceGuid.PcdBootDeviceListScanCode|0x0011
+ gPlatformTokenSpaceGuid.PcdBootMenuFile|{ 0xdc, 0x5b, 0xc2, 0xee, 0xf2, 0x67, 0x95, 0x4d, 0xb1, 0xd5, 0xf8, 0x1b, 0x20, 0x39, 0xd1, 0x1d }
+ gMinPlatformPkgTokenSpaceGuid.PcdPcIoApicEnable|0x0
+ gEfiSecurityPkgTokenSpaceGuid.PcdTpm2AcpiTableRev|4
+ gEfiSecurityPkgTokenSpaceGuid.PcdTcg2PhysicalPresenceFlags|0x600C0
+
+[PcdsDynamicExDefault.X64]
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0
+
+ #
+ # Set video to 1024x768 resolution
+ #
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1024
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|768
+
+[PcdsDynamicExDefault]
+
+!if $(CPUTARGET) == "CPX"
+ !include $(RP_PKG)/StructurePcdCpx.dsc
+!else
+ !include $(RP_PKG)/StructurePcd.dsc
+!endif
+
+[PcdsFeatureFlag]
+!if $(gMinPlatformPkgTokenSpaceGuid.PcdBootStage) >= 5
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |TRUE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |TRUE
+ gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |TRUE
+ gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable|TRUE
+!else
+ gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable |FALSE
+ gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable |FALSE
+ gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable |FALSE
+ gNetworkFeaturePkgTokenSpaceGuid.PcdNetworkFeatureEnable|FALSE
+!endif
+
+[Defines]
+!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable == TRUE
+ DEFINE SECURE_BOOT_ENABLE = TRUE
+!endif
+
+ !include AdvancedFeaturePkg/Include/AdvancedFeatures.dsc
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+
+!include MinPlatformPkg/Include/Dsc/CoreCommonLib.dsc
+!include MinPlatformPkg/Include/Dsc/CorePeiLib.dsc
+!include MinPlatformPkg/Include/Dsc/CoreDxeLib.dsc
+
+[LibraryClasses]
+
+ #
+ # Simics source level debugging requires the non-null version of PeCoffExtraActionLib
+ #
+!if $(TARGET) == "DEBUG"
+ PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
+!else
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+!endif
+
+ #
+ # Basic
+ #
+
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
+
+ #
+ # Framework
+ #
+ S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
+ FrameBufferBltLib|MdeModulePkg/Library/FrameBufferBltLib/FrameBufferBltLib.inf
+
+ SiliconPolicyInitLib|WhitleySiliconPkg/Library/SiliconPolicyInitLibShim/SiliconPolicyInitLibShim.inf
+!if ($(FSP_MODE) == 0)
+ SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLibFsp.inf
+!else
+ SiliconPolicyUpdateLib|$(RP_PKG)/Library/SiliconPolicyUpdateLib/SiliconPolicyUpdateLib.inf
+!endif
+
+ SetupLib|WhitleySiliconPkg/Library/SetupLib/SetupLib.inf
+
+ #
+ # ToDo: Can we use BaseAcpiTimerLib from MinPlatform?
+ #
+ TimerLib|PcAtChipsetPkg/Library/AcpiTimerLib/DxeAcpiTimerLib.inf
+
+ MultiPlatSupportLib|$(RP_PKG)/Library/MultiPlatSupportLib/MultiPlatSupportLib.inf
+ ReadFfsLib|$(RP_PKG)/Library/ReadFfsLib/ReadFfsLib.inf
+ PlatformSetupVariableSyncLib|$(RP_PKG)/Library/PlatformSetupVariableSyncLibNull/PlatformSetupVariableSyncLibNull.inf
+ PlatformVariableHookLib |$(RP_PKG)/Library/PlatformVariableHookLibNull/PlatformVariableHookLibNull.inf
+
+ PlatformBootManagerLib|$(PLATFORM_PKG)/Bds/Library/DxePlatformBootManagerLib/DxePlatformBootManagerLib.inf
+ SerialPortLib|$(RP_PKG)/Library/SerialPortLib/SerialPortLib.inf
+ PlatformHooksLib|$(RP_PKG)/Library/PlatformHooksLib/PlatformHooksLib.inf
+
+ CmosAccessLib|BoardModulePkg/Library/CmosAccessLib/CmosAccessLib.inf
+ PlatformCmosAccessLib|$(RP_PKG)/Library/PlatformCmosAccessLib/PlatformCmosAccessLib.inf
+ SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf
+ TpmCommLib|SecurityPkg/Library/TpmCommLib/TpmCommLib.inf
+
+ #
+ # MinPlatform uses port 80, we don't want to assume HW
+ #
+ PostCodeLib|MdePkg/Library/BasePostCodeLibDebug/BasePostCodeLibDebug.inf
+
+ TcgPpVendorLib|SecurityPkg/Library/TcgPpVendorLibNull/TcgPpVendorLibNull.inf
+ Tcg2PpVendorLib|SecurityPkg/Library/Tcg2PpVendorLibNull/Tcg2PpVendorLibNull.inf
+ AslUpdateLib|$(PLATFORM_PKG)/Acpi/Library/DxeAslUpdateLib/DxeAslUpdateLib.inf
+ PciSegmentInfoLib|$(PLATFORM_PKG)/Pci/Library/PciSegmentInfoLibSimple/PciSegmentInfoLibSimple.inf
+ PlatformOpromPolicyLib|$(RP_PKG)/Library/PlatformOpromPolicyLibNull/PlatformOpromPolicyLibNull.inf
+ VmgExitLib|UefiCpuPkg/Library/VmgExitLibNull/VmgExitLibNull.inf
+
+[LibraryClasses.Common.SEC, LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
+ FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFspWrapperApiLib.inf
+ FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib/PeiFspWrapperApiTestLib.inf
+ FspWrapperPlatformLib|WhitleySiliconPkg/Library/FspWrapperPlatformLib/FspWrapperPlatformLib.inf
+ FspWrapperHobProcessLib|WhitleyOpenBoardPkg/Library/PeiFspWrapperHobProcessLib/PeiFspWrapperHobProcessLib.inf
+
+ FspSwitchStackLib|IntelFsp2Pkg/Library/BaseFspSwitchStackLib/BaseFspSwitchStackLib.inf
+ FspCommonLib|IntelFsp2Pkg/Library/BaseFspCommonLib/BaseFspCommonLib.inf
+ FspPlatformLib|IntelFsp2Pkg/Library/BaseFspPlatformLib/BaseFspPlatformLib.inf
+
+[LibraryClasses.Common.SEC]
+ #
+ # SEC phase
+ #
+ TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplate.inf
+
+ PlatformSecLib|$(RP_PKG)/Library/SecFspWrapperPlatformSecLib/SecFspWrapperPlatformSecLib.inf
+ SecBoardInitLib|MinPlatformPkg/PlatformInit/Library/SecBoardInitLibNull/SecBoardInitLibNull.inf
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SecTestPointCheckLib.inf
+ VariableReadLib|MinPlatformPkg/Library/BaseVariableReadLibNull/BaseVariableReadLibNull.inf
+
+[LibraryClasses.Common.PEI_CORE, LibraryClasses.Common.PEIM]
+ #
+ # ToDo: Can we remove
+ #
+ CpuExceptionHandlerLib|UefiCpuPkg/Library/CpuExceptionHandlerLib/PeiCpuExceptionHandlerLib.inf
+
+ MpInitLib|UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf
+
+
+ PeiPlatformHookLib|$(RP_PKG)/$(BOARD_NAME)/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
+ PlatformClocksLib|$(RP_PKG)/Library/PlatformClocksLib/Pei/PlatformClocksLib.inf
+
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/PeiTestPointCheckLib.inf
+ TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/PeiTestPointLib.inf
+
+ ReportFvLib|$(RP_PKG)/Library/PeiReportFvLib/PeiReportFvLib.inf
+
+[LibraryClasses.Common.PEIM]
+ #
+ # Library instance consumed by MinPlatformPkg PlatformInit modules.
+ #
+ ReportCpuHobLib|MinPlatformPkg/PlatformInit/Library/ReportCpuHobLib/ReportCpuHobLib.inf
+ SetCacheMtrrLib|$(RP_PKG)/Library/SetCacheMtrrLib/SetCacheMtrrLib.inf
+ ResetSystemLib|MdeModulePkg/Library/PeiResetSystemLib/PeiResetSystemLib.inf
+
+!if gIpmiFeaturePkgTokenSpaceGuid.PcdIpmiFeatureEnable == TRUE
+ IpmiPlatformHookLib| $(RP_PKG)/$(BOARD_NAME)/Library/IpmiPlatformHookLib/IpmiPlatformHookLib.inf
+!endif
+
+
+[LibraryClasses.common.DXE_CORE, LibraryClasses.common.DXE_SMM_DRIVER, LibraryClasses.common.SMM_CORE, LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION]
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+
+ Tcg2PhysicalPresenceLib|SecurityPkg/Library/DxeTcg2PhysicalPresenceLib/DxeTcg2PhysicalPresenceLib.inf
+ TcgPhysicalPresenceLib|SecurityPkg/Library/DxeTcgPhysicalPresenceLib/DxeTcgPhysicalPresenceLib.inf
+
+ BiosIdLib|BoardModulePkg/Library/BiosIdLib/DxeBiosIdLib.inf
+ MpInitLib|UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf
+
+ TpmMeasurementLib|SecurityPkg/Library/DxeTpmMeasurementLib/DxeTpmMeasurementLib.inf
+
+ Tpm12DeviceLib|SecurityPkg/Library/Tpm12DeviceLibDTpm/Tpm12DeviceLibDTpm.inf
+
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+ TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/DxeTestPointLib.inf
+ BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.inf
+ BoardBootManagerLib|MinPlatformPkg/Bds/Library/BoardBootManagerLibNull/BoardBootManagerLibNull.inf
+
+ CompressDxeLib|MinPlatformPkg/Library/CompressLib/CompressLib.inf
+
+[LibraryClasses.Common.DXE_SMM_DRIVER]
+ SpiFlashCommonLib|$(RP_PKG)/Library/SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf
+
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLib/SmmTestPointCheckLib.inf
+ TestPointLib|MinPlatformPkg/Test/Library/TestPointLib/SmmTestPointLib.inf
+ MmServicesTableLib|MdePkg/Library/MmServicesTableLib/MmServicesTableLib.inf
+ Tcg2PhysicalPresenceLib|SecurityPkg/Library/SmmTcg2PhysicalPresenceLib/SmmTcg2PhysicalPresenceLib.inf
+
+[LibraryClasses.Common.SMM_CORE]
+ S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptLibNull.inf
+
+[LibraryClasses.Common]
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
+ PeiLib|MinPlatformPkg/Library/PeiLib/PeiLib.inf
+
+[Components.IA32]
+ UefiCpuPkg/SecCore/SecCore.inf
+
+ !include MinPlatformPkg/Include/Dsc/CorePeiInclude.dsc
+
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ #
+ # Beware of circular dependencies on PCD if you want to use another DebugLib instance.
+ #
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNull.inf # Include FSP DynamicEx PCD
+ NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateSilicon.inf # Include FvLateSilicon DynamicEx PCD
+ NULL|$(FSP_BIN_PKG)/Library/FspPcdListLibNull/FspPcdListLibNullFvLateOpenBoard.inf # Include FvLateBoard DynamicEx PCD
+ }
+ $(RP_PKG)/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf
+ $(RP_PKG)/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf
+ $(RP_PKG)/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf
+
+ $(RP_PKG)/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf
+
+ $(RP_PKG)/$(BOARD_NAME)/Platform/Pei/PlatformInfo/PlatformInfo.inf
+ $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf {
+ <LibraryClasses>
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+ BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitPreMemLib.inf
+ }
+ $(PLATFORM_PKG)/PlatformInit/ReportFv/ReportFvPei.inf
+
+ $(PLATFORM_PKG)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf{
+ <LibraryClasses>
+ SiliconWorkaroundLib|WhitleySiliconPkg/Library/SiliconWorkaroundLibNull/SiliconWorkaroundLibNull.inf
+ }
+ $(RP_PKG)/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf
+ $(PLATFORM_PKG)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf {
+ <LibraryClasses>
+ TestPointCheckLib|MinPlatformPkg/Test/Library/TestPointCheckLibNull/TestPointCheckLibNull.inf
+ BoardInitLib|$(PLATFORM_PKG)/PlatformInit/Library/BoardInitLibNull/BoardInitLibNull.inf
+ }
+
+ IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+!if ($(FSP_MODE) == 0)
+ IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+ $(RP_PKG)/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
+!endif
+
+ $(RP_PKG)/BiosInfo/BiosInfo.inf
+
+ WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationPei.inf
+
+ UefiCpuPkg/CpuMpPei/CpuMpPei.inf
+
+ UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf {
+ <LibraryClasses>
+ !if $(PERFORMANCE_ENABLE) == TRUE
+ TimerLib|UefiCpuPkg/Library/SecPeiDxeTimerLibUefiCpu/SecPeiDxeTimerLibUefiCpu.inf
+ !endif
+ }
+
+[Components.X64]
+ !include WhitleyOpenBoardPkg/Include/Dsc/CoreDxeInclude.dsc
+
+ $(RP_PKG)/Platform/Dxe/PlatformType/PlatformType.inf
+
+ MinPlatformPkg/Test/TestPointDumpApp/TestPointDumpApp.inf
+
+ MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
+ MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+ MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
+
+ MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+ UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
+
+ ShellPkg/Application/Shell/Shell.inf {
+ <LibraryClasses>
+ ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+ NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+ HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+
+ <PcdsFixedAtBuild>
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+ gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+ gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+ }
+
+ $(RP_PKG)/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf
+ UefiCpuPkg/CpuDxe/CpuDxe.inf
+ UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+
+ $(RP_PKG)/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf
+ IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+
+ $(RP_PKG)/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
+
+ $(RP_PKG)/Features/AcpiVtd/AcpiVtd.inf
+
+ $(PLATFORM_PKG)/Acpi/AcpiSmm/AcpiSmm.inf {
+ <LibraryClasses>
+ BoardAcpiEnableLib|$(RP_PKG)/Library/BoardAcpiLib/SmmBoardAcpiEnableLib.inf
+ }
+
+ $(PLATFORM_PKG)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf {
+ <LibraryClasses>
+ BoardInitLib|$(RP_PKG)/Library/BoardInitLib/BoardInitDxeLib.inf
+ }
+ $(RP_PKG)/Platform/Dxe/S3NvramSave/S3NvramSave.inf {
+!if ($(FSP_MODE) == 0)
+ <BuildOptions>
+ *_*_*_CC_FLAGS = -D FSP_API_MODE
+!endif
+ }
+
+ $(PLATFORM_PKG)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+
+ $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf
+ $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf
+
+ MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
+ BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
+
+ MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf
+
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+
+ #
+ # SiliconPkg code for Platform Integration are defined here
+ #
+!if $(CPUTARGET) == "CPX"
+ DEFINE CPU_CPX_SUPPORT = TRUE
+!else
+ DEFINE CPU_CPX_SUPPORT = FALSE
+!endif
+[PcdsFixedAtBuild]
+!if ($(CPU_SKX_ONLY_SUPPORT) == TRUE)
+ gSiPkgTokenSpaceGuid.PcdPostedCsrAccessSupported |FALSE
+!endif
+[LibraryClasses.common.DXE_DRIVER, LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION]
+ ResetSystemLib|MdeModulePkg/Library/DxeResetSystemLib/DxeResetSystemLib.inf
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+ ResetSystemLib|MdeModulePkg/Library/RuntimeResetSystemLib/RuntimeResetSystemLib.inf
+
+
+###################################################################################################
+#
+# BuildOptions Section - Define the module specific tool chain flags that should be used as
+# the default flags for a module. These flags are appended to any
+# standard flags that are defined by the build process. They can be
+# applied for any modules or only those modules with the specific
+# module style (EDK or EDKII) specified in [Components] section.
+#
+###################################################################################################
+[BuildOptions.Common.EDKII]
+# Append build options for EDK and EDKII drivers (= is Append, == is Replace)
+!if $(CRB_FLAG_ENABLE) == TRUE
+ DEFINE CRB_EDKII_BUILD_OPTIONS = -D CRB_FLAG
+!else
+ DEFINE CRB_EDKII_BUILD_OPTIONS =
+!endif
+
+!if $(DEBUG_FLAGS_ENABLE) == TRUE
+ DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D DEBUG_CODE_BLOCK=1 -D PLATFORM_VARIABLE_ATTRIBUTES=0x3
+!else
+ DEFINE EDKII_DEBUG_BUILD_OPTIONS = -D SILENT_MODE -D PLATFORM_VARIABLE_ATTRIBUTES=0x3
+!endif
+
+!if $(SPARING_SCRATCHPAD_ENABLE) == TRUE
+ DEFINE SPARING_SCRATCHPAD_OPTION = -D SPARING_SCRATCHPAD_SUPPORT
+!else
+ DEFINE SPARING_SCRATCHPAD_OPTIONS =
+!endif
+
+!if $(SCRATCHPAD_DEBUG) == TRUE
+ DEFINE SCRATCHPAD_DEBUG_OPTION = -D SCRATCHPAD_DEBUG
+!else
+ DEFINE SCRATCHPAD_DEBUG_OPTION =
+!endif
+
+!if $(PCH_SERVER_BIOS_ENABLE) == TRUE
+ DEFINE PCH_BUILD_OPTION = -DPCH_SERVER_BIOS_FLAG=1
+!else
+ DEFINE PCH_BUILD_OPTION =
+!endif
+
+!if $(SERVER_BIOS_ENABLE) == TRUE
+ DEFINE SERVER_BUILD_OPTION = -DSERVER_BIOS_FLAG=1
+!else
+ DEFINE SERVER_BUILD_OPTION =
+!endif
+
+DEFINE SC_PATH = -D SC_PATH="Pch/SouthClusterLbg"
+
+DEFINE ME_PATH = -D ME_PATH="Me/MeSps.4"
+
+DEFINE IE_PATH = -D IE_PATH="Ie/v1"
+
+DEFINE NVDIMM_OPTIONS =
+
+!if $(CPUTARGET) == "ICX"
+ DEFINE CPU_TYPE_OPTIONS = -D ICX_HOST -D A0_HOST -D B0_HOST
+!elseif $(CPUTARGET) == "CPX"
+ DEFINE CPU_TYPE_OPTIONS = -D SKX_HOST -D CLX_HOST -D CPX_HOST -D A0_HOST -D B0_HOST
+!endif
+
+DEFINE MAX_SOCKET_CORE_THREAD_OPTIONS = -D MAX_SOCKET=$(MAX_SOCKET) -D MAX_CORE=$(MAX_CORE) -D MAX_THREAD=$(MAX_THREAD)
+
+DEFINE MRC_OPTIONS = -D LRDIMM_SUPPORT -D DDRT_SUPPORT
+
+!if $(CPU_SKX_ONLY_SUPPORT) == FALSE
+ DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=4 -D MAX_MC_CH=2
+!else
+ DEFINE MAX_IMC_CH_OPTIONS = -D MAX_IMC=2 -D MAX_MC_CH=3
+!endif
+
+DEFINE MAX_SAD_RULE_OPTION = -D MAX_SAD_RULES=24 -D MAX_DRAM_CLUSTERS=1
+
+DEFINE LT_BUILD_OPTIONS = -D LT_FLAG
+
+DEFINE FSP_BUILD_OPTIONS = -D FSP_DISPATCH_MODE_ENABLE=1
+
+#
+# MAX_KTI_PORTS needs to be updated based on the silicon type
+#
+!if $(CPUTARGET) == "CPX"
+ DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=6
+!else
+ DEFINE KTI_OPTIONS = -D MAX_KTI_PORTS=3
+!endif
+
+DEFINE IIO_STACK_OPTIONS = -D MAX_IIO_STACK=6 -D MAX_LOGIC_IIO_STACK=8
+
+DEFINE PCH_BIOS_BUILD_OPTIONS = $(PCH_BUILD_OPTION) $(SC_PATH) $(SERVER_BUILD_OPTION)
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(CRB_EDKII_BUILD_OPTIONS) $(EDKII_DEBUG_BUILD_OPTIONS) $(PCH_BIOS_BUILD_OPTIONS) $(PCH_PKG_OPTIONS) $(MAX_SOCKET_CORE_THREAD_OPTIONS) $(MAX_IMC_CH_OPTIONS) $(MAX_SAD_RULE_OPTION) $(KTI_OPTIONS) $(IIO_STACK_OPTIONS) $(LT_BUILD_OPTIONS) $(SECURITY_OPTIONS) $(SPARING_SCRATCHPAD_OPTION) $(SCRATCHPAD_DEBUG_OPTION) $(NVDIMM_OPTIONS) -D EFI_PCI_IOV_SUPPORT -D WHEA_SUPPORT $(CPU_TYPE_OPTIONS) -D MMCFG_BASE_ADDRESS=0x80000000 -D DISABLE_NEW_DEPRECATED_INTERFACES $(MRC_OPTIONS) $(FSP_BUILD_OPTIONS)
+
+DEFINE IE_OPTIONS = $(IE_PATH) -DIE_SUPPORT=0
+
+!if $(LINUX_GCC_BUILD) == TRUE
+ DEFINE EDK2_LINUX_BUILD_OPTIONS = -D EDK2_CTE_BUILD
+!else
+ DEFINE EDK2_LINUX_BUILD_OPTIONS =
+!endif
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(EDK2_LINUX_BUILD_OPTIONS) $(IE_OPTIONS)
+
+DEFINE ME_OPTIONS = -DSPS_VERSION=4 $(ME_PATH)
+
+DEFINE ASPEED_ENABLE_BUILD_OPTIONS = -D ASPEED_ENABLE -D ESPI_ENABLE
+
+DEFINE EDKII_DSC_FEATURE_BUILD_OPTIONS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS) $(ME_OPTIONS) $(ASPEED_ENABLE_BUILD_OPTIONS)
+
+ MSFT:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS) /wd4819
+ GCC:*_*_*_CC_FLAGS= $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_VFRPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_APP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_PP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_ASLPP_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+ *_*_*_ASLCC_FLAGS = $(EDKII_DSC_FEATURE_BUILD_OPTIONS)
+
+
+#
+# Enable source level debugging for RELEASE build
+#
+!if $(TARGET) == "RELEASE"
+ DEFINE EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS =
+ DEFINE EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS =
+ DEFINE EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS =
+
+ MSFT:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS) /Zi
+ MSFT:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS) /Z7
+ MSFT:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS) /DEBUG
+ GCC:*_*_*_ASM_FLAGS = $(EDKII_RELEASE_SRCDBG_ASM_BUILD_OPTIONS)
+ GCC:*_*_*_CC_FLAGS = $(EDKII_RELEASE_SRCDBG_CC_BUILD_OPTIONS)
+ GCC:*_*_*_DLINK_FLAGS = $(EDKII_RELEASE_SRCDBG_DLINK_BUILD_OPTIONS)
+!endif
+
+#
+# Override ASL Compiler parameters in tools_def.template.
+#
+ *_*_*_ASL_FLAGS == -vr -we -oi
+#
+# Override the VFR compile flags to speed the build time
+#
+
+*_*_*_VFR_FLAGS == -n
+
+#
+# add to the build options for DXE/SMM drivers to remove the log message:
+# !!!!!!!! InsertImageRecord - Section Alignment(0x20) is not 4K !!!!!!!!
+#
+[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER, BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_CORE]
+ MSFT:*_*_*_DLINK_FLAGS = /ALIGN:4096
+
+[BuildOptions]
+ GCC:*_GCC5_*_CC_FLAGS = -Wno-overflow -Wno-discarded-qualifiers -Wno-unused-variable -Wno-unused-but-set-variable -Wno-incompatible-pointer-types -mabi=ms
+ GCC:*_GCC5_IA32_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
+ GCC:*_GCC5_X64_DLINK_FLAGS = -z common-page-size=0x20 -z muldefs
+ MSFT:*_*_*_CC_FLAGS = /FAsc
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf
new file mode 100644
index 0000000000..deaac1bd7a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.fdf
@@ -0,0 +1,821 @@
+## @file
+# FDF file of platform with 64-bit DXE
+# This package provides platform specific modules and flash layout information.
+#
+# @copyright
+# Copyright 2006 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+DEFINE PLATFORM_PKG = MinPlatformPkg
+
+# 0x00000060 = (EFI_FIRMWARE_VOLUME_HEADER. HeaderLength + sizeof (EFI_FFS_FILE_HEADER))
+DEFINE FDF_FIRMWARE_HEADER_SIZE = 0x00000060
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv = 0x90 # FV Header plus FFS header
+
+DEFINE VPD_HEADER_SIZE = 0x00000090
+
+!if $(FSP_MODE) == 0
+ DEFINE FSP_BIN_DIR = Api
+!else
+ DEFINE FSP_BIN_DIR = Dispatch
+!endif
+
+#
+# Note: FlashNv PCD naming conventions are as follows:
+# Note: This should be 100% true of all PCD's in the gCpPlatFlashTokenSpaceGuid space, and for
+# Others should be examined with an effort to work toward this guideline.
+# PcdFlash*Base is an address, usually in the range of 0xf* of FD's, note change in FDF spec
+# PcdFlash*Size is a hex count of the length of the FD or FV
+# All Fv will have the form 'PcdFlashFv', and all Fd will have the form 'PcdFlashFd'
+#
+# Also all values will have a PCD assigned so that they can be used in the system, and
+# the FlashMap edit tool can be used to change the values here, without effecting the code.
+# This requires all code to only use the PCD tokens to recover the values.
+
+
+#
+# 16MiB Total FLASH Image (visible in memory mapped IO)
+#
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF000000
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize = 0x01000000
+
+################################################################################
+#
+# FD SECPEI
+#
+# Contains all the SEC and PEI modules
+#
+# Layout: (Low address to high address)
+#
+# FvBsp for board specific components
+# FvPostMemory for compressed post memory MinPlatform spec required components
+# FvFspS for compressed post memory silicon initialization components
+# FvPostMemorySilicon for silicon components
+# FvFspM for pre memory silicon initialization components
+# FvPreMemorySilicon for silicon components
+# FvFspT for temp RAM silicon initilization components
+# FvBspPreMemory for board specific components required to intialize memory
+# FvAdvancedPreMemory FV for advanced features components
+# FvPreMemory for components required by MinPlatform spec and to initialize memory
+# FvPreMemorySecurity FV for stage 6 required components
+# Contains reset vector
+#
+################################################################################
+
+[FD.SecPei]
+ BaseAddress = 0xFFCA0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase #The base address of the FLASH Device
+ Size = 0x00360000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize #The size in bytes of the FLASH Device
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x360
+
+ #
+ # These must add up to the FD Size.
+ # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
+ # At this time, the FSP FV must be aligned at the same address they were built to, 0xFFD00000
+ # This will be corrected in the future.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize = 0x00010000 # BaseAddress + PcdFlashFvBspSize + PcdFlashFvPostMemorySize must = 0xFFD00000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize = 0x00040000 # Size must match WhitleyFspPkg.fdf content
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize = 0x00221000 # Size must match WhitleyFspPkg.fdf content
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize = 0x00006000 # Size must match WhitleyFspPkg.fdf content
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize = 0x00009000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+ #
+ # Calculate Offsets Once (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each offset is the prior region's offset plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset = 0x00000000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+ #
+ # FV Layout (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+ FV = FvBsp
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+ FV = FvPostMemory
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+ FILE = $(FSP_BIN_PKG)/Fsp_Rebased_S.fd
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ FILE = $(FSP_BIN_PKG)/Fsp_Rebased_M.fd
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+ FILE = $(FSP_BIN_PKG)/Fsp_Rebased_T.fd
+
+ #
+ # Shared FV layout
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+ FV = FvBspPreMemory
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+ FV = FvPreMemory
+
+ #
+ # Calculate base addresses (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each base is the prior region's base plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdSecPeiBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspOffset
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemoryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvBspPreMemorySize
+
+ #
+ # Set duplicate PCD
+ # These should not need to be changed
+ #
+
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvMrcNormalSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvSecPeiSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize
+
+ #
+ # For API mode, wrappers have some duplicate PCD as well
+ #
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase
+ SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase
+
+################################################################################
+#
+# FD Main
+#
+# All DXE modules and other regions
+#
+# Layout: (Low address to high address)
+#
+# FvAdvanced for advanced feature components
+# Assorted advanced feature FV
+# FvSecurity for MinPlatform spec required components needed to boot securely
+# FvOsBoot for MinPlatform spec required components needed to boot OS
+# FvLateSilicon for silicon specific components
+# FvUefiBoot for MinPlatform spec required components needed to boot to UEFI shell
+#
+################################################################################
+[FD.Main]
+ BaseAddress = 0xFF2E0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase # The base address of the FLASH Device
+ Size = 0x009C0000 | gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize # The size in bytes of the FLASH Device
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x9C0
+
+ #
+ # These must add up to the FD Size.
+ # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
+ # These are out of flash layout order because FvAdvanced gets any remaining space
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize = 0x00040000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize = 0x00230000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize = 0x0004C000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize - gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+
+ #
+ # Calculate Offsets Once (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each offset is the prior region's offset plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset = 0x00000000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+
+ #
+ # FV Layout (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ #
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+ FV = FvAdvanced
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+ FV = FvSecurity
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+ FV = FvOsBoot
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize
+ FV = FvUefiBoot
+
+ #
+ # Calculate base addresses (Do not modify)
+ # This layout is specified by the EDK II Minimum Platform Archicture specification.
+ # Each base is the prior region's base plus the prior region's size.
+ #
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFdMainBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize
+
+################################################################################
+#
+# FD BINARY
+#
+# Contains the OPROM and other binary modules
+#
+# Layout: (Low address to high address)
+#
+# FvOpRom containing pre-built components
+# FvAcmRegion containing ACM related content
+# FV Header + Blank Space (1K)
+# Policy block (3K)
+# Blank space to align ACM on 64K boundary (60K)
+# ACM binary
+# FvMicrocode containing microcode update patches
+# Unformatted region for PCI Gen 3 Data
+# FvVpd containing PCD VPD data
+# FvWhea for WHEA data recording
+# FvNvStorageVariable for UEFI Variable storage
+# FvNvStorageEventLog for NV Store management
+# FvNvStorageFtwWorking for Fault Tolerant Write solution
+# FvNvStorageFtwSpare for Fault Tolerant Write solution
+#
+################################################################################
+[FD.Binary]
+ BaseAddress = 0xFF000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase
+ Size = 0x002E0000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinarySize
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x2E0
+
+ #
+ # These must add up to the FD Size.
+ # This makes it easy to adjust the various sizes without having to manually calculate the offsets.
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize = 0x00100000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize = 0x00050000
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize = 0x000D0000
+ SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize = 0x00010000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize = 0x00030000
+ #
+ # These four items are tightly coupled.
+ # The spare area size must be >= the first three areas.
+ #
+ # There isn't really a benefit to a larger spare area unless the FLASH device
+ # block size is larger than the size specified.
+ #
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize = 0x0003C000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize = 0x00002000
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize = 0x00002000
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+ #
+ # Calculate Offsets Once (You should not need to modify this section)
+ # Each offset is the prior region's offset plus the prior region's size.
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset = 0x00000000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+ SET gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+ SET gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset = gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset = gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+ #
+ # Set gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress dynamically
+ #
+ SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset + gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
+ SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize - gMinPlatformPkgTokenSpaceGuid.PcdMicrocodeOffsetInFv
+
+ #
+ # FV Layout (You should not need to modify this section)
+ #
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ FV = FvOprom
+
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+ FV = FvAcm
+
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset|gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+ FV = FvMicrocode
+
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdOffset|gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize
+ FV = FvVPD
+
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+ FV = FvWhea
+
+ #
+ # Do not modify.
+ # See comments in size discussion above. These four areas are tightly coupled and should be modified with utmost care.
+ #
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ !include WhitleyOpenBoardPkg/Include/Fdf/NvStorage512K.fdf
+ gPlatformModuleTokenSpaceGuid.PcdFlashFvNvStorageEventLogOffset|gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+ DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonNvStorageFtwWorking.fdf
+ gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ DATA = { 0xFF } # Hack to ensure build doesn't treat the next PCD as Base/Size to be written
+
+ #
+ # Calculate base addresses (You should not need to modify this section)
+ # Each base is the prior region's base plus the prior region's size.
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromOffset
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize + $(VPD_HEADER_SIZE)
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase = gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress + gPlatformModuleTokenSpaceGuid.PcdFlashFvVpdSize - $(VPD_HEADER_SIZE)
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvWheaSize
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvNvStorageEventLogSize
+ SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase = gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase + gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+
+ #
+ # ACM details
+ #
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicyBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x1000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvPeiPolicySize = 0x3000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionBase + 0x10000
+ SET gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmSize = 0x00040000
+
+ #
+ # Other duplicate PCD
+ #
+ SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase = gCpPlatFlashTokenSpaceGuid.PcdFlashFvBinaryBase + gCpPlatFlashTokenSpaceGuid.PcdFlashFvAcmRegionSize + gCpPlatFlashTokenSpaceGuid.PcdFlashFvOpromSize
+ SET gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize = gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize
+ SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeBase
+ SET gIntelSiliconPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize = gCpuUncoreTokenSpaceGuid.PcdFlashNvStorageMicrocodeSize
+################################################################################
+#
+# FD FPGA
+#
+# Contains the FPGA modules
+#
+################################################################################
+
+[FD.Fpga]
+ BaseAddress = 0xFD000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaBase #The base address of the FPGA Device ( 4G - 48M )
+ Size = 0x02000000 |gCpPlatFlashTokenSpaceGuid.PcdFlashFdFpgaSize #The size in bytes of the FPGA Device ( 32M )
+ ErasePolarity = 1
+ BlockSize = 0x1000
+ NumBlocks = 0x2000
+
+ 0x00000000|0x02000000
+ gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsBase | gCpPlatFlashTokenSpaceGuid.PcdFlashFvFpgaBbsSize
+ FV = FvFpga
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file. This section also defines order the components and modules are positioned
+# within the image. The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvSecurityPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 40ab290f-8494-41cf-b302-31b178b4ce0b
+
+ !include MinPlatformPkg/Include/Fdf/CoreSecurityPreMemoryInclude.fdf
+
+[FV.FvPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 6522280D-28F9-4131-ADC4-F40EBFA45864
+
+ INF UefiCpuPkg/SecCore/SecCore.inf
+ INF MdeModulePkg/Core/Pei/PeiMain.inf
+
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+ INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeRouter/ExReportStatusCodeRouterPei.inf
+ INF WhitleyOpenBoardPkg/Universal/PeiExStatusCodeHandler/ExStatusCodeHandlerPei.inf
+
+ INF UefiCpuPkg/CpuIoPei/CpuIoPei.inf
+
+ INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+
+ INF WhitleyOpenBoardPkg/BiosInfo/BiosInfo.inf
+
+ INF WhitleySiliconPkg/Pch/SouthClusterLbg/MultiPch/Pei/MultiPchPei.inf
+
+ FILE PEIM = ac4b7f1b-e057-47d3-b2b5-1137493c0f38 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ac4b7f1b-e057-47d3-b2b5-1137493c0f38DynamicSiLibrary.efi
+ SECTION UI = "DynamicSiLibraryPei"
+ }
+
+ INF WhitleyOpenBoardPkg/Features/Variable/PlatformVariable/Pei/PlatformVariableInitPei.inf
+
+ INF WhitleyOpenBoardPkg/Platform/Pei/EmulationPlatformInit/EmulationPlatformInit.inf
+
+ INF WhitleyOpenBoardPkg/$(BOARD_NAME)/Platform/Pei/PlatformInfo/PlatformInfo.inf
+
+ #
+ # UBA common and board specific components
+ #
+ !include WhitleyOpenBoardPkg/Uba/UbaPei.fdf
+
+ INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf
+
+ INF MinPlatformPkg/PlatformInit/ReportFv/ReportFvPei.inf
+
+ FILE PEIM = ca8efb69-d7dc-4e94-aad6-9fb373649161 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/ca8efb69-d7dc-4e94-aad6-9fb373649161SiliconPolicyInitPreAndPostMem.efi
+ SECTION UI = "SiliconPolicyInitPreAndPostMem"
+ }
+
+ INF MinPlatformPkg/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem.inf
+
+ !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePreMemory.fdf
+
+ INF WhitleyOpenBoardPkg/Universal/PeiInterposerToSvidMap/PeiInterposerToSvidMap.inf
+
+ INF UefiCpuPkg/CpuMpPei/CpuMpPei.inf
+
+ !if $(FSP_MODE) == 0
+ FILE PEIM = 8F7F3D20-9823-42DD-9FF7-53DAC93EF407 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/8F7F3D20-9823-42DD-9FF7-53DAC93EF407CsrPseudoOffsetInitPeim.efi
+ SECTION UI = "CsrPseudoOffsetInitPeim"
+ }
+ FILE PEIM = 2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352 {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/2C6CACC6-6C3C-4AA7-B2DE-384DAE2B0352RegAccessPeim.efi
+ SECTION UI = "RegAccessPeim"
+ }
+ FILE PEIM = C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67F {
+ SECTION PEI_DEPEX = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.depex
+ SECTION Align = 32 PE32 = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/C7D9BAF4-DC9D-4B22-B4E7-7500EAA7B67FSiliconDataInitPeim.efi
+ SECTION UI = "SiliconDataInitPeim"
+ }
+ INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf
+ INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf
+ INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+ INF WhitleyOpenBoardPkg/Platform/Pei/DummyPchSpi/DummyPchSpi.inf
+ !endif
+
+ FILE FV_IMAGE = 40ab290f-8494-41cf-b302-31b178b4ce0b {
+ SECTION FV_IMAGE = FvSecurityPreMemory
+ }
+
+[FV.FvAdvancedPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 09f25d44-b2ef-4225-8b2e-e0e094b51775
+
+ !include AdvancedFeaturePkg/Include/PreMemory.fdf
+
+[FV.FvBspPreMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = e6c65995-8c2d-4119-a52d-7dbf1acb45a1
+
+ FILE FV_IMAGE = 09f25d44-b2ef-4225-8b2e-e0e094b51775 {
+ SECTION FV_IMAGE = FvAdvancedPreMemory
+ }
+
+#
+# FvPostMemory includes common hardware, common core variable services, load and invoke DXE etc
+#
+[FV.FvPostMemoryUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA
+
+[FV.FvPostMemory]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 3298afc4-c484-47f1-a65a-5917a54b5e8c
+
+ FILE FV_IMAGE = B4705B4B-0BE6-4BDB-A83A-51CAD2345CEA {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvPostMemoryUncompressed
+ }
+ }
+
+#
+# FvBsp includes board specific components
+#
+[FV.FvBspUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = e4c65347-fd90-4143-8a41-113e1015fe07
+
+[FV.FvBsp]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 9e151cf3-ca90-444f-b33b-a9941cbc772f
+
+ FILE FV_IMAGE = e4c65347-fd90-4143-8a41-113e1015fe07 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvBspUncompressed
+ }
+ }
+
+[FV.FvUefiBootUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = C4D3B0E2-FB26-44f8-A05B-E95895FCB960
+
+ INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ INF MdeModulePkg/Bus/Pci/UhciDxe/UhciDxe.inf
+ INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+
+ INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
+
+ INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ INF MdeModulePkg/Universal/PlatformDriOverrideDxe/PlatformDriOverrideDxe.inf
+
+ INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+ INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+ INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+ INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+ INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+ INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ INF MdeModulePkg/Universal/SmbiosMeasurementDxe/SmbiosMeasurementDxe.inf
+ #ATA for IDE/AHCI/RAID support
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+ INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf
+
+ FILE DRIVER = 85299F8F-F2B9-4487-AF60-231434A5EFF6 {
+ SECTION PE32 = edk2-non-osi/Drivers/ASpeed/ASpeedGopBinPkg/X64/ASpeedAst2500Gop.efi
+ }
+
+
+[FV.FvUefiBoot]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = ab9fe87b-1e37-440c-91cc-9aea03ce7bec
+
+ FILE FV_IMAGE = C4D3B0E2-FB26-44f8-A05B-E95895FCB960 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvUefiBootUncompressed
+ }
+ }
+
+[FV.FvOsBootUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0
+
+ #
+ # DXE Phase modules
+ #
+ INF MdeModulePkg/Core/Dxe/DxeMain.inf
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+ INF MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+
+ FILE FV_IMAGE = B7C9F0CB-15D8-26FC-CA3F-C63947B12831 {
+ SECTION UI = "FvLateSilicon"
+ SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateSilicon.fv
+ }
+
+ INF MdeModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
+
+ !include WhitleyOpenBoardPkg/Include/Fdf/EnablePerformanceMonitoringInfrastructurePostMemory.fdf
+
+ #
+ # UBA DXE common and board specific components
+ #
+ !include WhitleyOpenBoardPkg/Uba/UbaDxeCommon.fdf
+ !include WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
+ INF WhitleyOpenBoardPkg/Platform/Dxe/PlatformType/PlatformType.inf
+ INF MinPlatformPkg/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf
+
+ !if ($(FSP_MODE) == 1)
+ INF WhitleyOpenBoardPkg/Platform/Dxe/S3NvramSave/S3NvramSave.inf
+ !else
+ INF MinPlatformPkg/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf
+ !endif
+
+ INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
+ INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ INF WhitleyOpenBoardPkg/Cpu/Dxe/PlatformCpuPolicy/PlatformCpuPolicy.inf
+ INF UefiCpuPkg/CpuDxe/CpuDxe.inf
+ INF UefiCpuPkg/CpuS3DataDxe/CpuS3DataDxe.inf
+
+ FILE FV_IMAGE = a0277d07-a725-4823-90f9-6cba00782111 {
+ SECTION UI = "FvLateOpenBoard"
+ SECTION FV_IMAGE = $(FSP_BIN_PKG)/UefiDrivers/$(FSP_BIN_DIR)/FvLateOpenBoard.fv
+ }
+
+ INF MdeModulePkg/Universal/Metronome/Metronome.inf
+ INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ INF PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
+ INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+ INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciHostBridge/PciHostBridge.inf
+ INF MinPlatformPkg/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf
+
+ INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+ INF RuleOverride = UI MdeModulePkg/Application/UiApp/UiApp.inf
+ INF MdeModulePkg/Application/BootManagerMenuApp/BootManagerMenuApp.inf
+ INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+ #TPM when TPM enable, SecurityStubDxe needs to be removed from this FV.
+ INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+
+ INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+
+ INF FatPkg/EnhancedFatDxe/Fat.inf
+
+ INF PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+
+ INF WhitleyOpenBoardPkg/Features/Pci/Dxe/PciPlatform/PciPlatform.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+ INF ShellPkg/Application/Shell/Shell.inf
+
+ INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+ INF MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
+ INF MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf
+
+ INF MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
+ INF MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
+
+ INF UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
+
+ INF MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
+ INF UefiCpuPkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
+
+ INF IntelSiliconPkg/Feature/Flash/SpiFvbService/SpiFvbServiceSmm.inf
+
+ INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmmRuntimeDxe.inf
+ INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableSmm.inf
+
+ INF MdeModulePkg/Universal/SmmCommunicationBufferDxe/SmmCommunicationBufferDxe.inf
+
+ INF MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
+
+ INF MdeModulePkg/Universal/Acpi/BootScriptExecutorDxe/BootScriptExecutorDxe.inf
+
+ # UEFI USB stack
+ INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
+
+ INF MdeModulePkg/Bus/Pci/PciSioSerialDxe/PciSioSerialDxe.inf
+ INF BoardModulePkg/LegacySioDxe/LegacySioDxe.inf
+ INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+
+ INF WhitleyOpenBoardPkg/Features/AcpiVtd/AcpiVtd.inf
+ INF MinPlatformPkg/Acpi/AcpiSmm/AcpiSmm.inf
+
+[FV.FvOsBoot]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = c7488640-5f51-4969-b63b-89fc369e1725
+
+ FILE FV_IMAGE = CDBB7B35-6833-4ed6-9AB2-57D2ACDDF6F0 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvOsBootUncompressed
+ }
+ }
+
+[FV.FvSecuritySilicon]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = AD262F8D-BDED-4668-A8D4-8BC73516652F
+
+ !include MinPlatformPkg/Include/Fdf/CoreSecurityLateInclude.fdf
+
+[FV.FvSecurityUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 03E25550-89A5-4ee6-AF60-DB0553D91FD2
+
+ FILE FV_IMAGE = 81F80AEA-91EB-4AD9-A563-7CEBAA167B25 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvSecuritySilicon
+ }
+ }
+
+[FV.FvSecurity]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 68134833-2ff6-4d22-973b-575d0eae8ffd
+
+ FILE FV_IMAGE = 03E25550-89A5-4ee6-AF60-DB0553D91FD2 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvSecurityUncompressed
+ }
+ }
+
+[FV.FvAdvancedUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 70aeaf57-4997-49ce-a4f7-122980745670
+
+ !include AdvancedFeaturePkg/Include/PostMemory.fdf
+
+[FV.FvAdvanced]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = f21ee7a1-53a9-453d-aee3-b6a5c25bada5
+
+ FILE FV_IMAGE = 70aeaf57-4997-49ce-a4f7-122980745670 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvAdvancedUncompressed
+ }
+ }
+
+#
+# FV for all Microcode Updates.
+#
+[FV.FvMicrocode]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ LOCK_STATUS = FALSE
+ FvNameGuid = D2C29BA7-3809-480F-9C3D-DE389C61425A
+
+!if $(CPUTARGET) == "CPX"
+ INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/CpxMicrocode/MicrocodeUpdates.inf
+!else
+ INF RuleOverride = MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/IcxMicrocode/MicrocodeUpdates.inf
+!endif
+
+
+[FV.FvVPD]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ LOCK_STATUS = FALSE
+ FvNameGuid = FFC29BA7-3809-480F-9C3D-DE389C61425A
+ FILE RAW = FF7DB236-F856-4924-90F8-CDF12FB875F3 {
+ $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/FV/8C3D856A-9BE6-468E-850A-24F7A8D38E08.bin
+ }
+
+#
+# Various Vendor UEFI Drivers (OROMs).
+#
+[FV.FvOpromUncompressed]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = B6EDE22C-DE30-45fa-BB09-CA202C1654B7
+
+[FV.FvOprom]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 983BCAB5-BF10-42ce-B85D-CB805DCB1EFD
+
+ FILE FV_IMAGE = B6EDE22C-DE30-45fa-BB09-CA202C1654B7 {
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+ SECTION FV_IMAGE = FvOpromUncompressed
+ }
+ }
+
+[FV.FvWhea]
+ BlockSize = 0x1000
+ NumBlocks = 0x30
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = d6a1cd70-4b33-4994-a6ea-375f2ccc5437
+
+#
+# FV For ACM Binary.
+#
+[FV.FvAcm]
+ BlockSize = 0x1000
+ NumBlocks = 0x50
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 11668261-8A8D-47ca-9893-052D24435E59
+
+[FV.FvFpga]
+ !include WhitleyOpenBoardPkg/Include/Fdf/CommonSpiFvHeaderInfo.fdf
+ FvNameGuid = 974650E7-6DFE-4998-A124-CEDEC5C9B47D
+
+################################################################################
+#
+# Rules are use with the [FV] section's module INF type to define
+# how an FFS file is created for a given INF file. The following Rule are the default
+# rules for the different module type. User can add the customized rules to define the
+# content of the FFS file.
+#
+################################################################################
+
+!include MinPlatformPkg/Include/Fdf/RuleInclude.fdf
+
+[Rule.Common.USER_DEFINED.ACPITABLE]
+ FILE FREEFORM = $(NAMED_GUID) {
+ RAW ACPI Optional |.acpi
+ RAW ASL Optional |.aml
+ }
+
+[Rule.Common.DXE_RUNTIME_DRIVER.DRIVER_ACPITABLE]
+ FILE DRIVER = $(NAMED_GUID) {
+ DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex
+ PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi
+ RAW ACPI Optional |.acpi
+ RAW ASL Optional |.aml
+ UI STRING="$(MODULE_NAME)" Optional
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
+ }
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py
new file mode 100644
index 0000000000..f50d786845
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_board.py
@@ -0,0 +1,127 @@
+# @ build_board.py
+# Extensions for building JunctioCity using build_bios.py
+#
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+"""
+This module serves as a sample implementation of the build extension
+scripts
+"""
+
+import os
+import sys
+
+def pre_build_ex(config, functions):
+ """Additional Pre BIOS build function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: nothing
+ """
+ print("pre_build_ex")
+ config["BUILD_DIR_PATH"] = os.path.join(config["WORKSPACE"],
+ 'Build',
+ config["PLATFORM_BOARD_PACKAGE"],
+ "{}_{}".format(
+ config["TARGET"],
+ config["TOOL_CHAIN_TAG"]))
+ # set BUILD_DIR path
+ config["BUILD_DIR"] = os.path.join('Build',
+ config["PLATFORM_BOARD_PACKAGE"],
+ "{}_{}".format(
+ config["TARGET"],
+ config["TOOL_CHAIN_TAG"]))
+ config["BUILD_X64"] = os.path.join(config["BUILD_DIR_PATH"], 'X64')
+ config["BUILD_IA32"] = os.path.join(config["BUILD_DIR_PATH"], 'IA32')
+
+ if not os.path.isdir(config["BUILD_DIR_PATH"]):
+ try:
+ os.makedirs(config["BUILD_DIR_PATH"])
+ except OSError:
+ print("Error while creating Build folder")
+ sys.exit(1)
+
+ #@todo: Replace this with PcdFspModeSelection
+ if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
+ config["EXT_BUILD_FLAGS"] += " -D FSP_MODE=0"
+ else:
+ config["EXT_BUILD_FLAGS"] += " -D FSP_MODE=1"
+
+ if config.get("API_MODE_FSP_WRAPPER_BUILD", "FALSE") == "TRUE":
+ raise ValueError("FSP API Mode is currently unsupported on Ice Lake Xeon Scalable")
+ return None
+
+def _merge_files(files, ofile):
+ with open(ofile, 'wb') as of:
+ for x in files:
+ if not os.path.exists(x):
+ return
+
+ with open(x, 'rb') as f:
+ of.write(f.read())
+
+def build_ex(config, functions):
+ """Additional BIOS build function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("build_ex")
+ fv_path = os.path.join(config["BUILD_DIR_PATH"], "FV")
+ binary_fd = os.path.join(fv_path, "BINARY.fd")
+ main_fd = os.path.join(fv_path, "MAIN.fd")
+ secpei_fd = os.path.join(fv_path, "SECPEI.fd")
+ board_fd = config["BOARD"].upper()
+ final_fd = os.path.join(fv_path, "{}.fd".format(board_fd))
+ _merge_files((binary_fd, main_fd, secpei_fd), final_fd)
+ return None
+
+
+def post_build_ex(config, functions):
+ """Additional Post BIOS build function
+
+ :param config: The environment variables to be used in the post
+ build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("post_build_ex")
+ fv_path = os.path.join(config["BUILD_DIR_PATH"], "FV")
+ board_fd = config["BOARD"].upper()
+ final_fd = os.path.join(fv_path, "{}.fd".format(board_fd))
+ final_ifwi = os.path.join(fv_path, "{}.bin".format(board_fd))
+
+ ifwi_ingredients_path = os.path.join(config["WORKSPACE_PLATFORM_BIN"], "Ifwi", config["BOARD"])
+ flash_descriptor = os.path.join(ifwi_ingredients_path, "FlashDescriptor.bin")
+ intel_me = os.path.join(ifwi_ingredients_path, "Me.bin")
+ _merge_files((flash_descriptor, intel_me, final_fd), final_ifwi)
+ if os.path.isfile(final_fd):
+ print("IFWI image can be found at {}".format(final_ifwi))
+ return None
+
+
+def clean_ex(config, functions):
+ """Additional clean function
+
+ :param config: The environment variables to be used in the build process
+ :type config: Dictionary
+ :param functions: A dictionary of function pointers
+ :type functions: Dictionary
+ :returns: config dictionary
+ :rtype: Dictionary
+ """
+ print("clean_ex")
+ return None
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg
new file mode 100644
index 0000000000..602987b922
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/JunctionCity/build_config.cfg
@@ -0,0 +1,37 @@
+# @ build_config.cfg
+# This is the JunctionCity board specific build settings
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+
+
+[CONFIG]
+WORKSPACE_PLATFORM_BIN = edk2-non-osi/Platform/Intel/WhitleyOpenBoardBinPkg
+EDK_SETUP_OPTION =
+openssl_path =
+PLATFORM_BOARD_PACKAGE = WhitleyOpenBoardPkg
+PROJECT = WhitleyOpenBoardPkg/JunctionCity
+BOARD = JunctionCity
+FLASH_MAP_FDF = WhitleyOpenBoardPkg/FspFlashOffsets.fdf
+PROJECT_DSC = WhitleyOpenBoardPkg/JunctionCity/PlatformPkg.dsc
+BOARD_PKG_PCD_DSC = WhitleyOpenBoardPkg/PlatformPkgConfig.dsc
+ADDITIONAL_SCRIPTS = WhitleyOpenBoardPkg/JunctionCity/build_board.py
+PrepRELEASE = DEBUG
+SILENT_MODE = FALSE
+EXT_CONFIG_CLEAR =
+CapsuleBuild = FALSE
+EXT_BUILD_FLAGS = -D CPUTARGET=ICX -D RP_PKG=WhitleyOpenBoardPkg -D SILICON_PKG=WhitleySiliconPkg -D PCD_DYNAMIC_AS_DYNAMICEX -D MAX_CORE=64 -D MAX_THREAD=2 -D PLATFORM_PKG=MinPlatformPkg
+MAX_SOCKET = 4
+CAPSULE_BUILD = 0
+TARGET = DEBUG
+TARGET_SHORT = D
+PERFORMANCE_BUILD = FALSE
+FSP_WRAPPER_BUILD = TRUE
+FSP_BIN_PKG = WhitleyFspBinPkg
+FSP_PKG_NAME = WhitleyFspPkg
+FSP_BINARY_BUILD = FALSE
+FSP_TEST_RELEASE = FALSE
+SECURE_BOOT_ENABLE = FALSE
+BIOS_INFO_GUID = 4A4CA1C6-871C-45BB-8801-6910A7AA5807
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
index 363d4e4059..d3d8bc84e7 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
+++ b/Platform/Intel/WhitleyOpenBoardPkg/PlatformPkg.dec
@@ -136,6 +136,7 @@


gEfiPlatformTypeWilsonCitySMTProtocolGuid = { 0xEE55562D, 0x4001, 0xFC27, { 0xDF, 0x16, 0x7B, 0x90, 0xEB, 0xE1, 0xAB, 0x04 } }

gEfiPlatformTypeCooperCityRPProtocolGuid = { 0x45c302e1, 0x4b86, 0x89be, { 0xab, 0x0f, 0x5e, 0xb5, 0x57, 0xdf, 0xe8, 0xd8 } }

+ gEfiPlatformTypeJunctionCityProtocolGuid = { 0xB1C2B1C9, 0xB606, 0x4B62, { 0x9D, 0x78, 0xCB, 0xD6, 0x0F, 0xF9, 0x0D, 0x0C } }



#

# UBA_END

diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c
index 212103f483..6cfa43a59d 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.c
@@ -3,6 +3,7 @@


@copyright

Copyright 2014 - 2021 Intel Corporation.

+ Copyright (c) 2021, American Megatrends International LLC. <BR>



SPDX-License-Identifier: BSD-2-Clause-Patent

**/

@@ -88,6 +89,16 @@ BoardInitDxeDriverEntry (
ASSERT_EFI_ERROR (Status);

break;



+ case TypeJunctionCity:

+ Status = gBS->InstallProtocolInterface (

+ &Handle,

+ &gEfiPlatformTypeJunctionCityProtocolGuid,

+ EFI_NATIVE_INTERFACE,

+ NULL

+ );

+ ASSERT_EFI_ERROR (Status);

+ break;

+

default:

// CAN'T GO TO HERE.

ASSERT (FALSE);

diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf
index 206d95658a..8948ab1f0a 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/BoardInit/Dxe/BoardInitDxe.inf
@@ -3,6 +3,7 @@
#

# @copyright

# Copyright 2014 - 2021 Intel Corporation.

+# Copyright (c) 2021, American Megatrends International LLC. <BR>

#

# SPDX-License-Identifier: BSD-2-Clause-Patent

##

@@ -62,6 +63,7 @@
gEfiPlatformTypeIsoscelesPeakProtocolGuid #PRODUCER

gEfiPlatformTypeWilsonCitySMTProtocolGuid #PRODUCER

gEfiPlatformTypeCooperCityRPProtocolGuid #PRODUCER

+ gEfiPlatformTypeJunctionCityProtocolGuid #PRODUCER



[FixedPcd]

gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount

diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
index fcf147885f..e20c576028 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaDxeRpBoards.fdf
@@ -3,6 +3,7 @@
#

# @copyright

# Copyright 2012 - 2021 Intel Corporation.

+# Copyright (c) 2021, American Megatrends International LLC. <BR>

#

# SPDX-License-Identifier: BSD-2-Clause-Patent

##

@@ -27,3 +28,10 @@ INF $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdate
INF $(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf

INF $(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf

INF $(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf

+

+#

+# Platform TypeJunctioCity

+#

+INF $(RP_PKG)/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf

+INF $(RP_PKG)/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf

+INF $(RP_PKG)/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf

diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c
new file mode 100644
index 0000000000..b6b81f188c
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.c
@@ -0,0 +1,100 @@
+/** @file
+ IIO Config Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "IioCfgUpdateDxe.h"
+
+EFI_STATUS
+UpdateJunctionCityIioConfig (
+ IN IIO_GLOBALS *IioGlobalData
+ )
+{
+ return EFI_SUCCESS;
+}
+
+PLATFORM_IIO_CONFIG_UPDATE_TABLE TypeJunctionCityIioConfigTable =
+{
+ PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE,
+ PLATFORM_IIO_CONFIG_UPDATE_VERSION,
+
+ IioBifurcationTable,
+ sizeof(IioBifurcationTable),
+ UpdateJunctionCityIioConfig,
+ IioSlotTable,
+ sizeof(IioSlotTable)
+
+};
+
+/**
+ The Driver Entry Point.
+
+ The function is the driver Entry point.
+
+ @param ImageHandle A handle for the image that is initializing this driver
+ @param SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS: Driver initialized successfully
+ @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded
+ @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+IioCfgUpdateEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status;
+ UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;
+
+ DEBUG((DEBUG_INFO, "UBA:IioCfgUpdate-TypeJunctionCity\n"));
+ Status = gBS->LocateProtocol (
+ &gUbaConfigDatabaseProtocolGuid,
+ NULL,
+ &UbaConfigProtocol
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid,
+ &TypeJunctionCityIioConfigTable,
+ sizeof(TypeJunctionCityIioConfigTable)
+ );
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid_1,
+ &TypeJunctionCityIioConfigTable,
+ sizeof(TypeJunctionCityIioConfigTable)
+ );
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid_2,
+ &TypeJunctionCityIioConfigTable,
+ sizeof(TypeJunctionCityIioConfigTable)
+ );
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformIioConfigDataDxeGuid_3,
+ &TypeJunctionCityIioConfigTable,
+ sizeof(TypeJunctionCityIioConfigTable)
+ );
+
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h
new file mode 100644
index 0000000000..53d3a49f9a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.h
@@ -0,0 +1,119 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _IIOCFG_UPDATE_DXE_H_
+#define _IIOCFG_UPDATE_DXE_H_
+
+#include <Base.h>
+#include <Uefi.h>
+#include <Protocol/UbaCfgDb.h>
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciLib.h>
+#include <Library/UbaIioConfigLib.h>
+#include <IioPlatformData.h>
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 =0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Mcp0,
+ Iio_Mcp1,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ VPP_PORT_0 = 0,
+ VPP_PORT_1,
+ VPP_PORT_2,
+ VPP_PORT_3
+} VPP_PORT;
+
+#define ENABLE 1
+#define DISABLE 0
+#define NO_SLT_IMP 0xFF
+#define SLT_IMP 1
+#define HIDE 1
+#define NOT_HIDE 0
+#define VPP_PORT_0 0
+#define VPP_PORT_1 1
+#define VPP_PORT_MAX 0xFF
+#define VPP_ADDR_MAX 0xFF
+#define PWR_VAL_MAX 0xFF
+#define PWR_SCL_MAX 0xFF
+
+static IIO_BIFURCATION_DATA_ENTRY IioBifurcationTable[] =
+{
+ // Neon City IIO bifurcation table (Based on Neon City Block Diagram rev 0.6)
+ { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_xxx8x4x4 },
+ { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket0, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket0, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxx8xxx8 },
+ { Iio_Socket1, Iio_Mcp0, IIO_BIFURCATE_xxxxxx16 },
+ { Iio_Socket1, Iio_Mcp1, IIO_BIFURCATE_xxxxxx16 },
+};
+
+static IIO_SLOT_CONFIG_DATA_ENTRY IioSlotTable[] = {
+ // Port | Slot | Inter | Power Limit | Power Limit | Hot | Vpp | Vpp | PcieSSD | PcieSSD | PcieSSD | Hidden
+ // Index | | lock | Scale | Value | Plug | Port | Addr | Cap | VppPort | VppAddr |
+ { PORT_1A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x4C , HIDE },//Oculink
+ { PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x4C , HIDE },//Oculink
+ { PORT_1C_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ { PORT_2A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ // Slot 2 supports HP: PCA9555 (CPU0) Addres 0x40, SCH (Rev 0.604) P 118 (MRL in J65)
+ { PORT_3A_INDEX, 2 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 , NOT_HIDE },
+ { PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 , HIDE },
+ { PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 , HIDE },
+ { PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_0_INDEX , 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ // Slot 4 supports HP: PCA9554 (CPU1) Address 0x40, SCH (Rev 0.604) P 121 (MRL in J287)
+ { SOCKET_1_INDEX +
+ PORT_1A_INDEX, 4 , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x40 , ENABLE , VPP_PORT_0 , 0x40 , NOT_HIDE },
+ { SOCKET_1_INDEX +
+ PORT_1B_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x40 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_1C_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x42 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_1D_INDEX, NO_SLT_IMP , ENABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x42 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2A_INDEX, 8 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_1 , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x44 , NOT_HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x44 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_0 , 0x46 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , ENABLE , VPP_PORT_1 , 0x46 , HIDE },
+ { SOCKET_1_INDEX +
+ PORT_3A_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ { SOCKET_1_INDEX +
+ PORT_3C_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE },
+ // Note: On Neon City, Slot 3 is assigned to PCH's PCIE port
+};
+
+#endif //_IIOCFG_UPDATE_DXE_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
new file mode 100644
index 0000000000..13d88a3748
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf
@@ -0,0 +1,48 @@
+## @file
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = IioCfgUpdateDxeJunctionCity
+ FILE_GUID = 9E1DECF5-C606-44A2-B99D-5BF4222A174C
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = IioCfgUpdateEntry
+
+[sources]
+ IioCfgUpdateDxe.c
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ UefiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[Guids]
+
+[FixedPcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
+[Protocols]
+ gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+ gEfiPlatformTypeJunctionCityProtocolGuid
\ No newline at end of file
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c
new file mode 100644
index 0000000000..37e9c6a9e6
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.c
@@ -0,0 +1,116 @@
+/** @file
+ Slot Data Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "SlotDataUpdateDxe.h"
+
+UINT8
+GetTypeJunctionCityIOU0Setting (
+ UINT8 IOU0Data
+)
+{
+ //
+ // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled.
+ //
+ IOU0Data = IIO_BIFURCATE_xxx8xxx8;
+ return IOU0Data;
+}
+
+UINT8
+GetTypeJunctionCityIOU2Setting (
+ UINT8 SkuPersonalityType,
+ UINT8 IOU2Data
+)
+{
+ return IOU2Data;
+}
+
+static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeJunctionCityBroadwayTable[] = {
+ {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 },
+ {Iio_Socket1, Iio_Iou1, Bw5_Addr_2},
+ {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 },
+};
+
+
+PLATFORM_SLOT_UPDATE_TABLE TypeJunctionCitySlotTable =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeJunctionCityBroadwayTable,
+ GetTypeJunctionCityIOU0Setting,
+ 0
+};
+
+PLATFORM_SLOT_UPDATE_TABLE2 TypeJunctionCitySlotTable2 =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeJunctionCityBroadwayTable,
+ GetTypeJunctionCityIOU0Setting,
+ 0,
+ GetTypeJunctionCityIOU2Setting
+};
+
+/**
+ The Driver Entry Point.
+
+ The function is the driver Entry point.
+
+ @param ImageHandle A handle for the image that is initializing this driver
+ @param SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS: Driver initialized successfully
+ @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded
+ @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+SlotDataUpdateEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status;
+ UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;
+
+ DEBUG((DEBUG_INFO, "UBA:SlotDataUpdate-TypeJunctionCity\n"));
+ Status = gBS->LocateProtocol (
+ &gUbaConfigDatabaseProtocolGuid,
+ NULL,
+ &UbaConfigProtocol
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformSlotDataDxeGuid,
+ &TypeJunctionCitySlotTable,
+ sizeof(TypeJunctionCitySlotTable)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gPlatformSlotDataDxeGuid,
+ &TypeJunctionCitySlotTable2,
+ sizeof(TypeJunctionCitySlotTable2)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h
new file mode 100644
index 0000000000..e59e70c9ee
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.h
@@ -0,0 +1,58 @@
+/** @file
+
+ @copyright
+ Copyright 2016 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SLOT_DATA_UPDATE_DXE_H_
+#define _SLOT_DATA_UPDATE_DXE_H_
+
+
+#include <Base.h>
+#include <Uefi.h>
+
+#include <Protocol/UbaCfgDb.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/PciLib.h>
+
+#include <Library/UbaSlotUpdateLib.h>
+#include <IioPlatformData.h>
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 =0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Mcp0,
+ Iio_Mcp1,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ Bw5_Addr_0 = 0,
+ Bw5_Addr_1,
+ Bw5_Addr_2,
+ Bw5_Addr_3,
+ Bw5_Addr_Max
+} BW5_ADDRESS;
+
+#endif //_SLOT_DATA_UPDATE_DXE_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
new file mode 100644
index 0000000000..8f107b9c42
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf
@@ -0,0 +1,48 @@
+## @file
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = SlotDataUpdateDxeJunctionCity
+ FILE_GUID = 98750E94-CCCB-45AA-9259-3CF7F8C43C33
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = SlotDataUpdateEntry
+
+[sources]
+ SlotDataUpdateDxe.c
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ UefiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[Guids]
+
+[FixedPcd]
+ gEfiCpRcPkgTokenSpaceGuid.PcdMaxCpuSocketCount
+
+[Protocols]
+ gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+ gEfiPlatformTypeJunctionCityProtocolGuid
\ No newline at end of file
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c
new file mode 100644
index 0000000000..f4d50beec8
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.c
@@ -0,0 +1,128 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "UsbOcUpdateDxe.h"
+
+#include <Library/UbaUsbOcUpdateLib.h>
+#include <PchLimits.h>
+#include <ConfigBlock/UsbConfig.h>
+#include <ConfigBlock/Usb2PhyConfig.h>
+
+USB_OVERCURRENT_PIN TypeJunctionCityUsb20OverCurrentMappings[PCH_MAX_USB2_PORTS] = {
+ UsbOverCurrentPinSkip, //Port00: BMC
+ UsbOverCurrentPinSkip, //Port01: BMC
+ UsbOverCurrentPin0, //Port02: Rear Panel
+ UsbOverCurrentPin1, //Port03: Rear Panel
+ UsbOverCurrentPin1, //Port04: Rear Panel
+ UsbOverCurrentPinSkip, //Port05: NC
+ UsbOverCurrentPinSkip, //Port06: NC
+ UsbOverCurrentPin4, //Port07: Type A internal
+ UsbOverCurrentPinSkip, //Port08: NC
+ UsbOverCurrentPinSkip, //Port09: NC
+ UsbOverCurrentPin6, //Port10: Front Panel
+ UsbOverCurrentPinSkip, //Port11: NC
+ UsbOverCurrentPin6, //Port12: Front Panel
+ UsbOverCurrentPinSkip, //Port13: NC
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB_OVERCURRENT_PIN TypeJunctionCityUsb30OverCurrentMappings[PCH_MAX_USB3_PORTS] = {
+ UsbOverCurrentPin6, //Port01: Front Panel
+ UsbOverCurrentPin6, //Port02: Front Panel
+ UsbOverCurrentPin0, //Port03: Rear Panel
+ UsbOverCurrentPin1, //Port04: Rear Panel
+ UsbOverCurrentPin1, //Port05: Rear Panel
+ UsbOverCurrentPinSkip, //Port06: NC
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB2_PHY_PARAMETERS TypeJunctionCityUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS] = {
+ {3, 0, 3, 1}, // PP0
+ {5, 0, 3, 1}, // PP1
+ {3, 0, 3, 1}, // PP2
+ {0, 5, 1, 1}, // PP3
+ {3, 0, 3, 1}, // PP4
+ {3, 0, 3, 1}, // PP5
+ {3, 0, 3, 1}, // PP6
+ {3, 0, 3, 1}, // PP7
+ {2, 2, 1, 0}, // PP8
+ {6, 0, 2, 1}, // PP9
+ {2, 2, 1, 0}, // PP10
+ {6, 0, 2, 1}, // PP11
+ {0, 5, 1, 1}, // PP12
+ {7, 0, 2, 1}, // PP13
+ };
+
+EFI_STATUS
+TypeJunctionCityPlatformUsbOcUpdateCallback (
+ IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings,
+ IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings,
+ IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams
+)
+{
+ *Usb20OverCurrentMappings = &TypeJunctionCityUsb20OverCurrentMappings[0];
+ *Usb30OverCurrentMappings = &TypeJunctionCityUsb30OverCurrentMappings[0];
+
+ *Usb20AfeParams = TypeJunctionCityUsb20AfeParams;
+ return EFI_SUCCESS;
+}
+
+PLATFORM_USBOC_UPDATE_TABLE TypeJunctionCityUsbOcUpdate =
+{
+ PLATFORM_USBOC_UPDATE_SIGNATURE,
+ PLATFORM_USBOC_UPDATE_VERSION,
+ TypeJunctionCityPlatformUsbOcUpdateCallback
+};
+
+/**
+ The Driver Entry Point.
+
+ The function is the driver Entry point.
+
+ @param ImageHandle A handle for the image that is initializing this driver
+ @param SystemTable A pointer to the EFI system table
+
+ @retval EFI_SUCCESS: Driver initialized successfully
+ @retval EFI_LOAD_ERROR: Failed to Initialize or has been loaded
+ @retval EFI_OUT_OF_RESOURCES Could not allocate needed resources
+
+**/
+EFI_STATUS
+EFIAPI
+UsbOcUpdateEntry (
+ IN EFI_HANDLE ImageHandle,
+ IN EFI_SYSTEM_TABLE *SystemTable
+)
+{
+ EFI_STATUS Status;
+ UBA_CONFIG_DATABASE_PROTOCOL *UbaConfigProtocol = NULL;
+
+ DEBUG((EFI_D_INFO, "UBA:UsbOcUpdate-TypeJunctionCity\n"));
+ Status = gBS->LocateProtocol (
+ &gUbaConfigDatabaseProtocolGuid,
+ NULL,
+ &UbaConfigProtocol
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigProtocol->AddData (
+ UbaConfigProtocol,
+ &gDxePlatformUbaOcConfigDataGuid,
+ &TypeJunctionCityUsbOcUpdate,
+ sizeof(TypeJunctionCityUsbOcUpdate)
+ );
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h
new file mode 100644
index 0000000000..2ba90c7598
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.h
@@ -0,0 +1,27 @@
+/** @file
+
+ @copyright
+ Copyright 2015 - 2021 Intel Corporation. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _USBOC_UPDATE_DXE_H_
+#define _USBOC_UPDATE_DXE_H_
+
+#include <Base.h>
+#include <Uefi.h>
+
+#include <Protocol/UbaCfgDb.h>
+
+#include <Library/UefiDriverEntryPoint.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+
+
+
+#endif //_USBOC_UPDATE_DXE_H_
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
new file mode 100644
index 0000000000..0f8e953e2b
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf
@@ -0,0 +1,45 @@
+## @file
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation. <BR>
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = UsbOcUpdateDxeJunctionCity
+ FILE_GUID = 5149EA77-8FCC-41B4-A8D0-CE652E817FD0
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = UsbOcUpdateEntry
+
+[sources]
+ UsbOcUpdateDxe.c
+ UsbOcUpdateDxe.h
+
+[LibraryClasses]
+ BaseLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ DebugLib
+ UefiBootServicesTableLib
+ UefiDriverEntryPoint
+ UefiRuntimeServicesTableLib
+ UefiLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+
+[Guids]
+
+[Protocols]
+ gUbaConfigDatabaseProtocolGuid
+
+[Depex]
+ gEfiPlatformTypeJunctionCityProtocolGuid
\ No newline at end of file
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/AcpiTablePcds.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/AcpiTablePcds.c
new file mode 100644
index 0000000000..25bbf30dab
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/AcpiTablePcds.c
@@ -0,0 +1,54 @@
+/** @file
+ ACPI table pcds update.
+
+ @copyright
+ Copyright 2015 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/PcdLib.h>
+#include <Library/HobLib.h>
+#include <Guid/PlatformInfo.h>
+#include <UncoreCommonIncludes.h>
+#include <Cpu/CpuIds.h>
+
+EFI_STATUS
+TypeJunctionCityPlatformUpdateAcpiTablePcds (
+ VOID
+ )
+{
+ CHAR8 AcpiName10nm[] = "EPRP10NM"; // USED for identify ACPI table for 10nm in systmeboard dxe driver
+ CHAR8 OemTableIdXhci[] = "xh_nccrb";
+
+ UINTN Size;
+ EFI_STATUS Status;
+
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+
+ DEBUG ((EFI_D_INFO, "Uba Callback: PlatformUpdateAcpiTablePcds entered\n"));
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+ //#
+ //#ACPI items
+ //#
+ Size = AsciiStrSize (AcpiName10nm);
+ Status = PcdSetPtrS (PcdOemSkuAcpiName , &Size, AcpiName10nm);
+ DEBUG ((DEBUG_INFO, "%a TypeJunctionCity ICX\n", __FUNCTION__));
+ ASSERT_EFI_ERROR (Status);
+
+ Size = AsciiStrSize (OemTableIdXhci);
+ Status = PcdSetPtrS (PcdOemTableIdXhci , &Size, OemTableIdXhci);
+ ASSERT_EFI_ERROR (Status);
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/GpioTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/GpioTable.c
new file mode 100644
index 0000000000..2d1e46b143
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/GpioTable.c
@@ -0,0 +1,296 @@
+/** @file
+
+ @copyright
+ Copyright 2020 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaGpioUpdateLib.h>
+
+#include <Library/GpioLib.h>
+#include <Library/UbaGpioInitLib.h>
+#include <GpioPinsSklH.h>
+#include <Library/PcdLib.h>
+
+//
+// Board : Wilson City RP
+//
+static GPIO_INIT_CONFIG mGpioTableJunctionCity [] =
+ {
+ {GPIO_SKL_H_GPP_A0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_0_LPC_RCIN_N_ESPI_ALERT1_N //IRQ_ESPI_FPGA_PCH_ALERT1_N PU not used
+ {GPIO_SKL_H_GPP_A1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_1_LPC_LAD0_ESPI_IO0
+ {GPIO_SKL_H_GPP_A2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_2_LPC_LAD1_ESPI_IO1
+ {GPIO_SKL_H_GPP_A3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_3_LPC_LAD2_ESPI_IO2
+ {GPIO_SKL_H_GPP_A4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_4_LPC_LAD3_ESPI_IO3
+ {GPIO_SKL_H_GPP_A5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_5_LPC_LFRAME_N_ESPI_CS0_N
+ {GPIO_SKL_H_GPP_A6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_6_IRQ_LPC_SERIRQ_ESPI_CS1_N
+ {GPIO_SKL_H_GPP_A7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_7_IRQ_LPC_PIRQA_N_ESPI_ALERT0_N
+ {GPIO_SKL_H_GPP_A8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_8_FM_LPC_CLKRUN_N //PU_LPC_CLKRUN_N PU not used
+ {GPIO_SKL_H_GPP_A9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_9_CLK_24M_66M_LPC0_ESPI
+ {GPIO_SKL_H_GPP_A10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_10_TP_PCH_GPP_A_10
+ {GPIO_SKL_H_GPP_A11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_11_FM_LPC_PME_N //PU_LPC_PME_N PU not used
+ {GPIO_SKL_H_GPP_A12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_12_IRQ_PCH_SCI_WHEA_N //PU_IRQ_PCH_SCI_WHEA_N PU not used
+ {GPIO_SKL_H_GPP_A13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_13_FM_EUP_LOT6_N //TP_PCH_GPP_A_13
+ {GPIO_SKL_H_GPP_A14, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_14_RST_ESPI_RESET_N
+ {GPIO_SKL_H_GPP_A15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_15_FM_SUSACK_N //TP_PCH_GPP_A_15
+ {GPIO_SKL_H_GPP_A16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_16_TP_PCH_GPP_A_16 //FM_PCHIE_BMC_N
+ {GPIO_SKL_H_GPP_A17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_17_TP_PCH_GPP_A_16 //FM_BMC_PCHIE_N
+ {GPIO_SKL_H_GPP_A18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_18_FM_BIOS_ADV_FUNCTIONS //IRQ_BMC_PCH_SMI_LPC_N
+// GPIO_SKL_H_GPP_A19 - Not Owned by BIOS //ME Recovery Jumper FM_ME_RCVR_N
+ {GPIO_SKL_H_GPP_A20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_20_TP_PCH_GPP_A_20 //FM_BMC_READY_N
+ {GPIO_SKL_H_GPP_A21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_21_TP_PCH_GPP_A_21
+ {GPIO_SKL_H_GPP_A22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_22_TP_PCH_GPP_A_22
+ {GPIO_SKL_H_GPP_A23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_A_23_TP_PCH_GPP_A_23
+ {GPIO_SKL_H_GPP_B0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_0_FM_PCH_CORE_VID_0
+ {GPIO_SKL_H_GPP_B1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_1_FM_PCH_CORE_VID_1
+ {GPIO_SKL_H_GPP_B2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_2_PU_PCH_VRALERT_N
+ {GPIO_SKL_H_GPP_B3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}}, //PU_SATA_EN
+// GPIO_SKL_H_GPP_B4 - Not Owned by BIOS //ME SMB Alert MGPIO IRQ_SML1_PMBUS_ALERT
+ {GPIO_SKL_H_GPP_B5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_5_FM_PCH_INTERPOSER_SEL1 //TP_PCH_GPP_B_5
+ {GPIO_SKL_H_GPP_B6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_6_FM_PCH_INTERPOSER_SEL2 //TP_PCH_GPP_B_6
+ {GPIO_SKL_H_GPP_B7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_7_TP_PCH_GPP_B_7
+ {GPIO_SKL_H_GPP_B8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_8_TP_PCH_GPP_B_8
+ {GPIO_SKL_H_GPP_B9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_9_FM_BOARD_REV_ID2 //TP_PCH_GPP_B_9
+ {GPIO_SKL_H_GPP_B10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_10_FM_TPM_MOD_PRES_N
+// GPIO_SKL_H_GPP_B11 - Not Owned by BIOS //ME SMB Alert_EN MGPIO FM_PMBUS_ALERT_BUF_EN_N
+ {GPIO_SKL_H_GPP_B12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_12_TP_SLP_S0_N //FM_GLOBAL_RST_WARN_N
+ {GPIO_SKL_H_GPP_B13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_13_RST_PLTRST_N
+ {GPIO_SKL_H_GPP_B14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_14_FM_PCH_BIOS_RCVR_SPKR
+ {GPIO_SKL_H_GPP_B15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_15_FM_CPU_ERR0_PCH_N
+ {GPIO_SKL_H_GPP_B16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_16_FM_CPU_ERR1_PCH_N
+ {GPIO_SKL_H_GPP_B17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_17_FM_CPU_ERR2_PCH_N
+ {GPIO_SKL_H_GPP_B18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_18_FM_NO_REBOOT //PU_NO_REBOOT Spare
+ {GPIO_SKL_H_GPP_B19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_19_FM_BOARD_SKU_ID5 //TP_PCH_GPP_B19
+ {GPIO_SKL_H_GPP_B20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone, GpioPadConfigLock}},//GPP_B_20_FM_BIOS_POST_CMPLT_N
+ {GPIO_SKL_H_GPP_B21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_21_TP_PCH_GPP_B_21
+ {GPIO_SKL_H_GPP_B22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_22_FM_PCH_BOOT_BIOS_DEVICE //FM_USB_PWR_EN
+ {GPIO_SKL_H_GPP_B23, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_B_23_FM_PCH_BMC_THERMTRIP_EXI_STRAP_N
+// GPIO_SKL_H_GPP_C0 - Not Owned by BIOS //ME SMBCLK
+// GPIO_SKL_H_GPP_C1 - Not Owned by BIOS //ME SMBDATA
+ {GPIO_SKL_H_GPP_C2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_2_PU_PCH_TLS_ENABLE_STRAP //IRQ_SMB_ALERT_N_TLS_EN_STRP
+// GPIO_SKL_H_GPP_C3 - Not Owned by BIOS //ME SML0CLK
+// GPIO_SKL_H_GPP_C4 - Not Owned by BIOS //ME SML0DATA
+ {GPIO_SKL_H_GPP_C5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_5_IRQ_SML0_ALERT_N
+// GPIO_SKL_H_GPP_C6 - Not Owned by BIOS //ME SML1CLK
+// GPIO_SKL_H_GPP_C7 - Not Owned by BIOS //ME SML1DATA
+ {GPIO_SKL_H_GPP_C8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_8_FM_PASSWORD_CLEAR_N
+ {GPIO_SKL_H_GPP_C9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_9_FM_MFG_MODE
+ {GPIO_SKL_H_GPP_C10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone}},//GPP_C_10_FM_PCH_SATA_RAID_KEY
+ {GPIO_SKL_H_GPP_C11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_11_TP_FP_AUD_DETECT_N //FM_BOARD_REV_ID0
+ {GPIO_SKL_H_GPP_C12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_12_FM_BOARD_REV_ID0 //FM_BOARD_REV_ID1
+ {GPIO_SKL_H_GPP_C13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_13_FM_BOARD_REV_ID1 //FM_BOARD_REV_ID2
+ {GPIO_SKL_H_GPP_C14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_14_FM_BMC_PCH_SCI_LPC_N //TP_PCH_GPP_C_14
+ {GPIO_SKL_H_GPP_C15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_15_FM_RISER1_ID_0 //TP_PCH_GPP_C_15
+ {GPIO_SKL_H_GPP_C16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_16_FM_RISER1_ID_1 //TP_PCH_GPP_C_16
+ {GPIO_SKL_H_GPP_C17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_17_FM_RISER2_ID_0 //TP_PCH_GPP_C_17
+ {GPIO_SKL_H_GPP_C18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_18_FM_RISER2_ID_1 //TP_PCH_GPP_C_18
+// GPIO_SKL_H_GPP_C19 - Not Owned by BIOS //SMBus Smbus Mux GPIO reset GPP_C_19_RST_SMB_HOST_PCH_MUX_N
+// GPIO_SKL_H_GPP_C20 - Not Owned by BIOS //ME PROCHOT MGPIO GPP_C_20_FM_THROTTLE_N
+ {GPIO_SKL_H_GPP_C21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_21_RST_PCH_MIC_MUX_N //TP_PCH_GPP_C_21
+ {GPIO_SKL_H_GPP_C22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_22_IRQ_BMC_PCH_SMI_LPC_N //FM_BMC_PCH_SCI_LPC_N
+ {GPIO_SKL_H_GPP_C23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_C_23_FM_CPU_CATERR_DLY_LVT3_N
+ {GPIO_SKL_H_GPP_D0, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, GpioOutDefault, GpioIntLevel | GpioIntNmi, GpioResetNormal, GpioTermNone, GpioPadConfigLock}},//GPP_D_0_IRQ_BMC_PCH_NMI
+ {GPIO_SKL_H_GPP_D1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioPlatformReset,GpioTermNone, GpioPadConfigLock}},//GPP_D_1_FP_PWR_LED_N
+ {GPIO_SKL_H_GPP_D2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_2_FM_TBT_FORCE_PWR //TP_PCH_GPP_D_2
+ {GPIO_SKL_H_GPP_D3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_3_FM_TBT_SCI_EVENT //TP_PCH_GPP_D_3
+ {GPIO_SKL_H_GPP_D4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_4_FM_PLD_PCH_DATA
+ {GPIO_SKL_H_GPP_D5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_5_TP_PCH_GPP_D_5 //FM_OCP_MOD1_PRSNT_N
+ {GPIO_SKL_H_GPP_D6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_6_TP_PCH_GPP_D_6
+ {GPIO_SKL_H_GPP_D7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_7_TP_PCH_GPP_D_7
+ {GPIO_SKL_H_GPP_D8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_8_FM_UPLINK_SEL //TP_PCH_GPP_D_8
+ {GPIO_SKL_H_GPP_D9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_9_TP_PCH_GPP_D_9
+ {GPIO_SKL_H_GPP_D10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_10_FM_M2_2_SSD_DEVSLP //TP_PCH_GPP_D_10
+ {GPIO_SKL_H_GPP_D11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_11_TP_PCH_GPP_D_11
+ {GPIO_SKL_H_GPP_D12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_12_SGPIO_SSATA_DATA1 //TP_PCH_GPP_D_12
+ {GPIO_SKL_H_GPP_D13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_13_SMB_SMLINK5_STBY_LVC3_R_SCL //TP_PCH_GPP_D_13
+ {GPIO_SKL_H_GPP_D14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_14_SMB_SMLINK5_STBY_LVC3_R_SDA //TP_PCH_GPP_D_14
+ {GPIO_SKL_H_GPP_D15, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_15_SGPIO_SSATA_DATA0
+ {GPIO_SKL_H_GPP_D16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_16_FM_ME_PFR_1 //FM_SLOT1_PRSNT
+ {GPIO_SKL_H_GPP_D17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_17_FM_ME_PFR_2 //FM_SLOT2_PRSNT
+ {GPIO_SKL_H_GPP_D18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_18_MCP_RESET_CTRL_N //TP_PCH_GPP_D_18
+ {GPIO_SKL_H_GPP_D19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_19_FM_PS_PWROK_DLY_SEL_R
+ {GPIO_SKL_H_GPP_D20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_20_TP_PCH_GPP_D_20
+ {GPIO_SKL_H_GPP_D21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_21_TP_PCH_GPP_D_21
+ {GPIO_SKL_H_GPP_D22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_22_TP_PCH_GPP_D_22
+ {GPIO_SKL_H_GPP_D23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_D_23_TP_PCH_GPP_D_23
+ {GPIO_SKL_H_GPP_E0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_0_FM_QAT_ENABLE_N //TP_PCH_GPP_E_0
+ {GPIO_SKL_H_GPP_E1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_1_FM_QAT_ENABLE_N //TP_PCH_GPP_E_1
+ {GPIO_SKL_H_GPP_E2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_2_FM_QAT_ENABLE_N //TP_PCH_GPP_E_2
+ {GPIO_SKL_H_GPP_E3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_3_FM_ADR_TRIGGER_N
+ {GPIO_SKL_H_GPP_E4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_4_TP_PCH_GPP_E_4 //FM_CPU0_SSD0_PRSNT_N
+ {GPIO_SKL_H_GPP_E5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_5_TP_PCH_GPP_E_5 //FM_CPU0_SSD1_PRSNT_N
+ {GPIO_SKL_H_GPP_E6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_6_TP_PCH_GPP_E_6 //FM_CPU0_SSD2_PRSNT_N
+ {GPIO_SKL_H_GPP_E7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_7_FM_ADR_SMI_GPIO_R_N
+ {GPIO_SKL_H_GPP_E8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_8_LED_PCH_SATA_HDD_N //FM_CPU0_SSD3_PRSNT_N
+ {GPIO_SKL_H_GPP_E9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_9_FM_OC0_USB_N
+ {GPIO_SKL_H_GPP_E10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_10_FM_OC1_USB_N
+ {GPIO_SKL_H_GPP_E11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_11_PU_OC2_USB_N
+ {GPIO_SKL_H_GPP_E12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_E_12_PU_OC3_USB_N
+ {GPIO_SKL_H_GPP_F0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_0_FM_QAT_ENABLE_N //FM_OCP_MOD2_PRSNT_N
+ {GPIO_SKL_H_GPP_F1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_1_FM_QAT_ENABLE_N //TP_PCH_GPP_F_1
+ {GPIO_SKL_H_GPP_F2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_2_FM_QAT_ENABLE_N //FM_EDSFF0_PRSNT0_N
+ {GPIO_SKL_H_GPP_F3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_3_FM_QAT_ENABLE_N //FM_EDSFF0_PRSNT1_N
+ {GPIO_SKL_H_GPP_F4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_4_FM_QAT_ENABLE_N //FM_BIOS_USB_RECOVERY
+ {GPIO_SKL_H_GPP_F5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_5_IRQ_TPM_SPI_N
+ {GPIO_SKL_H_GPP_F6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_6_JTAG_PCH_PLD_TCK //FM_EDSFF1_PRSNT0_N
+ {GPIO_SKL_H_GPP_F7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_7_JTAG_PCH_PLD_TDI //FM_EDSFF1_PRSNT1_N
+ {GPIO_SKL_H_GPP_F8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_8_JTAG_PCH_PLD_TMS //FM_EDSFF2_PRSNT0_N
+ {GPIO_SKL_H_GPP_F9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_9_JTAG_PCH_PLD_TDO //FM_EDSFF2_PRSNT1_N
+ {GPIO_SKL_H_GPP_F10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_10_SGPIO_SATA_CLOCK
+ {GPIO_SKL_H_GPP_F11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_11_SGPIO_SATA_LOAD
+ {GPIO_SKL_H_GPP_F12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_12_SGPIO_SATA_DATA1
+ {GPIO_SKL_H_GPP_F13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_13_SGPIO_SATA_DATA0
+ {GPIO_SKL_H_GPP_F14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_14_LED_PCH_SSATA_HDD_N //TP_PCH_GPP_F14
+ {GPIO_SKL_H_GPP_F15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_15_FM_OC4_USB_N //FM_EDSFF3_PRSNT0_N
+ {GPIO_SKL_H_GPP_F16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_16_PU_OC5_USB_N //FM_EDSFF3_PRSNT1_N
+ {GPIO_SKL_H_GPP_F17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_17_FM_OC6_USB_N //FM_EDSFF4_PRSNT0_N
+ {GPIO_SKL_H_GPP_F18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_18_PU_OC7_USB_N //FM_EDSFF4_PRSNT1_N
+ {GPIO_SKL_H_GPP_F19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_19_SMB_GBE_STBY_LVC3_SCL //FM_EDSFF5_PRSNT0_N
+ {GPIO_SKL_H_GPP_F20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_20_SMB_GBE_STBY_LVC3_SDA //FM_EDSFF5_PRSNT1_N
+ {GPIO_SKL_H_GPP_F21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_21_TP_PCH_GPP_F_21
+ {GPIO_SKL_H_GPP_F22, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_22_SGPIO_SSATA_CLOCK
+ {GPIO_SKL_H_GPP_F23, { GpioPadModeNative3, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_F_23_SGPIO_SSATA_LOAD
+ {GPIO_SKL_H_GPP_G0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_0_TP_FAN_PCH_TACH0 //FM_BOARD_SKU_ID0
+ {GPIO_SKL_H_GPP_G1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_1_TP_FAN_PCH_TACH1 //FM_BOARD_SKU_ID1
+ {GPIO_SKL_H_GPP_G2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_2_TP_FAN_PCH_TACH2 //FM_BOARD_SKU_ID2
+ {GPIO_SKL_H_GPP_G3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_3_TP_FAN_PCH_TACH3 //FM_BOARD_SKU_ID3
+ {GPIO_SKL_H_GPP_G4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_4_TP_FAN_PCH_TACH4 //FM_BOARD_SKU_ID4
+ {GPIO_SKL_H_GPP_G5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_5_TP_FAN_PCH_TACH5 //FM_BOARD_SKU_ID5
+ {GPIO_SKL_H_GPP_G6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_6_TP_FAN_PCH_TACH6 //FM_MIDPLANE_PCH_ID0
+ {GPIO_SKL_H_GPP_G7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_7_TP_FAN_PCH_TACH7 //FM_MIDPLANE_PCH_ID1
+ {GPIO_SKL_H_GPP_G8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_8_TP_FAN_PCH_PWM0 //FM_PCH_GPP_G8
+ {GPIO_SKL_H_GPP_G9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_9_TP_FAN_PCH_PWM1 //FM_PCH_GPP_G9
+ {GPIO_SKL_H_GPP_G10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_10_TP_FAN_PCH_PWM2 //FM_PCH_GPP_G10
+ {GPIO_SKL_H_GPP_G11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_11_TP_FAN_PCH_PWM3 //FM_PCH_GPP_G11
+ {GPIO_SKL_H_GPP_G12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_12_GSXDOUT //IRQ_FORCE_NM_THROTTLE_N
+ {GPIO_SKL_H_GPP_G13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_13_FM_BOARD_SKU_ID1 //TP_PCH_GPP_G_13
+ {GPIO_SKL_H_GPP_G14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_14_FM_BOARD_SKU_ID2 //TP_PCH_GPP_G_14
+ {GPIO_SKL_H_GPP_G15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_15_FM_BOARD_SKU_ID3 //TP_PCH_GPP_G_15
+ {GPIO_SKL_H_GPP_G16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_16_FM_BOARD_SKU_ID4 //TP_PCH_GPP_G_16
+ {GPIO_SKL_H_GPP_G17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_17_FM_ADR_COMPLETE
+ {GPIO_SKL_H_GPP_G18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_18_IRQ_NMI_EVENT_N
+ {GPIO_SKL_H_GPP_G19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_19_IRQ_SMI_ACTIVE_N
+ {GPIO_SKL_H_GPP_G20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}}, //TP_PCH_GPP_G_20
+ {GPIO_SKL_H_GPP_G21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_21_FM_BIOS_IMAGE_SWAP_N //TP_PCH_GPP_G_21
+ {GPIO_SKL_H_GPP_G22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_22_FM_M2_2_SSD_DEVSLP //TP_PCH_GPP_G_22
+ {GPIO_SKL_H_GPP_G23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_G_23_TP_PCH_GPP_G_23
+ {GPIO_SKL_H_GPP_H0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_0_FM_PCH_MGPIO_TEST2 //FM_CLKREQ_M2_SSD_A_N
+ {GPIO_SKL_H_GPP_H1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_1_FM_SWAP_OVERRIDE_N //FM_CLKREQ_M2_SSD_B_N
+ {GPIO_SKL_H_GPP_H2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_2_FM_PCH_MGPIO_TEST0 //FM_ROWOL_ENABLE
+ {GPIO_SKL_H_GPP_H3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_3_FM_PCH_MGPIO_TEST1 //FM_ROWOL_LATCH
+ {GPIO_SKL_H_GPP_H4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_4_FM_PCH_MGPIO_TEST4 //TP_PCH_GPP_H_4
+ {GPIO_SKL_H_GPP_H5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_5_FM_CLKREQ_M2_1_N //TP_PCH_GPP_H_5
+ {GPIO_SKL_H_GPP_H6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_6_FM_CLKREQ_M2_2_N //TP_PCH_GPP_H_6
+ {GPIO_SKL_H_GPP_H7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_7_FM_PCH_MGPIO_TEST3 //TP_PCH_GPP_H_7
+ {GPIO_SKL_H_GPP_H8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_8_FM_CLKREQ_NIC1_N //TP_PCH_GPP_H_8
+ {GPIO_SKL_H_GPP_H9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_9_FM_PCH_MGPIO_TEST5 //TP_PCH_GPP_H_9
+// GPIO_SKL_H_GPP_H10 - Not Owned by BIOS //ME SML2CLK
+// GPIO_SKL_H_GPP_H11 - Not Owned by BIOS //ME SML2DATA
+ {GPIO_SKL_H_GPP_H12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_12_FM_ESPI_FLASH_MODE //IRQ_SML2_ALERT_N
+ {GPIO_SKL_H_GPP_H15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_15_PU_ADR_TIMER_HOLD_OFF_N
+ {GPIO_SKL_H_GPP_H18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_18_FM_LT_KEY_DOWNGRADE_N
+ {GPIO_SKL_H_GPP_H19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_19_FM_PCH_10GBE_PCI_DISABLE_N //TP_PCH_GPP_H_19
+ {GPIO_SKL_H_GPP_H20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_20_FM_SSATA_PCIE_M2_1_SEL //TP_PCH_GPP_H_20
+ {GPIO_SKL_H_GPP_H21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_21_FM_PCH_10GBE_LAN_DISABLE_N //TP_PCH_GPP_H_21
+ {GPIO_SKL_H_GPP_H22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_22_FM_SSATA_PCIE_M2_2_SEL //TP_PCH_GPP_H_22
+ {GPIO_SKL_H_GPP_H23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_H_23_TP_PCH_GPP_H_23
+ {GPIO_SKL_H_GPP_I0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_0_TP_PCH_GPP_I_0
+ {GPIO_SKL_H_GPP_I1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_1_TP_PCH_GPP_I_1
+ {GPIO_SKL_H_GPP_I2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_2_TP_PCH_GPP_I_2
+ {GPIO_SKL_H_GPP_I3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_3_TP_PCH_GPP_I_3
+ {GPIO_SKL_H_GPP_I4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_4_TP_PCH_GPP_I_4
+ {GPIO_SKL_H_GPP_I5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_5_TP_PCH_GPP_I_5
+ {GPIO_SKL_H_GPP_I6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_6_TP_PCH_GPP_I_6
+ {GPIO_SKL_H_GPP_I7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_7_TP_PCH_GPP_I_7
+ {GPIO_SKL_H_GPP_I8, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_8_FM_PCH_10GBE_PCI_DISABLE_N
+ {GPIO_SKL_H_GPP_I9, { GpioPadModeNative2, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_9_FM_PCH_10GBE_LAN_DISABLE_N
+ {GPIO_SKL_H_GPP_I10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_I_10_TP_PCH_GPP_I_10 //FM_BIOS_MRC_DEBUG_MSG_DIS_N
+// GPIO_SKL_H_GPP_I11 - Not Owned by BIOS
+// GPIO_SKL_H_GPD0 - Not Owned by BIOS //ME FIVRBREAK
+ {GPIO_SKL_H_GPD1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_1_PU_ACPRESENT
+ {GPIO_SKL_H_GPD2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutHigh, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_2_FM_LAN_WAKE_N //RST_BMC_SRST_N
+ {GPIO_SKL_H_GPD3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_3_FM_PCH_PWRBTN_N
+ {GPIO_SKL_H_GPD4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_4_FM_SLPS3_N
+ {GPIO_SKL_H_GPD5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_5_FM_SLPS4_N
+ {GPIO_SKL_H_GPD6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_6_FM_SLPA_N
+ {GPIO_SKL_H_GPD7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_7_TP_GPD_7
+ {GPIO_SKL_H_GPD8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_8_TP_GPD_8_SUSCLK
+ {GPIO_SKL_H_GPD9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_9_TP_GPD_9_SLP
+ {GPIO_SKL_H_GPD10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_10_FM_SLPS5_N
+ {GPIO_SKL_H_GPD11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPD_11_FM_PHY_DISABLE_N
+ {GPIO_SKL_H_GPP_J0, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_0_TP_PCH_GPP_J_0
+ {GPIO_SKL_H_GPP_J1, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_1_TP_PCH_GPP_J_1
+ {GPIO_SKL_H_GPP_J2, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_2_TP_PCH_GPP_J_2
+ {GPIO_SKL_H_GPP_J3, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_3_TP_PCH_GPP_J_3
+ {GPIO_SKL_H_GPP_J4, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_4_TP_PCH_GPP_J_4
+ {GPIO_SKL_H_GPP_J5, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_5_TP_PCH_GPP_J_5
+ {GPIO_SKL_H_GPP_J6, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_6_TP_PCH_GPP_J_6
+ {GPIO_SKL_H_GPP_J7, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_7_TP_PCH_GPP_J_7
+ {GPIO_SKL_H_GPP_J8, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_8_TP_PCH_GPP_J_8
+ {GPIO_SKL_H_GPP_J9, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_9_TP_PCH_GPP_J_9
+ {GPIO_SKL_H_GPP_J10, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_10_TP_PCH_GPP_J_10
+ {GPIO_SKL_H_GPP_J11, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_11_TP_PCH_GPP_J_11
+ {GPIO_SKL_H_GPP_J12, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_12_TP_PCH_GPP_J_12
+ {GPIO_SKL_H_GPP_J13, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_13_TP_PCH_GPP_J_13
+ {GPIO_SKL_H_GPP_J14, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_14_TP_PCH_GPP_J_14
+ {GPIO_SKL_H_GPP_J15, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_15_TP_PCH_GPP_J_15
+ {GPIO_SKL_H_GPP_J16, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_16_TP_PCH_GPP_J_16
+ {GPIO_SKL_H_GPP_J17, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_17_TP_PCH_GPP_J_17
+ {GPIO_SKL_H_GPP_J18, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_18_TP_PCH_GPP_J_18
+ {GPIO_SKL_H_GPP_J19, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_19_TP_PCH_GPP_J_19
+ {GPIO_SKL_H_GPP_J20, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_20_TP_PCH_GPP_J_20
+ {GPIO_SKL_H_GPP_J21, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_21_TP_PCH_GPP_J_21
+ {GPIO_SKL_H_GPP_J22, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_22_TP_PCH_GPP_J_22
+ {GPIO_SKL_H_GPP_J23, { GpioPadModeGpio, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_J_23_TP_PCH_GPP_J_23
+ {GPIO_SKL_H_GPP_K0, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_0_CLK_50M_CKMNG_PCH
+ {GPIO_SKL_H_GPP_K1, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_1_RMII_BMC_PCH_TXD0
+ {GPIO_SKL_H_GPP_K2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_2_RMII_BMC_PCH_TXD1
+ {GPIO_SKL_H_GPP_K3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_3_RMII_BMC_PCH_TX_EN
+ {GPIO_SKL_H_GPP_K4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_4_RMII_PCH_BMC_CRS_DV
+ {GPIO_SKL_H_GPP_K5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_5_RMII_PCH_BMC_RXD0
+ {GPIO_SKL_H_GPP_K6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_6_RMII_PCH_BMC_RXD1
+ {GPIO_SKL_H_GPP_K7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirInOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_7_RMII_PCH_BMC_RX_ER
+ {GPIO_SKL_H_GPP_K8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_8_RMII_PCH_CONN_ARB_IN
+ {GPIO_SKL_H_GPP_K9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_9_RMII_PCH_CONN_ARB_OUT
+ {GPIO_SKL_H_GPP_K10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirIn, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_K_10_RST_PCIE_PCH_PERST_N
+// GPIO_SKL_H_GPP_K11 - Not Owned by BIOS
+ {GPIO_SKL_H_GPP_L2, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_2_TRC_2CH0_D0
+ {GPIO_SKL_H_GPP_L3, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_3_TRC_2CH0_D1
+ {GPIO_SKL_H_GPP_L4, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_4_TRC_2CH0_D2
+ {GPIO_SKL_H_GPP_L5, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_5_TRC_2CH0_D3
+ {GPIO_SKL_H_GPP_L6, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_6_TRC_2CH0_D4
+ {GPIO_SKL_H_GPP_L7, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_7_TRC_2CH0_D5
+ {GPIO_SKL_H_GPP_L8, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_8_TRC_2CH0_D6
+ {GPIO_SKL_H_GPP_L9, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_9_TRC_2CH0_D7
+ {GPIO_SKL_H_GPP_L10, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_10_TRC_2CH0_CLK
+ {GPIO_SKL_H_GPP_L11, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_11_TRC_2CH1_D0
+ {GPIO_SKL_H_GPP_L12, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_12_TRC_2CH1_D1
+ {GPIO_SKL_H_GPP_L13, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_13_TRC_2CH1_D2
+ {GPIO_SKL_H_GPP_L14, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_14_TRC_2CH1_D3
+ {GPIO_SKL_H_GPP_L15, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_15_TRC_2CH1_D4
+ {GPIO_SKL_H_GPP_L16, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_16_TRC_2CH1_D5
+ {GPIO_SKL_H_GPP_L17, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_17_TRC_2CH1_D6
+ {GPIO_SKL_H_GPP_L18, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_18_TRC_2CH1_D7
+ {GPIO_SKL_H_GPP_L19, { GpioPadModeNative1, GpioHostOwnDefault, GpioDirOut, GpioOutLow, GpioIntDis, GpioResetPwrGood, GpioTermNone, GpioPadConfigLock}},//GPP_L_19_TRC_2CH1_CLK
+};
+
+EFI_STATUS
+TypeJunctionCityInstallGpioData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformGpioInitDataGuid,
+ &mGpioTableJunctionCity,
+ sizeof(mGpioTableJunctionCity)
+ );
+ Status = PcdSet32S (PcdOemSku_GPIO_TABLE_SIZE, sizeof (mGpioTableJunctionCity));
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/IioBifurInit.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/IioBifurInit.c
new file mode 100644
index 0000000000..4c376964e2
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/IioBifurInit.c
@@ -0,0 +1,242 @@
+/** @file
+ IIO Config Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaIioConfigLib.h>
+#include <IioPlatformData.h>
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 = 0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Iou3,
+ Iio_Iou4,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ VPP_PORT_0 = 0,
+ VPP_PORT_1,
+ VPP_PORT_2,
+ VPP_PORT_3
+} VPP_PORT;
+
+#define ENABLE 1
+#define DISABLE 0
+
+static IIO_BIFURCATION_DATA_ENTRY_EX IioBifurcationTable[] =
+{
+
+ { Iio_Socket0, Iio_Iou0, IIO_BIFURCATE_x4x4xxx8, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket0, Iio_Iou1, IIO_BIFURCATE_xxx8xxx8, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket0, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket0, Iio_Iou3, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket0, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+
+ { Iio_Socket1, Iio_Iou0, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket1, Iio_Iou1, IIO_BIFURCATE_xxx8xxx8, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket1, Iio_Iou2, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket1, Iio_Iou3, IIO_BIFURCATE_xxx8x4x4, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX },
+ { Iio_Socket1, Iio_Iou4, IIO_BIFURCATE_xxxxxx16, VPP_PORT_MAX, SMB_ADDR_MAX, SMB_ADDR_MAX, SMB_DATA_MAX }
+};
+//[-start-210223-Enhance_Dynamic_Type9-modify]//
+static IIO_SLOT_CONFIG_DATA_ENTRY_EX IioSlotTable[] = {
+ // Port Index | Slot |Interlock |power |Power |Hotplug |Vpp Port |Vpp Addr |PCIeSSD |PCIeSSD |PCIeSSD |Hidden |Common | SRIS |Uplink |Retimer |Retimer |Retimer |Retimer |Mux |Mux |ExtnCard |ExtnCard |ExtnCard |ExtnCard |ExtnCard Retimer|ExtnCard Retimer|ExtnCard |ExtnCard Hotplug|ExtnCard Hotplug|Max Retimer|
+ // | | |Limit Scale |Limit Value |Cap | | |Cap |Port |Address | |Clock | |Port | |Address |Channel |Width |Address |Channel |Support |SMBus Port |SMBus Addr |Retimer |SMBus Address |Width |Hotplug |Vpp Port |Vpp Address | |
+ {SOCKET_0_INDEX +
+ PORT_1A_INDEX, 1 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_1C_INDEX, 2 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_1D_INDEX, 3 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2A_INDEX, 4 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2C_INDEX, 5 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_4A_INDEX, 6 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_4B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_4C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_5A_INDEX, 7 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_5B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_5C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_0_INDEX +
+ PORT_5D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+
+ {SOCKET_1_INDEX +
+ PORT_1A_INDEX, 8 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_1B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x42 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_1C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_1D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x40 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_2A_INDEX, 9 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_2B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x44 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_2C_INDEX, 10 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_2D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x46 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_3A_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_3B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_3C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_3D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4A_INDEX, 11 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4B_INDEX, 12 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x48 , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4C_INDEX, 13 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_1 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_4D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , ENABLE , VPP_PORT_0 , 0x4A , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_5A_INDEX, 14 , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_5B_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_5C_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 },
+ {SOCKET_1_INDEX +
+ PORT_5D_INDEX, NO_SLT_IMP , DISABLE , PWR_SCL_MAX , PWR_VAL_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , DISABLE , VPP_PORT_MAX , VPP_ADDR_MAX , NOT_HIDE , ENABLE , DISABLE , DISABLE , DISABLE , SMB_ADDR_MAX , SMB_DATA_MAX , NOT_EXIST , SMB_ADDR_MAX , SMB_DATA_MAX , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , DISABLE , SMB_ADDR_MAX , NOT_EXIST , DISABLE , VPP_PORT_MAX , SMB_ADDR_MAX , 0x0 }
+};
+
+EFI_STATUS
+UpdateJunctionCityIioConfig (
+ IN IIO_GLOBALS *IioGlobalData
+ )
+{
+ return EFI_SUCCESS;
+}
+
+PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX TypeJunctionCityIioConfigTable =
+{
+ PLATFORM_IIO_CONFIG_UPDATE_SIGNATURE,
+ PLATFORM_IIO_CONFIG_UPDATE_VERSION_2,
+
+ IioBifurcationTable,
+ sizeof(IioBifurcationTable),
+ UpdateJunctionCityIioConfig,
+ IioSlotTable,
+ sizeof(IioSlotTable)
+};
+
+/**
+ Entry point function for the PEIM
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS If we installed our PPI
+
+**/
+EFI_STATUS
+TypeJunctionCityIioPortBifurcationInit (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+ PLATFORM_IIO_CONFIG_UPDATE_TABLE_EX *PlatformIioInfoPtr;
+ UINTN PlatformIioInfoSize;
+
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+
+ //
+ // This is config for ICX
+ //
+ PlatformIioInfoPtr = &TypeJunctionCityIioConfigTable;
+ PlatformIioInfoSize = sizeof(TypeJunctionCityIioConfigTable);
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid_1,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid_2,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformIioConfigDataGuid_3,
+ PlatformIioInfoPtr,
+ PlatformIioInfoSize
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/KtiEparam.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/KtiEparam.c
new file mode 100644
index 0000000000..1ec1424d23
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/KtiEparam.c
@@ -0,0 +1,69 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <KtiSetupDefinitions.h>
+#include <UbaKti.h>
+
+extern EFI_GUID gPlatformKtiEparamUpdateDataGuid;
+
+ALL_LANES_EPARAM_LINK_INFO KtiJunctionCityIcxAllLanesEparamTable[] = {
+ //
+ // SocketID, Freq, Link, TXEQL, CTLEPEAK
+ // Please propagate changes to WilsonCitySMT and WilsonCityModular UBA KtiEparam tables
+ //
+ //
+ // Socket 0
+ //
+ {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2B33373F, ADAPTIVE_CTLE},
+ {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK1), 0x2A33363F, ADAPTIVE_CTLE},
+ {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK2), 0x2B34363F, ADAPTIVE_CTLE},
+ //
+ // Socket 1
+ //
+ {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK0), 0x2A31383F, ADAPTIVE_CTLE},
+ {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK1), 0x2A30393F, ADAPTIVE_CTLE},
+ {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT) | (1 << SPEED_REC_112GT), (1 << KTI_LINK2), 0x2C34373F, ADAPTIVE_CTLE}
+};
+
+PLATFORM_KTI_EPARAM_UPDATE_TABLE TypeJunctionCityIcxKtiEparamUpdate = {
+ PLATFORM_KTIEP_UPDATE_SIGNATURE,
+ PLATFORM_KTIEP_UPDATE_VERSION,
+ KtiJunctionCityIcxAllLanesEparamTable,
+ sizeof (KtiJunctionCityIcxAllLanesEparamTable),
+ NULL,
+ 0
+};
+
+
+EFI_STATUS
+TypeJunctionCityInstallKtiEparamData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA (GuidHob);
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformKtiEparamUpdateDataGuid,
+ &TypeJunctionCityIcxKtiEparamUpdate,
+ sizeof(TypeJunctionCityIcxKtiEparamUpdate)
+ );
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PcdData.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PcdData.c
new file mode 100644
index 0000000000..901e2b8f32
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PcdData.c
@@ -0,0 +1,275 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <ImonVrSvid.h>
+#include <Library/MemVrSvidMapLib.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/UbaPcdUpdateLib.h>
+#include <Library/PcdLib.h>
+#include <UncoreCommonIncludes.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+#include <CpuAndRevisionDefines.h>
+
+#define GPIO_SKL_H_GPP_B20 0x01010014
+
+VOID TypeJunctionCityPlatformUpdateVrIdAddress (VOID);
+
+/**
+ Update JunctionCity IMON SVID Information
+
+ retval N/A
+**/
+VOID
+TypeJunctionCityPlatformUpdateImonAddress (
+ VOID
+ )
+{
+ VCC_IMON *VccImon = NULL;
+ UINTN Size = 0;
+
+ Size = sizeof (VCC_IMON);
+ VccImon = (VCC_IMON *) PcdGetPtr (PcdImonAddr);
+ if (VccImon == NULL) {
+ DEBUG ((EFI_D_ERROR, "UpdateImonAddress() - PcdImonAddr == NULL\n"));
+ return;
+ }
+
+ VccImon->VrSvid[0] = PcdGet8 (PcdWilsonCitySvidVrP1V8);
+ VccImon->VrSvid[1] = PcdGet8 (PcdWilsonCitySvidVrVccAna);
+ VccImon->VrSvid[2] = IMON_ADDR_LIST_END; // End array with 0xFF
+
+ PcdSetPtrS (PcdImonAddr, &Size, (VOID *) VccImon);
+}
+
+/**
+ Update WilsonCity VR ID SVID Information
+
+ retval N/A
+**/
+VOID
+TypeJunctionCityPlatformUpdateVrIdAddress (
+ VOID
+ )
+{
+ MEM_SVID_MAP *MemSvidMap = NULL;
+ UINTN Size = 0;
+
+ Size = sizeof (MEM_SVID_MAP);
+ MemSvidMap = (MEM_SVID_MAP *) PcdGetPtr (PcdMemSrvidMap);
+ if (MemSvidMap == NULL) {
+ DEBUG ((EFI_D_ERROR, "UpdateVrIdAddress() - PcdMemSrvidMap == NULL\n"));
+ return;
+ }
+ /*
+ Map VR ID Address to Memory controller
+ The mailbox command can support up to 4 DDR VR ID's, 0x10, 0x12, 0x14, and 0x16.
+ Whitley PHAS indicates that Whitley (like Purley) only connects 2 VRs (VR ID's 0x10 and 0x12).
+ Those are typically shared such that MC0/MC2 share the same DDR VR (as they are on the same side of the CPU)
+ and MC1/MC3 share the other. Depending on motherboard layout and other design constraints, this could change
+ BIT 4 => 0 or 1, SVID BUS\Interface 0 or 1 respectively
+ BIT 0:3 => SVID ADDRESS
+ */
+
+ MemSvidMap->Socket[0].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[0].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[1].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[1].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[2].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[2].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[3].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[3].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[4].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[4].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[5].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[5].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[6].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[6].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+ MemSvidMap->Socket[7].Mc[0] = 0x10; //SVID BUS 1, ADDR 0
+ MemSvidMap->Socket[7].Mc[1] = 0x12; //SVID BUS 1, ADDR 2
+
+ PcdSetPtrS (PcdMemSrvidMap, &Size, (VOID *) MemSvidMap);
+}
+
+EFI_STATUS
+TypeJunctionCityPlatformPcdUpdateCallback (
+ VOID
+)
+{
+ CHAR8 FamilyName[] = "Whitley";
+
+ CHAR8 BoardName[] = "EPRP";
+ UINT32 Data32;
+ UINTN Size;
+ UINTN PlatformFeatureFlag = 0;
+
+ CHAR16 PlatformName[] = L"TypeJunctionCity";
+ UINTN PlatformNameSize = 0;
+ EFI_STATUS Status;
+
+ //#Integer for BoardID, must match the SKU number and be unique.
+ Status = PcdSet16S (PcdOemSkuBoardID , TypeJunctionCity);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSet16S (PcdOemSkuBoardFamily , 0x30);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ // Number of Sockets on Board.
+ Status = PcdSet32S (PcdOemSkuBoardSocketCount, 2);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ // Max channel and max DIMM
+ Status = PcdSet32S (PcdOemSkuMaxChannel , 8);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSet32S (PcdOemSkuMaxDimmPerChannel , 2);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSetBoolS (PcdOemSkuDimmLayout, TRUE);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //Update Onboard Video Controller PCI Ven_id, Dev_id
+ Status = PcdSet16S (PcdOnboardVideoPciVendorId, 0x1A03);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = PcdSet16S (PcdOnboardVideoPciDeviceId, 0x2000);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //#
+ //# Misc.
+ //#
+ //# V_PCIE_PORT_PXPSLOTCTRL_ATNLED_OFF
+ Status = PcdSet16S (PcdOemSkuMrlAttnLed , 0xc0);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //SDP Active Flag
+ Status = PcdSet8S (PcdOemSkuSdpActiveFlag , 0x0);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# Zero terminated string to ID family
+ Size = AsciiStrSize (FamilyName);
+ Status = PcdSetPtrS (PcdOemSkuFamilyName , &Size, FamilyName);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# Zero terminated string to Board Name
+ Size = AsciiStrSize (BoardName);
+ Status = PcdSetPtrS (PcdOemSkuBoardName , &Size, BoardName);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ PlatformNameSize = sizeof (PlatformName);
+ Status = PcdSet32S (PcdOemSkuPlatformNameSize , (UINT32)PlatformNameSize);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSetPtrS (PcdOemSkuPlatformName , &PlatformNameSize, PlatformName);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# FeaturesBasedOnPlatform
+ Status = PcdSet32S (PcdOemSkuPlatformFeatureFlag , (UINT32)PlatformFeatureFlag);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# Assert GPIO
+ Data32 = 0;
+ Status = PcdSet32S (PcdOemSkuAssertPostGPIOValue, Data32);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ Status = PcdSet32S (PcdOemSkuAssertPostGPIO, GPIO_SKL_H_GPP_B20);
+ ASSERT_EFI_ERROR(Status);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ //# UplinkPortIndex
+ Status = PcdSet8S (PcdOemSkuUplinkPortIndex, 5);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ DEBUG ((EFI_D_INFO, "Uba Callback: PlatformPcdUpdateCallback is called!\n"));
+ Status = TypeJunctionCityPlatformUpdateAcpiTablePcds ();
+ //# BMC Pcie Port Number
+ PcdSet8S (PcdOemSkuBmcPciePortNumber, 5);
+ ASSERT_EFI_ERROR(Status);
+
+ //# Board Type Bit Mask
+ PcdSet32S (PcdBoardTypeBitmask, CPU_TYPE_F_MASK | (CPU_TYPE_F_MASK << 4));
+ ASSERT_EFI_ERROR(Status);
+
+ //Update IMON Address
+ TypeJunctionCityPlatformUpdateImonAddress ();
+
+ return Status;
+}
+
+PLATFORM_PCD_UPDATE_TABLE TypeJunctionCityPcdUpdateTable =
+{
+ PLATFORM_PCD_UPDATE_SIGNATURE,
+ PLATFORM_PCD_UPDATE_VERSION,
+ TypeJunctionCityPlatformPcdUpdateCallback
+};
+
+EFI_STATUS
+TypeJunctionCityInstallPcdData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPcdConfigDataGuid,
+ &TypeJunctionCityPcdUpdateTable,
+ sizeof(TypeJunctionCityPcdUpdateTable)
+ );
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PchEarlyUpdate.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PchEarlyUpdate.c
new file mode 100644
index 0000000000..e8cc05155a
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PchEarlyUpdate.c
@@ -0,0 +1,93 @@
+/** @file
+ Pch Early update.
+
+ @copyright
+ Copyright 2019 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+
+#include <Library/UbaPchEarlyUpdateLib.h>
+
+#include <PchAccess.h>
+#include <GpioPinsSklH.h>
+#include <Library/GpioLib.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+EFI_STATUS
+TypeJunctionCityPchLanConfig (
+ IN SYSTEM_CONFIGURATION *SystemConfig
+)
+{
+ DYNAMIC_SI_LIBARY_PPI *DynamicSiLibraryPpi = NULL;
+ EFI_STATUS Status;
+
+ Status = PeiServicesLocatePpi (&gDynamicSiLibraryPpiGuid, 0, NULL, &DynamicSiLibraryPpi);
+ if (EFI_ERROR (Status)) {
+ ASSERT_EFI_ERROR (Status);
+ return Status;
+ }
+
+ DynamicSiLibraryPpi->GpioSetOutputValue (GPIO_SKL_H_GPP_I9, (UINT32)SystemConfig->LomDisableByGpio);
+ DynamicSiLibraryPpi->PchDisableGbe ();
+
+ return EFI_SUCCESS;
+}
+
+EFI_STATUS
+TypeJunctionCityOemInitLateHook (
+ IN SYSTEM_CONFIGURATION *SystemConfig
+)
+{
+ return EFI_SUCCESS;
+}
+
+
+PLATFORM_PCH_EARLY_UPDATE_TABLE TypeJunctionCityPchEarlyUpdateTable =
+{
+ PLATFORM_PCH_EARLY_UPDATE_SIGNATURE,
+ PLATFORM_PCH_EARLY_UPDATE_VERSION,
+ TypeJunctionCityPchLanConfig,
+ TypeJunctionCityOemInitLateHook
+};
+
+
+/**
+ Entry point function for the PEIM
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS If we installed our PPI
+
+**/
+EFI_STATUS
+EFIAPI
+TypeJunctionCityPchEarlyUpdate(
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+ )
+{
+ EFI_STATUS Status;
+
+ Status = PeiServicesLocatePpi (
+ &gUbaConfigDatabasePpiGuid,
+ 0,
+ NULL,
+ &UbaConfigPpi
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPchEarlyConfigDataGuid,
+ &TypeJunctionCityPchEarlyUpdateTable,
+ sizeof(TypeJunctionCityPchEarlyUpdateTable)
+ );
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInit.h b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInit.h
new file mode 100644
index 0000000000..1c596a30c4
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInit.h
@@ -0,0 +1,78 @@
+/** @file
+ PeiBoardInit.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_BOARD_INIT_PEIM_H_
+#define _PEI_BOARD_INIT_PEIM_H_
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Ppi/UbaCfgDb.h>
+#include <Guid/PlatformInfo.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/HobLib.h>
+#include <Library/PeiServicesTablePointerLib.h>
+#include <Library/GpioLib.h>
+#include <GpioPinsSklH.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+// TypeJunctionCity
+EFI_STATUS
+TypeJunctionCityPlatformUpdateUsbOcMappings (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityPlatformUpdateAcpiTablePcds (
+ VOID
+);
+
+EFI_STATUS
+TypeJunctionCityInstallClockgenData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityInstallPcdData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityPchEarlyUpdate (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityIioPortBifurcationInit (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityInstallSlotTableData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+EFI_STATUS
+TypeJunctionCityInstallKtiEparamData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+
+// TypeJunctionCity
+EFI_STATUS
+TypeJunctionCityInstallGpioData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+) ;
+
+EFI_STATUS
+TypeJunctionCityInstallSoftStrapData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+);
+#endif // _PEI_BOARD_INIT_PEIM_H_
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.c
new file mode 100644
index 0000000000..7895f4d975
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.c
@@ -0,0 +1,157 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation.
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+
+/**
+ The constructor function for Board Init Libray.
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @retval EFI_SUCCESS Table initialization successfully.
+ @retval EFI_OUT_OF_RESOURCES No enough memory to initialize table.
+**/
+
+#include "PeiBoardInit.h"
+#include <UncoreCommonIncludes.h>
+#include <Library/PchMultiPchBase.h>
+#include <Ppi/DynamicSiLibraryPpi.h>
+
+EFI_STATUS
+EFIAPI
+TypeJunctionCityPeiBoardInitLibConstructor (
+ IN EFI_PEI_FILE_HANDLE FileHandle,
+ IN CONST EFI_PEI_SERVICES **PeiServices
+ )
+{
+ EFI_STATUS Status = EFI_SUCCESS;
+ UBA_CONFIG_DATABASE_PPI *UbaConfigPpi;
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+ UINT8 SocketIndex;
+ UINT8 ChannelIndex;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT (GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return EFI_NOT_FOUND;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA(GuidHob);
+
+ if (PlatformInfo->BoardId == TypeJunctionCity) {
+
+ DEBUG ((EFI_D_INFO, "PEI UBA init BoardId 0x%X: JunctionCity\n", PlatformInfo->BoardId));
+
+ // Socket 0 has SMT DIMM connector, Socket 1 has PTH DIMM connector
+ for (SocketIndex = 0; SocketIndex < MAX_SOCKET; SocketIndex++) {
+ for (ChannelIndex = 0; ChannelIndex < MAX_CH; ChannelIndex++) {
+ switch (SocketIndex) {
+ case 0:
+ PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = DimmConnectorSmt;
+ break;
+ case 1:
+ // Fall through since socket 1 is PTH type
+ default:
+ // Use the more restrictive type as the default case
+ PlatformInfo->MemoryConnectorType[SocketIndex][ChannelIndex] = DimmConnectorPth;
+ break;
+ }
+ }
+ }
+
+ BuildGuidDataHob (
+ &gEfiPlatformInfoGuid,
+ &(PlatformInfo),
+ sizeof (EFI_PLATFORM_INFO)
+ );
+
+ Status = PeiServicesLocatePpi (
+ &gUbaConfigDatabasePpiGuid,
+ 0,
+ NULL,
+ &UbaConfigPpi
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->InitSku (
+ UbaConfigPpi,
+ PlatformInfo->BoardId,
+ NULL,
+ NULL
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ Status = TypeJunctionCityInstallGpioData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityInstallPcdData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityInstallSoftStrapData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityPchEarlyUpdate (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityPlatformUpdateUsbOcMappings (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityInstallSlotTableData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = TypeJunctionCityInstallKtiEparamData (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ for (SocketIndex = 0; SocketIndex < MAX_SOCKET; SocketIndex++) {
+
+ //
+ // Set default memory type connector.
+ // Socket 0: DimmConnectorSmt
+ // Socket 1: DimmConnectorPth
+ //
+ if (SocketIndex % 2 == 0) {
+ (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketIndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnectorSmt);
+ } else {
+ (*PeiServices)->SetMem (&PlatformInfo->MemoryConnectorType[SocketIndex], sizeof (PlatformInfo->MemoryConnectorType[SocketIndex]), DimmConnectorPth);
+ }
+ }
+
+ //
+ // Initialize InterposerType to InterposerUnknown
+ //
+ for (SocketIndex = 0; SocketIndex < MAX_SOCKET; ++SocketIndex) {
+ PlatformInfo->InterposerType[SocketIndex] = InterposerUnknown;
+ }
+
+ //
+ // TypeJunctionCityIioPortBifurcationInit will use PlatformInfo->InterposerType for PPO.
+ //
+ Status = TypeJunctionCityIioPortBifurcationInit (UbaConfigPpi);
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+ }
+ return Status;
+}
\ No newline at end of file
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.inf b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.inf
new file mode 100644
index 0000000000..ee6fdb95ff
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.inf
@@ -0,0 +1,167 @@
+## @file
+# Component information file for BoardInitLib in PEI post memory phase.
+#
+# @copyright
+# Copyright 2018 - 2021 Intel Corporation.
+# Copyright (c) 2021, American Megatrends International LLC. <BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+# @par Specification Reference:
+#
+##
+
+[Defines]
+ INF_VERSION = 0x00010005
+ BASE_NAME = TypeJunctionCityPeiBoardInitLib
+ FILE_GUID = F92478AE-058E-4E2A-939C-B806D461398E
+ MODULE_TYPE = PEIM
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = NULL|PEIM
+ CONSTRUCTOR = TypeJunctionCityPeiBoardInitLibConstructor
+
+[LibraryClasses]
+ BaseLib
+ DebugLib
+ BaseMemoryLib
+ MemoryAllocationLib
+ PeiServicesLib
+ HobLib
+ PeiServicesTablePointerLib
+
+[Packages]
+ MdePkg/MdePkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ WhitleySiliconPkg/WhitleySiliconPkg.dec
+ WhitleyOpenBoardPkg/PlatformPkg.dec
+ WhitleySiliconPkg/SiliconPkg.dec
+ WhitleySiliconPkg/CpRcPkg.dec
+
+[Sources]
+ PeiBoardInitLib.c
+ GpioTable.c
+ PcdData.c
+ UsbOC.c
+ AcpiTablePcds.c
+ IioBifurInit.c
+ SlotTable.c
+ KtiEparam.c
+ PchEarlyUpdate.c
+ SoftStrapFixup.c
+ PeiBoardInit.h
+
+[FixedPcd]
+
+[Pcd]
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardID
+ gOemSkuTokenSpaceGuid.PcdOemSkuSubBoardID
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardFamily
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuFamilyName
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardName
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuBoardSocketCount
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuMaxChannel
+ gOemSkuTokenSpaceGuid.PcdOemSkuMaxDimmPerChannel
+ gOemSkuTokenSpaceGuid.PcdOemSkuDimmLayout
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort00
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort01
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort02
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort03
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort04
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort05
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort06
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort07
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort08
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort09
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort10
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort11
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort12
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbOverCurrentPort13
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort00
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort01
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort02
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort03
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort04
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort05
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort06
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort07
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort08
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort09
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort10
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort11
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort12
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsbPortLengthPort13
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort00
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort01
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort02
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort03
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort04
+ gOemSkuTokenSpaceGuid.PcdOemSkuPchUsb3OverCurrentPort05
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuAcpiName
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuMrlAttnLed
+ gOemSkuTokenSpaceGuid.PcdOemSkuSdpActiveFlag
+
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL2_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_USE_SEL3_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL2_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_IO_SEL3_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL2_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_LVL3_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_INV_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_BLINK_VAL
+ gOemSkuTokenSpaceGuid.PcdOemSku_GPIO_TABLE_SIZE
+
+ gOemSkuTokenSpaceGuid.PcdOemSku_Reg78Data32
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator00
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator01
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator02
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator03
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator04
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator05
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator06
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator07
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator08
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator09
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator10
+ gOemSkuTokenSpaceGuid.PcdOemSkuClockGenerator11
+
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformName
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformNameSize
+ gOemSkuTokenSpaceGuid.PcdOemSkuPlatformFeatureFlag
+ gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIO
+ gOemSkuTokenSpaceGuid.PcdOemSkuAssertPostGPIOValue
+ gOemSkuTokenSpaceGuid.PcdOemSkuBmcPciePortNumber
+ gOemSkuTokenSpaceGuid.PcdOemTableIdXhci
+ gOemSkuTokenSpaceGuid.PcdOemSkuUplinkPortIndex
+ gPlatformTokenSpaceGuid.PcdBoardTypeBitmask
+ gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrP1V8
+ gPlatformTokenSpaceGuid.PcdWilsonCitySvidVrVccAna
+ gEfiCpRcPkgTokenSpaceGuid.PcdImonAddr
+ gEfiCpRcPkgTokenSpaceGuid.PcdMemSrvidMap
+
+ gPlatformTokenSpaceGuid.PcdMemInterposerMap
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciVendorId
+ gPlatformTokenSpaceGuid.PcdOnboardVideoPciDeviceId
+
+[Ppis]
+ gUbaConfigDatabasePpiGuid
+ gDynamicSiLibraryPpiGuid ## CONSUMES
+
+[Guids]
+ gPlatformGpioInitDataGuid
+
+[Depex]
+ gDynamicSiLibraryPpiGuid
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SlotTable.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SlotTable.c
new file mode 100644
index 0000000000..963515ea41
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SlotTable.c
@@ -0,0 +1,172 @@
+/** @file
+ Slot Table Update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaSlotUpdateLib.h>
+#include <IioPlatformData.h>
+
+#define PCI_DEVICE_ON_BOARD_TRUE 0
+#define PCI_DEVICE_ON_BOARD_FALSE 1
+
+typedef enum {
+ Iio_Socket0 = 0,
+ Iio_Socket1,
+ Iio_Socket2,
+ Iio_Socket3,
+ Iio_Socket4,
+ Iio_Socket5,
+ Iio_Socket6,
+ Iio_Socket7
+} IIO_SOCKETS;
+
+typedef enum {
+ Iio_Iou0 =0,
+ Iio_Iou1,
+ Iio_Iou2,
+ Iio_Iou3,
+ Iio_Iou4,
+ Iio_IouMax
+} IIO_IOUS;
+
+typedef enum {
+ Bw5_Addr_0 = 0,
+ Bw5_Addr_1,
+ Bw5_Addr_2,
+ Bw5_Addr_3,
+ Bw5_Addr_Max
+} BW5_ADDRESS;
+
+static UINT8 TypeJunctionCityPchPciSlotImpementedTableData[] = {
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 0
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 1
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 2
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 3
+ PCI_DEVICE_ON_BOARD_TRUE, // Root Port 4
+ PCI_DEVICE_ON_BOARD_TRUE, // Root Port 5
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 6
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 7
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 8
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 9
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 10
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 11
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 12
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 13
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 14
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 15
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 16
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 17
+ PCI_DEVICE_ON_BOARD_FALSE, // Root Port 18
+ PCI_DEVICE_ON_BOARD_FALSE // Root Port 19
+};
+
+UINT8
+GetTypeJunctionCityIOU0Setting (
+ UINT8 IOU0Data
+)
+{
+ //
+ // Change bifurcation of Port1A-1B as xxx8 when QATGpio enabled.
+ //
+ IOU0Data = IIO_BIFURCATE_xxx8xxx8;
+ return IOU0Data;
+}
+
+UINT8
+GetTypeJunctionCityIOU2Setting (
+ UINT8 SkuPersonalityType,
+ UINT8 IOU2Data
+)
+{
+ return IOU2Data;
+}
+
+static IIO_BROADWAY_ADDRESS_DATA_ENTRY SlotTypeJunctionCityBroadwayTable[] = {
+ {Iio_Socket0, Iio_Iou2, Bw5_Addr_0 },
+ {Iio_Socket1, Iio_Iou1, Bw5_Addr_2},
+ {Iio_Socket1, Iio_Iou0, Bw5_Addr_1 },
+};
+
+
+PLATFORM_SLOT_UPDATE_TABLE TypeJunctionCitySlotTable =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeJunctionCityBroadwayTable,
+ GetTypeJunctionCityIOU0Setting,
+ 0
+};
+
+PLATFORM_SLOT_UPDATE_TABLE2 TypeJunctionCitySlotTable2 =
+{
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ SlotTypeJunctionCityBroadwayTable,
+ GetTypeJunctionCityIOU0Setting,
+ 0,
+ GetTypeJunctionCityIOU2Setting
+};
+
+PLATFORM_PCH_PCI_SLOT_IMPLEMENTED_UPDATE_TABLE TypeJunctionCityPchPciSlotImplementedTable = {
+ PLATFORM_SLOT_UPDATE_SIGNATURE,
+ PLATFORM_SLOT_UPDATE_VERSION,
+
+ TypeJunctionCityPchPciSlotImpementedTableData
+};
+
+/**
+ Entry point function for the PEIM
+
+ @param FileHandle Handle of the file being invoked.
+ @param PeiServices Describes the list of possible PEI Services.
+
+ @return EFI_SUCCESS If we installed our PPI
+
+**/
+EFI_STATUS
+TypeJunctionCityInstallSlotTableData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformSlotDataGuid,
+ &TypeJunctionCitySlotTable,
+ sizeof(TypeJunctionCitySlotTable)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformSlotDataGuid2,
+ &TypeJunctionCitySlotTable2,
+ sizeof(TypeJunctionCitySlotTable2)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPciSlotImplementedGuid,
+ &TypeJunctionCityPchPciSlotImplementedTable,
+ sizeof(TypeJunctionCityPchPciSlotImplementedTable)
+ );
+ if (EFI_ERROR(Status)) {
+ return Status;
+ }
+
+ return Status;
+}
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SoftStrapFixup.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SoftStrapFixup.c
new file mode 100644
index 0000000000..541961b020
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/SoftStrapFixup.c
@@ -0,0 +1,121 @@
+/** @file
+ Soft Strap update.
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+#include <Library/UbaSoftStrapUpdateLib.h>
+
+PLATFORM_PCH_SOFTSTRAP_FIXUP_ENTRY TypeJunctionCitySoftStrapTable[] =
+{
+// SoftStrapNumber, LowBit, BitLength, Value
+ {3, 1, 1, 0x1 }, // Intel QuickAssist Endpoint 2 (EP[2]) Primary Mux Select
+ {4, 24, 1, 0x0 }, // 10 GbE MAC Power Gate Control
+ {15, 4, 2, 0x3 }, // sSATA / PCIe Select for Port 2 (SATA_PCIE_SP2)
+ {15, 6, 2, 0x1 }, // sSATA / PCIe Select for Port 3 (SATA_PCIE_SP3)
+ {15, 18, 1, 0x1 }, // Polarity of GPP_H20 (GPIO polarity of Select between sSATA Port 2 and PCIe Port 8)
+ {16, 4, 2, 0x3 }, // sSATA / PCIe GP Select for Port 2 (SATA_PCIE_GP2)
+ {16, 6, 2, 0x1 }, // sSATA / PCIe GP Select for Port 3 (SATA_PCIE_GP3)
+ {17, 6, 1, 0x0 }, // Intel (R) GbE Legacy PHY over PCIe Enabled
+ {17, 12, 2, 0x3 }, // sSATA / PCIe Combo Port 2
+ {18, 0, 2, 0x1 }, // sSATA / PCIe Combo Port 3
+ {18, 6, 2, 0x3 }, // SATA / PCIe Combo Port 0
+ {18, 8, 2, 0x3 }, // SATA / PCIe Combo Port 1
+ {18, 10, 2, 0x3 }, // SATA / PCIe Combo Port 2
+ {18, 12, 2, 0x3 }, // SATA / PCIe Combo Port 3
+ {18, 14, 2, 0x3 }, // SATA / PCIe Combo Port 4
+ {19, 2, 1, 0x1 }, // Polarity Select sSATA / PCIe Combo Port 2
+ {19, 16, 2, 0x3 }, // SATA / PCIe Combo Port 5
+ {19, 18, 2, 0x3 }, // SATA / PCIe Combo Port 6
+ {19, 20, 2, 0x3 }, // SATA / PCIe Combo Port 7
+ {19, 26, 1, 0x1 }, // Statically assign PCH PCIe NP8 Uplink to act as Downlink or Uplink(PCIEUDS)
+ {33, 24, 7, 0x17}, // IE SMLink1 I2C Target Address
+ {64, 24, 7, 0x17}, // ME SMLink1 I2C Target Address
+ {84, 24, 1, 0x0 }, // SMS1 Gbe Legacy MAC SMBus Address Enable
+ {85, 8, 3, 0x0 }, // SMS1 PMC SMBus Connect
+ {88, 8, 2, 0x3 }, // Root Port Configuration 0
+ {93, 0, 2, 0x3 }, // Flex IO Port 18 AUXILLARY Mux Select between SATA Port 0 and PCIe Port 12
+ {93, 2, 2, 0x3 }, // Flex IO Port 19 AUXILLARY Mux Select between SATA Port 1 and PCIe Port 13
+ {93, 4, 2, 0x3 }, // Flex IO Port 20 AUXILLARY Mux Select between SATA Port 2 and PCIe Port 14
+ {94, 0, 2, 0x3 }, // Flex IO Port 21 AUXILLARY Mux Select between SATA Port 3 and PCIe Port 15
+ {94, 2, 2, 0x3 }, // Flex IO Port 22 AUXILLARY Mux Select between SATA Port 4 and PCIe Port 16
+ {94, 4, 2, 0x3 }, // Flex IO Port 23 AUXILLARY Mux Select between SATA Port 5 and PCIe Port 17
+ {94, 6, 2, 0x3 }, // Flex IO Port 24 AUXILLARY Mux Select between SATA Port 6 and PCIe Port 18
+ {94, 8, 2, 0x3 }, // Flex IO Port 25 AUXILLARY Mux Select between SATA Port 7 and PCIe Port 19
+ {102, 0, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 0 and PCIe Port 12
+ {102, 2, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 1 and PCIe Port 13
+ {102, 4, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 2 and PCIe Port 14
+ {102, 6, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 3 and PCIe Port 15
+ {102, 8, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 4 and PCIe Port 16
+ {102, 10, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 5 and PCIe Port 17
+ {102, 12, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 6 and PCIe Port 18
+ {102, 14, 2, 0x3 }, // Flex IO Port 18 Mux Select between SATA Port 7 and PCIe Port 19
+ {103, 16, 3, 0x0 }, // GbE Legacy PHY Smbus Connection
+ {103, 26, 1, 0x0 }, // GbE Legacy LCD SMBus PHY Address Enabled
+ {103, 27, 1, 0x0 }, // GbE Legacy LC SMBus Address Enabled
+// {133, 1, 1, 0x1 }, // Dual I/O Read Enabled
+// {133, 2, 1, 0x1 }, // Quad Output Read Enabled
+// {133, 3, 1, 0x1 }, // Quad I/O Read Enabled
+// {136, 10, 2, 0x3 }, // eSPI / EC Maximum I/O Mode
+// {136, 12, 1, 0x1 }, // Slave 1 (2nd eSPI device) Enable
+// {136, 16, 3, 0x4 }, // eSPI / EC Slave 1 Device Bus Frequency
+// {136, 19, 2, 0x3 }, // eSPI / EC Slave Device Maximum I/O Mode
+
+//
+// END OF LIST
+//
+ {0, 0, 0, 0}
+};
+
+UINT32
+TypeJunctionCitySystemBoardRevIdValue (VOID)
+{
+ EFI_HOB_GUID_TYPE *GuidHob;
+ EFI_PLATFORM_INFO *PlatformInfo;
+
+ GuidHob = GetFirstGuidHob (&gEfiPlatformInfoGuid);
+ ASSERT(GuidHob != NULL);
+ if (GuidHob == NULL) {
+ return 0xFF;
+ }
+ PlatformInfo = GET_GUID_HOB_DATA(GuidHob);
+ return PlatformInfo->TypeRevisionId;
+}
+
+VOID
+TypeJunctionCityPlatformSpecificUpdate (
+ IN OUT UINT8 *FlashDescriptorCopy
+ )
+{
+}
+
+PLATFORM_PCH_SOFTSTRAP_UPDATE TypeJunctionCitySoftStrapUpdate =
+{
+ PLATFORM_SOFT_STRAP_UPDATE_SIGNATURE,
+ PLATFORM_SOFT_STRAP_UPDATE_VERSION,
+ TypeJunctionCitySoftStrapTable,
+ TypeJunctionCityPlatformSpecificUpdate
+};
+
+EFI_STATUS
+TypeJunctionCityInstallSoftStrapData (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+ )
+{
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPlatformPchSoftStrapConfigDataGuid,
+ &TypeJunctionCitySoftStrapUpdate,
+ sizeof(TypeJunctionCitySoftStrapUpdate)
+ );
+
+ return Status;
+}
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/UsbOC.c b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/UsbOC.c
new file mode 100644
index 0000000000..eaf59de869
--- /dev/null
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaMain/TypeJunctionCity/Pei/UsbOC.c
@@ -0,0 +1,127 @@
+/** @file
+
+ @copyright
+ Copyright 2018 - 2021 Intel Corporation. <BR>
+ Copyright (c) 2021, American Megatrends International LLC. <BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "PeiBoardInit.h"
+
+
+#include <Library/PcdLib.h>
+#include <Library/UbaUsbOcUpdateLib.h>
+#include <PchLimits.h>
+#include <ConfigBlock/UsbConfig.h>
+#include <ConfigBlock/Usb2PhyConfig.h>
+
+USB_OVERCURRENT_PIN TypeJunctionCityUsb20OverCurrentMappings[PCH_MAX_USB2_PORTS] = {
+ UsbOverCurrentPin0,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin2,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPin7,
+ UsbOverCurrentPin7,
+ UsbOverCurrentPin6,
+ UsbOverCurrentPin4,
+ UsbOverCurrentPin6,
+ UsbOverCurrentPin4,
+ UsbOverCurrentPin5,
+ UsbOverCurrentPin4,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB_OVERCURRENT_PIN TypeJunctionCityUsb30OverCurrentMappings[PCH_MAX_USB3_PORTS] = {
+ UsbOverCurrentPin0,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin1,
+ UsbOverCurrentPin2,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPin3,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip,
+ UsbOverCurrentPinSkip
+ };
+
+USB2_PHY_PARAMETERS TypeJunctionCityUsb20AfeParams[PCH_H_XHCI_MAX_USB2_PHYSICAL_PORTS] = {
+ {3, 0, 3, 1}, // PP0
+ {5, 0, 3, 1}, // PP1
+ {3, 0, 3, 1}, // PP2
+ {0, 5, 1, 1}, // PP3
+ {3, 0, 3, 1}, // PP4
+ {3, 0, 3, 1}, // PP5
+ {3, 0, 3, 1}, // PP6
+ {3, 0, 3, 1}, // PP7
+ {2, 2, 1, 0}, // PP8
+ {6, 0, 2, 1}, // PP9
+ {2, 2, 1, 0}, // PP10
+ {6, 0, 2, 1}, // PP11
+ {0, 5, 1, 1}, // PP12
+ {7, 0, 2, 1}, // PP13
+ };
+
+EFI_STATUS
+TypeJunctionCityPlatformUsbOcUpdateCallback (
+ IN OUT USB_OVERCURRENT_PIN **Usb20OverCurrentMappings,
+ IN OUT USB_OVERCURRENT_PIN **Usb30OverCurrentMappings,
+ IN OUT USB2_PHY_PARAMETERS **Usb20AfeParams
+)
+{
+ *Usb20OverCurrentMappings = &TypeJunctionCityUsb20OverCurrentMappings[0];
+ *Usb30OverCurrentMappings = &TypeJunctionCityUsb30OverCurrentMappings[0];
+
+ *Usb20AfeParams = TypeJunctionCityUsb20AfeParams;
+ return EFI_SUCCESS;
+}
+
+PLATFORM_USBOC_UPDATE_TABLE TypeJunctionCityUsbOcUpdate =
+{
+ PLATFORM_USBOC_UPDATE_SIGNATURE,
+ PLATFORM_USBOC_UPDATE_VERSION,
+ TypeJunctionCityPlatformUsbOcUpdateCallback
+};
+
+EFI_STATUS
+TypeJunctionCityPlatformUpdateUsbOcMappings (
+ IN UBA_CONFIG_DATABASE_PPI *UbaConfigPpi
+)
+{
+ //#
+ //# USB, see PG 104 in GZP SCH
+ //#
+
+// USB2 USB3 Port OC
+//
+//Port00: PORT5 Back Panel ,OC0#
+//Port01: PORT2 Back Panel ,OC0#
+//Port02: PORT3 Back Panel ,OC1#
+//Port03: PORT0 NOT USED ,NA
+//Port04: BMC1.0 ,NA
+//Port05: INTERNAL_2X5_A ,OC2#
+//Port06: INTERNAL_2X5_A ,OC2#
+//Port07: NOT USED ,NA
+//Port08: EUSB (AKA SSD) ,NA
+//Port09: INTERNAL_TYPEA ,OC6#
+//Port10: PORT1 Front Panel ,OC5#
+//Port11: NOT USED ,NA
+//Port12: BMC2.0 ,NA
+//Port13: PORT4 Front Panel ,OC5#
+
+ EFI_STATUS Status;
+
+ Status = UbaConfigPpi->AddData (
+ UbaConfigPpi,
+ &gPeiPlatformUbaOcConfigDataGuid,
+ &TypeJunctionCityUsbOcUpdate,
+ sizeof(TypeJunctionCityUsbOcUpdate)
+ );
+
+ return Status;
+}
+
+
diff --git a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
index f37093bccd..f527632f4f 100644
--- a/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
+++ b/Platform/Intel/WhitleyOpenBoardPkg/Uba/UbaRpBoards.dsc
@@ -3,6 +3,7 @@
#

# @copyright

# Copyright 2012 - 2021 Intel Corporation. <BR>

+# Copyright (c) 2021, American Megatrends International LLC. <BR>

#

# SPDX-License-Identifier: BSD-2-Clause-Patent

##

@@ -16,6 +17,7 @@ $(RP_PKG)/Uba/BoardInit/Pei/BoardInitPei.inf {
NULL|$(RP_PKG)/Uba/UbaMain/TypeWilsonCityRP/Pei/PeiBoardInitLib.inf

NULL|$(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Pei/PeiBoardInitLib.inf

NULL|$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Pei/PeiBoardInitLib.inf

+ NULL|$(RP_PKG)/Uba/UbaMain/TypeJunctionCity/Pei/PeiBoardInitLib.inf

#

#### NO PLATFORM SPECIFIC LIBRARY CLASSES AFTER THIS LINE!!!!

#

@@ -50,3 +52,10 @@ $(RP_PKG)/Uba/UbaMain/TypeCooperCityRP/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.i
$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf

$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf

$(RP_PKG)/Uba/UbaMain/TypeWilsonCitySMT/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf

+

+#

+# Platform TypeJunctionCity

+#

+$(RP_PKG)/Uba/UbaMain/TypeJunctionCity/Dxe/UsbOcUpdateDxe/UsbOcUpdateDxe.inf

+$(RP_PKG)/Uba/UbaMain/TypeJunctionCity/Dxe/IioCfgUpdateDxe/IioCfgUpdateDxe.inf

+$(RP_PKG)/Uba/UbaMain/TypeJunctionCity/Dxe/SlotDataUpdateDxe/SlotDataUpdateDxe.inf

diff --git a/Platform/Intel/build.cfg b/Platform/Intel/build.cfg
index 2827334797..de656633cd 100644
--- a/Platform/Intel/build.cfg
+++ b/Platform/Intel/build.cfg
@@ -67,3 +67,4 @@ TigerlakeURvp = TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg
CooperCityRvp = WhitleyOpenBoardPkg/CooperCityRvp/build_config.cfg

WilsonCityRvp = WhitleyOpenBoardPkg/WilsonCityRvp/build_config.cfg

BoardTiogaPass = PurleyOpenBoardPkg/BoardTiogaPass/build_config.cfg

+JunctionCity = WhitleyOpenBoardPkg/JunctionCity/build_config.cfg

diff --git a/Readme.md b/Readme.md
index 62876b4b7d..78771ff82d 100644
--- a/Readme.md
+++ b/Readme.md
@@ -248,6 +248,7 @@ they will be documented with the platform.
* [Comet Lake](Platform/Intel/CometlakeOpenBoardPkg)

* [Tiger Lake](Platform/Intel/TigerlakeOpenBoardPkg)

* [Whitley/Cedar Island](Platform/Intel/WhitleyOpenBoardPkg)

+* [Whitley/JunctionCity](Platform/Intel/WhitleyOpenBoardPkg)



For more information, see the

[EDK II Minimum Platform Specification](https://nam12.safelinks.protection.outlook.com/?url=https%3A%2F%2Fedk2-docs.gitbooks.io%2Fedk-ii-minimum-platform-specification&;data=04%7C01%7Cmanickavasakamk%40ami.com%7Cc74234f0d053445b29a208d9b9b8622e%7C27e97857e15f486cb58e86c2b3040f93%7C1%7C0%7C637745023862725733%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&amp;sdata=rpJCIfluwlrpygIOcnsxPoqfoSBb1pLam5Z%2BUguddjQ%3D&amp;reserved=0).

diff --git a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
index ca91434663..bdbf6a8d02 100644
--- a/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
+++ b/Silicon/Intel/WhitleySiliconPkg/Include/PlatformInfoTypes.h
@@ -2,6 +2,7 @@


@copyright

Copyright 2020 - 2021 Intel Corporation. <BR>

+ Copyright (c) 2021, American Megatrends International LLC.<BR>



SPDX-License-Identifier: BSD-2-Clause-Patent

**/

@@ -63,6 +64,7 @@ typedef enum {
TypeArcherCityXPV,

TypeBigPineKey,

TypeExperWorkStationRP,

+ TypeJunctionCity,

EndOfEfiPlatformTypeEnum

} EFI_PLATFORM_TYPE;



--
2.25.0.windows.1


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-The information contained in this message may be confidential and proprietary to American Megatrends (AMI). This communication is intended to be read only by the individual or entity to whom it is addressed or by their designee. If the reader of this message is not the intended recipient, you are on notice that any distribution of this message, in any form, is strictly prohibited. Please promptly notify the sender by reply e-mail or by telephone at 770-246-8600, and then delete or destroy all copies of the transmission.


Re: [edk2-platforms][PATCH V1 04/11] Platform/ARM/Morello: Add ConfigurationManager for Morello SoC

chandni cherukuri
 

Hi Khasim,

The modifications would have to be done for both Morello FVP and
Morello SoC platforms and
can be taken up as part of changes to align both the platforms.

Thanks
Chandni

On Wed, Dec 8, 2021 at 8:32 AM Khasim Mohammed <khasim.mohammed@arm.com> wrote:

Hi Chandni,

One input,

On Sat, Dec 4, 2021 at 04:31 AM, chandni cherukuri wrote:

This patch implements the configuration manager for Morello
SoC platform. It enables support for generating the following
ACPI tables for Morello SoC Platform:
1. FADT
2. DSDT
3. GTDT
4. MADT
5. SPCR
6. DBG2
7. PPTT

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
---
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerSoc.dsc.inc | 16 ++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeSoc.inf | 72 +++++++++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.h | 97 ++++++++++++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.c | 161 ++++++++++++++++++++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtSoc.asl | 41 +++++
5 files changed, 387 insertions(+)

diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerSoc.dsc.inc b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerSoc.dsc.inc
new file mode 100644
index 000000000000..f7e58185696e
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerSoc.dsc.inc

I think there is no need for this separate .dsc.inc file, can you please refer to the N1SDP implementation, I had received a suggestion from Pierre after which I had removed a similar file in N1SDP patch set.



@@ -0,0 +1,16 @@
+## @file
+# dsc include file for Configuration Manager
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+
+[BuildOptions]
+
+[Components.common]
+ # Configuration Manager
+ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeSoc.inf
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeSoc.inf b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeSoc.inf
new file mode 100644
index 000000000000..6f9199a6fda2
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeSoc.inf
@@ -0,0 +1,72 @@
+## @file
+# Configuration Manager Dxe
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = ConfigurationManagerDxe
+ FILE_GUID = BF8FBCEE-AD95-466B-9185-50A1BB651DDA
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = ConfigurationManagerDxeInitialize
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+
+[Sources]
+ AslTables/DsdtSoc.asl
+ ConfigurationManager.c
+ ConfigurationManager.h
+ ConfigurationManagerSoc.c
+ ConfigurationManagerSoc.h
+ Platform.h
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ DynamicTablesPkg/DynamicTablesPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/Morello/MorelloPlatform.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+
+[Protocols]
+ gEdkiiConfigurationManagerProtocolGuid
+
+[FixedPcd]
+ ## PL011 Serial Debug UART
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz
+
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ # SBSA Generic Watchdog
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+
+[Depex]
+ TRUE
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.h b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.h
new file mode 100644
index 000000000000..8a521b83c8dc
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.h
@@ -0,0 +1,97 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+ - Cm or CM - Configuration Manager
+ - Obj or OBJ - Object
+**/
+
+#ifndef SOC_CONFIGURATION_MANAGER_H_
+#define SOC_CONFIGURATION_MANAGER_H_
+
+#include "ConfigurationManager.h"
+
+/** The number of ACPI tables to install
+*/
+#define PLAT_ACPI_TABLE_COUNT 7
+
+/** A helper macro for mapping a reference token
+*/
+#define REFERENCE_TOKEN_SOC(Field) \
+ (CM_OBJECT_TOKEN)((UINT8*)&MorelloSocRepositoryInfo + \
+ OFFSET_OF (EDKII_SOC_PLATFORM_REPOSITORY_INFO, Field))
+
+/** C array containing the compiled AML template.
+ These symbols are defined in the auto generated C file
+ containing the AML bytecode array.
+*/
+extern CHAR8 dsdtsoc_aml_code[];
+
+/** A structure describing the SoC Platform specific information
+*/
+typedef struct SocPlatformRepositoryInfo {
+ /// List of ACPI tables
+ CM_STD_OBJ_ACPI_TABLE_INFO CmAcpiTableList[PLAT_ACPI_TABLE_COUNT];
+} EDKII_SOC_PLATFORM_REPOSITORY_INFO;
+
+/** A structure describing the platform configuration
+ manager repository information
+*/
+typedef struct PlatformRepositoryInfo {
+ /// Common information
+ EDKII_COMMON_PLATFORM_REPOSITORY_INFO *CommonPlatRepoInfo;
+
+ /// SoC Platform specific information
+ EDKII_SOC_PLATFORM_REPOSITORY_INFO *SocPlatRepoInfo;
+} EDKII_PLATFORM_REPOSITORY_INFO;
+
+extern EDKII_COMMON_PLATFORM_REPOSITORY_INFO CommonPlatformInfo;
+
+/** Return platform specific ARM namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetArmNameSpaceObjectPlat (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject
+ );
+
+/** Return platform specific standard namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetStandardNameSpaceObjectPlat (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject
+ );
+
+#endif // SOC_CONFIGURATION_MANAGER_H_
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.c b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.c
new file mode 100644
index 000000000000..7ca8ae212a61
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.c
@@ -0,0 +1,161 @@
+/** @file
+ Configuration Manager Dxe
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+ - Cm or CM - Configuration Manager
+ - Obj or OBJ - Object
+**/
+
+#include <IndustryStandard/DebugPort2Table.h>
+#include <IndustryStandard/IoRemappingTable.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/ConfigurationManagerProtocol.h>
+
+#include "ConfigurationManagerSoc.h"
+#include "Platform.h"
+
+EDKII_SOC_PLATFORM_REPOSITORY_INFO MorelloSocRepositoryInfo = {
+ // ACPI Table List
+ {
+ // FADT Table
+ {
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdFadt),
+ NULL
+ },
+ // GTDT Table
+ {
+ EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdGtdt),
+ NULL
+ },
+ // MADT Table
+ {
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMadt),
+ NULL
+ },
+ // SPCR Table
+ {
+ EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSpcr),
+ NULL
+ },
+ // DSDT Table
+ {
+ EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ 0, // Unused
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDsdt),
+ (EFI_ACPI_DESCRIPTION_HEADER *)dsdtsoc_aml_code
+ },
+ // DBG2 Table
+ {
+ EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDbg2),
+ NULL
+ },
+ // PPTT Table
+ {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdPptt),
+ NULL
+ },
+ },
+};
+
+EDKII_PLATFORM_REPOSITORY_INFO MorelloRepositoryInfo = {
+ &CommonPlatformInfo,
+ &MorelloSocRepositoryInfo
+};
+
+/** Return platform specific ARM namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetArmNameSpaceObjectPlat (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject
+ )
+{
+ return EFI_NOT_FOUND;
+}
+
+/** Return platform specific standard namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetStandardNameSpaceObjectPlat (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject
+ )
+{
+ EFI_STATUS Status;
+ EDKII_SOC_PLATFORM_REPOSITORY_INFO *PlatformRepo;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_NOT_FOUND;
+ PlatformRepo = This->PlatRepoInfo->SocPlatRepoInfo;
+
+ switch (GET_CM_OBJECT_ID (CmObjectId)) {
+ case EStdObjAcpiTableList:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->CmAcpiTableList,
+ sizeof (PlatformRepo->CmAcpiTableList),
+ ARRAY_SIZE (PlatformRepo->CmAcpiTableList),
+ CmObject
+ );
+ break;
+
+ default:
+ {
+ break;
+ }
+ }
+
+ return Status;
+}
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtSoc.asl b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtSoc.asl
new file mode 100644
index 000000000000..806e170515b7
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtSoc.asl
@@ -0,0 +1,41 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2021, ARM Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Reference(s):
+ - ACPI for Arm Components 1.0, Platform Design Document
+
+**/
+
+#include "ConfigurationManager.h"
+
+DefinitionBlock("Dsdt.aml", "DSDT", 1, "ARMLTD", "MORELLO", CFG_MGR_OEM_REVISION) {
+ Scope(_SB) {
+ Device(CP00) { // Cluster 0, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ Name(_STA, 0xF)
+ }
+
+ Device(CP01) { // Cluster 0, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 1)
+ Name(_STA, 0xF)
+ }
+
+ Device(CP02) { // Cluster 1, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 2)
+ Name(_STA, 0xF)
+ }
+
+ Device(CP03) { // Cluster 1, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 3)
+ Name(_STA, 0xF)
+ }
+ } // Scope(_SB)
+}
--
2.17.1


Re: [edk2-platforms][PATCH V1 04/11] Platform/ARM/Morello: Add ConfigurationManager for Morello SoC

chandni cherukuri
 

Hi Sami,

Thanks for reviewing the patch.
Sure, will try to use the SSDT CPU generator for both the Morello FVP
and Morello SoC platforms.

Thanks
Chandni

On Wed, Dec 8, 2021 at 2:22 AM Sami Mujawar <sami.mujawar@arm.com> wrote:

Hi Chandni,

Since you have the CPU information in MADT.GICC and the PPTT table, it
should be possible to use the SSDT CPU generator to create the AML
description for the CPUs. This patch series can go ahead. However, you
may want to consider using the SSDT Cpu Generator in the furture.

Otherwise, these changes look good to me.

Reviewed-by: Sami Mujawar <sami.mujawar@arm.com>

Regards,

Sami Mujawar



On 04/12/2021 12:30 PM, Chandni Cherukuri wrote:
This patch implements the configuration manager for Morello
SoC platform. It enables support for generating the following
ACPI tables for Morello SoC Platform:
1. FADT
2. DSDT
3. GTDT
4. MADT
5. SPCR
6. DBG2
7. PPTT

Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
---
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerSoc.dsc.inc | 16 ++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeSoc.inf | 72 +++++++++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.h | 97 ++++++++++++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.c | 161 ++++++++++++++++++++
Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtSoc.asl | 41 +++++
5 files changed, 387 insertions(+)

diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerSoc.dsc.inc b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerSoc.dsc.inc
new file mode 100644
index 000000000000..f7e58185696e
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerSoc.dsc.inc
@@ -0,0 +1,16 @@
+## @file
+# dsc include file for Configuration Manager
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+
+[BuildOptions]
+
+[Components.common]
+ # Configuration Manager
+ Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeSoc.inf
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeSoc.inf b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeSoc.inf
new file mode 100644
index 000000000000..6f9199a6fda2
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxeSoc.inf
@@ -0,0 +1,72 @@
+## @file
+# Configuration Manager Dxe
+#
+# Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = ConfigurationManagerDxe
+ FILE_GUID = BF8FBCEE-AD95-466B-9185-50A1BB651DDA
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ ENTRY_POINT = ConfigurationManagerDxeInitialize
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = AARCH64
+#
+
+[Sources]
+ AslTables/DsdtSoc.asl
+ ConfigurationManager.c
+ ConfigurationManager.h
+ ConfigurationManagerSoc.c
+ ConfigurationManagerSoc.h
+ Platform.h
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ ArmPlatformPkg/ArmPlatformPkg.dec
+ DynamicTablesPkg/DynamicTablesPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/Morello/MorelloPlatform.dec
+
+[LibraryClasses]
+ UefiDriverEntryPoint
+
+[Protocols]
+ gEdkiiConfigurationManagerProtocolGuid
+
+[FixedPcd]
+ ## PL011 Serial Debug UART
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartBaudRate
+ gArmPlatformTokenSpaceGuid.PcdSerialDbgUartClkInHz
+
+ gArmPlatformTokenSpaceGuid.PL011UartClkInHz
+ gArmPlatformTokenSpaceGuid.PL011UartInterrupt
+
+ gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+ gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+
+ # SBSA Generic Watchdog
+ gArmTokenSpaceGuid.PcdGenericWatchdogControlBase
+ gArmTokenSpaceGuid.PcdGenericWatchdogEl2IntrNum
+ gArmTokenSpaceGuid.PcdGenericWatchdogRefreshBase
+
+ gArmTokenSpaceGuid.PcdGicDistributorBase
+ gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+ gArmTokenSpaceGuid.PcdGicRedistributorsBase
+
+ gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+ gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+
+[Depex]
+ TRUE
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.h b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.h
new file mode 100644
index 000000000000..8a521b83c8dc
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.h
@@ -0,0 +1,97 @@
+/** @file
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+ - Cm or CM - Configuration Manager
+ - Obj or OBJ - Object
+**/
+
+#ifndef SOC_CONFIGURATION_MANAGER_H_
+#define SOC_CONFIGURATION_MANAGER_H_
+
+#include "ConfigurationManager.h"
+
+/** The number of ACPI tables to install
+*/
+#define PLAT_ACPI_TABLE_COUNT 7
+
+/** A helper macro for mapping a reference token
+*/
+#define REFERENCE_TOKEN_SOC(Field) \
+ (CM_OBJECT_TOKEN)((UINT8*)&MorelloSocRepositoryInfo + \
+ OFFSET_OF (EDKII_SOC_PLATFORM_REPOSITORY_INFO, Field))
+
+/** C array containing the compiled AML template.
+ These symbols are defined in the auto generated C file
+ containing the AML bytecode array.
+*/
+extern CHAR8 dsdtsoc_aml_code[];
+
+/** A structure describing the SoC Platform specific information
+*/
+typedef struct SocPlatformRepositoryInfo {
+ /// List of ACPI tables
+ CM_STD_OBJ_ACPI_TABLE_INFO CmAcpiTableList[PLAT_ACPI_TABLE_COUNT];
+} EDKII_SOC_PLATFORM_REPOSITORY_INFO;
+
+/** A structure describing the platform configuration
+ manager repository information
+*/
+typedef struct PlatformRepositoryInfo {
+ /// Common information
+ EDKII_COMMON_PLATFORM_REPOSITORY_INFO *CommonPlatRepoInfo;
+
+ /// SoC Platform specific information
+ EDKII_SOC_PLATFORM_REPOSITORY_INFO *SocPlatRepoInfo;
+} EDKII_PLATFORM_REPOSITORY_INFO;
+
+extern EDKII_COMMON_PLATFORM_REPOSITORY_INFO CommonPlatformInfo;
+
+/** Return platform specific ARM namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetArmNameSpaceObjectPlat (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject
+ );
+
+/** Return platform specific standard namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetStandardNameSpaceObjectPlat (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject
+ );
+
+#endif // SOC_CONFIGURATION_MANAGER_H_
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.c b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.c
new file mode 100644
index 000000000000..7ca8ae212a61
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerSoc.c
@@ -0,0 +1,161 @@
+/** @file
+ Configuration Manager Dxe
+
+ Copyright (c) 2021, ARM Limited. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Glossary:
+ - Cm or CM - Configuration Manager
+ - Obj or OBJ - Object
+**/
+
+#include <IndustryStandard/DebugPort2Table.h>
+#include <IndustryStandard/IoRemappingTable.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
+#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Protocol/ConfigurationManagerProtocol.h>
+
+#include "ConfigurationManagerSoc.h"
+#include "Platform.h"
+
+EDKII_SOC_PLATFORM_REPOSITORY_INFO MorelloSocRepositoryInfo = {
+ // ACPI Table List
+ {
+ // FADT Table
+ {
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdFadt),
+ NULL
+ },
+ // GTDT Table
+ {
+ EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdGtdt),
+ NULL
+ },
+ // MADT Table
+ {
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMadt),
+ NULL
+ },
+ // SPCR Table
+ {
+ EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSpcr),
+ NULL
+ },
+ // DSDT Table
+ {
+ EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ 0, // Unused
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDsdt),
+ (EFI_ACPI_DESCRIPTION_HEADER *)dsdtsoc_aml_code
+ },
+ // DBG2 Table
+ {
+ EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,
+ EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDbg2),
+ NULL
+ },
+ // PPTT Table
+ {
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
+ EFI_ACPI_6_3_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdPptt),
+ NULL
+ },
+ },
+};
+
+EDKII_PLATFORM_REPOSITORY_INFO MorelloRepositoryInfo = {
+ &CommonPlatformInfo,
+ &MorelloSocRepositoryInfo
+};
+
+/** Return platform specific ARM namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetArmNameSpaceObjectPlat (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject
+ )
+{
+ return EFI_NOT_FOUND;
+}
+
+/** Return platform specific standard namespace object.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token An optional token identifying the object. If
+ unused this must be CM_NULL_TOKEN.
+ @param [in, out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+**/
+EFI_STATUS
+EFIAPI
+GetStandardNameSpaceObjectPlat (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL *CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token OPTIONAL,
+ IN OUT CM_OBJ_DESCRIPTOR *CONST CmObject
+ )
+{
+ EFI_STATUS Status;
+ EDKII_SOC_PLATFORM_REPOSITORY_INFO *PlatformRepo;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ Status = EFI_NOT_FOUND;
+ PlatformRepo = This->PlatRepoInfo->SocPlatRepoInfo;
+
+ switch (GET_CM_OBJECT_ID (CmObjectId)) {
+ case EStdObjAcpiTableList:
+ Status = HandleCmObject (
+ CmObjectId,
+ PlatformRepo->CmAcpiTableList,
+ sizeof (PlatformRepo->CmAcpiTableList),
+ ARRAY_SIZE (PlatformRepo->CmAcpiTableList),
+ CmObject
+ );
+ break;
+
+ default:
+ {
+ break;
+ }
+ }
+
+ return Status;
+}
diff --git a/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtSoc.asl b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtSoc.asl
new file mode 100644
index 000000000000..806e170515b7
--- /dev/null
+++ b/Platform/ARM/Morello/ConfigurationManager/ConfigurationManagerDxe/AslTables/DsdtSoc.asl
@@ -0,0 +1,41 @@
+/** @file
+ Differentiated System Description Table Fields (DSDT)
+
+ Copyright (c) 2021, ARM Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+ @par Reference(s):
+ - ACPI for Arm Components 1.0, Platform Design Document
+
+**/
+
+#include "ConfigurationManager.h"
+
+DefinitionBlock("Dsdt.aml", "DSDT", 1, "ARMLTD", "MORELLO", CFG_MGR_OEM_REVISION) {
+ Scope(_SB) {
+ Device(CP00) { // Cluster 0, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 0)
+ Name(_STA, 0xF)
+ }
+
+ Device(CP01) { // Cluster 0, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 1)
+ Name(_STA, 0xF)
+ }
+
+ Device(CP02) { // Cluster 1, Cpu 0
+ Name(_HID, "ACPI0007")
+ Name(_UID, 2)
+ Name(_STA, 0xF)
+ }
+
+ Device(CP03) { // Cluster 1, Cpu 1
+ Name(_HID, "ACPI0007")
+ Name(_UID, 3)
+ Name(_STA, 0xF)
+ }
+ } // Scope(_SB)
+}





Re: [PATCH V2 2/3] MdePkg/Base.h: Introduce various alignment-related macros

Marvin Häuser <mhaeuser@...>
 

Hey Mike,

Thanks! I agree using "offset" may make it more readable, but I haven't seen it being used much outside of memory terminology (the macro also applies to plain integers). Any feedback from the maintainers for preferences? Thanks!

Best regards,
Marvin

On 08.12.21 10:10, mjsbeaton@gmail.com wrote:
Can I tentatively suggest ALIGN_VALUE_OFFSET as a better name? (Speaking as a native English speaker, and with a relatively high level of command including technical language, addend is not at all a common word!) While I'm here additional ping and +1 for this to be merged, pls!


[PATCH v2 2/2] MdeModulePkg/BrotliCustomDecompressLib: Update brotli

Pedro Falcato
 

Update the brotli submodule to the latest commit (4ec6703)
so that the build isn't broken in GCC 11 compilers.

Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Hao A Wu <hao.a.wu@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com>
---
MdeModulePkg/Library/BrotliCustomDecompressLib/BrotliCustomDecompressLib.inf | 3 +++
MdeModulePkg/Library/BrotliCustomDecompressLib/brotli | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/MdeModulePkg/Library/BrotliCustomDecompressLib/BrotliCustomDecompressLib.inf b/MdeModulePkg/Library/BrotliCustomDecompressLib/BrotliCustomDecompressLib.inf
index 525e92408d67..fabbb86d16c1 100644
--- a/MdeModulePkg/Library/BrotliCustomDecompressLib/BrotliCustomDecompressLib.inf
+++ b/MdeModulePkg/Library/BrotliCustomDecompressLib/BrotliCustomDecompressLib.inf
@@ -39,7 +39,10 @@
stdlib.h
string.h
# Wrapper header files end #
+ brotli/c/common/constants.c
+ brotli/c/common/context.c
brotli/c/common/dictionary.c
+ brotli/c/common/shared_dictionary.c
brotli/c/common/transform.c
brotli/c/dec/bit_reader.c
brotli/c/dec/decode.c
diff --git a/MdeModulePkg/Library/BrotliCustomDecompressLib/brotli b/MdeModulePkg/Library/BrotliCustomDecompressLib/brotli
index 666c3280cc11..4ec67035c0d9 160000
--- a/MdeModulePkg/Library/BrotliCustomDecompressLib/brotli
+++ b/MdeModulePkg/Library/BrotliCustomDecompressLib/brotli
@@ -1 +1 @@
-Subproject commit 666c3280cc11dc433c303d79a83d4ffbdd12cc8d
+Subproject commit 4ec67035c0d97c270c1c73038cc66fc5fcdfc120
--
2.34.1


[PATCH v2 1/2] BaseTools: Update brotli to the latest upstream commit

Pedro Falcato
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3417

This updates BaseTools's brotli submodule to the latest upstream,
which fixes GCC 11's issue building BaseTools.

Cc: Bob Feng <bob.c.feng@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Yuwei Chen <yuwei.chen@intel.com>
Signed-off-by: Pedro Falcato <pedro.falcato@gmail.com>
---
BaseTools/Source/C/BrotliCompress/GNUmakefile | 7 +++++++
BaseTools/Source/C/BrotliCompress/Makefile | 12 +++++++++++-
BaseTools/Source/C/BrotliCompress/brotli | 2 +-
3 files changed, 19 insertions(+), 2 deletions(-)

diff --git a/BaseTools/Source/C/BrotliCompress/GNUmakefile b/BaseTools/Source/C/BrotliCompress/GNUmakefile
index b150e5dd2bb9..79d7c405069d 100644
--- a/BaseTools/Source/C/BrotliCompress/GNUmakefile
+++ b/BaseTools/Source/C/BrotliCompress/GNUmakefile
@@ -10,7 +10,11 @@ APPNAME = BrotliCompress

OBJECTS = \
BrotliCompress.o \
+ brotli/c/common/constants.o \
+ brotli/c/common/context.o \
brotli/c/common/dictionary.o \
+ brotli/c/common/platform.o \
+ brotli/c/common/shared_dictionary.o \
brotli/c/common/transform.o \
brotli/c/dec/bit_reader.o \
brotli/c/dec/decode.o \
@@ -22,12 +26,15 @@ OBJECTS = \
brotli/c/enc/block_splitter.o \
brotli/c/enc/brotli_bit_stream.o \
brotli/c/enc/cluster.o \
+ brotli/c/enc/command.o \
+ brotli/c/enc/compound_dictionary.o \
brotli/c/enc/compress_fragment.o \
brotli/c/enc/compress_fragment_two_pass.o \
brotli/c/enc/dictionary_hash.o \
brotli/c/enc/encode.o \
brotli/c/enc/encoder_dict.o \
brotli/c/enc/entropy_encode.o \
+ brotli/c/enc/fast_log.o \
brotli/c/enc/histogram.o \
brotli/c/enc/literal_cost.o \
brotli/c/enc/memory.o \
diff --git a/BaseTools/Source/C/BrotliCompress/Makefile b/BaseTools/Source/C/BrotliCompress/Makefile
index 038d1ec24226..0ed39d4b5a2c 100644
--- a/BaseTools/Source/C/BrotliCompress/Makefile
+++ b/BaseTools/Source/C/BrotliCompress/Makefile
@@ -13,7 +13,14 @@ APPNAME = BrotliCompress

#LIBS = $(LIB_PATH)\Common.lib

-COMMON_OBJ = brotli\c\common\dictionary.obj brotli\c\common\transform.obj
+COMMON_OBJ = \
+ brotli\c\common\constants.obj \
+ brotli\c\common\context.obj \
+ brotli\c\common\dictionary.obj \
+ brotli\c\common\platform.obj \
+ brotli\c\common\shared_dictionary.obj \
+ brotli\c\common\transform.obj
+
DEC_OBJ = \
brotli\c\dec\bit_reader.obj \
brotli\c\dec\decode.obj \
@@ -26,12 +33,15 @@ ENC_OBJ = \
brotli\c\enc\block_splitter.obj \
brotli\c\enc\brotli_bit_stream.obj \
brotli\c\enc\cluster.obj \
+ brotli\c\enc\command.obj \
+ brotli\c\enc\compound_dictionary.obj \
brotli\c\enc\compress_fragment.obj \
brotli\c\enc\compress_fragment_two_pass.obj \
brotli\c\enc\dictionary_hash.obj \
brotli\c\enc\encode.obj \
brotli\c\enc\encoder_dict.obj \
brotli\c\enc\entropy_encode.obj \
+ brotli\c\enc\fast_log.obj \
brotli\c\enc\histogram.obj \
brotli\c\enc\literal_cost.obj \
brotli\c\enc\memory.obj \
diff --git a/BaseTools/Source/C/BrotliCompress/brotli b/BaseTools/Source/C/BrotliCompress/brotli
index 666c3280cc11..4ec67035c0d9 160000
--- a/BaseTools/Source/C/BrotliCompress/brotli
+++ b/BaseTools/Source/C/BrotliCompress/brotli
@@ -1 +1 @@
-Subproject commit 666c3280cc11dc433c303d79a83d4ffbdd12cc8d
+Subproject commit 4ec67035c0d97c270c1c73038cc66fc5fcdfc120
--
2.34.1


[PATCH v2 0/2] Update brotli to the latest commit

Pedro Falcato
 

BZ: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3417

This patch set updates the brotli submodule to the latest commit, which
fixes a warning that triggers build failures for both BaseTools and
MdeModulePkg/BrotliCustomDecompressLib in GCC 11 compilers.

Pedro Falcato (2):
BaseTools: Update brotli to the latest upstream commit
MdeModulePkg/BrotliCustomDecompressLib: Update brotli

BaseTools/Source/C/BrotliCompress/GNUmakefile | 7 +++++++
BaseTools/Source/C/BrotliCompress/Makefile | 12 +++++++++++-
BaseTools/Source/C/BrotliCompress/brotli | 2 +-
MdeModulePkg/Library/BrotliCustomDecompressLib/BrotliCustomDecompressLib.inf | 3 +++
MdeModulePkg/Library/BrotliCustomDecompressLib/brotli | 2 +-
5 files changed, 23 insertions(+), 3 deletions(-)

--
2.34.1


Re: [PATCH V3 27/29] OvmfPkg/BaseMemEncryptTdxLib: Add TDX helper library

Min Xu
 

Hi,

Add Intel Tdx helper library. The library provides the routines to:
- set or clear Shared bit for a given memory region.
- query whether TDX is enabled.
Hmm, patch 22 adds functions to set the shared bit too.
Looks like duplicate functionality on a first glance.
Ah yes, patch 22 (setting the shared bit) is duplicated with BaseMemEncryptTdxLib. And setting shared bit for Mmio space can be moved to TdxDxe driver (It is more reasonable). Then MdeModulePkg/Core/DxeIplPeim can be un-touched. To be honest I am a little nervous to touch the core code.
Thanks much for the reminder.

Min

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