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Re: [PATCH v5 03/21] ArmPkg/ArmMonitorLib: Add ArmMonitorLib
Leif Lindholm
Hi Pierre,
Apologies for delay in feedback. On 2022-09-19 12:21, Pierre.Gondois@... wrote: From: Pierre Gondois <Pierre.Gondois@...>For 1-3/21: Reviewed-by: Leif Lindholm <quic_llindhol@...> / Leif ---
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Re: MK BOOT.MXF.1.1.c1-00035-MAKENA-1 compilation is failing
Michael D Kinney
Did you recently upgrade to Python 3.9. Are you using the latest version of BaseTools?  I see an issue that was fixed in BaseTools in August 2020 that may be related.  https://edk2.groups.io/g/devel/message/64002 https://github.com/tianocore/edk2/commit/5d8648345cd9ad729837118c731063c59edea192  Mike   From: devel@edk2.groups.io <devel@edk2.groups.io>
On Behalf Of Ajinkya Bhavalkar  Can someone please help with this. This issue is observed on all our machines.  Command to compile:  Logs:
Â
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MK BOOT.MXF.1.1.c1-00035-MAKENA-1 compilation is failing
Ajinkya Bhavalkar <abhavalk@...>
Can someone please help with this. This issue is observed on all our machines. Â Command to compile: Â Logs:
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[PATCH v1 1/1] UefiCpuPkg: Reset a parameter when BSP Exit in CPU relaxed mode.
Li, Zhihao
From: Zhihao Li <zhihao.li@...>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4083 In CPU relaxed mode, it doesn't reset the value of mSmmMpSyncData->AllApArrivedWithException when BSP exit smm mode. So this patch will reset this variable. Cc: Eric Dong <eric.dong@...> Cc: Ray Ni <ray.ni@...> Signed-off-by: Zhihao Li <zhihao.li@...> --- UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c b/UefiCpuPkg/PiSmmCpuDxe= Smm/MpService.c index 13c2cb8da4c3..c79da418e37c 100644 --- a/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c +++ b/UefiCpuPkg/PiSmmCpuDxeSmm/MpService.c @@ -696,8 +696,9 @@ BSPHandler ( //=0D // Allow APs to check in from this point on=0D //=0D - *mSmmMpSyncData->Counter =3D 0;=0D - *mSmmMpSyncData->AllCpusInSync =3D FALSE;=0D + *mSmmMpSyncData->Counter =3D 0;=0D + *mSmmMpSyncData->AllCpusInSync =3D FALSE;=0D + mSmmMpSyncData->AllApArrivedWithException =3D FALSE;=0D }=0D =0D /**=0D --=20 2.26.2.windows.1
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Re: [PATCH v3 29/34] MdePkg/BaseSynchronizationLib: LoongArch cache related code.
Hi Mike, I have converted the inline assembly code to ASM code, please review this patch again, thanks!
On 9月 27 2022, at 7:13 晚上, Chao Li <lichao@...> wrote:
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[PATCH v3 34/34] NetworkPkg: Add LoongArch64 architecture.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
Add LoongArch64 architecture in to NetworkPkg. Cc: Maciej Rabeda <maciej.rabeda@...> Cc: Jiaxin Wu <jiaxin.wu@...> Cc: Siyuan Fu <siyuan.fu@...> Signed-off-by: Chao Li <lichao@...> Reviewed-by: Michael D Kinney <michael.d.kinney@...> --- NetworkPkg/Network.dsc.inc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/NetworkPkg/Network.dsc.inc b/NetworkPkg/Network.dsc.inc index 99fad885bf..04b515a0bb 100644 --- a/NetworkPkg/Network.dsc.inc +++ b/NetworkPkg/Network.dsc.inc @@ -9,6 +9,7 @@ #=0D # Copyright (c) 2019 - 2020, Intel Corporation. All rights reserved.<BR>=0D # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.<BR>=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -38,7 +39,7 @@ !include NetworkPkg/NetworkComponents.dsc.inc=0D =0D !else=0D -[Components.IA32, Components.X64, Components.ARM, Components.AARCH64, Comp= onents.RISCV64]=0D +[Components.IA32, Components.X64, Components.ARM, Components.AARCH64, Comp= onents.RISCV64, Components.LOONGARCH64]=0D !include NetworkPkg/NetworkComponents.dsc.inc=0D =0D !endif=0D --=20 2.27.0
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[PATCH v3 33/34] MdeModulePkg/DxeIplPeim : LoongArch DxeIPL implementation.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
Implement LoongArch DxeIPL instance. Cc: Liming Gao <gaoliming@...> Cc: Guomin Jiang <guomin.jiang@...> Signed-off-by: Chao Li <lichao@...> Co-authored-by: Baoqi Zhang <zhangbaoqi@...> Reviewed-by: Liming Gao <gaoliming@...> --- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf | 6 +- .../Core/DxeIplPeim/LoongArch64/DxeLoadFunc.c | 63 +++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletion(-) create mode 100644 MdeModulePkg/Core/DxeIplPeim/LoongArch64/DxeLoadFunc.c diff --git a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf b/MdeModulePkg/Core/Dx= eIplPeim/DxeIpl.inf index 19b8a4c8ae..052ea0ec1a 100644 --- a/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf +++ b/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf @@ -8,6 +8,7 @@ # Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>= =0D # Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>=0D # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.<BR>=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights= reserved.<BR>=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -26,7 +27,7 @@ #=0D # The following information is for reference only and not required by the = build tools.=0D #=0D -# VALID_ARCHITECTURES =3D IA32 X64 EBC (EBC is for build only) = AARCH64 RISCV64=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC (EBC is for build only) = AARCH64 RISCV64 LOONGARCH64=0D #=0D =0D [Sources]=0D @@ -53,6 +54,9 @@ [Sources.RISCV64]=0D RiscV64/DxeLoadFunc.c=0D =0D +[Sources.LOONGARCH64]=0D + LoongArch64/DxeLoadFunc.c=0D +=0D [Packages]=0D MdePkg/MdePkg.dec=0D MdeModulePkg/MdeModulePkg.dec=0D diff --git a/MdeModulePkg/Core/DxeIplPeim/LoongArch64/DxeLoadFunc.c b/MdeMo= dulePkg/Core/DxeIplPeim/LoongArch64/DxeLoadFunc.c new file mode 100644 index 0000000000..95d3af19ea --- /dev/null +++ b/MdeModulePkg/Core/DxeIplPeim/LoongArch64/DxeLoadFunc.c @@ -0,0 +1,63 @@ +/** @file=0D + LoongArch specifc functionality for DxeLoad.=0D +=0D + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include "DxeIpl.h"=0D +=0D +/**=0D + Transfers control to DxeCore.=0D +=0D + This function performs a CPU architecture specific operations to execut= e=0D + the entry point of DxeCore with the parameters of HobList.=0D + It also installs EFI_END_OF_PEI_PPI to signal the end of PEI phase.=0D +=0D + @param[in] DxeCoreEntryPoint The entry point of DxeCore.=0D + @param[in] HobList The start of HobList passed to Dxe= Core.=0D +=0D +**/=0D +VOID=0D +HandOffToDxeCore (=0D + IN EFI_PHYSICAL_ADDRESS DxeCoreEntryPoint,=0D + IN EFI_PEI_HOB_POINTERS HobList=0D + )=0D +{=0D + VOID *BaseOfStack;=0D + VOID *TopOfStack;=0D + EFI_STATUS Status;=0D +=0D + //=0D + // Allocate 128KB for the Stack=0D + //=0D + BaseOfStack =3D AllocatePages (EFI_SIZE_TO_PAGES (STACK_SIZE));=0D + ASSERT (BaseOfStack !=3D NULL);=0D +=0D + //=0D + // Compute the top of the stack we were allocated. Pre-allocate a UINTN= =0D + // for safety.=0D + //=0D + TopOfStack =3D (VOID *)((UINTN)BaseOfStack + EFI_SIZE_TO_PAGES (STACK_SI= ZE) * EFI_PAGE_SIZE - CPU_STACK_ALIGNMENT);=0D + TopOfStack =3D ALIGN_POINTER (TopOfStack, CPU_STACK_ALIGNMENT);=0D +=0D + //=0D + // End of PEI phase signal=0D + //=0D + Status =3D PeiServicesInstallPpi (&gEndOfPeiSignalPpi);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Update the contents of BSP stack HOB to reflect the real stack info p= assed to DxeCore.=0D + //=0D + UpdateStackHob ((EFI_PHYSICAL_ADDRESS)(UINTN)BaseOfStack, STACK_SIZE);=0D +=0D + SwitchStack (=0D + (SWITCH_STACK_ENTRY_POINT)(UINTN)DxeCoreEntryPoint,=0D + HobList.Raw,=0D + NULL,=0D + TopOfStack=0D + );=0D +}=0D --=20 2.27.0
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[PATCH v3 32/34] MdeModulePkg/CapsuleRuntimeDxe: Add LoongArch64 architecture.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
Add LoongArch in INF for building CapsuleRuntimeDxe LoongArch64 image. Cc: Liming Gao <gaoliming@...> Cc: Guomin Jiang <guomin.jiang@...> Sigend-off-by: Chao Li <lichao@...> Reviewed-by: Michael D Kinney <michael.d.kinney@...> --- .../Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf= b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf index 8bf5035a69..601eada170 100644 --- a/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf +++ b/MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf @@ -6,6 +6,7 @@ #=0D # Copyright (c) 2006 - 2020, Intel Corporation. All rights reserved.<BR>= =0D # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.<BR>=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights= reserved.<BR>=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D ##=0D @@ -22,20 +23,20 @@ #=0D # The following information is for reference only and not required by the = build tools.=0D #=0D -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 LOON= GARCH64=0D #=0D =0D [Sources]=0D CapsuleService.c=0D CapsuleService.h=0D =0D -[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64]= =0D +[Sources.Ia32, Sources.EBC, Sources.ARM, Sources.AARCH64, Sources.RISCV64,= Sources.LOONGARCH64]=0D SaveLongModeContext.c=0D =0D -[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64, Sources.RISCV64]= =0D +[Sources.Ia32, Sources.X64, Sources.ARM, Sources.AARCH64, Sources.RISCV64,= Sources.LOONGARCH64]=0D CapsuleCache.c=0D =0D -[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64]=0D +[Sources.Ia32, Sources.X64, Sources.EBC, Sources.RISCV64, Sources.LOONGARC= H64]=0D CapsuleReset.c=0D =0D [Sources.ARM, Sources.AARCH64]=0D --=20 2.27.0
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[PATCH v3 31/34] MdeModulePkg/Logo: Add LoongArch64 architecture.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
Add LoongArch64 architecture to the Logo. Cc: Zhichao Gao <zhichao.gao@...> Cc: Ray Ni <ray.ni@...> Signed-off-by: Chao Li <lichao@...> Reviewed-by: Michael D Kinney <michael.d.kinney@...> Reviewed-by: Zhichao Gao <zhichao.gao@...> --- MdeModulePkg/Logo/Logo.inf | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MdeModulePkg/Logo/Logo.inf b/MdeModulePkg/Logo/Logo.inf index 70a66cae98..294482ccdc 100644 --- a/MdeModulePkg/Logo/Logo.inf +++ b/MdeModulePkg/Logo/Logo.inf @@ -3,6 +3,7 @@ #=0D # Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>= =0D # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.<BR>=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights= reserved.<BR>=0D =0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D @@ -21,7 +22,7 @@ #=0D # The following information is for reference only and not required by the = build tools.=0D #=0D -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 LOON= GARCH64=0D #=0D =0D [Binaries]=0D --=20 2.27.0
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[PATCH v3 30/34] MdePkg/BaseSafeIntLib: Add LoongArch64 architecture for BaseSafeIntLib.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
Add LoongArch64 architecture for BaseSafeIntLib library. Cc: Michael D Kinney <michael.d.kinney@...> Cc: Liming Gao <gaoliming@...> Cc: Zhiguang Liu <zhiguang.liu@...> Signed-off-by: Chao Li <lichao@...> Reviewed-by: Michael D Kinney <michael.d.kinney@...> --- MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf b/MdePkg/Libr= ary/BaseSafeIntLib/BaseSafeIntLib.inf index 40017ec88b..9d039f2e5b 100644 --- a/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf +++ b/MdePkg/Library/BaseSafeIntLib/BaseSafeIntLib.inf @@ -4,9 +4,10 @@ # This library provides helper functions to prevent integer overflow durin= g=0D # type conversion, addition, subtraction, and multiplication.=0D #=0D -# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>=0D +# Copyright (c) 2018, Intel Corporation. All rights reserved.<BR>=0D # Copyright (c) 2017, Microsoft Corporation=0D -# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.<BR>=0D +# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.<BR>=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D =0D #=0D # All rights reserved.=0D @@ -25,7 +26,7 @@ #=0D # The following information is for reference only and not required by the = build tools.=0D #=0D -# VALID_ARCHITECTURES =3D IA32 X64 ARM AARCH64 RISCV64=0D +# VALID_ARCHITECTURES =3D IA32 X64 ARM AARCH64 RISCV64 LOONGARC= H64=0D #=0D =0D [Sources]=0D @@ -34,7 +35,7 @@ [Sources.Ia32, Sources.ARM]=0D SafeIntLib32.c=0D =0D -[Sources.X64, Sources.AARCH64, Sources.RISCV64]=0D +[Sources.X64, Sources.AARCH64, Sources.RISCV64, Sources.LOONGARCH64]=0D SafeIntLib64.c=0D =0D [Sources.EBC]=0D --=20 2.27.0
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[PATCH v3 29/34] MdePkg/BaseSynchronizationLib: LoongArch cache related code.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
Support LoongArch cache related functions. Cc: Michael D Kinney <michael.d.kinney@...> Cc: Liming Gao <gaoliming@...> Cc: Zhiguang Liu <zhiguang.liu@...> Signed-off-by: Chao Li <lichao@...> Co-authored-by: Baoqi Zhang <zhangbaoqi@...> --- .../BaseSynchronizationLib.inf | 6 + .../LoongArch64/AsmSynchronization.S | 122 +++++++++ .../LoongArch64/Synchronization.c | 233 ++++++++++++++++++ 3 files changed, 361 insertions(+) create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSy= nchronization.S create mode 100644 MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synch= ronization.c diff --git a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.i= nf b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf index 02ba12961a..dd66ec1d03 100755 --- a/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf +++ b/MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf @@ -4,6 +4,7 @@ # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>= =0D # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>= =0D # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.<BR>=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights= reserved.<BR>=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -82,6 +83,11 @@ Synchronization.c=0D RiscV64/Synchronization.S=0D =0D +[Sources.LOONGARCH64]=0D + Synchronization.c=0D + LoongArch64/Synchronization.c | GCC=0D + LoongArch64/AsmSynchronization.S | GCC=0D +=0D [Packages]=0D MdePkg/MdePkg.dec=0D =0D diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchroni= zation.S b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchroniza= tion.S new file mode 100644 index 0000000000..3f1b06172d --- /dev/null +++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/AsmSynchronization.S @@ -0,0 +1,122 @@ +#-------------------------------------------------------------------------= ----- +# +# LoongArch synchronization ASM functions. +# +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#-------------------------------------------------------------------------= ----- + +ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange16) +ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange32) +ASM_GLOBAL ASM_PFX(AsmInternalSyncCompareExchange64) +ASM_GLOBAL ASM_PFX(AsmInternalSyncIncrement) +ASM_GLOBAL ASM_PFX(AsmInternalSyncDecrement) + +/** +UINT32 +EFIAPI +AsmInternalSyncCompareExchange16 ( + IN volatile UINT32 *Ptr32, + IN UINT64 Mask, + IN UINT64 LocalCompareValue, + IN UINT64 LocalExchangeValue + ) +**/ +ASM_PFX(AsmInternalSyncCompareExchange16): +1: + ll.w $t0, $a0, 0x0 + and $t1, $t0, $a1 + bne $t1, $a2, 2f + andn $t1, $t0, $a1 + or $t1, $t1, $a3 + sc.w $t1, $a0, 0x0 + beqz $t1, 1b + b 3f +2: + dbar 0 +3: + move $a0, $t0 + jirl $zero, $ra, 0 + +/** +UINT32 +EFIAPI +AsmInternalSyncCompareExchange32 ( + IN volatile UINT32 *Value, + IN UINT64 CompareValue, + IN UINT64 ExchangeValue + ) +**/ +ASM_PFX(AsmInternalSyncCompareExchange32): +1: + ll.w $t0, $a0, 0x0 + bne $t0, $a1, 2f + move $t0, $a2 + sc.w $t0, $a0, 0x0 + beqz $t0, 1b + b 3f +2: + dbar 0 +3: + move $a0, $t0 + jirl $zero, $ra, 0 + +/** +UINT64 +EFIAPI +AsmInternalSyncCompareExchange64 ( + IN volatile UINT64 *Value, + IN UINT64 CompareValue, + IN UINT64 ExchangeValue + ) +**/ +ASM_PFX(AsmInternalSyncCompareExchange64): +1: + ll.d $t0, $a0, 0x0 + bne $t0, $a1, 2f + move $t0, $a2 + sc.d $t0, $a0, 0x0 + beqz $t0, 1b + b 3f +2: + dbar 0 +3: + move $a0, $t0 + jirl $zero, $ra, 0 + +/** +UINT32 +EFIAPI +AsmInternalSyncIncrement ( + IN volatile UINT32 *Value + ) +**/ +ASM_PFX(AsmInternalSyncIncrement): + move $t0, $a0 + dbar 0 + ld.w $t1, $t0, 0x0 + li.w $t2, 1 + amadd.w $t1, $t2, $t0 + + ld.w $a0, $t0, 0x0 + jirl $zero, $ra, 0 + +/** +UINT32 +EFIAPI +AsmInternalSyncDecrement ( + IN volatile UINT32 *Value + ) +**/ +ASM_PFX(AsmInternalSyncDecrement): + move $t0, $a0 + dbar 0 + ld.w $t1, $t0, 0x0 + li.w $t2, -1 + amadd.w $t1, $t2, $t0 + + ld.w $a0, $t0, 0x0 + jirl $zero, $ra, 0 +.end diff --git a/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronizat= ion.c b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c new file mode 100644 index 0000000000..d696c8ce10 --- /dev/null +++ b/MdePkg/Library/BaseSynchronizationLib/LoongArch64/Synchronization.c @@ -0,0 +1,233 @@ +/** @file=0D + LoongArch synchronization functions.=0D +=0D + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#include <Library/DebugLib.h>=0D +=0D +UINT32=0D +EFIAPI=0D +AsmInternalSyncCompareExchange16 (=0D + IN volatile UINT32 *,=0D + IN UINT64,=0D + IN UINT64,=0D + IN UINT64=0D + );=0D +=0D +UINT32=0D +EFIAPI=0D +AsmInternalSyncCompareExchange32 (=0D + IN volatile UINT32 *,=0D + IN UINT64,=0D + IN UINT64=0D + );=0D +=0D +UINT64=0D +EFIAPI=0D +AsmInternalSyncCompareExchange64 (=0D + IN volatile UINT64 *,=0D + IN UINT64,=0D + IN UINT64=0D + );=0D +=0D +UINT32=0D +EFIAPI=0D +AsmInternalSyncIncrement (=0D + IN volatile UINT32 *=0D + );=0D +=0D +UINT32=0D +EFIAPI=0D +AsmInternalSyncDecrement (=0D + IN volatile UINT32 *=0D + );=0D +=0D +/**=0D + Performs an atomic compare exchange operation on a 16-bit=0D + unsigned integer.=0D +=0D + Performs an atomic compare exchange operation on the 16-bit=0D + unsigned integer specified by Value. If Value is equal to=0D + CompareValue, then Value is set to ExchangeValue and=0D + CompareValue is returned. If Value is not equal to=0D + CompareValue, then Value is returned. The compare exchange=0D + operation must be performed using MP safe mechanisms.=0D +=0D + @param[in] Value A pointer to the 16-bit value for the=0D + compare exchange operation.=0D + @param[in] CompareValue 16-bit value used in compare operation.=0D + @param[in] ExchangeValue 16-bit value used in exchange operation.=0D +=0D + @return The original *Value before exchange.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +InternalSyncCompareExchange16 (=0D + IN volatile UINT16 *Value,=0D + IN UINT16 CompareValue,=0D + IN UINT16 ExchangeValue=0D + )=0D +{=0D + UINT32 RetValue;=0D + UINT32 Shift;=0D + UINT64 Mask;=0D + UINT64 LocalCompareValue;=0D + UINT64 LocalExchangeValue;=0D + volatile UINT32 *Ptr32;=0D +=0D + /* Check that ptr is naturally aligned */=0D + ASSERT (!((UINT64)Value & (sizeof (Value) - 1)));=0D +=0D + /* Mask inputs to the correct size. */=0D + Mask =3D (((~0UL) - (1UL << (0)) + 1) & (~0UL >> (64 - 1 -= ((sizeof (UINT16) * 8) - 1))));=0D + LocalCompareValue =3D ((UINT64)CompareValue) & Mask;=0D + LocalExchangeValue =3D ((UINT64)ExchangeValue) & Mask;=0D +=0D + /*=0D + * Calculate a shift & mask that correspond to the value we wish to=0D + * compare & exchange within the naturally aligned 4 byte integer=0D + * that includes it.=0D + */=0D + Shift =3D (UINT64)Value & 0x3;=0D + Shift *=3D 8; /* BITS_PER_BYTE */=0D + LocalCompareValue <<=3D Shift;=0D + LocalExchangeValue <<=3D Shift;=0D + Mask <<=3D Shift;=0D +=0D + /*=0D + * Calculate a pointer to the naturally aligned 4 byte integer that=0D + * includes our byte of interest, and load its value.=0D + */=0D + Ptr32 =3D (UINT32 *)((UINT64)Value & ~0x3);=0D +=0D + RetValue =3D AsmInternalSyncCompareExchange16 (=0D + Ptr32,=0D + Mask,=0D + LocalCompareValue,=0D + LocalExchangeValue=0D + );=0D +=0D + return (RetValue & Mask) >> Shift;=0D +}=0D +=0D +/**=0D + Performs an atomic compare exchange operation on a 32-bit=0D + unsigned integer.=0D +=0D + Performs an atomic compare exchange operation on the 32-bit=0D + unsigned integer specified by Value. If Value is equal to=0D + CompareValue, then Value is set to ExchangeValue and=0D + CompareValue is returned. If Value is not equal to=0D + CompareValue, then Value is returned. The compare exchange=0D + operation must be performed using MP safe mechanisms.=0D +=0D + @param[in] Value A pointer to the 32-bit value for the=0D + compare exchange operation.=0D + @param[in] CompareValue 32-bit value used in compare operation.=0D + @param[in] ExchangeValue 32-bit value used in exchange operation.=0D +=0D + @return The original *Value before exchange.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +InternalSyncCompareExchange32 (=0D + IN volatile UINT32 *Value,=0D + IN UINT32 CompareValue,=0D + IN UINT32 ExchangeValue=0D + )=0D +{=0D + UINT32 RetValue;=0D +=0D + RetValue =3D AsmInternalSyncCompareExchange32 (=0D + Value,=0D + CompareValue,=0D + ExchangeValue=0D + );=0D +=0D + return RetValue;=0D +}=0D +=0D +/**=0D + Performs an atomic compare exchange operation on a 64-bit unsigned integ= er.=0D +=0D + Performs an atomic compare exchange operation on the 64-bit unsigned int= eger specified=0D + by Value. If Value is equal to CompareValue, then Value is set to Excha= ngeValue and=0D + CompareValue is returned. If Value is not equal to CompareValue, then V= alue is returned.=0D + The compare exchange operation must be performed using MP safe mechanism= s.=0D +=0D + @param[in] Value A pointer to the 64-bit value for the compare = exchange=0D + operation.=0D + @param[in] CompareValue 64-bit value used in compare operation.=0D + @param[in] ExchangeValue 64-bit value used in exchange operation.=0D +=0D + @return The original *Value before exchange.=0D +=0D +**/=0D +UINT64=0D +EFIAPI=0D +InternalSyncCompareExchange64 (=0D + IN volatile UINT64 *Value,=0D + IN UINT64 CompareValue,=0D + IN UINT64 ExchangeValue=0D + )=0D +{=0D + UINT64 RetValue;=0D +=0D + RetValue =3D AsmInternalSyncCompareExchange64 (=0D + Value,=0D + CompareValue,=0D + ExchangeValue=0D + );=0D +=0D + return RetValue;=0D +}=0D +=0D +/**=0D + Performs an atomic increment of an 32-bit unsigned integer.=0D +=0D + Performs an atomic increment of the 32-bit unsigned integer specified by= =0D + Value and returns the incremented value. The increment operation must be= =0D + performed using MP safe mechanisms. The state of the return value is not= =0D + guaranteed to be MP safe.=0D +=0D + @param[in] Value A pointer to the 32-bit value to increment.=0D +=0D + @return The incremented value.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +InternalSyncIncrement (=0D + IN volatile UINT32 *Value=0D + )=0D +{=0D + return AsmInternalSyncIncrement (Value);=0D +}=0D +=0D +/**=0D + Performs an atomic decrement of an 32-bit unsigned integer.=0D +=0D + Performs an atomic decrement of the 32-bit unsigned integer specified by= =0D + Value and returns the decrement value. The decrement operation must be=0D + performed using MP safe mechanisms. The state of the return value is not= =0D + guaranteed to be MP safe.=0D +=0D + @param[in] Value A pointer to the 32-bit value to decrement.=0D +=0D + @return The decrement value.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +InternalSyncDecrement (=0D + IN volatile UINT32 *Value=0D + )=0D +{=0D + return AsmInternalSyncDecrement (Value);=0D +}=0D --=20 2.27.0
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[PATCH v3 28/34] MdePkg/BaseCpuLib: LoongArch Base CPU library implementation.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
Implement LoongArch CPU related functions in BaseCpuLib. Cc: Michael D Kinney <michael.d.kinney@...> Cc: Liming Gao <gaoliming@...> Cc: Zhiguang Liu <zhiguang.liu@...> Signed-off-by: Chao Li <lichao@...> Reviewed-by: Michael D Kinney <michael.d.kinney@...> --- MdePkg/Library/BaseCpuLib/BaseCpuLib.inf | 7 ++++++- MdePkg/Library/BaseCpuLib/BaseCpuLib.uni | 5 +++-- MdePkg/Library/BaseCpuLib/LoongArch/CpuFlushTlb.S | 15 +++++++++++++++ MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S | 15 +++++++++++++++ 4 files changed, 39 insertions(+), 3 deletions(-) create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/CpuFlushTlb.S create mode 100644 MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf b/MdePkg/Library/Base= CpuLib/BaseCpuLib.inf index c4cd29a783..6b230f6e6d 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.inf @@ -8,6 +8,7 @@ # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>= =0D # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>=0D # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.<BR>=0D +# Portions Copyright (c) 2022, Loongson Technology Corporation Limited. A= ll rights reserved.<BR>=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -25,7 +26,7 @@ =0D =0D #=0D -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 LOON= GARCH64=0D #=0D =0D [Sources.IA32]=0D @@ -61,6 +62,10 @@ [Sources.RISCV64]=0D RiscV/Cpu.S=0D =0D +[Sources.LOONGARCH64]=0D + LoongArch/CpuFlushTlb.S | GCC=0D + LoongArch/CpuSleep.S | GCC=0D +=0D [Packages]=0D MdePkg/MdePkg.dec=0D =0D diff --git a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni b/MdePkg/Library/Base= CpuLib/BaseCpuLib.uni index 80dc495786..7c5c8dfb37 100644 --- a/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni +++ b/MdePkg/Library/BaseCpuLib/BaseCpuLib.uni @@ -1,13 +1,14 @@ // /** @file=0D // Instance of CPU Library for various architecture.=0D //=0D -// CPU Library implemented using ASM functions for IA-32, X64 and RISCV64,= =0D +// CPU Library implemented using ASM functions for IA-32, X64, RISCV64 and= LoongArch64,=0D // PAL CALLs for IPF, and empty functions for EBC.=0D //=0D // Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>= =0D // Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>= =0D // Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>=0D // Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.<BR>=0D +// Portions Copyright (c) 2022, Loongson Technology Corporation Limited. A= ll rights reserved.<BR>=0D //=0D // SPDX-License-Identifier: BSD-2-Clause-Patent=0D //=0D @@ -16,5 +17,5 @@ =0D #string STR_MODULE_ABSTRACT #language en-US "Instance of CPU L= ibrary for various architectures"=0D =0D -#string STR_MODULE_DESCRIPTION #language en-US "CPU Library imple= mented using ASM functions for IA-32, X64 and RISCV64, PAL CALLs for IPF, a= nd empty functions for EBC."=0D +#string STR_MODULE_DESCRIPTION #language en-US "CPU Library imple= mented using ASM functions for IA-32, X64, RISCV64 and LoongArch64, PAL CAL= Ls for IPF, and empty functions for EBC."=0D =0D diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/CpuFlushTlb.S b/MdePkg/Lib= rary/BaseCpuLib/LoongArch/CpuFlushTlb.S new file mode 100644 index 0000000000..8b792f0a37 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/LoongArch/CpuFlushTlb.S @@ -0,0 +1,15 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# CpuFlushTlb() for LoongArch64=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +ASM_GLOBAL ASM_PFX(CpuFlushTlb)=0D +=0D +ASM_PFX(CpuFlushTlb):=0D + tlbflush=0D + jirl $zero, $ra, 0=0D + .end=0D diff --git a/MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S b/MdePkg/Librar= y/BaseCpuLib/LoongArch/CpuSleep.S new file mode 100644 index 0000000000..eb31b10714 --- /dev/null +++ b/MdePkg/Library/BaseCpuLib/LoongArch/CpuSleep.S @@ -0,0 +1,15 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# CpuSleep() for LoongArch64=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +ASM_GLOBAL ASM_PFX(CpuSleep)=0D +=0D +ASM_PFX(CpuSleep):=0D + idle 0=0D + jirl $zero, $ra, 0=0D + .end=0D --=20 2.27.0
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[PATCH v3 27/34] MdePkg/BasePeCoff: Add LoongArch PE/Coff related code.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
Add LoongArch image relocation. Cc: Michael D Kinney <michael.d.kinney@...> Cc: Liming Gao <gaoliming@...> Cc: Zhiguang Liu <zhiguang.liu@...> Signed-off-by: Chao Li <lichao@...> Co-authored-by: Baoqi Zhang <zhangbaoqi@...> Reviewed-by: Michael D Kinney <michael.d.kinney@...> --- MdePkg/Library/BasePeCoffLib/BasePeCoff.c | 3 +- .../Library/BasePeCoffLib/BasePeCoffLib.inf | 5 + .../Library/BasePeCoffLib/BasePeCoffLib.uni | 2 + .../BasePeCoffLib/LoongArch/PeCoffLoaderEx.c | 137 ++++++++++++++++++ 4 files changed, 146 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Library/BasePeCoffLib/LoongArch/PeCoffLoaderEx.c diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c b/MdePkg/Library/Bas= ePeCoffLib/BasePeCoff.c index 6d8d9faeb8..97a8aaf8c7 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoff.c +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoff.c @@ -1,6 +1,6 @@ /** @file=0D Base PE/COFF loader supports loading any PE32/PE32+ or TE image, but=0D - only supports relocating IA32, x64, IPF, ARM, RISC-V and EBC images.=0D + only supports relocating IA32, x64, IPF, ARM, RISC-V, LoongArch and EBC = images.=0D =0D Caution: This file requires additional review when modified.=0D This library will have external input - PE/COFF image.=0D @@ -18,6 +18,7 @@ Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>=0D Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>= =0D Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. = All rights reserved.<BR>=0D + Portions Copyright (c) 2022, Loongson Technology Corporation Limited. Al= l rights reserved.<BR>=0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D **/=0D diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf b/MdePkg/Librar= y/BasePeCoffLib/BasePeCoffLib.inf index 110b6d5a09..3b8b8eb191 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf @@ -4,6 +4,7 @@ # The IA32 version library support loading IA32, X64 and EBC PE/COFF imag= es.=0D # The X64 version library support loading IA32, X64 and EBC PE/COFF image= s.=0D # The RISC-V version library support loading RISC-V images.=0D +# The LoongArch version library support loading LoongArch images.=0D #=0D # Caution: This module requires additional review when modified.=0D # This library will have external input - PE/COFF image.=0D @@ -13,6 +14,7 @@ # Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>= =0D # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>= =0D # Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP.= All rights reserved.<BR>=0D +# Portions Copyright (c) 2022, Loongson Technology Corporation Limited. A= ll rights reserved.<BR>=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -46,6 +48,9 @@ [Sources.RISCV64]=0D RiscV/PeCoffLoaderEx.c=0D =0D +[Sources.LOONGARCH64]=0D + LoongArch/PeCoffLoaderEx.c=0D +=0D [Packages]=0D MdePkg/MdePkg.dec=0D =0D diff --git a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni b/MdePkg/Librar= y/BasePeCoffLib/BasePeCoffLib.uni index 55417029f2..1f731344e1 100644 --- a/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni +++ b/MdePkg/Library/BasePeCoffLib/BasePeCoffLib.uni @@ -5,6 +5,7 @@ // The IA32 version library support loading IA32, X64 and EBC PE/COFF imag= es.=0D // The X64 version library support loading IA32, X64 and EBC PE/COFF image= s.=0D // The RISC-V version library support loading RISC-V32 and RISC-V64 PE/COF= F images.=0D +// The LoongArch version library support loading LoongArch32 and LoongArch= 64 PE/COFF images.=0D //=0D // Caution: This module requires additional review when modified.=0D // This library will have external input - PE/COFF image.=0D @@ -14,6 +15,7 @@ // Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>= =0D // Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>= =0D // Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP.= All rights reserved.<BR>=0D +// Portions Copyright (c) 2022, Loongson Technology Corporation Limited. A= ll rights reserved.<BR>=0D //=0D // SPDX-License-Identifier: BSD-2-Clause-Patent=0D //=0D diff --git a/MdePkg/Library/BasePeCoffLib/LoongArch/PeCoffLoaderEx.c b/MdeP= kg/Library/BasePeCoffLib/LoongArch/PeCoffLoaderEx.c new file mode 100644 index 0000000000..417096f334 --- /dev/null +++ b/MdePkg/Library/BasePeCoffLib/LoongArch/PeCoffLoaderEx.c @@ -0,0 +1,137 @@ +/** @file=0D + PE/Coff loader for LoongArch PE image=0D +=0D + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "BasePeCoffLibInternals.h"=0D +#include <Library/BaseLib.h>=0D +=0D +/**=0D + Performs an LoongArch specific relocation fixup and is a no-op on other= =0D + instruction sets.=0D +=0D + @param[in] Reloc Pointer to the relocation record.=0D + @param[in, out] Fixup Pointer to the address to fix up.=0D + @param[in, out] FixupData Pointer to a buffer to log the fixups.=0D + @param[in] Adjust The offset to adjust the fixup.=0D +=0D + @return Status code.=0D +=0D +**/=0D +RETURN_STATUS=0D +PeCoffLoaderRelocateImageEx (=0D + IN UINT16 *Reloc,=0D + IN OUT CHAR8 *Fixup,=0D + IN OUT CHAR8 **FixupData,=0D + IN UINT64 Adjust=0D + )=0D +{=0D + UINT8 RelocType;=0D + UINT64 Value;=0D + UINT64 Tmp1;=0D + UINT64 Tmp2;=0D +=0D + RelocType =3D (*Reloc) >> 12;=0D + Value =3D 0;=0D + Tmp1 =3D 0;=0D + Tmp2 =3D 0;=0D +=0D + switch (RelocType) {=0D + case EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA:=0D + // The next four instructions are used to load a 64 bit address, rel= ocate all of them=0D + Value =3D (*(UINT32 *)Fixup & 0x1ffffe0) << 7 | // lu12i.w 20b= its from bit5=0D + (*((UINT32 *)Fixup + 1) & 0x3ffc00) >> 10; // ori 12bit= s from bit10=0D + Tmp1 =3D *((UINT32 *)Fixup + 2) & 0x1ffffe0; // lu32i.d 20b= its from bit5=0D + Tmp2 =3D *((UINT32 *)Fixup + 3) & 0x3ffc00; // lu52i.d 12b= its from bit10=0D + Value =3D Value | (Tmp1 << 27) | (Tmp2 << 42);=0D + Value +=3D Adjust;=0D +=0D + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> 1= 2) & 0xfffff) << 5);=0D + if (*FixupData !=3D NULL) {=0D + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UIN= T32));=0D + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup;=0D + *FixupData =3D *FixupData + sizeof (UINT32);=0D + }=0D +=0D + Fixup +=3D sizeof (UINT32);=0D + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x3ffc00) | ((Value & 0xff= f) << 10);=0D + if (*FixupData !=3D NULL) {=0D + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UIN= T32));=0D + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup;=0D + *FixupData =3D *FixupData + sizeof (UINT32);=0D + }=0D +=0D + Fixup +=3D sizeof (UINT32);=0D + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x1ffffe0) | (((Value >> 3= 2) & 0xfffff) << 5);=0D + if (*FixupData !=3D NULL) {=0D + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UIN= T32));=0D + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup;=0D + *FixupData =3D *FixupData + sizeof (UINT32);=0D + }=0D +=0D + Fixup +=3D sizeof (UINT32);=0D + *(UINT32 *)Fixup =3D (*(UINT32 *)Fixup & ~0x3ffc00) | (((Value >> 52= ) & 0xfff) << 10);=0D + if (*FixupData !=3D NULL) {=0D + *FixupData =3D ALIGN_POINTER (*FixupData, sizeof (UIN= T32));=0D + *(UINT32 *)(*FixupData) =3D *(UINT32 *)Fixup;=0D + *FixupData =3D *FixupData + sizeof (UINT32);=0D + }=0D +=0D + break;=0D + default:=0D + return RETURN_UNSUPPORTED;=0D + }=0D +=0D + return RETURN_SUCCESS;=0D +}=0D +=0D +/**=0D + Returns TRUE if the machine type of PE/COFF image is supported. Supporte= d=0D + does not mean the image can be executed it means the PE/COFF loader supp= orts=0D + loading and relocating of the image type. It's up to the caller to suppo= rt=0D + the entry point.=0D +=0D + @param[in] Machine Machine type from the PE Header.=0D +=0D + @return TRUE if this PE/COFF loader can load the image=0D +=0D +**/=0D +BOOLEAN=0D +PeCoffLoaderImageFormatSupported (=0D + IN UINT16 Machine=0D + )=0D +{=0D + if (Machine =3D=3D IMAGE_FILE_MACHINE_LOONGARCH64) {=0D + return TRUE;=0D + }=0D +=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Performs an LOONGARCH-based specific re-relocation fixup and is a no-op = on other=0D + instruction sets. This is used to re-relocated the image into the EFI vi= rtual=0D + space for runtime calls.=0D +=0D + @param[in] Reloc The pointer to the relocation record.=0D + @param[in, out] Fixup The pointer to the address to fix up.=0D + @param[in, out] FixupData The pointer to a buffer to log the fixups.= =0D + @param[in] Adjust The offset to adjust the fixup.=0D +=0D + @return Status code.=0D +=0D +**/=0D +RETURN_STATUS=0D +PeHotRelocateImageEx (=0D + IN UINT16 *Reloc,=0D + IN OUT CHAR8 *Fixup,=0D + IN OUT CHAR8 **FixupData,=0D + IN UINT64 Adjust=0D + )=0D +{=0D + // To check=0D + return PeCoffLoaderRelocateImageEx (Reloc, Fixup, FixupData, Adjust);=0D +}=0D --=20 2.27.0
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[PATCH v3 26/34] MdePkg/BaseIoLibIntrinsic: IoLibNoIo for LoongArch architecture.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
LoongArch MMIO library instance, use the IoLibNoIo. Cc: Michael D Kinney <michael.d.kinney@...> Cc: Liming Gao <gaoliming@...> Cc: Zhiguang Liu <zhiguang.liu@...> Signed-off-by: Chao Li <lichao@...> Reviewed-by: Michael D Kinney <michael.d.kinney@...> --- .../Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf | 10 +++++++--- MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c | 3 ++- 2 files changed, 9 insertions(+), 4 deletions(-) diff --git a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf b/Mde= Pkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf index 27b15d9ae2..aeb072ee95 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf +++ b/MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf @@ -4,13 +4,14 @@ # I/O Library that uses compiler intrinsics to perform IN and OUT instruc= tions=0D # for IA-32 and x64. On IPF, I/O port requests are translated into MMIO = requests.=0D # MMIO requests are forwarded directly to memory. For EBC, I/O port requ= ests=0D -# ASSERT(). For ARM, AARCH64 and RISCV64, this I/O library only provides = non I/O=0D -# read and write.=0D +# ASSERT(). For ARM, AARCH64, RISCV64 and LoongArch, this I/O library onl= y provides=0D +# non I/O read and write.=0D #=0D # Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>= =0D # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>= =0D # Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>=0D # Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP.= All rights reserved.<BR>=0D +# Portions Copyright (c) 2022, Loongson Technology Corporation Limited. A= ll rights reserved.<BR>=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -27,7 +28,7 @@ =0D =0D #=0D -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 LOON= GARCH64=0D #=0D =0D [Sources]=0D @@ -62,6 +63,9 @@ [Sources.RISCV64]=0D IoLibNoIo.c=0D =0D +[Sources.LOONGARCH64]=0D + IoLibNoIo.c=0D +=0D [Packages]=0D MdePkg/MdePkg.dec=0D =0D diff --git a/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c b/MdePkg/Library= /BaseIoLibIntrinsic/IoLibNoIo.c index c71f45b22e..c51e5da39b 100644 --- a/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c +++ b/MdePkg/Library/BaseIoLibIntrinsic/IoLibNoIo.c @@ -1,11 +1,12 @@ /** @file=0D I/O library for non I/O read and write access (memory map I/O read and=0D - write only) architecture, such as ARM and RISC-V processor.=0D + write only) architecture, such as ARM, RISC-V and LoongArch processor.=0D =0D Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>=0D Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>= =0D Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>=0D Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.<BR>=0D + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D --=20 2.27.0
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[PATCH v3 25/34] MdePkg/BaseCacheMaintenanceLib: LoongArch cache maintenance implementation.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
Implement LoongArch cache maintenance functions in BaseCacheMaintenanceLib. Cc: Michael D Kinney <michael.d.kinney@...> Cc: Liming Gao <gaoliming@...> Cc: Zhiguang Liu <zhiguang.liu@...> Signed-off-by: Chao Li <lichao@...> Reviewed-by: Michael D Kinney <michael.d.kinney@...> --- .../BaseCacheMaintenanceLib.inf | 6 +- .../BaseCacheMaintenanceLib/LoongArchCache.c | 254 ++++++++++++++++++ 2 files changed, 259 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib= .inf b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf index 33114243d5..6fd9cbe5f6 100644 --- a/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf +++ b/MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf @@ -7,6 +7,7 @@ # Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>= =0D # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>= =0D # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All righ= ts reserved.<BR>=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights= reserved.<BR>=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -24,7 +25,7 @@ =0D =0D #=0D -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 LOON= GARCH64=0D #=0D =0D [Sources.IA32]=0D @@ -45,6 +46,9 @@ [Sources.RISCV64]=0D RiscVCache.c=0D =0D +[Sources.LOONGARCH64]=0D + LoongArchCache.c=0D +=0D [Packages]=0D MdePkg/MdePkg.dec=0D =0D diff --git a/MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c b/MdeP= kg/Library/BaseCacheMaintenanceLib/LoongArchCache.c new file mode 100644 index 0000000000..4c8773278c --- /dev/null +++ b/MdePkg/Library/BaseCacheMaintenanceLib/LoongArchCache.c @@ -0,0 +1,254 @@ +/** @file=0D + Cache Maintenance Functions for LoongArch.=0D + LoongArch cache maintenance functions has not yet been completed, and wi= ll added in later.=0D + Functions are null functions now.=0D +=0D + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +//=0D +// Include common header file for this module.=0D +//=0D +#include <Base.h>=0D +#include <Library/BaseLib.h>=0D +#include <Library/DebugLib.h>=0D +=0D +/**=0D + LoongArch data barrier operation.=0D +**/=0D +VOID=0D +EFIAPI=0D +AsmDataBarrierLoongArch (=0D + VOID=0D + );=0D +=0D +/**=0D + LoongArch instruction barrier operation.=0D +**/=0D +VOID=0D +EFIAPI=0D +AsmInstructionBarrierLoongArch (=0D + VOID=0D + );=0D +=0D +/**=0D + Invalidates the entire instruction cache in cache coherency domain of th= e=0D + calling CPU.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +InvalidateInstructionCache (=0D + VOID=0D + )=0D +{=0D + AsmInstructionBarrierLoongArch ();=0D +}=0D +=0D +/**=0D + Invalidates a range of instruction cache lines in the cache coherency do= main=0D + of the calling CPU.=0D +=0D + Invalidates the instruction cache lines specified by Address and Length.= If=0D + Address is not aligned on a cache line boundary, then entire instruction= =0D + cache line containing Address is invalidated. If Address + Length is not= =0D + aligned on a cache line boundary, then the entire instruction cache line= =0D + containing Address + Length -1 is invalidated. This function may choose = to=0D + invalidate the entire instruction cache if that is more efficient than=0D + invalidating the specified range. If Length is 0, the no instruction cac= he=0D + lines are invalidated. Address is returned.=0D +=0D + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D +=0D + @param[in] Address The base address of the instruction cache lines to=0D + invalidate. If the CPU is in a physical addressing mode,= then=0D + Address is a physical address. If the CPU is in a virtua= l=0D + addressing mode, then Address is a virtual address.=0D +=0D + @param[in] Length The number of bytes to invalidate from the instructi= on cache.=0D +=0D + @return Address.=0D +=0D +**/=0D +VOID *=0D +EFIAPI=0D +InvalidateInstructionCacheRange (=0D + IN VOID *Address,=0D + IN UINTN Length=0D + )=0D +{=0D + AsmInstructionBarrierLoongArch ();=0D + return Address;=0D +}=0D +=0D +/**=0D + Writes Back and Invalidates the entire data cache in cache coherency dom= ain=0D + of the calling CPU.=0D +=0D + Writes Back and Invalidates the entire data cache in cache coherency dom= ain=0D + of the calling CPU. This function guarantees that all dirty cache lines = are=0D + written back to system memory, and also invalidates all the data cache l= ines=0D + in the cache coherency domain of the calling CPU.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +WriteBackInvalidateDataCache (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_ERROR, "%a: Not currently implemented on LoongArch.\n", __= FUNCTION__));=0D +}=0D +=0D +/**=0D + Writes Back and Invalidates a range of data cache lines in the cache=0D + coherency domain of the calling CPU.=0D +=0D + Writes Back and Invalidate the data cache lines specified by Address and= =0D + Length. If Address is not aligned on a cache line boundary, then entire = data=0D + cache line containing Address is written back and invalidated. If Addres= s +=0D + Length is not aligned on a cache line boundary, then the entire data cac= he=0D + line containing Address + Length -1 is written back and invalidated. Thi= s=0D + function may choose to write back and invalidate the entire data cache i= f=0D + that is more efficient than writing back and invalidating the specified= =0D + range. If Length is 0, the no data cache lines are written back and=0D + invalidated. Address is returned.=0D +=0D + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D +=0D + @param[in] Address The base address of the data cache lines to write ba= ck and=0D + invalidate. If the CPU is in a physical addressing mode,= then=0D + Address is a physical address. If the CPU is in a virtua= l=0D + addressing mode, then Address is a virtual address.=0D + @param[in] Length The number of bytes to write back and invalidate fro= m the=0D + data cache.=0D +=0D + @return Address of cache invalidation.=0D +=0D +**/=0D +VOID *=0D +EFIAPI=0D +WriteBackInvalidateDataCacheRange (=0D + IN VOID *Address,=0D + IN UINTN Length=0D + )=0D +{=0D + DEBUG ((DEBUG_ERROR, "%a: Not currently implemented on LoongArch.\n", __= FUNCTION__));=0D + return Address;=0D +}=0D +=0D +/**=0D + Writes Back the entire data cache in cache coherency domain of the calli= ng=0D + CPU.=0D +=0D + Writes Back the entire data cache in cache coherency domain of the calli= ng=0D + CPU. This function guarantees that all dirty cache lines are written bac= k to=0D + system memory. This function may also invalidate all the data cache line= s in=0D + the cache coherency domain of the calling CPU.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +WriteBackDataCache (=0D + VOID=0D + )=0D +{=0D + WriteBackInvalidateDataCache ();=0D +}=0D +=0D +/**=0D + Writes Back a range of data cache lines in the cache coherency domain of= the=0D + calling CPU.=0D +=0D + Writes Back the data cache lines specified by Address and Length. If Add= ress=0D + is not aligned on a cache line boundary, then entire data cache line=0D + containing Address is written back. If Address + Length is not aligned o= n a=0D + cache line boundary, then the entire data cache line containing Address = +=0D + Length -1 is written back. This function may choose to write back the en= tire=0D + data cache if that is more efficient than writing back the specified ran= ge.=0D + If Length is 0, the no data cache lines are written back. This function = may=0D + also invalidate all the data cache lines in the specified range of the c= ache=0D + coherency domain of the calling CPU. Address is returned.=0D +=0D + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D +=0D + @param[in] Address The base address of the data cache lines to write ba= ck. If=0D + the CPU is in a physical addressing mode, then Address i= s a=0D + physical address. If the CPU is in a virtual addressing= =0D + mode, then Address is a virtual address.=0D + @param[in] Length The number of bytes to write back from the data cach= e.=0D +=0D + @return Address of cache written in main memory.=0D +=0D +**/=0D +VOID *=0D +EFIAPI=0D +WriteBackDataCacheRange (=0D + IN VOID *Address,=0D + IN UINTN Length=0D + )=0D +{=0D + DEBUG ((DEBUG_ERROR, "%a: Not currently implemented on LoongArch.\n", __= FUNCTION__));=0D + return Address;=0D +}=0D +=0D +/**=0D + Invalidates the entire data cache in cache coherency domain of the calli= ng=0D + CPU.=0D +=0D + Invalidates the entire data cache in cache coherency domain of the calli= ng=0D + CPU. This function must be used with care because dirty cache lines are = not=0D + written back to system memory. It is typically used for cache diagnostic= s. If=0D + the CPU does not support invalidation of the entire data cache, then a w= rite=0D + back and invalidate operation should be performed on the entire data cac= he.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +InvalidateDataCache (=0D + VOID=0D + )=0D +{=0D + AsmDataBarrierLoongArch ();=0D +}=0D +=0D +/**=0D + Invalidates a range of data cache lines in the cache coherency domain of= the=0D + calling CPU.=0D +=0D + Invalidates the data cache lines specified by Address and Length. If Add= ress=0D + is not aligned on a cache line boundary, then entire data cache line=0D + containing Address is invalidated. If Address + Length is not aligned on= a=0D + cache line boundary, then the entire data cache line containing Address = +=0D + Length -1 is invalidated. This function must never invalidate any cache = lines=0D + outside the specified range. If Length is 0, the no data cache lines are= =0D + invalidated. Address is returned. This function must be used with care=0D + because dirty cache lines are not written back to system memory. It is=0D + typically used for cache diagnostics. If the CPU does not support=0D + invalidation of a data cache range, then a write back and invalidate=0D + operation should be performed on the data cache range.=0D +=0D + If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().=0D +=0D + @param[in] Address The base address of the data cache lines to invalida= te. If=0D + the CPU is in a physical addressing mode, then Address i= s a=0D + physical address. If the CPU is in a virtual addressing = mode,=0D + then Address is a virtual address.=0D + @param[in] Length The number of bytes to invalidate from the data cach= e.=0D +=0D + @return Address.=0D +=0D +**/=0D +VOID *=0D +EFIAPI=0D +InvalidateDataCacheRange (=0D + IN VOID *Address,=0D + IN UINTN Length=0D + )=0D +{=0D + AsmDataBarrierLoongArch ();=0D + return Address;=0D +}=0D --=20 2.27.0
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[PATCH v3 24/34] MdePkg/BaseLib: BaseLib for LOONGARCH64 architecture.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
Add LoongArch LOONGARCH64 BaseLib functions. Cc: Michael D Kinney <michael.d.kinney@...> Cc: Liming Gao <gaoliming@...> Cc: Zhiguang Liu <zhiguang.liu@...> Signed-off-by: Chao Li <lichao@...> Co-authored-by: Baoqi Zhang <zhangbaoqi@...> Reviewed-by: Michael D Kinney <michael.d.kinney@...> --- MdePkg/Include/Library/BaseLib.h | 24 ++++++++ MdePkg/Library/BaseLib/BaseLib.inf | 16 ++++- MdePkg/Library/BaseLib/LoongArch64/Barrier.S | 28 +++++++++ .../BaseLib/LoongArch64/CpuBreakpoint.S | 24 ++++++++ MdePkg/Library/BaseLib/LoongArch64/CpuPause.S | 31 ++++++++++ .../BaseLib/LoongArch64/DisableInterrupts.S | 21 +++++++ .../BaseLib/LoongArch64/EnableInterrupts.S | 21 +++++++ .../BaseLib/LoongArch64/GetInterruptState.S | 35 +++++++++++ .../BaseLib/LoongArch64/InternalSwitchStack.c | 58 +++++++++++++++++++ .../Library/BaseLib/LoongArch64/MemoryFence.S | 18 ++++++ .../BaseLib/LoongArch64/SetJumpLongJump.S | 49 ++++++++++++++++ .../Library/BaseLib/LoongArch64/SwitchStack.S | 39 +++++++++++++ 12 files changed, 363 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Library/BaseLib/LoongArch64/Barrier.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/CpuPause.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c create mode 100644 MdePkg/Library/BaseLib/LoongArch64/MemoryFence.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S create mode 100644 MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/Base= Lib.h index a6f9a194ef..f3f59f21c2 100644 --- a/MdePkg/Include/Library/BaseLib.h +++ b/MdePkg/Include/Library/BaseLib.h @@ -6,6 +6,7 @@ Copyright (c) 2006 - 2021, Intel Corporation. All rights re= served.<BR> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>=0D Copyright (c) Microsoft Corporation.<BR>=0D Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.<BR>=0D +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All = rights reserved.<BR>=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -152,6 +153,29 @@ typedef struct { =0D #endif // defined (MDE_CPU_RISCV64)=0D =0D +#if defined (MDE_CPU_LOONGARCH64)=0D +///=0D +/// The LoongArch architecture context buffer used by SetJump() and LongJu= mp()=0D +///=0D +typedef struct {=0D + UINT64 S0;=0D + UINT64 S1;=0D + UINT64 S2;=0D + UINT64 S3;=0D + UINT64 S4;=0D + UINT64 S5;=0D + UINT64 S6;=0D + UINT64 S7;=0D + UINT64 S8;=0D + UINT64 SP;=0D + UINT64 FP;=0D + UINT64 RA;=0D +} BASE_LIBRARY_JUMP_BUFFER;=0D +=0D +#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8=0D +=0D +#endif // defined (MDE_CPU_LOONGARCH64)=0D +=0D //=0D // String Services=0D //=0D diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/Ba= seLib.inf index 6be5be9428..9ed46a584a 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -21,7 +21,7 @@ LIBRARY_CLASS =3D BaseLib=0D =0D #=0D -# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64=0D +# VALID_ARCHITECTURES =3D IA32 X64 EBC ARM AARCH64 RISCV64 LOON= GARCH64=0D #=0D =0D [Sources]=0D @@ -402,6 +402,20 @@ RiscV64/RiscVInterrupt.S | GCC=0D RiscV64/FlushCache.S | GCC=0D =0D +[Sources.LOONGARCH64]=0D + Math64.c=0D + Unaligned.c=0D + LoongArch64/InternalSwitchStack.c=0D + LoongArch64/GetInterruptState.S | GCC=0D + LoongArch64/EnableInterrupts.S | GCC=0D + LoongArch64/DisableInterrupts.S | GCC=0D + LoongArch64/Barrier.S | GCC=0D + LoongArch64/MemoryFence.S | GCC=0D + LoongArch64/CpuBreakpoint.S | GCC=0D + LoongArch64/CpuPause.S | GCC=0D + LoongArch64/SetJumpLongJump.S | GCC=0D + LoongArch64/SwitchStack.S | GCC=0D +=0D [Packages]=0D MdePkg/MdePkg.dec=0D =0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/Barrier.S b/MdePkg/Library/= BaseLib/LoongArch64/Barrier.S new file mode 100644 index 0000000000..58f21ad725 --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/Barrier.S @@ -0,0 +1,28 @@ +#-------------------------------------------------------------------------= ----- +# +# LoongArch Barrier Operations +# +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR> +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#-------------------------------------------------------------------------= ----- + +ASM_GLOBAL ASM_PFX(AsmDataBarrierLoongArch) +ASM_GLOBAL ASM_PFX(AsmInstructionBarrierLoongArch) + +# +# Data barrier operation for LoongArch. +# +ASM_PFX(AsmDataBarrierLoongArch): + dbar 0 + jirl $zero, $ra, 0 + +# +# Instruction barrier operation for LoongArch. +# +ASM_PFX(AsmInstructionBarrierLoongArch): + ibar 0 + jirl $zero, $ra, 0 + + .end diff --git a/MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S b/MdePkg/Li= brary/BaseLib/LoongArch64/CpuBreakpoint.S new file mode 100644 index 0000000000..4e022e9bb5 --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/CpuBreakpoint.S @@ -0,0 +1,24 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# CpuBreakpoint for LoongArch=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +ASM_GLOBAL ASM_PFX(CpuBreakpoint)=0D +=0D +#/**=0D +# Generates a breakpoint on the CPU.=0D +#=0D +# Generates a breakpoint on the CPU. The breakpoint must be implemented s= uch=0D +# that code can resume normal execution after the breakpoint.=0D +#=0D +#**/=0D +=0D +ASM_PFX(CpuBreakpoint):=0D + break 3=0D + jirl $zero, $ra, 0=0D + .end=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/CpuPause.S b/MdePkg/Library= /BaseLib/LoongArch64/CpuPause.S new file mode 100644 index 0000000000..e9140e8742 --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/CpuPause.S @@ -0,0 +1,31 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# CpuPause for LoongArch=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +ASM_GLOBAL ASM_PFX(CpuPause)=0D +=0D +#/**=0D +# Requests CPU to pause for a short period of time.=0D +#=0D +# Requests CPU to pause for a short period of time. Typically used in MP= =0D +# systems to prevent memory starvation while waiting for a spin lock.=0D +#=0D +#**/=0D +=0D +ASM_PFX(CpuPause):=0D + nop=0D + nop=0D + nop=0D + nop=0D + nop=0D + nop=0D + nop=0D + nop=0D + jirl $zero, $ra, 0=0D + .end=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S b/MdePk= g/Library/BaseLib/LoongArch64/DisableInterrupts.S new file mode 100644 index 0000000000..0f228339af --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/DisableInterrupts.S @@ -0,0 +1,21 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# LoongArch interrupt disable=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +ASM_GLOBAL ASM_PFX(DisableInterrupts)=0D +=0D +#/**=0D +# Disables CPU interrupts.=0D +#**/=0D +=0D +ASM_PFX(DisableInterrupts):=0D + li.w $t0, 0x4=0D + csrxchg $zero, $t0, 0x0=0D + jirl $zero, $ra, 0=0D + .end=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S b/MdePkg= /Library/BaseLib/LoongArch64/EnableInterrupts.S new file mode 100644 index 0000000000..3c34fb2cdd --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/EnableInterrupts.S @@ -0,0 +1,21 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# LoongArch interrupt enable=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +ASM_GLOBAL ASM_PFX(EnableInterrupts)=0D +=0D +#/**=0D +# Enables CPU interrupts.=0D +#**/=0D +=0D +ASM_PFX(EnableInterrupts):=0D + li.w $t0, 0x4=0D + csrxchg $t0, $t0, 0x0=0D + jirl $zero, $ra, 0=0D + .end=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S b/MdePk= g/Library/BaseLib/LoongArch64/GetInterruptState.S new file mode 100644 index 0000000000..bfd1f2d5f7 --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/GetInterruptState.S @@ -0,0 +1,35 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# Get LoongArch interrupt status=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +ASM_GLOBAL ASM_PFX(GetInterruptState)=0D +=0D +#/**=0D +# Retrieves the current CPU interrupt state.=0D +#=0D +# Returns TRUE means interrupts are currently enabled. Otherwise,=0D +# returns FALSE.=0D +#=0D +# @retval TRUE CPU interrupts are enabled.=0D +# @retval FALSE CPU interrupts are disabled.=0D +#=0D +#**/=0D +=0D +ASM_PFX(GetInterruptState):=0D + li.w $t1, 0x4=0D + csrrd $t0, 0x0=0D + and $t0, $t0, $t1=0D + beqz $t0, 1f=0D + li.w $a0, 0x1=0D + b 2f=0D +1:=0D + li.w $a0, 0x0=0D +2:=0D + jirl $zero, $ra, 0=0D + .end=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c b/Mde= Pkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c new file mode 100644 index 0000000000..859bc96329 --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/InternalSwitchStack.c @@ -0,0 +1,58 @@ +/** @file=0D + SwitchStack() function for LoongArch.=0D +=0D + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "BaseLibInternals.h"=0D +=0D +UINTN=0D +EFIAPI=0D +InternalSwitchStackAsm (=0D + IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer=0D + );=0D +=0D +/**=0D + Transfers control to a function starting with a new stack.=0D +=0D + Transfers control to the function specified by EntryPoint using the=0D + new stack specified by NewStack and passing in the parameters specified= =0D + by Context1 and Context2. Context1 and Context2 are optional and may=0D + be NULL. The function EntryPoint must never return.=0D +=0D + If EntryPoint is NULL, then ASSERT().=0D + If NewStack is NULL, then ASSERT().=0D +=0D + @param[in] EntryPoint A pointer to function to call with the new stack= .=0D + @param[in] Context1 A pointer to the context to pass into the EntryP= oint=0D + function.=0D + @param[in] Context2 A pointer to the context to pass into the EntryP= oint=0D + function.=0D + @param[in] NewStack A pointer to the new stack to use for the EntryP= oint=0D + function.=0D + @param[in] Marker VA_LIST marker for the variable argument list.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +InternalSwitchStack (=0D + IN SWITCH_STACK_ENTRY_POINT EntryPoint,=0D + IN VOID *Context1 OPTIONAL,=0D + IN VOID *Context2 OPTIONAL,=0D + IN VOID *NewStack,=0D + IN VA_LIST Marker=0D + )=0D +=0D +{=0D + BASE_LIBRARY_JUMP_BUFFER JumpBuffer;=0D +=0D + JumpBuffer.RA =3D (UINTN)EntryPoint;=0D + JumpBuffer.SP =3D (UINTN)NewStack - sizeof (VOID *)= ;=0D + JumpBuffer.SP -=3D sizeof (Context1) + sizeof (Conte= xt2);=0D + ((VOID **)(UINTN)JumpBuffer.SP)[0] =3D Context1;=0D + ((VOID **)(UINTN)JumpBuffer.SP)[1] =3D Context2;=0D +=0D + InternalSwitchStackAsm (&JumpBuffer);=0D +}=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/MemoryFence.S b/MdePkg/Libr= ary/BaseLib/LoongArch64/MemoryFence.S new file mode 100644 index 0000000000..2b3d34366f --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/MemoryFence.S @@ -0,0 +1,18 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# MemoryFence() for LoongArch=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +ASM_GLOBAL ASM_PFX(MemoryFence)=0D +=0D +#=0D +# Memory fence for LoongArch=0D +#=0D +ASM_PFX(MemoryFence):=0D + b AsmDataBarrierLoongArch=0D + .end=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S b/MdePkg/= Library/BaseLib/LoongArch64/SetJumpLongJump.S new file mode 100644 index 0000000000..1c6ee54b6f --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/SetJumpLongJump.S @@ -0,0 +1,49 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# Set/Long jump for LoongArch=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +#define STORE st.d /* 64 bit mode regsave instruction */=0D +#define LOAD ld.d /* 64 bit mode regload instruction */=0D +#define RSIZE 8 /* 64 bit mode register size */=0D +=0D +ASM_GLOBAL ASM_PFX(SetJump)=0D +ASM_GLOBAL ASM_PFX(InternalLongJump)=0D +=0D +ASM_PFX(SetJump):=0D + STORE $s0, $a0, RSIZE * 0=0D + STORE $s1, $a0, RSIZE * 1=0D + STORE $s2, $a0, RSIZE * 2=0D + STORE $s3, $a0, RSIZE * 3=0D + STORE $s4, $a0, RSIZE * 4=0D + STORE $s5, $a0, RSIZE * 5=0D + STORE $s6, $a0, RSIZE * 6=0D + STORE $s7, $a0, RSIZE * 7=0D + STORE $s8, $a0, RSIZE * 8=0D + STORE $sp, $a0, RSIZE * 9=0D + STORE $fp, $a0, RSIZE * 10=0D + STORE $ra, $a0, RSIZE * 11=0D + li.w $a0, 0 # Setjmp return=0D + jirl $zero, $ra, 0=0D +=0D +ASM_PFX(InternalLongJump):=0D + LOAD $ra, $a0, RSIZE * 11=0D + LOAD $s0, $a0, RSIZE * 0=0D + LOAD $s1, $a0, RSIZE * 1=0D + LOAD $s2, $a0, RSIZE * 2=0D + LOAD $s3, $a0, RSIZE * 3=0D + LOAD $s4, $a0, RSIZE * 4=0D + LOAD $s5, $a0, RSIZE * 5=0D + LOAD $s6, $a0, RSIZE * 6=0D + LOAD $s7, $a0, RSIZE * 7=0D + LOAD $s8, $a0, RSIZE * 8=0D + LOAD $sp, $a0, RSIZE * 9=0D + LOAD $fp, $a0, RSIZE * 10=0D + move $a0, $a1=0D + jirl $zero, $ra, 0=0D + .end=0D diff --git a/MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S b/MdePkg/Libr= ary/BaseLib/LoongArch64/SwitchStack.S new file mode 100644 index 0000000000..ad9aa8b343 --- /dev/null +++ b/MdePkg/Library/BaseLib/LoongArch64/SwitchStack.S @@ -0,0 +1,39 @@ +#-------------------------------------------------------------------------= -----=0D +#=0D +# InternalSwitchStackAsm for LoongArch=0D +#=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +#=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +#-------------------------------------------------------------------------= -----=0D +=0D +#define STORE st.d /* 64 bit mode regsave instruction */=0D +#define LOAD ld.d /* 64 bit mode regload instruction */=0D +#define RSIZE 8 /* 64 bit mode register size */=0D +=0D +ASM_GLOBAL ASM_PFX(InternalSwitchStackAsm)=0D +=0D +/**=0D + This allows the caller to switch the stack and goes to the new entry poi= nt=0D +=0D + @param JumpBuffer A pointer to CPU context buffer.=0D +**/=0D +=0D +ASM_PFX(InternalSwitchStackAsm):=0D + LOAD $ra, $a0, RSIZE * 11=0D + LOAD $s0, $a0, RSIZE * 0=0D + LOAD $s1, $a0, RSIZE * 1=0D + LOAD $s2, $a0, RSIZE * 2=0D + LOAD $s3, $a0, RSIZE * 3=0D + LOAD $s4, $a0, RSIZE * 4=0D + LOAD $s5, $a0, RSIZE * 5=0D + LOAD $s6, $a0, RSIZE * 6=0D + LOAD $s7, $a0, RSIZE * 7=0D + LOAD $s8, $a0, RSIZE * 8=0D + LOAD $sp, $a0, RSIZE * 9=0D + LOAD $fp, $a0, RSIZE * 10=0D + LOAD $a0, $sp, 0=0D + LOAD $a1, $sp, 8=0D + jirl $zero, $ra, 0=0D + .end=0D --=20 2.27.0
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[PATCH v3 23/34] MdePkg/Include: LoongArch definitions.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
Add LoongArch processor related definitions. For the Http boot and PXE boot types seeing this URL section "Processor Architecture Type" for the LOONGARCH values: https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml For definitions of PE/COFF and LOONGARCH relocation types, see the "Machine Types" and "Basic Relocation Types" sections of this URL for LOONGARCH values: https://docs.microsoft.com/en-us/windows/win32/debug/pe-format For the register definitions of exceptions context, see the UEFI V2.10 18.2.2, 18.2.4 and 18.2.5 sections of this URL for LOONGARCH definitions: https://uefi.org/specs/UEFI/2.10/18_Protocols_Debugger_Support.html Cc: Michael D Kinney <michael.d.kinney@...> Cc: Liming Gao <gaoliming@...> Cc: Zhiguang Liu <zhiguang.liu@...> Signed-off-by: Chao Li <lichao@...> Reviewed-by: Michael D Kinney <michael.d.kinney@...> Reviewed-by: Liming Gao <gaoliming@...> --- MdePkg/Include/IndustryStandard/PeImage.h | 9 ++ MdePkg/Include/Protocol/DebugSupport.h | 107 ++++++++++++++++++++-- MdePkg/Include/Protocol/PxeBaseCode.h | 3 + MdePkg/Include/Uefi/UefiBaseType.h | 14 +++ MdePkg/Include/Uefi/UefiSpec.h | 16 ++-- 5 files changed, 136 insertions(+), 13 deletions(-) diff --git a/MdePkg/Include/IndustryStandard/PeImage.h b/MdePkg/Include/Ind= ustryStandard/PeImage.h index 3109dc20f8..dd4cc25483 100644 --- a/MdePkg/Include/IndustryStandard/PeImage.h +++ b/MdePkg/Include/IndustryStandard/PeImage.h @@ -10,6 +10,7 @@ Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>=0D Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>=0D Portions Copyright (c) 2016 - 2020, Hewlett Packard Enterprise Development= LP. All rights reserved.<BR>=0D +Portions Copyright (c) 2022, Loongson Technology Corporation Limited. All = rights reserved.<BR>=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -38,6 +39,8 @@ SPDX-License-Identifier: BSD-2-Clause-Patent #define IMAGE_FILE_MACHINE_RISCV32 0x5032=0D #define IMAGE_FILE_MACHINE_RISCV64 0x5064=0D #define IMAGE_FILE_MACHINE_RISCV128 0x5128=0D +#define IMAGE_FILE_MACHINE_LOONGARCH32 0x6232=0D +#define IMAGE_FILE_MACHINE_LOONGARCH64 0x6264=0D =0D //=0D // EXE file formats=0D @@ -503,6 +506,12 @@ typedef struct { #define EFI_IMAGE_REL_BASED_RISCV_LOW12I 7=0D #define EFI_IMAGE_REL_BASED_RISCV_LOW12S 8=0D =0D +//=0D +// Relocation types of LoongArch processor.=0D +//=0D +#define EFI_IMAGE_REL_BASED_LOONGARCH32_MARK_LA 8=0D +#define EFI_IMAGE_REL_BASED_LOONGARCH64_MARK_LA 8=0D +=0D ///=0D /// Line number format.=0D ///=0D diff --git a/MdePkg/Include/Protocol/DebugSupport.h b/MdePkg/Include/Protoc= ol/DebugSupport.h index ec5b92a5c5..2b0ae2d157 100644 --- a/MdePkg/Include/Protocol/DebugSupport.h +++ b/MdePkg/Include/Protocol/DebugSupport.h @@ -654,17 +654,110 @@ typedef struct { UINT64 X31;=0D } EFI_SYSTEM_CONTEXT_RISCV64;=0D =0D +//=0D +// LoongArch processor exception types.=0D +//=0D +#define EXCEPT_LOONGARCH_INT 0=0D +#define EXCEPT_LOONGARCH_PIL 1=0D +#define EXCEPT_LOONGARCH_PIS 2=0D +#define EXCEPT_LOONGARCH_PIF 3=0D +#define EXCEPT_LOONGARCH_PME 4=0D +#define EXCEPT_LOONGARCH_PNR 5=0D +#define EXCEPT_LOONGARCH_PNX 6=0D +#define EXCEPT_LOONGARCH_PPI 7=0D +#define EXCEPT_LOONGARCH_ADE 8=0D +#define EXCEPT_LOONGARCH_ALE 9=0D +#define EXCEPT_LOONGARCH_BCE 10=0D +#define EXCEPT_LOONGARCH_SYS 11=0D +#define EXCEPT_LOONGARCH_BRK 12=0D +#define EXCEPT_LOONGARCH_INE 13=0D +#define EXCEPT_LOONGARCH_IPE 14=0D +#define EXCEPT_LOONGARCH_FPD 15=0D +#define EXCEPT_LOONGARCH_SXD 16=0D +#define EXCEPT_LOONGARCH_ASXD 17=0D +#define EXCEPT_LOONGARCH_FPE 18=0D +#define EXCEPT_LOONGARCH_TBR 64 // For code only, there is no such type = in the ISA spec, the TLB refill is defined for an independent exception.=0D +=0D +//=0D +// LoongArch processor Interrupt types.=0D +//=0D +#define EXCEPT_LOONGARCH_INT_SIP0 0=0D +#define EXCEPT_LOONGARCH_INT_SIP1 1=0D +#define EXCEPT_LOONGARCH_INT_IP0 2=0D +#define EXCEPT_LOONGARCH_INT_IP1 3=0D +#define EXCEPT_LOONGARCH_INT_IP2 4=0D +#define EXCEPT_LOONGARCH_INT_IP3 5=0D +#define EXCEPT_LOONGARCH_INT_IP4 6=0D +#define EXCEPT_LOONGARCH_INT_IP5 7=0D +#define EXCEPT_LOONGARCH_INT_IP6 8=0D +#define EXCEPT_LOONGARCH_INT_IP7 9=0D +#define EXCEPT_LOONGARCH_INT_PMC 10=0D +#define EXCEPT_LOONGARCH_INT_TIMER 11=0D +#define EXCEPT_LOONGARCH_INT_IPI 12=0D +=0D +//=0D +// For coding convenience, define the maximum valid=0D +// LoongArch interrupt.=0D +//=0D +#define MAX_LOONGARCH_INTERRUPT 14=0D +=0D +typedef struct {=0D + UINT64 R0;=0D + UINT64 R1;=0D + UINT64 R2;=0D + UINT64 R3;=0D + UINT64 R4;=0D + UINT64 R5;=0D + UINT64 R6;=0D + UINT64 R7;=0D + UINT64 R8;=0D + UINT64 R9;=0D + UINT64 R10;=0D + UINT64 R11;=0D + UINT64 R12;=0D + UINT64 R13;=0D + UINT64 R14;=0D + UINT64 R15;=0D + UINT64 R16;=0D + UINT64 R17;=0D + UINT64 R18;=0D + UINT64 R19;=0D + UINT64 R20;=0D + UINT64 R21;=0D + UINT64 R22;=0D + UINT64 R23;=0D + UINT64 R24;=0D + UINT64 R25;=0D + UINT64 R26;=0D + UINT64 R27;=0D + UINT64 R28;=0D + UINT64 R29;=0D + UINT64 R30;=0D + UINT64 R31;=0D +=0D + UINT64 CRMD; // CuRrent MoDe information=0D + UINT64 PRMD; // PRe-exception MoDe information=0D + UINT64 EUEN; // Extended component Unit ENable=0D + UINT64 MISC; // MISCellaneous controller=0D + UINT64 ECFG; // Exception ConFiGuration=0D + UINT64 ESTAT; // Exception STATus=0D + UINT64 ERA; // Exception Return Address=0D + UINT64 BADV; // BAD Virtual address=0D + UINT64 BADI; // BAD Instruction=0D +} EFI_SYSTEM_CONTEXT_LOONGARCH64;=0D +=0D ///=0D /// Universal EFI_SYSTEM_CONTEXT definition.=0D ///=0D typedef union {=0D - EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;=0D - EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;=0D - EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;=0D - EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;=0D - EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;=0D - EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;=0D - EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;=0D + EFI_SYSTEM_CONTEXT_EBC *SystemContextEbc;=0D + EFI_SYSTEM_CONTEXT_IA32 *SystemContextIa32;=0D + EFI_SYSTEM_CONTEXT_X64 *SystemContextX64;=0D + EFI_SYSTEM_CONTEXT_IPF *SystemContextIpf;=0D + EFI_SYSTEM_CONTEXT_ARM *SystemContextArm;=0D + EFI_SYSTEM_CONTEXT_AARCH64 *SystemContextAArch64;=0D + EFI_SYSTEM_CONTEXT_RISCV64 *SystemContextRiscV64;=0D + EFI_SYSTEM_CONTEXT_LOONGARCH64 *SystemContextLoongArch64;=0D } EFI_SYSTEM_CONTEXT;=0D =0D //=0D diff --git a/MdePkg/Include/Protocol/PxeBaseCode.h b/MdePkg/Include/Protoco= l/PxeBaseCode.h index 11872d602d..6787941a5d 100644 --- a/MdePkg/Include/Protocol/PxeBaseCode.h +++ b/MdePkg/Include/Protocol/PxeBaseCode.h @@ -4,6 +4,7 @@ =0D Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>=0D Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights = reserved.<BR>=0D +Copyright (c) 2022, Loongson Technology Corporation Limited. All rights re= served.<BR>=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -158,6 +159,8 @@ typedef UINT16 EFI_PXE_BASE_CODE_UDP_PORT; #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x000B=0D #elif defined (MDE_CPU_RISCV64)=0D #define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x001B=0D +#elif defined (MDE_CPU_LOONGARCH64)=0D +#define EFI_PXE_CLIENT_SYSTEM_ARCHITECTURE 0x0027=0D #endif=0D =0D ///=0D diff --git a/MdePkg/Include/Uefi/UefiBaseType.h b/MdePkg/Include/Uefi/UefiB= aseType.h index 4a34ce8e25..83975a08eb 100644 --- a/MdePkg/Include/Uefi/UefiBaseType.h +++ b/MdePkg/Include/Uefi/UefiBaseType.h @@ -4,6 +4,7 @@ Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>=0D Portions copyright (c) 2011 - 2016, ARM Ltd. All rights reserved.<BR>=0D Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights = reserved.<BR>=0D +Copyright (c) 2022, Loongson Technology Corporation Limited. All rights re= served.<BR>=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -246,6 +247,12 @@ typedef union { #define EFI_IMAGE_MACHINE_RISCV64 0x5064=0D #define EFI_IMAGE_MACHINE_RISCV128 0x5128=0D =0D +///=0D +/// PE32+ Machine type for LoongArch 32/64 images.=0D +///=0D +#define EFI_IMAGE_MACHINE_LOONGARCH32 0x6232=0D +#define EFI_IMAGE_MACHINE_LOONGARCH64 0x6264=0D +=0D #if !defined (EFI_IMAGE_MACHINE_TYPE_VALUE) && !defined (EFI_IMAGE_MACHINE= _CROSS_TYPE_VALUE)=0D #if defined (MDE_CPU_IA32)=0D =0D @@ -278,6 +285,13 @@ typedef union { #define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \=0D ((Machine) =3D=3D EFI_IMAGE_MACHINE_RISCV64)=0D =0D +#define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)=0D +=0D + #elif defined (MDE_CPU_LOONGARCH64)=0D +=0D +#define EFI_IMAGE_MACHINE_TYPE_SUPPORTED(Machine) \=0D + ((Machine) =3D=3D EFI_IMAGE_MACHINE_LOONGARCH64)=0D +=0D #define EFI_IMAGE_MACHINE_CROSS_TYPE_SUPPORTED(Machine) (FALSE)=0D =0D #elif defined (MDE_CPU_EBC)=0D diff --git a/MdePkg/Include/Uefi/UefiSpec.h b/MdePkg/Include/Uefi/UefiSpec.h index 2b38b100f6..3abebbb8d9 100644 --- a/MdePkg/Include/Uefi/UefiSpec.h +++ b/MdePkg/Include/Uefi/UefiSpec.h @@ -7,6 +7,7 @@ =0D Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>=0D Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. Al= l rights reserved.<BR>=0D +Copyright (c) 2022, Loongson Technology Corporation Limited. All rights re= served.<BR>=0D =0D SPDX-License-Identifier: BSD-2-Clause-Patent=0D =0D @@ -2195,12 +2196,13 @@ typedef struct { //=0D // EFI File location to boot from on removable media devices=0D //=0D -#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 L"\\EFI\\BOOT\\BOOTIA32.EFI= "=0D -#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64 L"\\EFI\\BOOT\\BOOTIA64.EFI= "=0D -#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.EFI"= =0D -#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.EFI"= =0D -#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64.EFI= "=0D -#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISCV64.= EFI"=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA32 L"\\EFI\\BOOT\\BOOTIA32= .EFI"=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME_IA64 L"\\EFI\\BOOT\\BOOTIA64= .EFI"=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME_X64 L"\\EFI\\BOOT\\BOOTX64.= EFI"=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME_ARM L"\\EFI\\BOOT\\BOOTARM.= EFI"=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH64 L"\\EFI\\BOOT\\BOOTAA64= .EFI"=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV64 L"\\EFI\\BOOT\\BOOTRISC= V64.EFI"=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME_LOONGARCH64 L"\\EFI\\BOOT\\BOOTLOON= GARCH64.EFI"=0D =0D #if !defined (EFI_REMOVABLE_MEDIA_FILE_NAME)=0D #if defined (MDE_CPU_IA32)=0D @@ -2214,6 +2216,8 @@ typedef struct { #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_AARCH= 64=0D #elif defined (MDE_CPU_RISCV64)=0D #define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_RISCV= 64=0D + #elif defined (MDE_CPU_LOONGARCH64)=0D +#define EFI_REMOVABLE_MEDIA_FILE_NAME EFI_REMOVABLE_MEDIA_FILE_NAME_LOONG= ARCH64=0D #else=0D #error Unknown Processor Type=0D #endif=0D --=20 2.27.0
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[PATCH v3 22/34] MdePkg: Add LoongArch LOONGARCH64 binding
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
Add LOONGARCH64 sections in MdePkg.dec and LOONGARCH64 ProcessorBind.h Cc: Michael D Kinney <michael.d.kinney@...> Cc: Liming Gao <gaoliming@...> Cc: Zhiguang Liu <zhiguang.liu@...> Signed-off-by: Chao Li <lichao@...> Co-authored-by: Baoqi Zhang <zhangbaoqi@...> Co-authored-by: Dongyan Qian <qiandongyan@...> Reviewed-by: Michael D Kinney <michael.d.kinney@...> --- MdePkg/Include/LoongArch64/ProcessorBind.h | 120 +++++++++++++++++++++ MdePkg/MdePkg.dec | 4 + MdePkg/MdePkg.dsc | 3 +- 3 files changed, 126 insertions(+), 1 deletion(-) create mode 100644 MdePkg/Include/LoongArch64/ProcessorBind.h diff --git a/MdePkg/Include/LoongArch64/ProcessorBind.h b/MdePkg/Include/Lo= ongArch64/ProcessorBind.h new file mode 100644 index 0000000000..502d479099 --- /dev/null +++ b/MdePkg/Include/LoongArch64/ProcessorBind.h @@ -0,0 +1,120 @@ +/** @file=0D + Processor or Compiler specific defines and types for LoongArch=0D +=0D + Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D +=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +=0D +**/=0D +=0D +#ifndef PROCESSOR_BIND_H_=0D +#define PROCESSOR_BIND_H_=0D +=0D +//=0D +// Define the processor type so other code can make processor based choice= s=0D +//=0D +#define MDE_CPU_LOONGARCH64=0D +=0D +#define EFIAPI=0D +=0D +//=0D +// Make sure we are using the correct packing rules per EFI specification= =0D +//=0D +#ifndef __GNUC__=0D + #pragma pack()=0D +#endif=0D +=0D +//=0D +// Assume standard LoongArch 64-bit alignment.=0D +// Need to check portability of long long=0D +//=0D +typedef unsigned long UINT64;=0D +typedef long INT64;=0D +typedef unsigned int UINT32;=0D +typedef int INT32;=0D +typedef unsigned short UINT16;=0D +typedef unsigned short CHAR16;=0D +typedef short INT16;=0D +typedef unsigned char BOOLEAN;=0D +typedef unsigned char UINT8;=0D +typedef char CHAR8;=0D +typedef char INT8;=0D +=0D +//=0D +// Unsigned value of native width. (4 bytes on supported 32-bit processor= instructions,=0D +// 8 bytes on supported 64-bit processor instructions)=0D +//=0D +=0D +typedef UINT64 UINTN;=0D +=0D +//=0D +// Signed value of native width. (4 bytes on supported 32-bit processor i= nstructions,=0D +// 8 bytes on supported 64-bit processor instructions)=0D +//=0D +typedef INT64 INTN;=0D +=0D +//=0D +// Processor specific defines=0D +//=0D +=0D +//=0D +// A value of native width with the highest bit set.=0D +//=0D +#define MAX_BIT 0x8000000000000000ULL=0D +//=0D +// A value of native width with the two highest bits set.=0D +//=0D +#define MAX_2_BITS 0xC000000000000000ULL=0D +=0D +//=0D +// Maximum legal LoongArch 64-bit address=0D +//=0D +#define MAX_ADDRESS 0xFFFFFFFFFFFFFFFFULL=0D +=0D +//=0D +// Maximum usable address at boot time (48 bits using 4KB pages)=0D +//=0D +#define MAX_ALLOC_ADDRESS 0xFFFFFFFFFFFFULL=0D +=0D +//=0D +// Maximum legal LoongArch 64-bit INTN and UINTN values.=0D +//=0D +#define MAX_INTN ((INTN)0x7FFFFFFFFFFFFFFFULL)=0D +#define MAX_UINTN ((UINTN)0xFFFFFFFFFFFFFFFFULL)=0D +=0D +//=0D +// Page allocation granularity for LoongArch=0D +//=0D +#define DEFAULT_PAGE_ALLOCATION_GRANULARITY (0x1000)=0D +#define RUNTIME_PAGE_ALLOCATION_GRANULARITY (0x10000)=0D +=0D +#if defined (__GNUC__)=0D +//=0D +// For GNU assembly code, .global or .globl can declare global symbols.=0D +// Define this macro to unify the usage.=0D +//=0D +#define ASM_GLOBAL .globl=0D +#endif=0D +=0D +//=0D +// The stack alignment required for LoongArch=0D +//=0D +#define CPU_STACK_ALIGNMENT 16=0D +=0D +/**=0D + Return the pointer to the first instruction of a function given a functi= on pointer.=0D + On LOONGARCH CPU architectures, these two pointer values are the same,=0D + so the implementation of this macro is very simple.=0D +=0D + @param FunctionPointer A pointer to a function.=0D +=0D + @return The pointer to the first instruction of a function given a funct= ion pointer.=0D +=0D +**/=0D +#define FUNCTION_ENTRY_POINT(FunctionPointer) (VOID *)(UINTN)(FunctionPoi= nter)=0D +=0D +#ifndef __USER_LABEL_PREFIX__=0D +#define __USER_LABEL_PREFIX__=0D +#endif=0D +=0D +#endif=0D diff --git a/MdePkg/MdePkg.dec b/MdePkg/MdePkg.dec index f1ebf9e251..4c81cbd75a 100644 --- a/MdePkg/MdePkg.dec +++ b/MdePkg/MdePkg.dec @@ -7,6 +7,7 @@ # Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>=0D # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>= =0D # (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP<BR>= =0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -43,6 +44,9 @@ [Includes.RISCV64]=0D Include/RiscV64=0D =0D +[Includes.LOONGARCH64]=0D + Include/LoongArch64=0D +=0D [LibraryClasses]=0D ## @libraryclass Provides most usb APIs to support the Hid requests de= fined in Usb Hid 1.1 spec=0D # and the standard requests defined in Usb 1.1 spec.=0D diff --git a/MdePkg/MdePkg.dsc b/MdePkg/MdePkg.dsc index cc1ac196a9..493a13ec91 100644 --- a/MdePkg/MdePkg.dsc +++ b/MdePkg/MdePkg.dsc @@ -4,6 +4,7 @@ # Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>=0D # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>= =0D # (C) Copyright 2020 Hewlett Packard Enterprise Development LP<BR>=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D #=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D @@ -15,7 +16,7 @@ PLATFORM_VERSION =3D 1.08=0D DSC_SPECIFICATION =3D 0x00010005=0D OUTPUT_DIRECTORY =3D Build/Mde=0D - SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64|RISCV64=0D + SUPPORTED_ARCHITECTURES =3D IA32|X64|EBC|ARM|AARCH64|RISCV64|LOON= GARCH64=0D BUILD_TARGETS =3D DEBUG|RELEASE|NOOPT=0D SKUID_IDENTIFIER =3D DEFAULT=0D =0D --=20 2.27.0
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[PATCH v3 21/34] .pytool: Add LoongArch64 architecture on LoongArch64 EDK2 CI.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
Add LoongArch64 architecture on LoongArch64 EDK2 CI testing. Cc: Michael D Kinney <michael.d.kinney@...> Cc: Liming Gao <gaoliming@...> Signed-off-by: Chao Li <lichao@...> Reviewed-by: Michael D Kinney <michael.d.kinney@...> --- .pytool/CISettings.py | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/.pytool/CISettings.py b/.pytool/CISettings.py index cf9e0d77b1..7ebec0ba0a 100644 --- a/.pytool/CISettings.py +++ b/.pytool/CISettings.py @@ -79,7 +79,8 @@ class Settings(CiBuildSettingsManager, UpdateSettingsMana= ger, SetupSettingsManag "X64",=0D "ARM",=0D "AARCH64",=0D - "RISCV64")=0D + "RISCV64",=0D + "LOONGARCH64")=0D =0D def GetTargetsSupported(self):=0D ''' return iterable of edk2 target tags supported by this build ''= '=0D @@ -170,6 +171,8 @@ class Settings(CiBuildSettingsManager, UpdateSettingsMa= nager, SetupSettingsManag scopes +=3D ("gcc_arm_linux",)=0D if "RISCV64" in self.ActualArchitectures:=0D scopes +=3D ("gcc_riscv64_unknown",)=0D + if "LOONGARCH64" in self.ActualArchitectures:=0D + scopes +=3D ("gcc_loongarch64_unknown_linux",)=0D self.ActualScopes =3D scopes=0D return self.ActualScopes=0D =0D --=20 2.27.0
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[PATCH v3 20/34] .azurepipelines: Add LoongArch64 architecture on LoongArch64 EDK2 CI.
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D4053
Add LoongArch64 architecture on LoongArch64 EDK2 CI. Cc: Michael D Kinney <michael.d.kinney@...> Cc: Liming Gao <gaoliming@...> Signed-off-by: Chao Li <lichao@...> Reviewed-by: Michael D Kinney <michael.d.kinney@...> --- .azurepipelines/Ubuntu-GCC5.yml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.azurepipelines/Ubuntu-GCC5.yml b/.azurepipelines/Ubuntu-GCC5.= yml index 3760c6efe1..1acd8d2a46 100644 --- a/.azurepipelines/Ubuntu-GCC5.yml +++ b/.azurepipelines/Ubuntu-GCC5.yml @@ -3,6 +3,7 @@ #=0D # Copyright (c) Microsoft Corporation.=0D # Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All right= s reserved.<BR>=0D +# Copyright (c) 2022, Loongson Technology Corporation Limited. All rights = reserved.<BR>=0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D ##=0D trigger:=0D @@ -17,5 +18,5 @@ jobs: parameters:=0D tool_chain_tag: 'GCC5'=0D vm_image: 'ubuntu-latest'=0D - arch_list: "IA32,X64,ARM,AARCH64,RISCV64"=0D + arch_list: "IA32,X64,ARM,AARCH64,RISCV64,LOONGARCH64"=0D =0D --=20 2.27.0
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