Date   

Re: [edk2-platforms][PATCH 1/1] Silicon/Broadcom/Bcm27xx: Allow more than one device on pcie busses >1

Jeremy Linton
 

Hi,

On 3/11/21 4:56 PM, René Treffer wrote:
There is only a single pcie port on the bcm2711 so limiting the number of
devices to 1 worked as long as there is no way to add a pcie switch.
I thought this got merged, but I just rebased and realized it didn't.

Which is just as well, because there is a bug on the CM4 that should be part of this patch. If nothing is pulled into the slot, then the PCIe link is down. At that point, access to BUS > 0 will fault. So we need an additional check.

On the compute module 4 it is possible to add a pcie switch (tested with
asm1184e) which adds 5 new pcie busses.
In the current state the pci enumeration fails for the pcie switch
internal bus (usually bus 2, device 1,3,5,7). The root port gets
configured with
subordniate=0x2 after enumeration. That blocks e.g. linux from discovering
devices behind the switch.
Devices behind the switch work after lifting the device limit on busses
other than 0 and 1.
---
 .../Library/Bcm2711PciSegmentLib/PciSegmentLib.c   | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)
diff --git
a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
index 44ce3b4b99..4af9374d23 100644
--- a/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
+++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2711PciSegmentLib/PciSegmentLib.c
@@ -78,6 +78,7 @@ PciSegmentLibGetConfigBase (
   UINT64        Base;
   UINT64        Offset;
   UINT32        Dev;
+  UINT32        Bus;
   Base = PCIE_REG_BASE;
   Offset = Address & 0xFFF;         /* Pick off the 4k register offset */
@@ -89,17 +90,16 @@ PciSegmentLibGetConfigBase (
     Base += PCIE_EXT_CFG_DATA;
     if (mPciSegmentLastAccess != Address) {
       Dev = EFI_PCI_ADDR_DEV (Address);
+      Bus = EFI_PCI_ADDR_BUS (Address);
       /*
-       * Scan things out directly rather than translating the "bus" to
a device, etc..
-       * only we need to limit each bus to a single device.
+       * There can only be a single device on bus 1 (downstream of root).
+       * Subsequent busses (behind a PCIe switch) could have more.
        */
-      if (Dev < 1) {
-          MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
-          mPciSegmentLastAccess = Address;
-      } else {
-          mPciSegmentLastAccess = 0;
+      if (Dev > 0 && (Bus == 1 || Bus == 0)) {
           return 0xFFFFFFFF;
       }
something like:

if (!(MmioRead32 (PCI_REG_BASE + PCI_MISC_PCI_STATUS) & 0x30))
return 0xFFFFFFFF; //link down

So, if you respin with that and the SOB Ard mentioned, I think its good. I finally got a CM4 last week, and have been plugging various things into it. This patch given the link check seems pretty solid, and surprisingly with the PCI/SMC+linux we even have AER!

That said, there is another link down "bug" in the constructor which shows up with debug builds when we exit out with a !0 return code.




+      MmioWrite32 (PCIE_REG_BASE + PCIE_EXT_CFG_INDEX, Address);
+      mPciSegmentLastAccess = Address;
     }
   }
   return Base + Offset;


Re: GSoC 2021 (MinPlatform, Ext2, ACPICA, etc)

Nate DeSimone
 

Hi Pedro,

 

Happy to hear our conversations here have helped 😊.

 

The ext4 project sounds good! I’d recommend putting write support on as a “if I have time at the end” stretch goal. Just getting read working and stable would be a great accomplishment. GSoC does end in August… but you can continue working on your driver afterwards. I don’t want you to find yourself in a situation in August were you have more work to do than time remaining and end up not getting paid!

 

Thanks,

Nate

 

From: Pedro Falcato <pedro.falcato@...>
Sent: Wednesday, March 31, 2021 1:43 PM
To: Desimone, Nathaniel L <nathaniel.l.desimone@...>; devel@edk2.groups.io
Subject: Re: [edk2-devel] GSoC 2021 (MinPlatform, Ext2, ACPICA, etc)

 

Hi Nate,

Everything you said sounds great :))
I did end up going with ext4 as a target, as I find it's the more useful and more interesting project, the only thing I'm not too sure of is whether or not to add write support as one of the project's targets.
Anyway, I've just shared my draft with Tianocore, feel free give out some much wanted(and needed!) feedback!

Thanks,

Pedro


Re: GSoC 2021 (MinPlatform, Ext2, ACPICA, etc)

Pedro Falcato
 

Hi Bret,

I've shared the project's draft with Tianocore, take a look and give out some feedback if you want to :)
Thanks, it's great to work with you folks too!

Pedro


Re: GSoC 2021 (MinPlatform, Ext2, ACPICA, etc)

Pedro Falcato
 

Hi Nate,

Everything you said sounds great :))
I did end up going with ext4 as a target, as I find it's the more useful and more interesting project, the only thing I'm not too sure of is whether or not to add write support as one of the project's targets.
Anyway, I've just shared my draft with Tianocore, feel free give out some much wanted(and needed!) feedback!

Thanks,

Pedro


[PATCH edk2-test 1/1] uefi-sct/SctPkg: fix BuildAtaDeviceNode()

Heinrich Schuchardt
 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3290

When BuildAtaDeviceNode() is called with L"Ata(0,0,0)" it creates a node
Ata(1,1,0). This leads to test to an assertion failed test result

../DevicePathToTextBBTestFunction.c:332:
Convert result: Ata(0,0,0) - Expected: Ata(Primary,Master,0)

Signed-off-by: Heinrich Schuchardt <xypron.glpk@...>
=2D--
.../BlackBoxTest/DevicePathToTextBBTestMain.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/DevicePathToText/B=
lackBoxTest/DevicePathToTextBBTestMain.c b/uefi-sct/SctPkg/TestCase/UEFI/E=
FI/Protocol/DevicePathToText/BlackBoxTest/DevicePathToTextBBTestMain.c
index 7cf473d30643..59f9cc71831b 100644
=2D-- a/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/DevicePathToText/BlackB=
oxTest/DevicePathToTextBBTestMain.c
+++ b/uefi-sct/SctPkg/TestCase/UEFI/EFI/Protocol/DevicePathToText/BlackBox=
Test/DevicePathToTextBBTestMain.c
@@ -1162,9 +1162,9 @@ BuildAtaDeviceNode (

Status =3D GetNextRequiredParam(&TextDeviceNode, L"Controller", &ParamI=
dentifierStr, &ParamIdentifierVal);
if ((!EFI_ERROR(Status)) && (ParamIdentifierVal !=3D NULL)) {
- if ((SctStrCmp (ParamIdentifierVal, L"Primary") =3D=3D 0) || (SctStrCm=
p(ParamIdentifierVal, L"0"))) {
+ if ((SctStrCmp (ParamIdentifierVal, L"Primary") =3D=3D 0) || (SctStrC=
mp(ParamIdentifierVal, L"0" =3D=3D 0))) {
Atapi->PrimarySecondary =3D 0;
- } else if ((SctStrCmp (ParamIdentifierVal, L"Secondary") =3D=3D 0) ||=
(SctStrCmp(ParamIdentifierVal, L"1"))) {
+ } else if ((SctStrCmp (ParamIdentifierVal, L"Secondary") =3D=3D 0) ||=
(SctStrCmp(ParamIdentifierVal, L"1" =3D=3D 0))) {
Atapi->PrimarySecondary =3D 1;
} else {
goto InValidText;
@@ -1175,9 +1175,9 @@ BuildAtaDeviceNode (

Status =3D GetNextRequiredParam(&TextDeviceNode, L"Drive", &ParamIdenti=
fierStr, &ParamIdentifierVal);
if ((!EFI_ERROR(Status)) && (ParamIdentifierVal !=3D NULL)) {
- if ((SctStrCmp (ParamIdentifierVal, L"Master") =3D=3D 0) || (SctStrCmp=
(ParamIdentifierVal, L"0"))) {
+ if ((SctStrCmp (ParamIdentifierVal, L"Master") =3D=3D 0) || (SctStrCm=
p(ParamIdentifierVal, L"0") =3D=3D 0)) {
Atapi->SlaveMaster =3D 0;
- } else if ((SctStrCmp (ParamIdentifierVal, L"Slave") =3D=3D 0) || (Sc=
tStrCmp(ParamIdentifierVal, L"1"))) {
+ } else if ((SctStrCmp (ParamIdentifierVal, L"Slave") =3D=3D 0) || (Sc=
tStrCmp(ParamIdentifierVal, L"1" =3D=3D 0))) {
Atapi->SlaveMaster =3D 1;
} else {
goto InValidText;
=2D-
2.30.2


Re: [PATCH v1] MdePkg: Support Extended Control Register(XCR) Read and Write.

Wu, Jiaxin
 

Please ignore this one because I just found already have the XGETBV instruction Support.


So, I create another patch to support XSETBV instruction for XCR write.

See email thread:
[edk2-devel] [PATCH v1] MdePkg/BaseLib: Add support for the XSETBV instruction

So, let's review above one.



Thanks,
Jiaxin

-----Original Message-----
From: Wu, Jiaxin
Sent: Wednesday, March 31, 2021 12:21 PM
To: Yao, Jiewen <jiewen.yao@...>; devel@edk2.groups.io;
gaoliming@...
Cc: Kinney, Michael D <michael.d.kinney@...>; Liu, Zhiguang
<zhiguang.liu@...>; Zhang, Hongbin1 <hongbin1.zhang@...>
Subject: RE: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
Register(XCR) Read and Write.

Thanks the comments, I will refine the patch according the feedback.



-----Original Message-----
From: Yao, Jiewen <jiewen.yao@...>
Sent: Wednesday, March 31, 2021 10:20 AM
To: devel@edk2.groups.io; gaoliming@...; Wu, Jiaxin
<jiaxin.wu@...>
Cc: Kinney, Michael D <michael.d.kinney@...>; Liu, Zhiguang
<zhiguang.liu@...>; Zhang, Hongbin1 <hongbin1.zhang@...>
Subject: RE: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
Register(XCR) Read and Write.

Agree with Liming.

For IA32, you get parameter from stack -
mov edx, [esp + 12]
mov eax, [esp + 8]
mov ecx, [esp + 4]

For X64, you get parameter from GP register - RCX, RDX, R8, R9 for the first
4
parameter. They are on the stack since the 5th parameter.

The code may be sharable only if they do not have any input parameter.
But
not in this case.

Even though, I still recommend we have two copy - like AsmReadCs() in 2
ReadCs.nasm, because we need different context definition, such as
"DEFAULT
REL"

Thank you
Yao Jiewen


-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
gaoliming
Sent: Wednesday, March 31, 2021 10:05 AM
To: devel@edk2.groups.io; Wu, Jiaxin <jiaxin.wu@...>
Cc: Kinney, Michael D <michael.d.kinney@...>; Liu, Zhiguang
<zhiguang.liu@...>; Zhang, Hongbin1 <hongbin1.zhang@...>
Subject: 回复: [edk2-devel] [PATCH v1] MdePkg: Support Extended
Control
Register(XCR) Read and Write.

Jiaxin:
32bit function and 64bit function have the different calling convention.
Their assembly function can't be shared.

This new API interface is same to AsmWriteMsr64(). You can refer
AsmWriteMsr64() implementation in BaseLib.

Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Wu,
Jiaxin
发送时间: 2021年3月31日 9:56
收件人: devel@edk2.groups.io; gaoliming@...
抄送: Kinney, Michael D <michael.d.kinney@...>; Liu, Zhiguang
<zhiguang.liu@...>; Zhang, Hongbin1
<hongbin1.zhang@...>
主题: Re: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
Register(XCR) Read and Write.

Actually, the implementation under ia32 should be also workable for
X64, I
just put it under ia32.

Liming, do you have suggestion where can we place the code?

Thanks,
Jiaxin

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
gaoliming
Sent: Wednesday, March 31, 2021 9:51 AM
To: devel@edk2.groups.io; Wu, Jiaxin <jiaxin.wu@...>
Cc: Kinney, Michael D <michael.d.kinney@...>; Liu, Zhiguang
<zhiguang.liu@...>; Zhang, Hongbin1
<hongbin1.zhang@...>
Subject: 回复: [edk2-devel] [PATCH v1] MdePkg: Support Extended
Control
Register(XCR) Read and Write.

Where is X64 implementation for this new API?

-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Wu,
Jiaxin
发送时间: 2021年3月31日 9:20
收件人: devel@edk2.groups.io
抄送: Michael D Kinney <michael.d.kinney@...>; Liming Gao
<gaoliming@...>; Zhiguang Liu
<zhiguang.liu@...>;
Zhang
Hongbin1 <hongbin1.zhang@...>
主题: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
Register(XCR) Read and Write.

https://bugzilla.tianocore.org/show_bug.cgi?id=3284

This patch is to support Extended Control Register(XCR) Read
and Write.

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>
Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@...>
Signed-off-by: Jiaxin Wu <Jiaxin.wu@...>
---
MdePkg/Include/Library/BaseLib.h | 46
++++++++++++++++++++++++++++++-
MdePkg/Library/BaseLib/BaseLib.inf | 4 ++-
MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm | 31
+++++++++++++++++++++
MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm | 34
+++++++++++++++++++++++
4 files changed, 113 insertions(+), 2 deletions(-)
create mode 100644 MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm

diff --git a/MdePkg/Include/Library/BaseLib.h
b/MdePkg/Include/Library/BaseLib.h
index 1171a0ffb5..c51633ad73 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -1,10 +1,10 @@
/** @file
Provides string functions, linked list functions, math functions,
synchronization
functions, file path functions, and CPU architecture-specific
functions.

-Copyright (c) 2006 - 2019, Intel Corporation. All rights
reserved.<BR>
+Copyright (c) 2006 - 2021, Intel Corporation. All rights
reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights
reserved.<BR>
Copyright (c) Microsoft Corporation.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise
Development
LP.
All
rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -7493,7 +7493,51 @@ PatchInstructionX86 (
OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
IN UINT64 PatchValue,
IN UINTN ValueSize
);

+/**
+ Returns a 64-bit Extended Control Register(XCR).
+
+ Reads and returns the 64-bit XCR specified by Index. No
parameter
checking is
+ performed on Index, and some Index values may cause CPU
exceptions.
The
+ caller must either guarantee that Index is valid, or the caller
must
set up
+ exception handlers to catch the exceptions. This function is only
available
+ on IA-32 and x64.
+
+ @param Index The 32-bit XCR index to read.
+
+ @return The value of the XCR identified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadXcr (
+ IN UINT32 Index
+ );
+
+/**
+ Writes a 64-bit value to a Extended Control Register(XCR), and
returns
the
+ value.
+
+ Writes the 64-bit value specified by Value to the XCR specified by
Index.
The
+ 64-bit value written to the XCR is returned. No parameter
checking
is
+ performed on Index or Value, and some of these may cause CPU
exceptions. The
+ caller must either guarantee that Index and Value are valid, or the
caller
+ must establish proper exception handlers. This function is only
available
on
+ IA-32 and x64.
+
+ @param Index The 32-bit XCR index to write.
+ @param Value The 64-bit value to write to the XCR.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+AsmWriteXcr (
+ IN UINT32 Index,
+ IN UINT64 Value
+ );
+
#endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
#endif // !defined (__BASE_LIB__)
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
b/MdePkg/Library/BaseLib/BaseLib.inf
index 3b85c56c3c..e62031ea11 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -1,9 +1,9 @@
## @file
# Base Library implementation.
#
-# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
<BR>
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights
reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights
reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP.
All
rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -63,10 +63,12 @@
BaseLibInternals.h

[Sources.Ia32]
Ia32/WriteTr.nasm
Ia32/Lfence.nasm
+ Ia32/ReadXcr.nasm
+ Ia32/WriteXcr.nasm

Ia32/Wbinvd.c | MSFT
Ia32/WriteMm7.c | MSFT
Ia32/WriteMm6.c | MSFT
Ia32/WriteMm5.c | MSFT
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
b/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
new file mode 100644
index 0000000000..5d50d8ba01
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
@@ -0,0 +1,31 @@
+;--------------------------------------------------------------------------
----
+;
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadXcr.Asm
+;
+; Abstract:
+;
+; AsmReadXcr function
+;
+; Notes:
+;
+;--------------------------------------------------------------------------
----
+
+ SECTION .text
+
+;--------------------------------------------------------------------------
----
+; UINT64
+; EFIAPI
+; AsmReadXcr (
+; IN UINT32 Index
+; );
+;--------------------------------------------------------------------------
----
+global ASM_PFX(AsmReadXcr)
+ASM_PFX(AsmReadXcr):
+ mov ecx, [esp + 4]
+ xgetbv
+ ret
\ No newline at end of file
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
b/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
new file mode 100644
index 0000000000..009d41864b
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
@@ -0,0 +1,34 @@
+;--------------------------------------------------------------------------
----
+;
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteXcr.nasm
+;
+; Abstract:
+;
+; AsmWriteXcr function
+;
+; Notes:
+;
+;--------------------------------------------------------------------------
----
+
+ SECTION .text
+
+;--------------------------------------------------------------------------
----
+; UINT64
+; EFIAPI
+; AsmWriteXcr (
+; IN UINT32 Index,
+; IN UINT64 Value
+; );
+;--------------------------------------------------------------------------
----
+global ASM_PFX(AsmWriteXcr)
+ASM_PFX(AsmWriteXcr):
+ mov edx, [esp + 12]
+ mov eax, [esp + 8]
+ mov ecx, [esp + 4]
+ xsetbv
+ ret
\ No newline at end of file
--
2.16.2.windows.1


















[PATCH v1] MdePkg/BaseLib: Add support for the XSETBV instruction

Wu, Jiaxin
 

https://bugzilla.tianocore.org/show_bug.cgi?id=3284

This patch is to support XSETBV instruction so as to support
Extended Control Register(XCR) write.

Extended Control Register(XCR) read has already been supported
by below commit to support XGETBV instruction:
9b3ca509abd4e45439bbdfe2c2fa8780c950320a

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>
Cc: Yao Jiewen <jiewen.yao@...>
Signed-off-by: Jiaxin Wu <Jiaxin.wu@...>
Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@...>
---
MdePkg/Include/Library/BaseLib.h | 25 +++++++++++++++++++++++-
MdePkg/Library/BaseLib/BaseLib.inf | 4 +++-
MdePkg/Library/BaseLib/Ia32/XSetBv.nasm | 34 +++++++++++++++++++++++++++++++++
MdePkg/Library/BaseLib/X64/XSetBv.nasm | 34 +++++++++++++++++++++++++++++++++
4 files changed, 95 insertions(+), 2 deletions(-)
create mode 100644 MdePkg/Library/BaseLib/Ia32/XSetBv.nasm
create mode 100644 MdePkg/Library/BaseLib/X64/XSetBv.nasm

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index 1171a0ffb5..035d6b655d 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -1,10 +1,10 @@
/** @file
Provides string functions, linked list functions, math functions, synchronization
functions, file path functions, and CPU architecture-specific functions.

-Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>
+Copyright (c) 2006 - 2021, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
Copyright (c) Microsoft Corporation.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -7436,10 +7436,33 @@ UINT64
EFIAPI
AsmXGetBv (
IN UINT32 Index
);

+/**
+ Executes a XSETBV instruction to write a 64-bit value to a Extended Control Register(XCR),
+ and returns the value.
+
+ Writes the 64-bit value specified by Value to the XCR specified by Index. The
+ 64-bit value written to the XCR is returned. No parameter checking is
+ performed on Index or Value, and some of these may cause CPU exceptions. The
+ caller must either guarantee that Index and Value are valid, or the caller
+ must establish proper exception handlers. This function is only available on
+ IA-32 and x64.
+
+ @param Index The 32-bit XCR index to write.
+ @param Value The 64-bit value to write to the XCR.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+AsmXSetBv (
+ IN UINT32 Index,
+ IN UINT64 Value
+ );

/**
Executes a VMGEXIT instruction (VMMCALL with a REP prefix)

Executes a VMGEXIT instruction. This function is only available on IA-32 and
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 3b85c56c3c..fe8f68bbcf 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -1,9 +1,9 @@
## @file
# Base Library implementation.
#
-# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -182,10 +182,11 @@
Ia32/LShiftU64.nasm| GCC
Ia32/EnableCache.nasm| GCC
Ia32/DisableCache.nasm| GCC
Ia32/RdRand.nasm
Ia32/XGetBv.nasm
+ Ia32/XSetBv.nasm
Ia32/VmgExit.nasm

Ia32/DivS64x64Remainder.c
Ia32/InternalSwitchStack.c | MSFT
Ia32/InternalSwitchStack.nasm | GCC
@@ -316,10 +317,11 @@
X64/GccInlinePriv.c | GCC
X64/EnableDisableInterrupts.nasm
X64/DisablePaging64.nasm
X64/RdRand.nasm
X64/XGetBv.nasm
+ X64/XSetBv.nasm
X64/VmgExit.nasm
ChkStkGcc.c | GCC

[Sources.EBC]
Ebc/CpuBreakpoint.c
diff --git a/MdePkg/Library/BaseLib/Ia32/XSetBv.nasm b/MdePkg/Library/BaseLib/Ia32/XSetBv.nasm
new file mode 100644
index 0000000000..9fa2f761cd
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/XSetBv.nasm
@@ -0,0 +1,34 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; XSetBv.nasm
+;
+; Abstract:
+;
+; AsmXSetBv function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmXSetBv (
+; IN UINT32 Index,
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmXSetBv)
+ASM_PFX(AsmXSetBv):
+ mov edx, [esp + 12]
+ mov eax, [esp + 8]
+ mov ecx, [esp + 4]
+ xsetbv
+ ret
\ No newline at end of file
diff --git a/MdePkg/Library/BaseLib/X64/XSetBv.nasm b/MdePkg/Library/BaseLib/X64/XSetBv.nasm
new file mode 100644
index 0000000000..aa72419e7f
--- /dev/null
+++ b/MdePkg/Library/BaseLib/X64/XSetBv.nasm
@@ -0,0 +1,34 @@
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; XSetBv.nasm
+;
+; Abstract:
+;
+; AsmXSetBv function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ DEFAULT REL
+ SECTION .text
+
+;------------------------------------------------------------------------------
+; UINT64
+; EFIAPI
+; AsmXSetBv (
+; IN UINT32 Index,
+; IN UINT64 Value
+; );
+;------------------------------------------------------------------------------
+global ASM_PFX(AsmXSetBv)
+ASM_PFX(AsmXSetBv):
+ mov rax, rdx ; meanwhile, rax <- return value
+ shr rdx, 0x20 ; edx:eax contains the value to write
+ xsetbv
+ ret
\ No newline at end of file
--
2.16.2.windows.1


File /Designs/2021/0319/New EFI Protocols for edk2 Redfish Implementation_conclusion.pdf uploaded #file-notice

devel@edk2.groups.io Notification <noreply@...>
 

The following files have been uploaded to the Files area of the devel@edk2.groups.io group.

By: Nickle Wang <nickle.wang@...>

Description:
New EFI Redfish Protocol conclusion version. All discussions from TianoCore design meeting are integrated into this document.


Re: VirtIO Sound Driver (GSoC 2021)

Nate DeSimone
 

Another option is to put the protocol definition in MdeModulePkg and mark it with the EDKII_ prefix. For my last “code first” UEFI spec contribution I did this with the PPI that added up getting added.

 

Thanks,

Nate

 

From: <devel@edk2.groups.io> on behalf of "Andrew Fish via groups.io" <afish@...>
Reply-To: "devel@edk2.groups.io" <devel@edk2.groups.io>, "afish@..." <afish@...>
Date: Tuesday, March 30, 2021 at 10:54 PM
To: edk2-devel-groups-io <devel@edk2.groups.io>, "harlydavidsen@..." <harlydavidsen@...>
Cc: Rafael Rodrigues Machado <rafaelrodrigues.machado@...>
Subject: Re: [edk2-devel] VirtIO Sound Driver (GSoC 2021)

 



On Mar 30, 2021, at 5:01 PM, Ethin Probst <harlydavidsen@...> wrote:

 

I'm wondering where exactly I should add the VirtIO sound protocol. I
just familiarized myself with the build system and am about to test it
by building OVMF if possible, but I'm wondering where I should
actually put the protocol and all that stuff. Maybe there's
documentation I've missed as well.

 

Ethin,

 

For the driver I’d match the patter of OVMF [1] and use OvmfPkg/VirtioSoundDxe/. Maybe even use one of the other drivers as a template. 

 

The protocol is more of a public thing. I think eventually we would like to publish the protocol in the UEFI Spec (I can help with that part) and that would mean we put the Protocol definition in MdePkg/Include/Protocol, but we don’t want to do that before it is standardized as that causes compatibility issues. So this is a “code first project” (code prototype and then contribute to the UEFI Forum for inclusion in the specification) so we need to follow some code first rules that I don’t remember of the top of my head? So why not start out the protocol definition OvmfPkg/Include/Protocol. You can also add a test application looks like you can just use the root [2] of OVMF for that. That way the project is not blocked. 

 

We can have a conversation on the mailing list about better places to put stuff, and it should be easy enough to move stuff around if everything else is working.  

 

[1] find OvmfPkg  -iname '*Virtio*.inf'

OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf

OvmfPkg/VirtioScsiDxe/VirtioScsi.inf

OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf

OvmfPkg/Library/VirtioLib/VirtioLib.inf

OvmfPkg/VirtioGpuDxe/VirtioGpu.inf

OvmfPkg/VirtioBlkDxe/VirtioBlk.inf

OvmfPkg/Virtio10Dxe/Virtio10.inf

OvmfPkg/VirtioNetDxe/VirtioNet.inf

OvmfPkg/VirtioRngDxe/VirtioRng.inf



[2] /Volumes/Case/edk2-github/OvmfPkg>git grep APPLICATION -- *.inf | grep MODULE_TYPE

EnrollDefaultKeys/EnrollDefaultKeys.inf:13:  MODULE_TYPE                    = UEFI_APPLICATION

 

Thanks,

 

Andrew Fish

 




On 3/30/21, Ethin Probst via 
groups.io
<
harlydavidsen@...> wrote:

I agree. Plus, it gives me a chance to finally learn the EDK2 build
system and how it works! I've been working on a hobby OS as a side
project and, though learning from other code examples from OSes is
fun, I have to say that learning from the firmware code like from
SeaBIOS has been some of the most enlightening and interesting times
thus far.
Thanks for the link to your code, Rafael; once I get virtIO support
in, I can work on HDA support, though I might tackle USB support
second and HDA third. We'll see, but VirtIO definitely is coming
first.

As I said before, I look forward to working with all of you wonderful
people!

On 3/30/21, Rafael Rodrigues Machado <rafaelrodrigues.machado@...>
wrote:

This would be amazing so people can continue my work related to
accessibility at BIOS. Something desired by the blind people since the
90's
Just for reference, this is what I have done:

https://github.com/RafaelRMachado/Msc_UefiHda_PreOs_Accessibility

Thanks
Rafael

Em seg, 29 de mar de 2021 20:24, Ethin Probst <harlydavidsen@...>
escreveu:


Hello everyone,

This is the first time I've ever contributed to EDK2. As part of GSoC
2021, I have submitted a proposal to implement a UEFI audio output
protocol that will utilize the VirtIO sound driver. I've already
submitted a draft proposal, and apologize if I've done things out of
order. This is my first time doing GSoC 2021, and contributing to EDK2
felt like a really fun thing to do!

I look forward to working with you guys on this and any future projects!
:-)

--
Signed,
Ethin D. Probst





 



--
Signed,
Ethin D. Probst







-- 
Signed,
Ethin D. Probst



 


Re: VirtIO Sound Driver (GSoC 2021)

Nate DeSimone
 

Hi Ethin,

 

I’m not quite sure what happened but I loaded it up again and the text shown now makes a lot more sense, thank you for your application!

 

Nate

 

From: <devel@edk2.groups.io> on behalf of Ethin Probst <harlydavidsen@...>
Reply-To: "devel@edk2.groups.io" <devel@edk2.groups.io>, "harlydavidsen@..." <harlydavidsen@...>
Date: Tuesday, March 30, 2021 at 7:41 AM
To: "Desimone, Nathaniel L" <nathaniel.l.desimone@...>, "devel@edk2.groups.io" <devel@edk2.groups.io>
Subject: Re: [edk2-devel] VirtIO Sound Driver (GSoC 2021)

 

Hi Nate,

I appreciate the feedback, but I'm quite confused on exactly what questions I've failed to answer? I didn't include my other contact information but I'm not sure what else might be missing from my proposal.


UEFI spec version in system table, shall we update it to 2.8?

Lin, Derek (HPS SW)
 

Hi,

In UefiSpec.h, we define the UEFI version 2.7 in system table.

#define EFI_2_70_SYSTEM_TABLE_REVISION  ((2 << 16| (70))
#define EFI_SYSTEM_TABLE_REVISION       EFI_2_70_SYSTEM_TABLE_REVISION
#define EFI_SPECIFICATION_VERSION       EFI_SYSTEM_TABLE_REVISION
#define EFI_RUNTIME_SERVICES_REVISION   EFI_SPECIFICATION_VERSION


In Linux dmesg
[    0.000000] efi: EFI v2.70 by EDK II


Shall it be updated to v2.8 to align with UEFI spec?

Thanks,
Derek


Re: VirtIO Sound Driver (GSoC 2021)

Andrew Fish
 


On Mar 30, 2021, at 5:01 PM, Ethin Probst <harlydavidsen@...> wrote:

I'm wondering where exactly I should add the VirtIO sound protocol. I
just familiarized myself with the build system and am about to test it
by building OVMF if possible, but I'm wondering where I should
actually put the protocol and all that stuff. Maybe there's
documentation I've missed as well.

Ethin,

For the driver I’d match the patter of OVMF [1] and use OvmfPkg/VirtioSoundDxe/. Maybe even use one of the other drivers as a template. 

The protocol is more of a public thing. I think eventually we would like to publish the protocol in the UEFI Spec (I can help with that part) and that would mean we put the Protocol definition in MdePkg/Include/Protocol, but we don’t want to do that before it is standardized as that causes compatibility issues. So this is a “code first project” (code prototype and then contribute to the UEFI Forum for inclusion in the specification) so we need to follow some code first rules that I don’t remember of the top of my head? So why not start out the protocol definition OvmfPkg/Include/Protocol. You can also add a test application looks like you can just use the root [2] of OVMF for that. That way the project is not blocked. 

We can have a conversation on the mailing list about better places to put stuff, and it should be easy enough to move stuff around if everything else is working.  

[1] find OvmfPkg  -iname '*Virtio*.inf'
OvmfPkg/VirtioPciDeviceDxe/VirtioPciDeviceDxe.inf
OvmfPkg/VirtioScsiDxe/VirtioScsi.inf
OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf
OvmfPkg/Library/VirtioLib/VirtioLib.inf
OvmfPkg/VirtioGpuDxe/VirtioGpu.inf
OvmfPkg/VirtioBlkDxe/VirtioBlk.inf
OvmfPkg/Virtio10Dxe/Virtio10.inf
OvmfPkg/VirtioNetDxe/VirtioNet.inf
OvmfPkg/VirtioRngDxe/VirtioRng.inf

[2] /Volumes/Case/edk2-github/OvmfPkg>git grep APPLICATION -- *.inf | grep MODULE_TYPE
EnrollDefaultKeys/EnrollDefaultKeys.inf:13:  MODULE_TYPE                    = UEFI_APPLICATION

Thanks,

Andrew Fish



On 3/30/21, Ethin Probst via groups.io
<harlydavidsen@...> wrote:
I agree. Plus, it gives me a chance to finally learn the EDK2 build
system and how it works! I've been working on a hobby OS as a side
project and, though learning from other code examples from OSes is
fun, I have to say that learning from the firmware code like from
SeaBIOS has been some of the most enlightening and interesting times
thus far.
Thanks for the link to your code, Rafael; once I get virtIO support
in, I can work on HDA support, though I might tackle USB support
second and HDA third. We'll see, but VirtIO definitely is coming
first.

As I said before, I look forward to working with all of you wonderful
people!

On 3/30/21, Rafael Rodrigues Machado <rafaelrodrigues.machado@...>
wrote:
This would be amazing so people can continue my work related to
accessibility at BIOS. Something desired by the blind people since the
90's
Just for reference, this is what I have done:

https://github.com/RafaelRMachado/Msc_UefiHda_PreOs_Accessibility

Thanks
Rafael

Em seg, 29 de mar de 2021 20:24, Ethin Probst <harlydavidsen@...>
escreveu:

Hello everyone,

This is the first time I've ever contributed to EDK2. As part of GSoC
2021, I have submitted a proposal to implement a UEFI audio output
protocol that will utilize the VirtIO sound driver. I've already
submitted a draft proposal, and apologize if I've done things out of
order. This is my first time doing GSoC 2021, and contributing to EDK2
felt like a really fun thing to do!

I look forward to working with you guys on this and any future projects!
:-)

--
Signed,
Ethin D. Probst









--
Signed,
Ethin D. Probst








-- 
Signed,
Ethin D. Probst




Re: [PATCH] UefiPayloadPkg: UefiPayload retrieve PCI root bridge from Guid Hob

Ni, Ray
 

Reviewed-by: Ray Ni <ray.ni@...>

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
Zhiguang Liu
Sent: Tuesday, March 30, 2021 4:45 PM
To: devel@edk2.groups.io
Cc: Dong, Guo <guo.dong@...>; You, Benjamin
<benjamin.you@...>; Park, Aiden <aiden.park@...>; Ma,
Maurice <maurice.ma@...>
Subject: [edk2-devel] [PATCH] UefiPayloadPkg: UefiPayload retrieve PCI root
bridge from Guid Hob

UefiPayload parse gPldPciRootBridgeInfoGuid Guid Hob to retrieve PCI root
bridges
information. gPldPciRootBridgeInfoGuid Guid Hob should be created by
Bootloader.

Cc: Guo Dong <guo.dong@...>
Cc: Benjamin You <benjamin.you@...>
Signed-off-by: Aiden Park <aiden.park@...>
Signed-off-by: Maurice Ma <maurice.ma@...>
Signed-off-by: Zhiguang Liu <zhiguang.liu@...>
---
UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h | 54
++++++++++++++++++++++++++++++++++++++++++++++++++++++
UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h | 40
++++++++++++++++++++++++++++++++++++++--
UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 41
++++++++++++++++++++++++++++++++++++++---
UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 9
++++++++-
UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c | 81
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
++++++++++++++++++++++-
UefiPayloadPkg/UefiPayloadPkg.dec | 11 ++++++-----
6 files changed, 224 insertions(+), 12 deletions(-)

diff --git a/UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h
b/UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h
new file mode 100644
index 0000000000..47a9a7aeb2
--- /dev/null
+++ b/UefiPayloadPkg/Include/Guid/PldPciRootBridgeInfoHob.h
@@ -0,0 +1,54 @@
+/** @file

+ This file defines the hob structure for the PCI Root Bridge Info.

+

+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>

+ SPDX-License-Identifier: BSD-2-Clause-Patent

+

+**/

+

+#ifndef __PLD_PCI_ROOT_BRIDGE_INFO_HOB_H__

+#define __PLD_PCI_ROOT_BRIDGE_INFO_HOB_H__

+

+#include <IndustryStandard/Pci.h>

+#include <Library/PciHostBridgeLib.h>

+

+///

+/// Payload PCI Root Bridge Information HOB

+///

+typedef struct {

+ UINT32 Segment; ///< Segment number.

+ UINT64 Supports; ///< Supported attributes.

+ ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by
GetAttributes()

+ ///< and SetAttributes() in
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.

+ UINT64 Attributes; ///< Initial attributes.

+ ///< Refer to EFI_PCI_ATTRIBUTE_xxx used by
GetAttributes()

+ ///< and SetAttributes() in
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.

+ BOOLEAN DmaAbove4G; ///< DMA above 4GB memory.

+ ///< Set to TRUE when root bridge supports DMA
above 4GB memory.

+ BOOLEAN NoExtendedConfigSpace; ///< When FALSE, the root
bridge supports

+ ///< Extended (4096-byte) Configuration Space.

+ ///< When TRUE, the root bridge supports

+ ///< 256-byte Configuration Space only.

+ BOOLEAN ResourceAssigned; ///< Resource assignment status
of the root bridge.

+ ///< Set to TRUE if Bus/IO/MMIO resources for
root bridge have been assigned.

+ UINT64 AllocationAttributes; ///< Allocation attributes.

+ ///< Refer to
EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM and

+ ///< EFI_PCI_HOST_BRIDGE_MEM64_DECODE
used by GetAllocAttributes()

+ ///< in
EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.

+ PCI_ROOT_BRIDGE_APERTURE Bus; ///< Bus aperture which can
be used by the root bridge.

+ PCI_ROOT_BRIDGE_APERTURE Io; ///< IO aperture which can be
used by the root bridge.

+ PCI_ROOT_BRIDGE_APERTURE Mem; ///< MMIO aperture below
4GB which can be used by the root bridge.

+ PCI_ROOT_BRIDGE_APERTURE MemAbove4G; ///< MMIO aperture
above 4GB which can be used by the root bridge.

+ PCI_ROOT_BRIDGE_APERTURE PMem; ///< Prefetchable MMIO
aperture below 4GB which can be used by the root bridge.

+ PCI_ROOT_BRIDGE_APERTURE PMemAbove4G; ///< Prefetchable
MMIO aperture above 4GB which can be used by the root bridge.

+ UINT32 HID;

+ UINT32 UID;

+} PLD_PCI_ROOT_BRIDGE;

+

+typedef struct {

+ UINT8 Revision;

+ UINT8 Count;

+ PLD_PCI_ROOT_BRIDGE RootBridge[0];

+} PLD_PCI_ROOT_BRIDGE_INFO_HOB;

+

+#endif // __PLD_PCI_ROOT_BRIDGE_INFO_HOB_H__

diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
index c2961b3bee..f6cb2a25d9 100644
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridge.h
@@ -2,7 +2,7 @@
Header file of PciHostBridgeLib.



Copyright (C) 2016, Red Hat, Inc.

- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>



SPDX-License-Identifier: BSD-2-Clause-Patent



@@ -11,14 +11,38 @@
#ifndef _PCI_HOST_BRIDGE_H

#define _PCI_HOST_BRIDGE_H



+#include <Guid/PldPciRootBridgeInfoHob.h>

+

typedef struct {

ACPI_HID_DEVICE_PATH AcpiDevicePath;

EFI_DEVICE_PATH_PROTOCOL EndDevicePath;

} CB_PCI_ROOT_BRIDGE_DEVICE_PATH;



+/**

+ Scan for all root bridges in platform.

+

+ @param[out] NumberOfRootBridges Number of root bridges detected

+

+ @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.

+**/

PCI_ROOT_BRIDGE *

ScanForRootBridges (

- UINTN *NumberOfRootBridges

+ OUT UINTN *NumberOfRootBridges

+);

+

+/**

+ Scan for all root bridges from PldPciRootBridgeInfoHob

+

+ @param[in] PciRootBridgeInfo Pointer of PLD PCI Root Bridge Info Hob

+ @param[out] NumberOfRootBridges Number of root bridges detected

+

+ @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.

+

+**/

+PCI_ROOT_BRIDGE *

+RetrieveRootBridgeInfoFromHob (

+ IN PLD_PCI_ROOT_BRIDGE_INFO_HOB *PciRootBridgeInfo,

+ OUT UINTN *NumberOfRootBridges

);



/**

@@ -77,4 +101,16 @@ InitRootBridge (
OUT PCI_ROOT_BRIDGE *RootBus

);



+/**

+ Initialize DevicePath for a PCI_ROOT_BRIDGE.

+ @param[in] HID HID for device path

+ @param[in] UID UID for device path

+

+ @retval A pointer to the new created device patch.

+**/

+EFI_DEVICE_PATH_PROTOCOL *

+CreateRootBridgeDevicePath (

+ IN UINT32 HID,

+ IN UINT32 UID

+);

#endif

diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
index 512c3127cc..8af98dc16a 100644
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.c
@@ -2,7 +2,7 @@
Library instance of PciHostBridgeLib library class for coreboot.



Copyright (C) 2016, Red Hat, Inc.

- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>



SPDX-License-Identifier: BSD-2-Clause-Patent



@@ -19,6 +19,7 @@
#include <Library/MemoryAllocationLib.h>

#include <Library/PciHostBridgeLib.h>

#include <Library/PciLib.h>

+#include <Library/HobLib.h>



#include "PciHostBridge.h"



@@ -48,7 +49,6 @@ CB_PCI_ROOT_BRIDGE_DEVICE_PATH
mRootBridgeDevicePathTemplate = {
}

};



-

/**

Initialize a PCI_ROOT_BRIDGE structure.



@@ -145,6 +145,27 @@ InitRootBridge (
return EFI_SUCCESS;

}



+/**

+ Initialize DevicePath for a PCI_ROOT_BRIDGE.

+ @param[in] HID HID for device path

+ @param[in] UID UID for device path

+

+ @retval A pointer to the new created device patch.

+**/

+EFI_DEVICE_PATH_PROTOCOL *

+CreateRootBridgeDevicePath (

+ IN UINT32 HID,

+ IN UINT32 UID

+)

+{

+ CB_PCI_ROOT_BRIDGE_DEVICE_PATH *DevicePath;

+ DevicePath = AllocateCopyPool (sizeof (mRootBridgeDevicePathTemplate),

+ &mRootBridgeDevicePathTemplate);

+ ASSERT (DevicePath != NULL);

+ DevicePath->AcpiDevicePath.HID = HID;

+ DevicePath->AcpiDevicePath.UID = UID;

+ return (EFI_DEVICE_PATH_PROTOCOL *)DevicePath;

+}



/**

Return all the root bridge instances in an array.

@@ -161,10 +182,24 @@ PciHostBridgeGetRootBridges (
UINTN *Count

)

{

+ PLD_PCI_ROOT_BRIDGE_INFO_HOB *PciRootBridgeInfo;

+ EFI_HOB_GUID_TYPE *GuidHob;

+ //

+ // Find PLD PCI Root Bridge Info hob

+ //

+ GuidHob = GetFirstGuidHob (&gPldPciRootBridgeInfoGuid);

+ if (GuidHob != NULL) {

+ PciRootBridgeInfo = (PLD_PCI_ROOT_BRIDGE_INFO_HOB *)
GET_GUID_HOB_DATA (GuidHob);

+ //

+ // The count of Root Bridge must be not large than the maximum Root
Bridge number that the Hob can carry

+ //

+ if (PciRootBridgeInfo->Count <= (GuidHob->Header.HobLength -
sizeof(PLD_PCI_ROOT_BRIDGE_INFO_HOB)) /
sizeof(PLD_PCI_ROOT_BRIDGE)) {

+ return RetrieveRootBridgeInfoFromHob (PciRootBridgeInfo, Count);

+ }

+ }

return ScanForRootBridges (Count);

}



-

/**

Free the root bridge instances array returned from

PciHostBridgeGetRootBridges().

diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
index 7896df2416..ba31d718b8 100644
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf
@@ -2,7 +2,7 @@
# Library instance of PciHostBridgeLib library class for coreboot.

#

# Copyright (C) 2016, Red Hat, Inc.

-# Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>

+# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>

#

# SPDX-License-Identifier: BSD-2-Clause-Patent

#

@@ -32,6 +32,7 @@
[Packages]

MdeModulePkg/MdeModulePkg.dec

MdePkg/MdePkg.dec

+ UefiPayloadPkg/UefiPayloadPkg.dec



[LibraryClasses]

BaseMemoryLib

@@ -39,3 +40,9 @@
DevicePathLib

MemoryAllocationLib

PciLib

+

+[Guids]

+ gPldPciRootBridgeInfoGuid

+

+[Pcd]

+ gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration

diff --git a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
index fffbf04cad..eb2d54fedc 100644
--- a/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
+++ b/UefiPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
@@ -1,7 +1,7 @@
/** @file

Scan the entire PCI bus for root bridges to support coreboot UEFI payload.



- Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>

+ Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.<BR>



SPDX-License-Identifier: BSD-2-Clause-Patent



@@ -582,3 +582,82 @@ ScanForRootBridges (


return RootBridges;

}

+

+/**

+ Scan for all root bridges from PldPciRootBridgeInfoHob

+

+ @param[in] PciRootBridgeInfo Pointer of PLD PCI Root Bridge Info Hob

+ @param[out] NumberOfRootBridges Number of root bridges detected

+

+ @retval Pointer to the allocated PCI_ROOT_BRIDGE structure array.

+

+**/

+PCI_ROOT_BRIDGE *

+RetrieveRootBridgeInfoFromHob (

+ IN PLD_PCI_ROOT_BRIDGE_INFO_HOB *PciRootBridgeInfo,

+ OUT UINTN *NumberOfRootBridges

+)

+{

+ PCI_ROOT_BRIDGE *PciRootBridges;

+ UINTN Size;

+ UINT8 Index;

+ BOOLEAN ResourceAssigned;

+

+ ASSERT (PciRootBridgeInfo != NULL);

+ ASSERT (NumberOfRootBridges != NULL);

+ if (PciRootBridgeInfo == NULL) {

+ return NULL;

+ }

+ if (PciRootBridgeInfo->Count == 0) {

+ return NULL;

+ }

+ Size = PciRootBridgeInfo->Count * sizeof (PCI_ROOT_BRIDGE);

+ PciRootBridges = (PCI_ROOT_BRIDGE *) AllocatePool (Size);

+ ASSERT (PciRootBridges != NULL);

+ if (PciRootBridges == NULL) {

+ return NULL;

+ }

+ ZeroMem (PciRootBridges, PciRootBridgeInfo->Count * sizeof
(PCI_ROOT_BRIDGE));

+

+ //

+ // Create all root bridges with PciRootBridgeInfoHob

+ //

+ for (Index = 0; Index < PciRootBridgeInfo->Count; Index++) {

+ PciRootBridges[Index].Segment = PciRootBridgeInfo-
RootBridge[Index].Segment;
+ PciRootBridges[Index].Supports = PciRootBridgeInfo-
RootBridge[Index].Supports;
+ PciRootBridges[Index].Attributes = PciRootBridgeInfo-
RootBridge[Index].Attributes;
+ PciRootBridges[Index].DmaAbove4G = PciRootBridgeInfo-
RootBridge[Index].DmaAbove4G;
+ PciRootBridges[Index].NoExtendedConfigSpace = PciRootBridgeInfo-
RootBridge[Index].NoExtendedConfigSpace;
+ PciRootBridges[Index].ResourceAssigned = PciRootBridgeInfo-
RootBridge[Index].ResourceAssigned;
+ PciRootBridges[Index].AllocationAttributes = PciRootBridgeInfo-
RootBridge[Index].AllocationAttributes;
+ PciRootBridges[Index].DevicePath =
CreateRootBridgeDevicePath(PciRootBridgeInfo->RootBridge[Index].HID,
PciRootBridgeInfo->RootBridge[Index].UID);

+ CopyMem(&PciRootBridges[Index].Bus, &PciRootBridgeInfo-
RootBridge[Index].Bus, sizeof(PCI_ROOT_BRIDGE_APERTURE));
+ CopyMem(&PciRootBridges[Index].Io, &PciRootBridgeInfo-
RootBridge[Index].Io, sizeof(PCI_ROOT_BRIDGE_APERTURE));
+ CopyMem(&PciRootBridges[Index].Mem, &PciRootBridgeInfo-
RootBridge[Index].Mem, sizeof(PCI_ROOT_BRIDGE_APERTURE));
+ CopyMem(&PciRootBridges[Index].MemAbove4G, &PciRootBridgeInfo-
RootBridge[Index].MemAbove4G, sizeof(PCI_ROOT_BRIDGE_APERTURE));
+ CopyMem(&PciRootBridges[Index].PMem, &PciRootBridgeInfo-
RootBridge[Index].PMem, sizeof(PCI_ROOT_BRIDGE_APERTURE));
+ CopyMem(&PciRootBridges[Index].PMemAbove4G, &PciRootBridgeInfo-
RootBridge[Index].PMemAbove4G, sizeof(PCI_ROOT_BRIDGE_APERTURE));
+ }

+

+ *NumberOfRootBridges = PciRootBridgeInfo->Count;

+ ResourceAssigned = PciRootBridges[0].ResourceAssigned;

+ for (Index = 1; Index < PciRootBridgeInfo->Count; Index++) {

+ if (PciRootBridges[Index].ResourceAssigned != ResourceAssigned) {

+ DEBUG ((DEBUG_ERROR, "All root birdges' field ResourceAssigned
should be the same\n"));

+ return NULL;

+ }

+ }

+

+ //

+ // Now, this library only supports RootBridge that ResourceAssigned is
True

+ //

+ if (ResourceAssigned) {

+ PcdSetBoolS (PcdPciDisableBusEnumeration, TRUE);

+ } else {

+ DEBUG ((DEBUG_ERROR, "There is root bridge whose ResourceAssigned
is FALSE\n"));

+ PcdSetBoolS (PcdPciDisableBusEnumeration, FALSE);

+ return NULL;

+ }

+

+ return PciRootBridges;

+}

diff --git a/UefiPayloadPkg/UefiPayloadPkg.dec
b/UefiPayloadPkg/UefiPayloadPkg.dec
index 99cb3311a6..a655a374e1 100644
--- a/UefiPayloadPkg/UefiPayloadPkg.dec
+++ b/UefiPayloadPkg/UefiPayloadPkg.dec
@@ -3,7 +3,7 @@
#

# Provides drivers and definitions to create uefi payload for bootloaders.

#

-# Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>

+# Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>

# SPDX-License-Identifier: BSD-2-Clause-Patent

#

##

@@ -29,10 +29,11 @@
#

gBmpImageGuid = { 0x878AC2CC, 0x5343, 0x46F2, { 0xB5, 0x63,
0x51, 0xF8, 0x9D, 0xAF, 0x56, 0xBA } }



- gUefiSystemTableInfoGuid = {0x16c8a6d0, 0xfe8a, 0x4082, {0xa2, 0x8, 0xcf,
0x89, 0xc4, 0x29, 0x4, 0x33}}

- gUefiAcpiBoardInfoGuid = {0xad3d31b, 0xb3d8, 0x4506, {0xae, 0x71, 0x2e,
0xf1, 0x10, 0x6, 0xd9, 0xf}}

- gUefiSerialPortInfoGuid = { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98, 0x95,
0x8d, 0x62, 0xde, 0x87, 0xf1 } }

- gLoaderMemoryMapInfoGuid = { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4,
0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 } }

+ gUefiSystemTableInfoGuid = { 0x16c8a6d0, 0xfe8a, 0x4082, { 0xa2, 0x08,
0xcf, 0x89, 0xc4, 0x29, 0x04, 0x33 }}

+ gUefiAcpiBoardInfoGuid = { 0x0ad3d31b, 0xb3d8, 0x4506, { 0xae, 0x71,
0x2e, 0xf1, 0x10, 0x06, 0xd9, 0x0f }}

+ gUefiSerialPortInfoGuid = { 0x6c6872fe, 0x56a9, 0x4403, { 0xbb, 0x98, 0x95,
0x8d, 0x62, 0xde, 0x87, 0xf1 }}

+ gLoaderMemoryMapInfoGuid = { 0xa1ff7424, 0x7a1a, 0x478e, { 0xa9, 0xe4,
0x92, 0xf3, 0x57, 0xd1, 0x28, 0x32 }}

+ gPldPciRootBridgeInfoGuid = { 0xec4ebacb, 0x2638, 0x416e, { 0xbe, 0x80,
0xe5, 0xfa, 0x4b, 0x51, 0x19, 0x01 }}



[Ppis]

gEfiPayLoadHobBasePpiGuid = { 0xdbe23aa1, 0xa342, 0x4b97, {0x85, 0xb6,
0xb2, 0x26, 0xf1, 0x61, 0x73, 0x89} }

--
2.30.0.windows.2



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Re: [PATCH v1] MdePkg: Support Extended Control Register(XCR) Read and Write.

Wu, Jiaxin
 

Thanks the comments, I will refine the patch according the feedback.

-----Original Message-----
From: Yao, Jiewen <jiewen.yao@...>
Sent: Wednesday, March 31, 2021 10:20 AM
To: devel@edk2.groups.io; gaoliming@...; Wu, Jiaxin
<jiaxin.wu@...>
Cc: Kinney, Michael D <michael.d.kinney@...>; Liu, Zhiguang
<zhiguang.liu@...>; Zhang, Hongbin1 <hongbin1.zhang@...>
Subject: RE: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
Register(XCR) Read and Write.

Agree with Liming.

For IA32, you get parameter from stack -
mov edx, [esp + 12]
mov eax, [esp + 8]
mov ecx, [esp + 4]

For X64, you get parameter from GP register - RCX, RDX, R8, R9 for the first 4
parameter. They are on the stack since the 5th parameter.

The code may be sharable only if they do not have any input parameter. But
not in this case.

Even though, I still recommend we have two copy - like AsmReadCs() in 2
ReadCs.nasm, because we need different context definition, such as "DEFAULT
REL"

Thank you
Yao Jiewen


-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
gaoliming
Sent: Wednesday, March 31, 2021 10:05 AM
To: devel@edk2.groups.io; Wu, Jiaxin <jiaxin.wu@...>
Cc: Kinney, Michael D <michael.d.kinney@...>; Liu, Zhiguang
<zhiguang.liu@...>; Zhang, Hongbin1 <hongbin1.zhang@...>
Subject: 回复: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
Register(XCR) Read and Write.

Jiaxin:
32bit function and 64bit function have the different calling convention.
Their assembly function can't be shared.

This new API interface is same to AsmWriteMsr64(). You can refer
AsmWriteMsr64() implementation in BaseLib.

Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Wu, Jiaxin
发送时间: 2021年3月31日 9:56
收件人: devel@edk2.groups.io; gaoliming@...
抄送: Kinney, Michael D <michael.d.kinney@...>; Liu, Zhiguang
<zhiguang.liu@...>; Zhang, Hongbin1 <hongbin1.zhang@...>
主题: Re: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
Register(XCR) Read and Write.

Actually, the implementation under ia32 should be also workable for X64, I
just put it under ia32.

Liming, do you have suggestion where can we place the code?

Thanks,
Jiaxin

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
gaoliming
Sent: Wednesday, March 31, 2021 9:51 AM
To: devel@edk2.groups.io; Wu, Jiaxin <jiaxin.wu@...>
Cc: Kinney, Michael D <michael.d.kinney@...>; Liu, Zhiguang
<zhiguang.liu@...>; Zhang, Hongbin1 <hongbin1.zhang@...>
Subject: 回复: [edk2-devel] [PATCH v1] MdePkg: Support Extended
Control
Register(XCR) Read and Write.

Where is X64 implementation for this new API?

-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Wu,
Jiaxin
发送时间: 2021年3月31日 9:20
收件人: devel@edk2.groups.io
抄送: Michael D Kinney <michael.d.kinney@...>; Liming Gao
<gaoliming@...>; Zhiguang Liu <zhiguang.liu@...>;
Zhang
Hongbin1 <hongbin1.zhang@...>
主题: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
Register(XCR) Read and Write.

https://bugzilla.tianocore.org/show_bug.cgi?id=3284

This patch is to support Extended Control Register(XCR) Read
and Write.

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>
Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@...>
Signed-off-by: Jiaxin Wu <Jiaxin.wu@...>
---
MdePkg/Include/Library/BaseLib.h | 46
++++++++++++++++++++++++++++++-
MdePkg/Library/BaseLib/BaseLib.inf | 4 ++-
MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm | 31
+++++++++++++++++++++
MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm | 34
+++++++++++++++++++++++
4 files changed, 113 insertions(+), 2 deletions(-)
create mode 100644 MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm

diff --git a/MdePkg/Include/Library/BaseLib.h
b/MdePkg/Include/Library/BaseLib.h
index 1171a0ffb5..c51633ad73 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -1,10 +1,10 @@
/** @file
Provides string functions, linked list functions, math functions,
synchronization
functions, file path functions, and CPU architecture-specific
functions.

-Copyright (c) 2006 - 2019, Intel Corporation. All rights
reserved.<BR>
+Copyright (c) 2006 - 2021, Intel Corporation. All rights
reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights
reserved.<BR>
Copyright (c) Microsoft Corporation.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development
LP.
All
rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -7493,7 +7493,51 @@ PatchInstructionX86 (
OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
IN UINT64 PatchValue,
IN UINTN ValueSize
);

+/**
+ Returns a 64-bit Extended Control Register(XCR).
+
+ Reads and returns the 64-bit XCR specified by Index. No parameter
checking is
+ performed on Index, and some Index values may cause CPU
exceptions.
The
+ caller must either guarantee that Index is valid, or the caller
must
set up
+ exception handlers to catch the exceptions. This function is only
available
+ on IA-32 and x64.
+
+ @param Index The 32-bit XCR index to read.
+
+ @return The value of the XCR identified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadXcr (
+ IN UINT32 Index
+ );
+
+/**
+ Writes a 64-bit value to a Extended Control Register(XCR), and
returns
the
+ value.
+
+ Writes the 64-bit value specified by Value to the XCR specified by
Index.
The
+ 64-bit value written to the XCR is returned. No parameter checking
is
+ performed on Index or Value, and some of these may cause CPU
exceptions. The
+ caller must either guarantee that Index and Value are valid, or the
caller
+ must establish proper exception handlers. This function is only
available
on
+ IA-32 and x64.
+
+ @param Index The 32-bit XCR index to write.
+ @param Value The 64-bit value to write to the XCR.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+AsmWriteXcr (
+ IN UINT32 Index,
+ IN UINT64 Value
+ );
+
#endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
#endif // !defined (__BASE_LIB__)
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
b/MdePkg/Library/BaseLib/BaseLib.inf
index 3b85c56c3c..e62031ea11 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -1,9 +1,9 @@
## @file
# Base Library implementation.
#
-# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
<BR>
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights
reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights
reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -63,10 +63,12 @@
BaseLibInternals.h

[Sources.Ia32]
Ia32/WriteTr.nasm
Ia32/Lfence.nasm
+ Ia32/ReadXcr.nasm
+ Ia32/WriteXcr.nasm

Ia32/Wbinvd.c | MSFT
Ia32/WriteMm7.c | MSFT
Ia32/WriteMm6.c | MSFT
Ia32/WriteMm5.c | MSFT
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
b/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
new file mode 100644
index 0000000000..5d50d8ba01
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
@@ -0,0 +1,31 @@
+;--------------------------------------------------------------------------
----
+;
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadXcr.Asm
+;
+; Abstract:
+;
+; AsmReadXcr function
+;
+; Notes:
+;
+;--------------------------------------------------------------------------
----
+
+ SECTION .text
+
+;--------------------------------------------------------------------------
----
+; UINT64
+; EFIAPI
+; AsmReadXcr (
+; IN UINT32 Index
+; );
+;--------------------------------------------------------------------------
----
+global ASM_PFX(AsmReadXcr)
+ASM_PFX(AsmReadXcr):
+ mov ecx, [esp + 4]
+ xgetbv
+ ret
\ No newline at end of file
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
b/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
new file mode 100644
index 0000000000..009d41864b
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
@@ -0,0 +1,34 @@
+;--------------------------------------------------------------------------
----
+;
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteXcr.nasm
+;
+; Abstract:
+;
+; AsmWriteXcr function
+;
+; Notes:
+;
+;--------------------------------------------------------------------------
----
+
+ SECTION .text
+
+;--------------------------------------------------------------------------
----
+; UINT64
+; EFIAPI
+; AsmWriteXcr (
+; IN UINT32 Index,
+; IN UINT64 Value
+; );
+;--------------------------------------------------------------------------
----
+global ASM_PFX(AsmWriteXcr)
+ASM_PFX(AsmWriteXcr):
+ mov edx, [esp + 12]
+ mov eax, [esp + 8]
+ mov ecx, [esp + 4]
+ xsetbv
+ ret
\ No newline at end of file
--
2.16.2.windows.1


















Re: [edk2-platforms] [patch V4 11/37] Platform/ARM: Consume MdeLibs.dsc.inc for RegisterFilterLib

Sami Mujawar
 

Hi Dandan,


On Sun, Mar 28, 2021 at 06:12 AM, Dandan Bi wrote:
diff --git a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc b/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc
index 5c87a0ca9b..d9dfa7c4ae 100644
--- a/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc
+++ b/Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.dsc
@@ -22,11 +22,14 @@ [Defines]
BOARD_DXE_FV_COMPONENTS = Platform/ARM/SgiPkg/RdN1EdgeX2/RdN1EdgeX2.fdf.inc
BUILD_NUMBER = 1

# include common definitions from SgiPlatform.dsc
!include Platform/ARM/SgiPkg/SgiPlatform.dsc.inc
-!include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.inc
+!include Platform/ARM/SgiPkg/SgiMemoryMap.dsc.
The change above is not needed and breaks the build for RdN1EdgeX2 platform. Can you take a look, please?

+
+# include common/basic libraries from MdePkg.
+!include MdePkg/MdeLibs.dsc.inc
With that changed.

Reviewed-by: Sami Mujawar <sami.mujawar@...>

Regards,

Sami Mujawar


Re: [PATCH v1] MdePkg: Support Extended Control Register(XCR) Read and Write.

Yao, Jiewen
 

Agree with Liming.

For IA32, you get parameter from stack -
mov edx, [esp + 12]
mov eax, [esp + 8]
mov ecx, [esp + 4]

For X64, you get parameter from GP register - RCX, RDX, R8, R9 for the first 4 parameter. They are on the stack since the 5th parameter.

The code may be sharable only if they do not have any input parameter. But not in this case.

Even though, I still recommend we have two copy - like AsmReadCs() in 2 ReadCs.nasm, because we need different context definition, such as "DEFAULT REL"

Thank you
Yao Jiewen

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of gaoliming
Sent: Wednesday, March 31, 2021 10:05 AM
To: devel@edk2.groups.io; Wu, Jiaxin <jiaxin.wu@...>
Cc: Kinney, Michael D <michael.d.kinney@...>; Liu, Zhiguang
<zhiguang.liu@...>; Zhang, Hongbin1 <hongbin1.zhang@...>
Subject: 回复: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
Register(XCR) Read and Write.

Jiaxin:
32bit function and 64bit function have the different calling convention.
Their assembly function can't be shared.

This new API interface is same to AsmWriteMsr64(). You can refer
AsmWriteMsr64() implementation in BaseLib.

Thanks
Liming
-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Wu, Jiaxin
发送时间: 2021年3月31日 9:56
收件人: devel@edk2.groups.io; gaoliming@...
抄送: Kinney, Michael D <michael.d.kinney@...>; Liu, Zhiguang
<zhiguang.liu@...>; Zhang, Hongbin1 <hongbin1.zhang@...>
主题: Re: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
Register(XCR) Read and Write.

Actually, the implementation under ia32 should be also workable for X64, I
just put it under ia32.

Liming, do you have suggestion where can we place the code?

Thanks,
Jiaxin

-----Original Message-----
From: devel@edk2.groups.io <devel@edk2.groups.io> On Behalf Of
gaoliming
Sent: Wednesday, March 31, 2021 9:51 AM
To: devel@edk2.groups.io; Wu, Jiaxin <jiaxin.wu@...>
Cc: Kinney, Michael D <michael.d.kinney@...>; Liu, Zhiguang
<zhiguang.liu@...>; Zhang, Hongbin1 <hongbin1.zhang@...>
Subject: 回复: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
Register(XCR) Read and Write.

Where is X64 implementation for this new API?

-----邮件原件-----
发件人: devel@edk2.groups.io <devel@edk2.groups.io> 代表 Wu,
Jiaxin
发送时间: 2021年3月31日 9:20
收件人: devel@edk2.groups.io
抄送: Michael D Kinney <michael.d.kinney@...>; Liming Gao
<gaoliming@...>; Zhiguang Liu <zhiguang.liu@...>;
Zhang
Hongbin1 <hongbin1.zhang@...>
主题: [edk2-devel] [PATCH v1] MdePkg: Support Extended Control
Register(XCR) Read and Write.

https://bugzilla.tianocore.org/show_bug.cgi?id=3284

This patch is to support Extended Control Register(XCR) Read
and Write.

Cc: Michael D Kinney <michael.d.kinney@...>
Cc: Liming Gao <gaoliming@...>
Cc: Zhiguang Liu <zhiguang.liu@...>
Signed-off-by: Zhang Hongbin1 <hongbin1.zhang@...>
Signed-off-by: Jiaxin Wu <Jiaxin.wu@...>
---
MdePkg/Include/Library/BaseLib.h | 46
++++++++++++++++++++++++++++++-
MdePkg/Library/BaseLib/BaseLib.inf | 4 ++-
MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm | 31
+++++++++++++++++++++
MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm | 34
+++++++++++++++++++++++
4 files changed, 113 insertions(+), 2 deletions(-)
create mode 100644 MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
create mode 100644 MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm

diff --git a/MdePkg/Include/Library/BaseLib.h
b/MdePkg/Include/Library/BaseLib.h
index 1171a0ffb5..c51633ad73 100644
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -1,10 +1,10 @@
/** @file
Provides string functions, linked list functions, math functions,
synchronization
functions, file path functions, and CPU architecture-specific
functions.

-Copyright (c) 2006 - 2019, Intel Corporation. All rights
reserved.<BR>
+Copyright (c) 2006 - 2021, Intel Corporation. All rights
reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights
reserved.<BR>
Copyright (c) Microsoft Corporation.<BR>
Portions Copyright (c) 2020, Hewlett Packard Enterprise Development
LP.
All
rights reserved.<BR>

SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -7493,7 +7493,51 @@ PatchInstructionX86 (
OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,
IN UINT64 PatchValue,
IN UINTN ValueSize
);

+/**
+ Returns a 64-bit Extended Control Register(XCR).
+
+ Reads and returns the 64-bit XCR specified by Index. No parameter
checking is
+ performed on Index, and some Index values may cause CPU
exceptions.
The
+ caller must either guarantee that Index is valid, or the caller
must
set up
+ exception handlers to catch the exceptions. This function is only
available
+ on IA-32 and x64.
+
+ @param Index The 32-bit XCR index to read.
+
+ @return The value of the XCR identified by Index.
+
+**/
+UINT64
+EFIAPI
+AsmReadXcr (
+ IN UINT32 Index
+ );
+
+/**
+ Writes a 64-bit value to a Extended Control Register(XCR), and
returns
the
+ value.
+
+ Writes the 64-bit value specified by Value to the XCR specified by
Index.
The
+ 64-bit value written to the XCR is returned. No parameter checking
is
+ performed on Index or Value, and some of these may cause CPU
exceptions. The
+ caller must either guarantee that Index and Value are valid, or the
caller
+ must establish proper exception handlers. This function is only
available
on
+ IA-32 and x64.
+
+ @param Index The 32-bit XCR index to write.
+ @param Value The 64-bit value to write to the XCR.
+
+ @return Value
+
+**/
+UINT64
+EFIAPI
+AsmWriteXcr (
+ IN UINT32 Index,
+ IN UINT64 Value
+ );
+
#endif // defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
#endif // !defined (__BASE_LIB__)
diff --git a/MdePkg/Library/BaseLib/BaseLib.inf
b/MdePkg/Library/BaseLib/BaseLib.inf
index 3b85c56c3c..e62031ea11 100644
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -1,9 +1,9 @@
## @file
# Base Library implementation.
#
-# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.
<BR>
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.
<BR>
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights
reserved.<BR>
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights
reserved.<BR>
# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All
rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -63,10 +63,12 @@
BaseLibInternals.h

[Sources.Ia32]
Ia32/WriteTr.nasm
Ia32/Lfence.nasm
+ Ia32/ReadXcr.nasm
+ Ia32/WriteXcr.nasm

Ia32/Wbinvd.c | MSFT
Ia32/WriteMm7.c | MSFT
Ia32/WriteMm6.c | MSFT
Ia32/WriteMm5.c | MSFT
diff --git a/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
b/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
new file mode 100644
index 0000000000..5d50d8ba01
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/ReadXcr.nasm
@@ -0,0 +1,31 @@
+;--------------------------------------------------------------------------
----
+;
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; ReadXcr.Asm
+;
+; Abstract:
+;
+; AsmReadXcr function
+;
+; Notes:
+;
+;--------------------------------------------------------------------------
----
+
+ SECTION .text
+
+;--------------------------------------------------------------------------
----
+; UINT64
+; EFIAPI
+; AsmReadXcr (
+; IN UINT32 Index
+; );
+;--------------------------------------------------------------------------
----
+global ASM_PFX(AsmReadXcr)
+ASM_PFX(AsmReadXcr):
+ mov ecx, [esp + 4]
+ xgetbv
+ ret
\ No newline at end of file
diff --git a/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
b/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
new file mode 100644
index 0000000000..009d41864b
--- /dev/null
+++ b/MdePkg/Library/BaseLib/Ia32/WriteXcr.nasm
@@ -0,0 +1,34 @@
+;--------------------------------------------------------------------------
----
+;
+; Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+; SPDX-License-Identifier: BSD-2-Clause-Patent
+;
+; Module Name:
+;
+; WriteXcr.nasm
+;
+; Abstract:
+;
+; AsmWriteXcr function
+;
+; Notes:
+;
+;--------------------------------------------------------------------------
----
+
+ SECTION .text
+
+;--------------------------------------------------------------------------
----
+; UINT64
+; EFIAPI
+; AsmWriteXcr (
+; IN UINT32 Index,
+; IN UINT64 Value
+; );
+;--------------------------------------------------------------------------
----
+global ASM_PFX(AsmWriteXcr)
+ASM_PFX(AsmWriteXcr):
+ mov edx, [esp + 12]
+ mov eax, [esp + 8]
+ mov ecx, [esp + 4]
+ xsetbv
+ ret
\ No newline at end of file
--
2.16.2.windows.1


















[PATCH 5/5] ArmPkg: Fix typo of Manufacturer in comment in SmbiosMiscDxe

Rebecca Cran <rebecca@...>
 

'Manufacturer' was spelled wrongly in a comment in
MiscChassisManufacturerData.c.

Signed-off-by: Rebecca Cran <rebecca@...>
---
ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c
index 137bd941d0b1..29449b871902 100644
--- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c
+++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerData.c
@@ -23,7 +23,7 @@ SMBIOS_MISC_TABLE_DATA(SMBIOS_TABLE_TYPE3, MiscChassisManufacturer) = {
0, // Length,
0 // Handle
},
- 1, // Manufactrurer
+ 1, // Manufacturer
MiscChassisTypeMainServerChassis, // Type
2, // Version
3, // SerialNumber
--
2.26.2


[PATCH 4/5] ArmPkg: Fix calculation of offset of chassis SKU Number in SmbiosMiscDxe

Rebecca Cran <rebecca@...>
 

The calculation of the chassis SKU number field was being calculated
incorrectly, forgetting that there's one element already present in
the structure.
Fix the calculation and improve code readability by introducing a
SkuNumberField variable.

Signed-off-by: Rebecca Cran <rebecca@...>
---
ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c
index 344343ed60a5..66e3e5327fc3 100644
--- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c
+++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c
@@ -39,6 +39,7 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer)
{
CHAR8 *OptionalStrStart;
CHAR8 *StrStart;
+ UINT8 *SkuNumberField;
UINTN RecordLength;
UINTN ManuStrLen;
UINTN VerStrLen;
@@ -117,10 +118,7 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer)
ChaNumStrLen = StrLen (ChassisSkuNumber);

ContainedElementCount = InputData->ContainedElementCount;
-
- if (ContainedElementCount > 1) {
- ExtendLength = (ContainedElementCount - 1) * sizeof (CONTAINED_ELEMENT);
- }
+ ExtendLength = ContainedElementCount * sizeof (CONTAINED_ELEMENT);

//
// Two zeros following the last string.
@@ -149,7 +147,11 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer)
(VOID)CopyMem (SmbiosRecord + 1, &ContainedElements, ExtendLength);

//ChassisSkuNumber
- *((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) + ExtendLength) = 5;
+ SkuNumberField = (UINT8 *)SmbiosRecord +
+ sizeof (SMBIOS_TABLE_TYPE3) -
+ sizeof (CONTAINED_ELEMENT) + ExtendLength;
+
+ *SkuNumberField = 5;

OptionalStrStart = (CHAR8 *)((UINT8 *)SmbiosRecord + sizeof (SMBIOS_TABLE_TYPE3) +
ExtendLength + 1);
--
2.26.2


[PATCH 3/5] ArmPkg: Allow platforms to report their boot status via OemMiscLib call

Rebecca Cran <rebecca@...>
 

Add a new function to OemMiscLib to allow platforms to report their boot
status into the Type32 SMBIOS table.

Signed-off-by: Rebecca Cran <rebecca@...>
---
ArmPkg/Include/Library/OemMiscLib.h | 10 ++++++++++
ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c | 14 ++++++++++++++
ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c | 3 +++
3 files changed, 27 insertions(+)

diff --git a/ArmPkg/Include/Library/OemMiscLib.h b/ArmPkg/Include/Library/OemMiscLib.h
index 25ae508ddb03..0b03fe8d4de3 100644
--- a/ArmPkg/Include/Library/OemMiscLib.h
+++ b/ArmPkg/Include/Library/OemMiscLib.h
@@ -162,6 +162,16 @@ OemUpdateSmbiosInfo (
IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
);

+/** Fetches the Type 32 boot information status.
+
+ @return Boot status.
+**/
+MISC_BOOT_INFORMATION_STATUS_DATA_TYPE
+EFIAPI
+OemGetBootStatus (
+ VOID
+ );
+
/** Fetches the chassis status when it was last booted.

@return Chassis status.
diff --git a/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c b/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c
index e6a4793fe1c2..74101beab1cb 100644
--- a/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c
+++ b/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c
@@ -140,6 +140,20 @@ OemUpdateSmbiosInfo (
ASSERT (FALSE);
}

+/** Fetches the Type 32 boot information status.
+
+ @return Boot status.
+**/
+MISC_BOOT_INFORMATION_STATUS_DATA_TYPE
+EFIAPI
+OemGetBootStatus (
+ VOID
+ )
+{
+ ASSERT (FALSE);
+ return BootInformationStatusNoError;
+}
+
/** Fetches the chassis status when it was last booted.

@return Chassis status.
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c
index 733615bbcf1a..4be1e1cd29a9 100644
--- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c
+++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type32/MiscBootInformationFunction.c
@@ -16,6 +16,7 @@
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
#include <Library/MemoryAllocationLib.h>
+#include <Library/OemMiscLib.h>
#include <Library/UefiBootServicesTableLib.h>

#include "SmbiosMisc.h"
@@ -59,6 +60,8 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscBootInformation)

SmbiosRecord->Hdr.Length = sizeof (SMBIOS_TABLE_TYPE32);

+ SmbiosRecord->BootStatus = OemGetBootStatus ();
+
//
// Now we have got the full smbios record, call smbios protocol to add this record.
//
--
2.26.2


[PATCH 2/5] ArmPkg: Allow platforms to supply more data for SMBIOS Type3 record

Rebecca Cran <rebecca@...>
 

Add OemMiscLib calls to allow platforms to provide the following
information about the chassis:

o Bootup state
o Power supply/supplies state
o Thermal state
o Security state
o Chassis height (in RMU)
o Number of power cords

Signed-off-by: Rebecca Cran <rebecca@...>
---
ArmPkg/Include/Library/OemMiscLib.h | 60 ++++++++++++++
ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c | 85 ++++++++++++++++++++
ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c | 8 ++
3 files changed, 153 insertions(+)

diff --git a/ArmPkg/Include/Library/OemMiscLib.h b/ArmPkg/Include/Library/OemMiscLib.h
index 6dcc76a214df..25ae508ddb03 100644
--- a/ArmPkg/Include/Library/OemMiscLib.h
+++ b/ArmPkg/Include/Library/OemMiscLib.h
@@ -162,4 +162,64 @@ OemUpdateSmbiosInfo (
IN OEM_MISC_SMBIOS_HII_STRING_FIELD Field
);

+/** Fetches the chassis status when it was last booted.
+
+ @return Chassis status.
+**/
+MISC_CHASSIS_STATE
+EFIAPI
+OemGetChassisBootupState (
+ VOID
+ );
+
+/** Fetches the chassis power supply/supplies status when last booted.
+
+ @return Chassis power supply/supplies status.
+**/
+MISC_CHASSIS_STATE
+EFIAPI
+OemGetChassisPowerSupplyState (
+ VOID
+ );
+
+/** Fetches the chassis thermal status when last booted.
+
+ @return Chassis thermal status.
+**/
+MISC_CHASSIS_STATE
+EFIAPI
+OemGetChassisThermalState (
+ VOID
+ );
+
+/** Fetches the chassis security status when last booted.
+
+ @return Chassis security status.
+**/
+MISC_CHASSIS_SECURITY_STATE
+EFIAPI
+OemGetChassisSecurityStatus (
+ VOID
+ );
+
+/** Fetches the chassis height in RMUs (Rack Mount Units).
+
+ @return The height of the chassis.
+**/
+UINT8
+EFIAPI
+OemGetChassisHeight (
+ VOID
+ );
+
+/** Fetches the number of power cords.
+
+ @return The number of power cords.
+**/
+UINT8
+EFIAPI
+OemGetChassisNumPowerCords (
+ VOID
+ );
+
#endif // OEM_MISC_LIB_H_
diff --git a/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c b/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c
index 21f106f1e060..e6a4793fe1c2 100644
--- a/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c
+++ b/ArmPkg/Universal/Smbios/OemMiscLibNull/OemMiscLib.c
@@ -139,3 +139,88 @@ OemUpdateSmbiosInfo (
{
ASSERT (FALSE);
}
+
+/** Fetches the chassis status when it was last booted.
+
+ @return Chassis status.
+**/
+MISC_CHASSIS_STATE
+EFIAPI
+OemGetChassisBootupState (
+ VOID
+ )
+{
+ ASSERT (FALSE);
+ return ChassisStateSafe;
+}
+
+/** Fetches the chassis power supply/supplies status when last booted.
+
+ @return Chassis power supply/supplies status.
+**/
+MISC_CHASSIS_STATE
+EFIAPI
+OemGetChassisPowerSupplyState (
+ VOID
+ )
+{
+ ASSERT (FALSE);
+ return ChassisStateSafe;
+}
+
+/** Fetches the chassis thermal status when last booted.
+
+ @return Chassis thermal status.
+**/
+MISC_CHASSIS_STATE
+EFIAPI
+OemGetChassisThermalState (
+ VOID
+ )
+{
+ ASSERT (FALSE);
+ return ChassisStateSafe;
+}
+
+/** Fetches the chassis security status when last booted.
+
+ @return Chassis security status.
+**/
+MISC_CHASSIS_SECURITY_STATE
+EFIAPI
+OemGetChassisSecurityStatus (
+ VOID
+ )
+{
+ ASSERT (FALSE);
+ return ChassisSecurityStatusNone;
+}
+
+/** Fetches the chassis height in RMUs (Rack Mount Units).
+
+ @return The height of the chassis.
+**/
+UINT8
+EFIAPI
+OemGetChassisHeight (
+ VOID
+ )
+{
+ ASSERT (FALSE);
+ return 1U;
+}
+
+/** Fetches the number of power cords.
+
+ @return The number of power cords.
+**/
+UINT8
+EFIAPI
+OemGetChassisNumPowerCords (
+ VOID
+ )
+{
+ ASSERT (FALSE);
+ return 1;
+}
+
diff --git a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c
index fc4dba319aad..344343ed60a5 100644
--- a/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c
+++ b/ArmPkg/Universal/Smbios/SmbiosMiscDxe/Type03/MiscChassisManufacturerFunction.c
@@ -162,6 +162,14 @@ SMBIOS_MISC_TABLE_FUNCTION(MiscChassisManufacturer)
UnicodeStrToAsciiStrS (AssertTag, StrStart, AssertTagStrLen + 1);
StrStart += AssertTagStrLen + 1;
UnicodeStrToAsciiStrS (ChassisSkuNumber, StrStart, ChaNumStrLen + 1);
+
+ SmbiosRecord->BootupState = OemGetChassisBootupState ();
+ SmbiosRecord->PowerSupplyState = OemGetChassisPowerSupplyState ();
+ SmbiosRecord->ThermalState = OemGetChassisThermalState ();
+ SmbiosRecord->SecurityStatus = OemGetChassisSecurityStatus ();
+ SmbiosRecord->Height = OemGetChassisHeight ();
+ SmbiosRecord->NumberofPowerCords = OemGetChassisNumPowerCords ();
+
//
// Now we have got the full smbios record, call smbios protocol to add this record.
//
--
2.26.2